Display panel and display apparatus

Abstract

A display panel (01) and a display apparatus. The display panel (01) comprises: a driving circuit (20), a plurality of pixels (p), a plurality of first scan lines (SL1) and a plurality of clock lines (CL); the driving circuit (20) comprises N cascaded first shift register units (22); the clock lines (CL) are electrically connected to the plurality of first shift register units (22); the first shift register units (22) are configured to receive at least an input signal and clock signals on the clock lines (CL), and provide the clock signals of the clock lines (CL) to the first scan line (SL1) as first scan signals (Scan1(i)); effective times of the first scan signals (Scan1(i)) of at least some of the first shift register units (22) connected to a same clock line (CL) overlap; the process of the clock signals transitioning from an inactive level to an active level is a first voltage edge (J1), and the process of the clock signals transitioning from the active level to the inactive level is a second voltage edge (J2); and, during at least part of a display time of one image frame, the transition duration of the second voltage edge (J2) of the clock signals is greater than or equal to a second preset duration.

Description

Display panel and display device

[0001] This application claims priority to Chinese Patent Application No. 202411555969.5, filed with the Chinese Patent Office on November 1, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of display technology, such as a display panel and display device. Background Technology

[0003] Currently, compared with traditional liquid crystal displays (LCDs), organic light-emitting diode (OLED) displays have advantages such as low power consumption, fast response, high contrast, and thinness, and are now widely used in many devices such as smartphones, tablets, laptops, televisions, and calculators.

[0004] In organic light-emitting diode (OLED) display technology, multi-pulse driving is a commonly used driving method that improves the response time of the display panel and can alleviate the threshold drift problem of the driving transistors in the pixel circuit.

[0005] However, the multi-pulse driving method in related technologies also causes uneven display of the display panel, that is, some areas of the display panel have abnormal display brightness. For example, the area near the upper or lower edge of the display panel has abnormal display brightness. Summary of the Invention

[0006] This application provides a display panel and a display device to improve the problem of uneven display on the display panel.

[0007] One aspect of this application provides a display panel, including: a driving circuit, a plurality of pixels arranged in an array, a plurality of first scan lines, and a plurality of clock lines;

[0008] At least some pixels located in the same row are electrically connected to the same first scan line;

[0009] The driving circuit is electrically connected to multiple first scan lines respectively; the driving circuit includes N cascaded first shift register units; the clock line is electrically connected to multiple first shift register units; the first shift register units are configured to receive at least the input signal and the clock signal on the clock line, and control the clock signal on the clock line to provide the first scan signal to the first scan line;

[0010] The effective times of the first scan signals of at least a portion of the first shift register units connected to the same clock line overlap.

[0011] The transition of the clock signal from an invalid level to an effective level is the first voltage edge, and the transition from an effective level to an invalid level is the second voltage edge.

[0012] During at least a portion of the display time of a frame, the transition duration of the second voltage edge of the clock signal is greater than or equal to a second preset duration.

[0013] Another aspect of this application provides a display device, including: the aforementioned display panel and housing.

[0014] It should be understood that the content described in this section is not intended to identify key or important features of the embodiments of this application, nor is it intended to limit the scope of this application. Attached Figure Description

[0015] Figure 1 is a schematic diagram of the structure of a display panel provided in an embodiment of this application;

[0016] Figure 2 is a structural schematic diagram and timing diagram of a driving circuit provided in an embodiment of this application;

[0017] Figure 3 is a schematic diagram of the structure of a first shift register unit provided in an embodiment of this application;

[0018] Figure 4 is a structural schematic diagram and timing diagram of another driving circuit provided in an embodiment of this application;

[0019] Figure 5 is a structural schematic diagram and timing diagram of another driving circuit provided in an embodiment of this application;

[0020] Figure 6 is a schematic diagram of the structure of another display panel provided in an embodiment of this application;

[0021] Figure 7 is a schematic diagram of the circuit structure of a pixel provided in an embodiment of this application;

[0022] Figure 8 is a schematic diagram of another pixel circuit structure provided in an embodiment of this application.

[0023] Figure 9 is a schematic diagram of the structure of another display panel provided in an embodiment of this application;

[0024] Figure 10 is a timing diagram of a pixel circuit provided in an embodiment of this application;

[0025] Figure 11 is a structural schematic diagram and timing diagram of another driving circuit provided in an embodiment of this application;

[0026] Figure 12 is a structural schematic diagram and timing diagram of another driving circuit provided in an embodiment of this application;

[0027] Figure 13 is a structural schematic diagram and timing diagram of another driving circuit provided in an embodiment of this application;

[0028] Figure 14 is a structural schematic diagram and timing diagram of another driving circuit provided in an embodiment of this application;

[0029] Figure 15 is a structural schematic diagram and timing diagram of another driving circuit provided in an embodiment of this application;

[0030] Figure 16 is a structural schematic diagram and timing diagram of another driving circuit provided in an embodiment of this application;

[0031] Figure 17 is a structural schematic diagram and timing diagram of another driving circuit provided in an embodiment of this application;

[0032] Figure 18 is a structural schematic diagram and timing diagram of another driving circuit provided in an embodiment of this application;

[0033] Figure 19 is a timing diagram of another pixel circuit provided in an embodiment of this application;

[0034] Figure 20 is a timing diagram of another pixel circuit provided in an embodiment of this application;

[0035] Figure 21 is a structural schematic diagram and timing diagram of another driving circuit provided in an embodiment of this application;

[0036] Figure 22 is a timing diagram of another pixel circuit provided in an embodiment of this application;

[0037] Figure 23 is a timing diagram of another pixel circuit provided in an embodiment of this application;

[0038] Figure 24 is a schematic diagram of the structure of a display device provided in an embodiment of this application. Detailed Implementation

[0039] The technical solutions of the embodiments of this application will be described below with reference to the accompanying drawings. The described embodiments are merely some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of this application.

[0040] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, for example, including, in addition to processes, methods, systems, products, or devices that include the series of steps or units shown in the embodiments of this application, other processes, methods, systems, products, or devices that are not explicitly listed in this series of steps or units, or other steps or units inherent to these processes, methods, systems, products, or devices.

[0041] As described in the background art, in the organic light-emitting diode display technology of related technologies, multi-pulse driving is a commonly used driving method. In this method, the driving circuit can receive a clock signal and control the clock signal as the driving signal output. During the display time of one frame, the driving signal includes multiple effective pulses, and the driving circuit can output the clock signal as the driving signal in multiple time periods.

[0042] During the display time of one frame, the driving circuit can output multiple driving signals. The effective pulse durations of different driving signals may overlap, meaning the driving circuit can control a single clock signal as multiple driving signals within a certain time period, resulting in a high load on the clock line transmitting that clock signal. The number of driving signals with overlapping effective durations may vary at different points in the display time of one frame, meaning the clock line load may also vary. Changes in the clock line load affect the signal delay when the driving circuit outputs driving signals, causing variations in the voltage edge transition speed of the driving signal. When the voltage edge transition speed of the driving signal is too fast, the coupling effect on some nodes in the pixel circuit becomes more pronounced, leading to an excessively high or low driving current supplied to the organic light-emitting diode by the pixel circuit, causing uneven display on the display panel.

[0043] This application provides a display panel, including: a driving circuit, a plurality of pixels arranged in an array, a plurality of first scan lines, and a plurality of clock lines; at least some pixels located in the same row are electrically connected to the same first scan line; the driving circuit is electrically connected to the plurality of first scan lines respectively; the driving circuit includes N cascaded first shift register units; the clock lines are electrically connected to the plurality of first shift register units; the first shift register units are configured to receive at least an input signal and a clock signal on the clock line, and control the clock signal of the clock line to be provided to the first scan line as a first scan signal; the effective time of the first scan signals of at least some of the first shift register units connected to the same clock line overlaps; the process of the clock signal transitioning from an invalid level to an effective level is a first voltage edge, and the process of transitioning from an effective level to an invalid level is a second voltage edge; during at least a portion of the display time of a frame, the transition duration of the second voltage edge of the clock signal is greater than or equal to a second preset duration.

[0044] By adopting the above technical solution, by setting the transition duration of the second voltage edge of the clock signal to be greater than or equal to the duration of the second preset duration for at least a portion of the display time of a frame, the transition speed of the second voltage edge of the clock signal can be reduced, making the process of the first scan signal transitioning from an effective level to an ineffective level slower. When parasitic capacitance exists in the pixel, the coupling effect of the first scan signal on the nodes in the pixel is smaller. In this way, even when the load on the clock line transmitting the clock signal fluctuates, such as when the load decreases, it can be ensured that the coupling effect of the first scan signal on the nodes will not significantly change the potential of the nodes, which is beneficial to the stability of the potential of the nodes in the pixel. This effectively improves the problem of uneven display caused by the load change of the clock line during a portion of the display time of a frame.

[0045] Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without inventive effort are within the scope of protection of this application. The technical solutions in the embodiments of this application will be described below with reference to the accompanying drawings.

[0046] Figure 1 is a schematic diagram of the structure of a display panel provided in an embodiment of this application. Referring to Figure 1, the display panel 01 includes a driving circuit 20, a plurality of pixels P arranged in an array, a plurality of first scan lines and a plurality of clock lines CL; at least some of the pixels P located in the same row are electrically connected to the same first scan line SL1; the driving circuit 20 is electrically connected to the plurality of clock lines CL and the plurality of first scan lines SL1 respectively.

[0047] Figure 2 is a schematic diagram of the structure and timing of a driving circuit provided in an embodiment of this application. Referring to Figure 2, the driving circuit 20 includes a first shift register 21, which includes N cascaded first shift register units 22. The first shift register units 22 are electrically connected to the first scan line SL1. The clock line CL is electrically connected to the multiple first shift register units 22. The i-th stage first shift register unit 22 is configured to receive at least the input signal and the clock signal (CK1, XCK1) on the clock line CL, and control the clock signal (CK1 or XCK1) on the clock line CL to be provided to the first scan line SL1 as the first scan signal Scan1(i), where i is a positive integer less than or equal to N.

[0048] Referring again to Figures 1 and 2, the effective times of the first scan signals Scan1 of at least a portion of the first shift register units 22 connected to the same clock line CL overlap; the transition of the clock signals (CK1, XCK1) from an invalid level to an effective level is the first voltage edge J1, and the transition of the clock signals (CK1, XCK1) from an effective level to an invalid level is the second voltage edge J2. During at least a portion of the display time DF of a frame, the transition duration of the second voltage edge J2 of the clock signals (CK1, XCK1) is greater than or equal to a second preset duration.

[0049] The second preset duration can be the shortest transition duration of the second voltage edge J2 of the clock signal (CK1, XCK1) in the display time DF of a frame. During a certain period of the display time DF of a frame, the transition duration of the second voltage edge J2 of the clock signal (CK1, XCK1) can be greater than the transition duration of the second voltage edge J2 in other periods. Alternatively, the second preset duration can also be the normal transition duration of the second voltage edge of the clock signal (CK1, XCK1) in the related art. For example, if the normal transition duration of the second voltage edge of the clock signal (CK1, XCK1) in the related art is 600ns, then the second preset duration can be 600ns. If the normal transition duration of the second voltage edge of the clock signal (CK1, XCK1) in the related art is 500-600ns, then the second preset duration can be 500-600ns. In an optional embodiment, during at least a portion of the display time DF of a frame, the transition duration of the second voltage edge J2 of the clock signal (CK1, XCK1) can be 600-700ns.

[0050] For example, Figure 3 is a schematic diagram of the structure of a first shift register unit provided in an embodiment of this application. Referring to Figures 2 and 3, the first shift register unit 22 can receive a first clock signal CK1, a second clock signal XCK1, a first level signal VGH, and a second level signal VGL. The first shift register unit 22 may include eight transistors (MS1, MS2, MS3, MS4, MS5, MS6, MS7, MS8) and two capacitors (CS1, CS2). In an optional embodiment, the clock periods of the first clock signal CK1 and the second clock signal XCK1 are the same; and the polarities of the first clock signal CK1 and the second clock signal XCK1 are opposite for at least a portion of the same clock period.

[0051] The first-stage first shift register unit 22 can receive the first initial signal STV1 as an input signal, and the subsequent first shift register unit 22 can receive the first scan signal Scan1 output by the previous stage first shift register unit 22 as an input signal.

[0052] For the odd-level first shift register unit 22, the first shift register unit 22 is turned on when both the input signal and the first clock signal CK1 are at an active level. The period during which the input signal is at an active level and the first clock signal CK1 is also at an active level, and the period after that during which the input signal is at an inactive level and the first clock signal CK1 is also at an inactive level, are the conduction periods of the first shift register unit 22. During the conduction periods, the first shift register unit 22 can output an active pulse of the second clock signal XCK1 as an active pulse of the first scan signal Scan1.

[0053] For the even-numbered first shift register unit 22, the first shift register unit 22 is turned on when the input signal and the second clock signal XCK1 are both at an active level. The period when the input signal is at an active level and the second clock signal XCK1 is also at an active level, and the period after that when the input signal is at an inactive level and the second clock signal XCK1 is also at an inactive level, are the conduction periods of the first shift register unit 22. During the conduction period, the first shift register unit 22 can output an active pulse of the first clock signal CK1 as an active pulse of the first scan signal Scan1.

[0054] The effective levels of the first clock signal CK1 and the second clock signal XCK1 can be either high or low. For N-type transistors, the effective level is high and the ineffective level is low; for P-type transistors, the effective level is low and the ineffective level is high. For ease of description, unless otherwise specified, this application embodiment uses the example of all P-type transistors in the first shift register unit 22 having an effective level of low to illustrate the technical solution of this application embodiment.

[0055] When the first initial signal STV1 includes multiple valid pulses, the first shift register unit 22 includes multiple conduction periods, that is, the first shift register unit 22 can output multiple valid pulses of the second clock signal XCK1 or the first clock signal CK1 as multiple valid pulses of the first scan signal Scan1.

[0056] Taking the first shift register 21 electrically connected to two clock lines CL, and the first shift register unit 22 being able to output two valid pulses of the first scan signal Scan1 during the display time DF of one frame as an example, referring to Figures 1-3, for the first scan signal Scan1 output by the first shift register unit 22 of the first two stages, the second valid pulse of the first scan signal Scan1(i) can overlap with the first valid pulse of the first scan signal Scan1(i+2); for the first scan signal Scan1 output by the first shift register unit 22 of the last two stages, the first valid pulse of the first scan signal Scan1(i) can overlap with the second valid pulse of the first scan signal Scan1(i-2); for the first scan signal Scan1 output by the first shift register unit 22 of other stages, the first valid pulse of the first scan signal Scan1(i) can overlap with the second valid pulse of the first scan signal Scan1(i-2), and the second valid pulse can overlap with the first valid pulse of the first scan signal Scan1(i+2).

[0057] As can be seen from the above, the first scan signals Scan1 with overlapping effective times all originate from either the odd-numbered or even-numbered first shift register units 22. The effective pulses of the first scan signals Scan1 output by the odd-numbered first shift register units 22 all originate from the second clock signal XCK1, and the effective pulses of the first scan signals Scan1 output by the even-numbered first shift register units 22 all originate from the first clock signal CK1. During a portion of the display time DF of a frame, such as the FT0' period, the effective time of the first scan signal Scan1 exists... The overlapping and simultaneous control of the same clock signal (CK1 or XCK1) by the first shift register unit 22 as the first scan signal Scan1 results in a large number of first shift register units 22. This leads to a large load on the clock line CL that transmits the second clock signal XCK1 or the first clock signal CK1. Consequently, when the first shift register unit 22 controls the clock signal (CK1, XCK1) as the first scan signal Scan1 output, the signal delay is greater, resulting in a slower level transition process for the first scan signal Scan1. This also makes the coupling effect on some nodes in pixel P less obvious, which is beneficial to the stability of the potential of the nodes in pixel P.

[0058] When the effective times of the first scan signal Scan1 do not overlap, such as the FT1' and FT2' time periods, the number of first shift register units 22 that control the same clock signal (CK1, XCK1) as the first scan signal Scan1 is small. This results in a smaller load on the clock line CL that transmits the second clock signal XCK1 or the first clock signal CK1, leading to less signal delay when the first shift register unit 22 controls the clock signal (CK1, XCK1) as the first scan signal Scan1 output. At least during the FT1' and FT2' periods, increasing the transition duration of the second voltage of the clock signals (CK1, XCK1) along J2, making the transition duration of the second voltage of the clock signals (CK1, XCK1) along J2 greater than or equal to the second preset duration, can reduce the transition speed of the second voltage of the clock signals (CK1, XCK1) along J2. Thus, even if the load on the clock line CL is reduced and the signal delay is less, the transition process of the first scan signal Scan1 from the effective level to the ineffective level can be slower, which can reduce the coupling effect of the first scan signal Scan1 on the node. This is beneficial for balancing the transition speed of multiple first scan signals Scan1 from the effective level to the ineffective level under different loads on the clock line CL during the display time DF of a frame, thereby improving the problem of uneven display on the display panel 01.

[0059] The clock signals (CK1, XCK1) can be directly provided by the driver chip (not shown in the figure) or the clock controller (not shown in the figure). When the load connected to the clock line CL used to transmit the clock signals (CK1 or XCK1) is large, it will affect the signal delay in the process of the first shift register unit 22 providing the clock signals (CK1 or XCK1) as the first scan signal Scan1(i) to the first scan line SL1, resulting in a large signal delay and a decrease in the level transition speed of the first scan signal Scan1(i). However, the impact on the level transition speed of the transmitted clock signals (CK1 or XCK1) themselves is small. Therefore, during certain periods, when the transition time of the second voltage of the clock signals (CK1, XCK1) along J2 is set to be less than the second preset time, the transition of the second voltage of the clock signals (CK1, XCK1) along J2 can be faster. However, due to the influence of the load connected to the clock line CL used to transmit the clock signals (CK1 or XCK1), the level transition speed of the first scan signal Scan1(i) may be slower.

[0060] The first scan signal Scan1 can control the switching devices in pixel P. When the first scan signal Scan1 is at an active level, it can transmit initialization signals, data signals, compensation signals, reset signals, bias signals, and other signals to pixel P, changing the node's potential. Even though the transition of the first scan signal Scan1 from an inactive level to an active level has a coupling effect on the node, the node will still be rewritten with the corresponding signals when the first scan signal Scan1 transitions to an active level. Therefore, the transition of the first scan signal Scan1 from an inactive level to an active level has a relatively small impact on the node's potential. By setting the transition duration of the second voltage of the clock signal along J2 to be greater than or equal to a second preset duration for at least a portion of the time, the transition process of the first scan signal Scan1 from an active level to an inactive level can be improved, thus improving the problem of uneven display.

[0061] In this embodiment, by setting the transition duration of the second voltage edge of the clock signal to be greater than or equal to a second preset duration for at least a portion of the display time of a frame, the transition speed of the second voltage edge of the clock signal can be reduced, making the process of the first scan signal transitioning from an effective level to an ineffective level slower. When parasitic capacitance exists in the pixel, the coupling effect of the first scan signal on the nodes in the pixel is smaller. Thus, even when the load on the clock line transmitting the clock signal fluctuates, such as when the load decreases, it is ensured that the coupling effect of the first scan signal on the nodes will not significantly change the potential of the nodes, which is beneficial to the stability of the potential of the nodes in the pixel. This effectively improves the display unevenness problem caused by the load change of the clock line during a portion of the display time of a frame.

[0062] In an optional embodiment, the second preset duration may be greater than or equal to 600 ns and less than or equal to 700 ns.

[0063] For example, during at least a portion of the display time DF of a frame, the transition duration of the second voltage of the clock signal along J2 can be a second preset duration plus 50-100ns, and the transition duration of the second voltage of the clock signal along J2 can be 650-800ns.

[0064] In another optional embodiment, the second preset duration is greater than or equal to 26% of the duration of the effective level of the clock signal, and less than or equal to 30% of the duration of the effective level of the clock signal.

[0065] In this application embodiment, the duration of the effective level is not limited. In an optional implementation, the duration of the effective level can be determined by amplifying the waveform and manually or automatically acquiring the duration during which the potential of the clock signal is within ±5% of the effective level.

[0066] For example, the effective level duration of a typical clock signal can be around 2300ns. 26% of 2300ns is approximately 600ns, and 30% of 2300ns is approximately 700ns. That is, the second preset duration can be greater than or equal to 600ns and less than or equal to 700ns. However, the effective level duration of the clock signal is not limited to 2300ns. For example, when the effective level duration of the clock signal is around 3000ns, the second preset duration can be greater than or equal to 780ns and less than or equal to 900ns.

[0067] In another alternative embodiment, during at least a portion of the display time of a frame, the thrust of the second voltage of the clock signal along J2 is less than the first preset thrust.

[0068] The thrust along the second voltage edge J2 can refer to the output power or charging current of the driver chip (not shown in the figure) or clock controller (not shown in the figure) providing the clock signal when the clock signal transitions from an active level to an inactive level. A greater thrust along the second voltage edge J2 allows the clock line CL, which transmits the clock signal, to handle a larger load, resulting in a smaller signal delay caused by the load. Conversely, a smaller thrust along the second voltage edge J2 results in a smaller load that the clock line CL, which transmits the clock signal, can handle, leading to a greater signal delay caused by the load.

[0069] The first preset thrust can be the maximum thrust of the second voltage edge J2 of the clock signal during the display time DF of one frame. During a portion of the display time DF of one frame, the thrust of the second voltage edge J2 of the clock signal (CK1, XCK1) can be less than the thrust of the second voltage edge J2 during other periods. Alternatively, the first preset thrust can also be the conventional thrust of the second voltage edge of the clock signal (CK1, XCK1) in related technologies. In an optional embodiment, the first preset thrust can also be the thrust of the first initial signal STV1 received by the first shift register unit of the first stage.

[0070] By reducing the thrust of the second voltage line J2 of the clock signal during at least a portion of the display time of a frame, making the thrust of the second voltage line J2 of the clock signal less than the first preset thrust, the signal delay is larger. Under the same load, the speed at which the first scan signal Scan1 transitions from an effective level to an ineffective level can be reduced. This avoids the parasitic capacitive coupling that affects the potential of nodes in the pixel due to the reduced load on the clock line CL and the excessively rapid transition of the first scan signal Scan1 during a portion of the display time. This is beneficial to the stability of the potential of nodes in the pixel, thereby effectively improving the display unevenness problem caused by the load change of the clock line during a portion of the display time of a frame.

[0071] In another optional embodiment, FIG4 is a structural schematic diagram and timing schematic diagram of another driving circuit provided in the present application embodiment. Referring to FIG4, during at least a portion of the display time DF of a frame, the second voltage edge J2 of the clock signal (CK1, XCK1) includes at least two second sub-voltage edges J02.

[0072] Wherein, the second sub-voltage is the process of the clock signal transitioning from the first sub-level to the second sub-level along J02; the first sub-level and / or the second sub-level is located between the invalid level and the valid level; the absolute value of the difference between the first sub-level and the valid level is less than the absolute value of the difference between the second sub-level and the valid level; the absolute value of the difference between the second sub-level and the invalid level is less than the absolute value of the difference between the first sub-level and the invalid level.

[0073] For example, the second voltage edge is divided into multiple second sub-voltage edges J02, allowing the clock signals (CK1, XCK1) to transition from an active level to an inactive level in a step-by-step manner. When the active level is low, the first sub-level is lower than the second sub-level, wherein the first sub-level is greater than or equal to the active level, and the second sub-level is less than or equal to the inactive level, but they are not simultaneously equal; at least one is located between the active and inactive levels. When the active level is high, the first sub-level is greater than the second sub-level, wherein the first sub-level is less than or equal to the active level, and the second sub-level is greater than or equal to the inactive level, but they are not simultaneously equal; at least one is located between the active and inactive levels. By setting the transition of the clock signals (CK1, XCK1) from an active level to an inactive level in a step-by-step manner, the transition duration of the second voltage edge of the clock signals (CK1, XCK1) can be increased, reducing parasitic capacitive coupling caused by excessively rapid signal transitions, thereby improving the problem of uneven display.

[0074] In another optional embodiment, FIG5 is a structural schematic diagram and timing schematic diagram of another driving circuit provided in the present application embodiment. Referring to FIG5, during at least a portion of the display time DF of a frame, the transition duration of the first voltage of the clock signal (CK1, XCK1) along J1 is greater than or equal to the first preset duration.

[0075] The first preset duration can be the shortest transition duration of the first voltage edge of the clock signal (CK1, XCK1) along J1 during the display time DF of a frame. During a certain period of the display time DF of a frame, the transition duration of the first voltage edge of the clock signal (CK1, XCK1) along J1 can be greater than the transition duration of the first voltage edge of J1 during other periods. Alternatively, the first preset duration can also be the normal transition duration of the first voltage edge of the clock signal (CK1, XCK1) in the related art. For example, if the normal transition duration of the first voltage edge of the clock signal (CK1, XCK1) in the related art is 600ns, then the first preset duration can be 600ns. If the normal transition duration of the first voltage edge of the clock signal (CK1, XCK1) in the related art is 500-600ns, then the first preset duration can be 500-600ns. In an optional embodiment, during at least a portion of the display time DF of a frame, the transition duration of the first voltage edge J1 of the clock signal (CK1, XCK1) can be 600-650ns.

[0076] By setting the transition duration of the first voltage of the clock signal along J1 to be greater than or equal to a first preset duration for at least a portion of the display time DF of a frame, on the one hand, the transition speed of the first scan signal Scan1 from an invalid level to an effective level can be reduced, and the load fluctuation on the clock line CL transmitting the clock signal can be reduced. For example, when the load decreases, the coupling effect on the nodes in pixel P is reduced, which is beneficial to the stability of the potential of the nodes in pixel P and improves the problem of uneven display. On the other hand, by increasing the transition duration of the first voltage of the clock signal along J1 for at least a portion of the time, the thrust of the first voltage of the clock signal along J1 can be reduced, which is beneficial to reducing the power consumption of the display panel O1.

[0077] Based on the above embodiments, the first preset duration is less than the second preset duration.

[0078] During at least a portion of the display time DF of a single frame, the transition duration of the first voltage edge J1 of the clock signal is less than or equal to the transition duration of the second voltage edge J2. Without affecting the display effect, setting a shorter transition duration of the first voltage edge J1 helps to increase the effective duration of the clock signal, thereby increasing the effective duration of the effective pulse of the first scan signal Scan1 and improving the signal charging rate.

[0079] Based on the above embodiments, FIG6 is a schematic diagram of the structure of another display panel provided in the present application. The display panel 01 includes a first pixel row PR1 and a second pixel row PR2 arranged alternately along the second direction Y. Adjacent first pixel rows PR1 and second pixel rows PR2 form a pixel row group; the pixels P in the same pixel row group can receive the same first pixel Scan1.

[0080] For example, the first scan signal Scan1 can control the switching device in pixel P. When the first scan signal Scan1 is active, the same initialization signal, the same compensation signal, the same reset signal, or the same bias signal can be transmitted simultaneously to multiple pixels P in the same pixel row group; or, when the first scan signal Scan1 is active, different data signals can be transmitted to multiple pixels P in the same pixel row group. When the first scan signal Scan1 is set to control the switching device in pixel P used to transmit data signals, each column of pixels P can be electrically connected to two data lines DL, one of which is set to transmit the data signal of pixel P in the first pixel row PR1 of that column, and the other data line DL is set to transmit the data signal of pixel P in the second pixel row PR2 of that column.

[0081] By setting pixels P in the same pixel row group to receive the same first pixel Scan1, on the one hand, the effective duration of the first scan signal Scan1 can be increased, thereby increasing the time for the signal to be written to pixel P when the switching device is turned on, ensuring that the signal can be accurately written to pixel P, which is beneficial to improving the signal charging rate and realizing high-frequency driving; on the other hand, the number of first scan signals Scan1 required in the display panel can be reduced, that is, the number of first shift register units 22 in the first shift register 21 can be reduced. In this way, the number of first shift registers 21 electrically connected to the clock line CL can be reduced, which is beneficial to reducing the load and realizing high-resolution driving.

[0082] Optionally, during the display time of one frame, the first scan signal includes a data write pulse and at least one virtual write pulse; the data write pulse of the first scan signal Scan1(i) output by a portion of the first shift register unit overlaps with the virtual write pulse of the first scan signal Scan1(j) output by other first shift register units, where i and j are both positive integers less than or equal to N, and i≠j.

[0083] For example, the first scan signal can be configured to control the switching device in the pixel used to transmit data signals. During the display time of one frame, the first shift register unit can output at least two valid pulses of the first scan signal, one of which is a data write pulse, and the other is a virtual write pulse. During the valid time of the data write pulse of the first scan signal Scan1(i), the driving transistors of some pixels can write data signals corresponding to the grayscale, such as the data signal of the current row, so that the light-emitting element in the pixel can display the corresponding grayscale; during the virtual write pulse stage of the first scan signal Scan1(i), the driving transistors of some pixels can write data signals that do not correspond to the grayscale, such as the data signals of other rows, which can clear the data signals written to the pixel before this, thereby avoiding the driving transistors in the pixel from being in a certain state for a long time, affecting the performance of the driving transistors. In an optional embodiment, there is no need to set additional bias transistors, nor is there a need to set additional bias signals and bias control signals, which is beneficial to reduce the pixel size and improve the resolution.

[0084] During the display time of a frame, the virtual write pulse of the same first scan signal can be located before or after the data write pulse. This application embodiment does not limit this.

[0085] For example, pixel P includes pixel circuit 11 and light-emitting element LED. Pixel circuit 11 can be any combination of pixel circuits known in the related art. For example, pixel circuit 11 can be a 2T1C circuit, as shown in FIG7; or pixel circuit 11 can also be a 7T1C circuit, as shown in FIG8. In this case, pixel circuit 11 can include a first light-emitting control transistor M1, an initialization transistor M4, a compensation transistor M5, a second light-emitting control transistor M6, a reset transistor M7, a write transistor M2, a drive transistor M3, and a storage capacitor C.

[0086] Taking the pixel circuit 11 as an example, as shown in Figure 8 (7T1C circuit), Figure 9 is a schematic diagram of another display panel structure provided in this application embodiment. Referring to Figures 8 and 9, the pixel circuits 11 arranged in rows along the first direction X can be electrically connected to the same first scan line SL1. The i-th first scan line SL1 can transmit a first scan signal Scan1(i) to the pixel circuits 11 in the i-th row to control the write transistor M2 and the compensation transistor M5 of the pixel circuits 11 in the i-th row. The display panel 01 also includes multiple data lines DL. The pixel circuits 11 arranged in columns along the second direction Y can be electrically connected to the same data line DL, wherein the second direction Y intersects with the first direction X. When the first scan signal Scan1(i) transmitted by the i-th first scan line SL1 is at an effective level, the multiple data lines DL can transmit data signals data to the pixel circuits 11 located in the i-th row but in different columns.

[0087] The display panel 01 may also include multiple second scan lines SL2 and multiple light emission control lines EL. The driving circuit 20 may also include a second shift register and a third shift register (not shown in the figure). The second shift register includes N cascaded second shift register units, and the third shift register includes N cascaded third shift register units. The second shift register units are electrically connected to the second scan lines SL2, and the third shift register units are electrically connected to the light emission control lines EL (not shown in the figure). The pixel circuits 11 arranged in X rows along the first direction may be electrically connected to the same second scan line SL2 and the same light emission control line EL. The i-th second scan line SL2 may transmit a second scan signal Scan2(i) to the i-th row pixel circuit 11 to control the initialization transistor M4 and the reset transistor M7 of the i-th row pixel circuit 11; the i-th light emission control line EL may transmit a light emission control signal Emit(i) to the i-th row pixel circuit 11 to control the first light emission control transistor M1 and the second light emission control transistor M6 of the i-th row pixel circuit 11.

[0088] Taking the pixel circuit 11 as the 7T1C circuit shown in Figure 8, the first scan signal includes a data write pulse and a virtual write pulse, and the virtual write pulse is located before the data write pulse. For example, Figure 10 is a timing diagram of a pixel circuit provided in an embodiment of this application. Referring to Figures 8-10, during the display time of one frame, the pixel circuit 11 includes a bias stage t0, an initialization stage t1, a write stage t2, a reset stage tf, and an emission stage t3.

[0089] The biasing stage t0 can be located before the initialization stage t1, the writing stage t2, and the light emission stage t3. In this stage, the virtual writing pulse S0 of the first scan signal Scan1(i) can control the writing transistor M2 to turn on, transmitting the data signals of other row pixels P to the driving transistor M3 of the current row pixel P, thereby eliminating the data signals written by the current row pixel P in the previous writing stage. In this stage, the virtual writing pulse S0 can also control the compensation transistor M5 to turn on, transmitting the data signals of other row pixels P to the gate of the driving transistor M3 of the current row pixel P. This can prevent the gate of the driving transistor M3 of the current row pixel P from being at a certain potential for a long time during continuous display of the image, thus affecting the performance of the driving transistor M3.

[0090] The initialization stage t1 is located before the writing stage t2. In this stage, the second scan signal Scan2(i) can control the initialization transistor M4 to turn on, transmit the initialization signal vref1 to the gate of the driving transistor M3, and control the driving transistor M3 to turn on, which is beneficial for the subsequent writing stage t2 to write the data signal data to the gate of the driving transistor M3.

[0091] The writing stage t2 is located after the initialization stage t1 and before the light emission stage t3. In this stage, the data writing pulse S1 of the first scan signal Scan1(i) can control the writing transistor M2 to turn on, transmitting the data signal data of the pixel circuit 11 in this row to the driving transistor M3 of the pixel circuit 11 in this row. At the same time, the data writing pulse S1 can also control the compensation transistor M5 to turn on, transmitting the data signal data to the gate of the driving transistor M3 in this row of pixel circuit 11 and compensating the threshold voltage of the driving transistor M3.

[0092] The reset phase tf is located before the light emission phase t3. During this phase, the first scan signal Scan1(i) or the second scan signal Scan2(i) can control the reset transistor M7 to transmit the reset signal to the light emission element LED, clearing the residual electrical signal in the light emission element LED.

[0093] The light-emitting stage t3 is located after the initialization stage t1, the writing stage t2, and the reset stage t3. In this stage, the first scan signal Scan1(i) and the second scan signal Scan2(i) are both at invalid levels. The storage capacitor C stores the data signal. The light-emitting control signal Emit(i) can control the first light-emitting control transistor M1 to turn on, transmitting the first power signal PVDD to the driving transistor M3. The light-emitting control signal Emit(i) can also control the second light-emitting control transistor M6 to turn on, controlling the driving transistor M3 to provide driving current to the light-emitting element LED. The driving current corresponds to the data signal stored in the storage capacitor C. The light-emitting element LED also receives the second power signal PVEE to form a path in the light-emitting element LED. The light-emitting element LED can display light emission according to the data signal stored in the storage capacitor C.

[0094] By setting the transition duration of the second voltage of the clock signal along J2 to be greater than or equal to the second preset duration for at least a portion of the time period, the transition speed of at least a portion of the first scan signal Scan1 when it transitions from an effective level to an ineffective level can be reduced. This reduces the coupling effect of the first scan signal Scan1 on the node, such as the coupling to the gate potential of the driving transistor M3, which is beneficial to improving the stability of the gate potential of the driving transistor M3. This improves the accuracy of the data signal stored in the storage capacitor C, and thus enables the correct grayscale to be displayed when the light-emitting element LED emits light according to the data signal stored in the storage capacitor C. This effectively improves the problem of uneven display on the display panel O1.

[0095] The figure only illustrates, by way of example, that all transistors in pixel circuit 11 are P-type transistors. In other embodiments, at least some transistors in pixel circuit 11 may be N-type transistors. For P-type transistors, the P-type transistor is turned on when the signal received at its gate is low, and turned off when the signal received at its gate is high. Similarly, for N-type transistors, the N-type transistor is turned on when the signal received at its gate is high, and turned off when the signal received at its gate is low. For ease of description, the embodiments of this application use P-type transistors in pixel circuit 11 as an example to illustrate the technical solutions of the embodiments of this application.

[0096] The above is merely an exemplary description of the specific structure and driving principle of the pixels provided in the embodiments of this application. The structure and driving principle of the pixels in the embodiments of this application can be designed according to actual needs, and the embodiments of this application do not impose specific limitations on them. For ease of description, unless otherwise specified, the embodiments of this application all take the structure of the pixels shown in FIG8 as an example to illustrate the technical solutions of the embodiments of this application.

[0097] Optionally, Figure 11 is a structural schematic diagram and timing schematic diagram of another driving circuit provided in the embodiment of this application. Referring to Figure 11, the first scan signal Scan1 includes a data write pulse S1 and a virtual write pulse S0; the data write pulse S1 output by each first shift register unit 22 is shifted sequentially; during the display time DF of a frame, at least one virtual write pulse S0 of the same first scan signal Scan1 is located before the data write pulse S1. The display time DF of a frame includes a first refresh period TF1 and a second refresh period TF2; during the first refresh period TF1, the first shift register unit 22 of the first stage to the (X-1)th stage first shift register unit 22 sequentially outputs data write pulse S1; during the second refresh period TF2, the first shift register unit 22 of the Xth stage to the Nth stage first shift register unit 22 sequentially outputs data write pulse S1; N / 2 < X ≤ N, and X is an integer; at least during the second refresh period TF2, the transition duration of the second voltage of the clock signal (CK1, XCK1, CK2, XCK2) along J2 is greater than or equal to the second preset duration.

[0098] For example, referring to Figure 11, the first shift register 21 can receive the first clock signal CK1, the second clock signal XCK1, the third clock signal CK2, and the fourth clock signal XCK2. The first-stage first shift register unit 22 can receive the first initial signal STV1 as an input signal. The second-stage first shift register unit 22 can receive the second initial signal STV1 as an input signal. The i-th stage first shift register unit 22 of the subsequent stage can receive the first scan signal Scan1(i-2) output by the (i-2)-th stage first shift register unit 22 as an input signal. Here, i is a positive integer greater than 2 and less than or equal to N.

[0099] The first shift register unit 22 of the 4x+1 stage can output a valid pulse of the first clock signal CK1 as a valid pulse of the first scan signal Scan1(4x+1); the first shift register unit 22 of the 4x+2 stage can output a valid pulse of the third clock signal CK2 as a valid pulse of the first scan signal Scan1(4x+2); the first shift register unit 22 of the 4x+3 stage can output a valid pulse of the second clock signal XCK1 as a valid pulse of the first scan signal Scan1(4x+3); the first shift register unit 22 of the 4x+4 stage can output a valid pulse of the fourth clock signal XCK2 as a valid pulse of the first scan signal Scan1(4x+4); where x is a positive integer greater than or equal to 0.

[0100] Taking the display time DF of one frame as an example, the first shift register unit 22 can output three valid pulses of the first scan signal Scan1, and the first two valid pulses are virtual write pulses S0, and the third valid pulse is a data write pulse S1. Referring to Figure 11, X = N-7. From the first stage to the (X-1)th stage, the data write pulse S1 of the first scan signal Scan1(i) output by the first shift register unit 22 can overlap with the virtual write pulses S0 of two other first scan signals Scan1. Among them, the data write pulse S1 of the first scan signal Scan1(i) can overlap with the second virtual write pulse S0 of the first scan signal Scan1(i+4), and can also overlap with the first virtual write pulse S0 of the first scan signal Scan1(i+8). At this time, i is a positive integer less than X.

[0101] From level X to level N, the data write pulse S1 of the first scan signal Scan1(i) output by the first shift register unit 22 overlaps only with the virtual write pulse S0 of another first scan signal Scan1, or does not overlap with the virtual write pulse S0 of another first scan signal Scan1. In this case, a portion of the data write pulse S1 of the first scan signal Scan1(i) overlaps only with the second virtual write pulse S0 of the first scan signal Scan1(i+4), and another portion of the data write pulse S1 of the first scan signal Scan1(i) does not overlap with the virtual write pulse S0. In this case, i is an integer greater than or equal to X and less than or equal to N-4.

[0102] As can be seen from the above, during at least a portion of the first refresh period TF1, the number of first shift register units 22 whose effective times overlap and are connected to the same clock line CL and output the first scan signal Scan1 is a first number; during at least a portion of the second refresh period TF2, the number of first shift register units 22 whose effective times overlap and are connected to the same clock line CL and output the first scan signal Scan1 is a second number; the first number is greater than the second number.

[0103] Referring to Figure 11, from the first stage to the (X-1)th stage, the data write pulse S1 of the first scan signal Scan1 output by the first shift register unit 22 can overlap with two virtual write pulses S0. That is, during the first refresh period TF1, when data is written, the number of first shift register units 22 that control the same clock signal (CK1, XCK1, CK2 or XCK2) as the first scan signal Scan1 is relatively large, which will make the load on the clock signal line CL too large. As a result, when the effective pulse of the clock signal output by the first shift register unit 22 is used as the data write pulse S1 of the first scan signal Scan1, more signal delay will occur. This will cause the process of the data write pulse S1 of the first scan signal Scan1 changing from an effective level to an ineffective level to be slower. The coupling effect on some nodes in pixel P is also less obvious, which is beneficial to the stability of the potential of the nodes in pixel P.

[0104] From level X to level N, the number of virtual write pulses S0 overlapping with the data write pulses S1 of the first scan signal Scan1 output by the first shift register unit 22 begins to decrease. That is, during the second refresh period TF2, when data is written, the number of first shift register units 22 that control the same clock signal (CK1, XCK1, CK2 or XCK2) as the first scan signal Scan1 decreases. This will cause the load on the signal line CL of the transmission clock signal (CK1, XCK1, CK2 or XCK2) to be smaller, resulting in less signal delay when the effective pulses of the clock signal (CK1, XCK1) output by the first shift register unit 22 are output as the data write pulses S1 of the first scan signal Scan1.

[0105] By setting the transition duration of the second voltage of the clock signal along J2 to be greater than or equal to the second preset duration at least during the second refresh period TF2, the transition speed of the second voltage of the clock signal along J2 can be reduced. Thus, when the load on the clock line CL decreases, the transition process of the data write pulse S1 of the first scan signal Scan1 from the effective level to the ineffective level is also slower, thereby reducing the coupling effect of the first scan signal Scan1 on the node. This is beneficial for balancing the transition speed of the data write pulse S1 of multiple first scan signals Scan1 from the effective level to the ineffective level under different loads on the clock line CL during the display time DF of a frame, thereby improving the problem of uneven display on the display panel 01.

[0106] During the effective time of the virtual write pulse S0, the pixel P writes a data signal that does not correspond to the grayscale, such as data signals from other rows. This is only used to improve the performance of the driving transistor. That is, when the virtual write pulse S0 changes, there is a coupling effect on the node, which will not affect the data signal stored in the storage capacitor C. Therefore, the change process of the virtual write pulse S0 has little impact on the display grayscale of the light-emitting element LED. By setting the change duration of the second voltage of the clock signal (CK1, XCK1, CK2, XCK2) along J2 to be greater than or equal to the second preset duration at least during the second refresh period TF2, the process of the data write pulse S1 of the first scan signal Scan1 changing from the effective level to the ineffective level can be improved, which can effectively improve the problem of uneven display.

[0107] In an optional embodiment, FIG12 is a structural schematic diagram and timing schematic diagram of another driving circuit provided in the present application embodiment. Referring to FIG12, during at least a portion of the first refresh period TF1, the transition duration of the second voltage of the clock signal (CK1, XCK1, CK2, XCK2) along J2 is the first transition duration Δt1; during the second refresh period TF2, the transition duration of the second voltage of the clock signal (CK1, XCK1, CK2, XCK2) along J2 is the second transition duration Δt2; the second transition duration Δt2 is greater than the first transition duration Δt1.

[0108] For example, during the first refresh period TF1, the load on the clock line CL is relatively large, which makes the transition process of the first scan signal Scan1 from the valid level to the invalid level slower, resulting in less coupling to the node of the driving transistor M3; during the second refresh period TF2, the load on the clock line CL is relatively small, requiring an increase in the transition time of the second voltage of the clock signals (CK1, XCK1, CK2, XCK2) along J2, which also makes the transition process of the first scan signal Scan1 from the valid level to the invalid level slower, in order to reduce the coupling to the node of the driving transistor M3.

[0109] Therefore, during at least a portion of the first refresh period TF1, it is not necessary to increase the first transition duration Δt1 of the second voltage of the clock signals (CK1, XCK1, CK2, XCK2) along J2. Alternatively, the first transition duration Δt1 of the second voltage of the clock signals (CK1, XCK1, CK2, XCK2) along J2 can be slightly increased, making the first transition duration Δt1 shorter than the second transition duration Δt2. Without affecting the display effect, setting a shorter first transition duration Δt1 helps to increase the effective duration of the clock signals (CK1, XCK1, CK2, XCK2), thereby increasing the effective duration of the data write pulse S1 of the first scan signal Scan1 and improving the charging rate of the data signal.

[0110] In another alternative embodiment, continuing to refer to FIG12, the second refresh period TF2 includes a first sub-refresh phase TF01 and a second sub-refresh phase TF02; the first sub-refresh phase TF01 is located before the second sub-refresh phase TF02; in the first sub-refresh phase TF01, the transition duration of the second voltage of the clock signals (CK1, XCK1, CK2, XCK2) along J2 is the third transition duration Δt3; in the second sub-refresh phase TF02, the transition duration of the second voltage of the clock signals (CK1, XCK1, CK2, XCK2) along J2 is the fourth transition duration Δt4; the third transition duration Δt3 is less than or equal to the fourth transition duration Δt4.

[0111] For example, taking the display time DF of one frame as an example, the first shift register unit 22 can output three valid pulses of the first scan signal Scan1, and the first two valid pulses are virtual write pulses S0, and the third valid pulse is a data write pulse S1. Referring to Figure 12, in the first sub-refresh stage TF01, the data write pulse S1 of the first scan signal Scan1 output by the first shift register unit 22 overlaps only with the virtual write pulse S0 of another first scan signal Scan1; in the second sub-refresh stage TF02, the data write pulse S1 of the first scan signal Scan1 output by the first shift register unit 22 does not overlap with the virtual write pulse S0 of other first scan signals Scan1.

[0112] Referring again to Figure 12, from the first refresh period TF1 to the first sub-refresh stage TF01, the number of first shift register units 22 whose effective times overlap and are connected to the same clock line CL decreases (from three to two); from the first sub-refresh stage TF01 to the second sub-refresh stage TF02, the number of first shift register units 22 whose effective times overlap and are connected to the same clock line CL also decreases (from two to one). Therefore, the load on the clock line CL gradually decreases from the first refresh period TF1 to the first sub-refresh stage TF01, and from the first sub-refresh stage TF01 to the second sub-refresh stage TF02.

[0113] In addition, in some embodiments, from the first refresh period TF1 to the second refresh period TF2, and from the first sub-refresh stage TF01 to the second sub-refresh stage TF02, the distance between the first shift register unit 22, which is configured to output the first scan signal Scan1, and the driver chip (not shown in the figure) or clock controller (not shown in the figure), which is configured to output clock signals (CK1, XCK1, CK2, XCK2), also gradually decreases.

[0114] The reduced load on the clock line CL and the reduced distance between the first shift register unit 22 and the driver chip (not shown in the figure) or clock controller (not shown in the figure) will both reduce the signal delay of the clock signal output by the first shift register unit 22 as the first scan signal Scan1. By setting the third transition duration Δt3 to be less than or equal to the fourth transition duration Δt4, the transition speed of the data write pulses S1 of multiple first scan signals Scan1 from the effective level to the ineffective level in the display time DF of a frame can be balanced. It is also beneficial to increase the effective duration of the clock signal, thereby increasing the effective duration of the data write pulses S1 of the first scan signal Scan1 and improving the charging rate of the data signal.

[0115] In another alternative embodiment, the driving circuit 20 includes M clock lines; M≥2, and M is an even number; during the display time DF of a frame, for the same first scan signal Scan1, Q virtual write pulses S0 are located before the data write pulse S1; Q≥1, and Q is an integer; N / 2<X≤N+1-Q×M.

[0116] For example, Figure 13 is a structural schematic diagram and timing schematic diagram of another driving circuit provided in an embodiment of this application. Referring to Figures 11-13, when M=4 and Q=2, from the N-7th stage to the Nth stage, the number of first shift register units 22 whose effective times overlap and are connected to the same clock line CL is reduced compared to before, and the load of the clock line CL is also reduced compared to before. N / 2 < X ≤ N-7 makes the second refresh period TF2 include at least the output of the first shift register units 22 from the N-7th stage to the Nth stage. The first scan signal Scan1 outputs a data write pulse S1. When M=6 and Q=2, from level N-11 to level N, the number of first shift register units 22 connected to the same clock line CL and whose effective times overlap is reduced compared to before, and the load on clock line CL is also reduced compared to before. N / 2 < X ≤ N-11 ensures that the second refresh period TF2 includes at least the data write pulse S1 of the first scan signal Scan1 output by the first shift register unit 22 from level N-11 to level N. It is understood that the number M of clock lines CL connected to the first shift register 21 of the driving circuit 20 can also be other integers, and the number Q of virtual write pulses S0 located before the data write pulse S1 for the same first scan signal Scan1 can also be other integers. This application embodiment will not describe them one by one.

[0117] By setting the transition duration of the second voltage of the clock signal along J2 to be greater than or equal to the second preset duration in the second refresh period TF2, and N / 2<X≤N+1-Q×M, it can be ensured that the transition duration of the second voltage of the clock signal along J2 is increased at least when the load of the clock line CL is small, so as to balance the transition speed of the data writing pulse S1 of multiple first scan signals Scan1 from the effective level to the ineffective level under different loads of the clock line CL, thereby improving the problem of uneven display of the display panel 01.

[0118] Based on the above embodiment, Q = 2; in the first sub-refresh stage TF01, the first shift register unit 22 of the Xth stage to the first shift register unit 22 of the NMth stage sequentially outputs data write pulse S1; in the second sub-refresh stage TF02, the first shift register unit 22 of the N-M+1th stage to the first shift register unit 22 of the Nth stage sequentially outputs data write pulse S1; the third transition duration Δt3 is less than the fourth transition duration Δt4.

[0119] For example, referring to Figures 11-13, when M=4, from level N-7 to level N-4, the number of first shift register units 22 with overlapping effective times of the first scan signal Scan1 connected to the same clock line CL is 2. From level N-3 to level N, the number of first shift register units 22 with overlapping effective times of the first scan signal Scan1 connected to the same clock line CL is 1. During at least a portion of the time period of the first sub-refresh stage TF01, the load of clock line CL is less than the load of clock line CL during at least a portion of the time period of the first sub-refresh stage TF01.

[0120] When M=6, from level N-11 to level N-6, the number of first shift register units 22 with overlapping effective times of the first scan signal Scan1 connected to the same clock line CL is 2. From level N-5 to level N, the number of first shift register units 22 with overlapping effective times of the first scan signal Scan1 connected to the same clock line CL is 1. During at least a portion of the time period of the first sub-refresh stage TF01, the load of clock line CL is less than the load of clock line CL during at least a portion of the time period of the first sub-refresh stage TF01.

[0121] By setting the first sub-refresh stage TF01 to include the data write pulse S1 output by the first shift register unit 22 from the Xth to the NMth stage, and the second sub-refresh stage TF02 to include the data write pulse S1 output by the first shift register unit 22 from the N-M+1th stage to the Nth stage, and setting the third transition duration Δt3 to be less than the fourth transition duration Δt4, the transition speed of the data write pulse S1 of multiple first scan signals Scan1 from the effective level to the ineffective level under different loads of the clock line CL can be balanced. It also helps to increase the effective duration of the clock signal, thereby increasing the effective duration of the data write pulse S1 of the first scan signal Scan1 and improving the charging rate of the data signal.

[0122] In another optional embodiment, the display panel further includes a plurality of second scan lines; at least some pixels located in the same row are electrically connected to the same second scan line; the second scan line is configured to transmit a second scan signal; the second scan line corresponds one-to-one with the first scan line, and at least some pixels located in the same row are simultaneously electrically connected to the corresponding second scan line and the first scan line; the s-th first scan line corresponds to the s-th second scan line; the s-th first scan line is electrically connected to the (s+k)-th second scan line; 1≤s≤Nk, 1≤k≤Ns, and s and k are both integers; where X=NQ×M-k+1.

[0123] For example, Figure 14 is a schematic diagram of the structure and timing of another driving circuit provided in an embodiment of this application. Referring to Figure 14, k=2. From the first stage to the (N-2)th stage, the first shift register unit 22(s) is simultaneously electrically connected to the s-th first scan line SL1 and the (s+2)-th second scan line SL2. The first shift register units 22 from the first stage to the (N-2)th stage are all electrically connected to two scan lines (SL1 and SL2). The load of the first shift register units 22 from the first stage to the (N-2)th stage is the same. From the (N-1)th stage to the Nth stage, the first shift register unit 22 is all electrically connected to one first scan line SL1. The load of the first shift register units 22 from the (N-1)th stage to the Nth stage is the same, and the load of the first shift register units 22 from the (N-1)th stage to the Nth stage is less than the load of the first shift register units 22 from the first stage to the (N-2)th stage.

[0124] Taking k=2, M=6, Q=2 as an example, X=N-13, starting from the (N-13th)th stage to the Nth stage, the data write pulse S1 output by the first shift register unit 22 begins to overlap with the virtual write pulse S0 output by the first shift register unit 22 from the (N-1th)th stage to the Nth stage, and / or, the number of virtual write pulses S0 overlapping with the data write pulse S1 output by the first shift register unit 22 decreases, thus reducing the load on the clock line CL. X=N-13 makes the second refresh period TF2 include the (N-13th)th stage. The data write pulse S1 of the first scan signal Scan1 output by the first shift register unit 22 of the Nth stage, during the second refresh period TF2, the transition duration of the second voltage of the clock signals (CK1, XCK1, CK2, XCK2, CK3, XCK3) along J2 is greater than or equal to the second preset duration. This can balance the transition speed of the data write pulses S1 of multiple first scan signals Scan1 from the effective level to the ineffective level under different loads of the clock line CL, thereby improving the problem of uneven display on the display panel 01. Here, k can also be other integers, which will not be described in detail in this embodiment.

[0125] Based on the above embodiment, Q = 2; the second refresh period TF2 includes a first sub-stage t01, a second sub-stage t02, a third sub-stage t03, a fourth sub-stage t04, and a fifth sub-stage t05; in the first sub-stage t01, the Xth level first shift register unit 22 to the N-2×Mth level first shift register unit 22 sequentially outputs data write pulse S1; in the second sub-stage t02, the N-2×M+1th level first shift register unit 22 to the NMkth level first shift register unit 22 sequentially outputs... Data write pulse S1; in the third sub-stage t03, the first shift register unit 22 of the N-M+1-k stage to the first shift register unit 22 of the NM stage sequentially outputs data write pulse S1; in the fourth sub-stage t04, the first shift register unit 22 of the N-M+1 stage to the first shift register unit 22 of the Nk stage sequentially outputs data write pulse S1; in the fifth sub-stage t05, the first shift register unit 22 of the N-k+1 stage to the first shift register unit 22 of the N stage sequentially outputs data write pulse S1.

[0126] In the a-th stage, the transition duration of the second voltage edge J2 of the clock signal is the fifth transition duration; in the b-th refresh stage, the transition duration of the second voltage edge of the clock signal is the sixth transition duration; 1≤a<b≤5, and a and b are both integers; wherein, the fifth transition duration is less than the sixth transition duration.

[0127] For example, taking k=2, M=6, X=NQ×M-k+1=N-13 as an example, continuing to refer to Figure 14, in the first sub-stage t01, the first shift register unit 22 of the N-13th stage to the N-12th stage outputs data write pulse S1 in sequence; in the first sub-stage t01, the data write pulse S1 output by the first shift register unit 22 overlaps with the virtual write pulse S0 output by the first shift register unit 22 of the N-1th stage to the Nth stage. The load of the first shift register unit 22 of the N-1th stage to the Nth stage is less than the load of other first shift register units 22. Therefore, in the first sub-stage t01, the load of the clock line CL is less than the load of the clock line CL in the first refresh period TF1.

[0128] In the second sub-stage t02, the first shift register unit 22 of the N-11th stage to the N-8th stage sequentially outputs data write pulse S1. In the second sub-stage t02, the data write pulse S1 output by the first shift register unit 22 overlaps with the virtual write pulse S0 output by another first shift register unit 22. The number of virtual write pulses S0 overlapping with the data write pulse S1 output by the first shift register unit 22 decreases. Therefore, in the second sub-stage t02, the load on the clock line CL is less than that in the first sub-stage t01.

[0129] In the third sub-stage t03, the first shift register unit 22 of the N-7th stage to the N-6th stage sequentially outputs data write pulse S1; in the third sub-stage t03, the data write pulse S1 output by the first shift register unit 22 overlaps with a virtual write pulse S0 output by the first shift register unit 22 of the N-1th stage to the Nth stage. Therefore, in the third sub-stage t03, the load on the clock line CL is less than that in the second sub-stage t02.

[0130] In the fourth sub-stage t04, the first shift register unit 22 of the N-5th stage to the first shift register unit 22 of the N-2th stage sequentially outputs data write pulse S1; in the fourth sub-stage t04, the data write pulse S1 output by the first shift register unit 22 does not overlap with the virtual write pulse S0 output by other first shift register units 22, and the number of virtual write pulses S0 overlapping with the data write pulse S1 output by the first shift register unit 22 is reduced. Therefore, in the fourth sub-stage t04, the load of the clock line CL is less than that in the third sub-stage t03.

[0131] In the fifth sub-stage t05, the first shift register unit 22 of the N-1th stage to the first shift register unit 22 of the Nth stage sequentially outputs data write pulse S1. In the fifth sub-stage t05, the data write pulse S1 output by the first shift register unit 22 does not overlap with the virtual write pulse S0 output by other first shift register units 22, and the load of the first shift register unit 22 that outputs data write pulse S1 is less than the load of other first shift register units 22. Therefore, in the fifth sub-stage t05, the load of the clock line CL is less than the load of the clock line CL in the fourth sub-stage t04.

[0132] By setting the fifth transition duration to be less than the sixth transition duration, it can be achieved that in the first sub-stage t01, the transition duration of the second voltage edge J2 of the clock signal is less than the transition duration of the second voltage edge J2 of the clock signal in the second sub-stage t02; in the second sub-stage t02, the transition duration of the second voltage edge J2 of the clock signal is less than the transition duration of the second voltage edge J2 of the clock signal in the third sub-stage t03; and in the third sub-stage t03, the transition duration of the second voltage edge J2 of the clock signal is less than the transition duration of the second voltage edge J2 of the clock signal in the fourth sub-stage t04. In the fourth sub-stage t04, the transition duration of the second voltage of the clock signal along J2 is shorter than that in the fifth sub-stage t05. This allows for a more detailed division of the different loads on the clock line CL, which is beneficial for better balancing the transition speed of the data write pulses S1 of the multiple first scan signals Scan1 from the effective level to the ineffective level under different loads on the clock line CL. It also helps to increase the effective duration of the clock signal, thereby increasing the effective duration of the data write pulses S1 of the first scan signal Scan1 and improving the charging rate of the data signal.

[0133] Optionally, Figure 15 is a structural schematic diagram and timing schematic diagram of another driving circuit provided in the embodiment of this application. Referring to Figure 15, the first scan signal Scan1 includes a data write pulse S1 and a virtual write pulse S0; the data write pulse S1 output by each first shift register unit 22 is shifted sequentially; during the display time DF of a frame, at least one virtual write pulse S0 of the same first scan signal Scan1 is located after the data write pulse S1. The display time DF of a frame includes the third refresh period TF3 and the fourth refresh period TF4; during the third refresh period TF3, the first shift register unit 22 of the first stage to the first shift register unit 22 of the Zth stage sequentially outputs data write pulse S1; 1≤Z<N / 2, and Z is an integer; during the fourth refresh period TF4, the first shift register unit 22 of the Z+1th stage to the first shift register unit 22 of the Nth stage sequentially outputs data write pulse S1; at least during the third refresh period TF3, the transition duration of the second voltage of the clock signal (CK1, XCK1, CK2, XCK2) along J2 is greater than or equal to the second preset duration.

[0134] For example, taking the display time DF of one frame as an example, the first shift register unit 22 can output three valid pulses of the first scan signal Scan1, and the first valid pulse is a data write pulse S1, and the latter two valid pulses are virtual write pulses S0. Referring to Figure 15, Z=8. From the first level to the Zth level, the data write pulse S1 of the first scan signal Scan1(i) output by the first shift register unit 22 does not overlap with the virtual write pulse S0 of other first scan signals Scan1, or only overlaps with the virtual write pulse S0 of one other first scan signal Scan1. In this case, a part of the data write pulse S1 of the first scan signal Scan1(i) does not overlap with the virtual write pulse S0, and another part of the data write pulse S1 of the first scan signal Scan1(i) only overlaps with the second virtual write pulse S0 of the first scan signal Scan1(i-4). At this time, i is an integer greater than or equal to 5 and less than or equal to Z.

[0135] Starting from level Z+1 to level N, the data write pulse S1 of the first scan signal Scan1(i) output by the first shift register unit 22 can overlap with the virtual write pulse S0 of two other first scan signals Scan1. Specifically, the data write pulse S1 of the first scan signal Scan1(i) can overlap with the second virtual write pulse S0 of the first scan signal Scan1(i-4), and can also overlap with the first virtual write pulse S0 of the first scan signal Scan1(i-8). Here, i is an integer greater than or equal to Z+1 and less than or equal to N.

[0136] As can be seen from the above, during at least a portion of the third refresh period TF3, the number of first shift register units 22 whose effective times overlap and are connected to the same clock line CL and output the first scan signal Scan1 is the third number; during at least a portion of the fourth refresh period TF4, the number of first shift register units 22 whose effective times overlap and are connected to the same clock line CL and output the first scan signal Scan1 is the fourth number; the third number is greater than the fourth number.

[0137] Referring back to Figure 15, from level 1 to level Z, the number of overlapping virtual write pulses S0 of the data write pulse S1 of the first scan signal Scan1 output by the first shift register unit 22 is relatively small. That is, during the third refresh period TF3, when data is written, the number of first shift register units 22 controlling the same clock signal (CK1, XCK1, CK2, or XCK2) as the first scan signal Scan1 is relatively small, resulting in a lower load on the clock signal line CL. From level Z+1 to level N, the data write pulse S1 of the first scan signal Scan1 output by the first shift register unit 22 can overlap with two virtual write pulses S0. That is, during the fourth refresh period TF4, when data is written, the number of first shift register units 22 controlling the same clock signal (CK1, XCK1, CK2, or XCK2) as the first scan signal Scan1 is relatively large, resulting in a higher load on the clock signal line CL.

[0138] By setting the transition duration of the second voltage of the clock signal along J2 to be greater than or equal to the second preset duration at least during the third refresh period TF3, the transition speed of the second voltage of the clock signal along J2 can be reduced. This can balance the transition speed of the data writing pulses S1 of multiple first scan signals Scan1 from the effective level to the ineffective level under different loads of the clock line CL, thereby improving the problem of uneven display on the display panel 01.

[0139] In an optional embodiment, FIG16 is a structural schematic diagram and timing schematic diagram of another driving circuit provided in the present application embodiment. Referring to FIG16, during the third refresh period TF3, the transition duration of the second voltage of the clock signal (CK1, XCK1, CK2, XCK2) along J2 is the seventh transition duration △t7; during at least a portion of the fourth refresh period TF4, the transition duration of the second voltage of the clock signal (CK1, XCK1, CK2, XCK2) along J2 is the eighth transition duration △t8; the seventh transition duration △t7 is greater than the eighth transition duration △t8.

[0140] During the third refresh period TF3, the load on the clock line CL is relatively small. Therefore, it is necessary to increase the transition duration of the second voltage of the clock signals (CK1, XCK1, CK2, XCK2) along J2. This slows down the transition process of the first scan signal Scan1 from an active level to an inactive level, reducing the coupling effect on the node of the driving transistor M3. During at least a portion of the fourth refresh period TF4, it is not necessary to increase the eighth transition duration Δt8 of the second voltage of the clock signals (CK1, XCK1, CK2, XCK2) along J2. Alternatively, the eighth transition duration Δt8 of the second voltage of the clock signals (CK1, XCK1, CK2, XCK2) along J2 can be slightly increased, making the eighth transition duration Δt8 smaller than the seventh transition duration Δt7. This is beneficial for increasing the effective duration of the clock signals (CK1, XCK1, CK2, XCK2), thereby increasing the effective duration of the data write pulse S1 of the first scan signal Scan1 and improving the charging rate of the data signal.

[0141] In another optional embodiment, continuing to refer to FIG16, the third refresh period TF3 includes a third sub-refresh stage TF03 and a fourth sub-refresh stage TF04; the third sub-refresh stage TF03 is located before the fourth sub-refresh stage TF04; in the third sub-refresh stage TF03, the transition duration of the second voltage of the clock signals (CK1, XCK1, CK2, XCK2) along J2 is the ninth transition duration △t9; in the fourth sub-refresh stage TF04, the transition duration of the second voltage of the clock signals (CK1, XCK1, CK2, XCK2) along J2 is the tenth transition duration △t10; the ninth transition duration △t9 is greater than or equal to the tenth transition duration △t10.

[0142] For example, taking the display time DF of one frame as an example, the first shift register unit 22 can output three valid pulses of the first scan signal Scan1, and the first valid pulse is a data write pulse S1, and the latter two valid pulses are virtual write pulses S0. Referring to Figure 16, in the third sub-refresh stage TF03, the data write pulse S1 of the first scan signal Scan1 output by the first shift register unit 22 does not overlap with the virtual write pulse S0 of other first scan signals Scan1; in the fourth sub-refresh stage TF04, the data write pulse S1 of the first scan signal Scan1 output by the first shift register unit 22 overlaps only with the virtual write pulse S0 of another first scan signal Scan1.

[0143] Referring again to Figure 16, from the third sub-refresh stage TF03 to the fourth sub-refresh stage TF04, the number of first shift register units 22 connected to the same clock line CL and whose effective times overlap (from one to two) increases, and the load on the clock line CL increases; from the fourth sub-refresh stage TF04 to the fourth refresh stage TF4, the number of first shift register units 22 connected to the same clock line CL and whose effective times overlap (from two to three) also increases, and the load on the clock line CL increases.

[0144] Increased load on clock line CL leads to increased signal delay for the clock signal (CK1, XCK1, CK2, or XCK2) output by the first shift register unit 22 as the first scan signal Scan1. The transition speed of the data write pulse S1 of the first scan signal Scan1 from active to inactive level varies across different refresh periods, resulting in different coupling effects on nodes within the pixel. This causes varying degrees of deviation in the data signals stored in the storage capacitor C in different areas of the pixel circuit. By setting the ninth transition duration Δt9 to be greater than or equal to the tenth transition duration Δt10, the transition speed of the data write pulses S1 of multiple first scan signals Scan1 from active to inactive levels within the display time DF of a single frame can be balanced. This also helps to increase the effective duration of the clock signals (CK1, XCK1, CK2, XCK2), thereby increasing the effective duration of the data write pulse S1 of the first scan signal Scan1 and improving the charging rate of the data signal.

[0145] In another optional embodiment, the driving circuit 20 includes M clock lines; M≥2, and M is an even number; during the display time DF of a frame, for the same first scan signal Scan1, P virtual write pulses S0 are located after the data write pulse S1; P≥1, and P is an integer; P×M≤z<N / 2.

[0146] For example, Figure 17 is a structural schematic diagram and timing schematic diagram of another driving circuit provided in the embodiment of this application. Referring to Figures 15-17, when M=4 and P=2, the number of first shift register units 22 with overlapping effective times of the first scan signal Scan1 output by the first shift register units 22 connected to the same clock line CL from the 9th to the Nth stage increases compared to before, and the load of the clock line CL also increases compared to before. 8≤z<N / 2 makes the third refresh period TF3 include at least the data writing pulse S1 of the first scan signal Scan1 output by the first shift register units 22 from the first to the eighth stage. When M=6 and P=2, the number of first shift register units 22 with overlapping effective times of the first scan signal Scan1 output by the first shift register units 22 connected to the same clock line CL from the thirteenth to the Nth stage increases compared to before, and the load of the clock line CL also increases compared to before. 12≤z<N / 2 makes the third refresh period TF3 include at least the data writing pulse S1 of the first scan signal Scan1 output by the first shift register units 22 from the first to the eleventh stage. It is understood that the number M of clock lines CL connected to the first shift register 21 of the driving circuit 20 can also be other integers. Similarly, the number P of virtual write pulses S0 following the data write pulse S1 for the same first scan signal Scan1 can also be other integers. These will not be described in detail in the embodiments of this application.

[0147] By setting the transition duration of the second voltage of the clock signal along J2 to be greater than or equal to the second preset duration in the third refresh period TF3, and P×M≤z<N / 2, it can be ensured that the transition duration of the second voltage of the clock signal along J2 is increased at least when the load of the clock line CL is small, so as to balance the transition speed of the data writing pulse S1 of multiple first scan signals Scan1 from the effective level to the ineffective level under different loads of the clock line CL, thereby improving the problem of uneven display of the display panel 01.

[0148] Based on the above embodiment, P = 2; in the third sub-refresh stage TF03, the first shift register unit 22 of the first stage to the first shift register unit 22 of the Mth stage sequentially outputs data write pulse S1; in the fourth sub-refresh stage TF04, the first shift register unit 22 of the M+1th stage to the first shift register unit 22 of the 2×Mth stage sequentially outputs data write pulse S1; the ninth transition duration △t9 is greater than the tenth transition duration △t10.

[0149] For example, referring to Figures 15-17, when M=4, from the first stage to the fourth stage, the number of first shift register units 22 with overlapping effective times of the first scan signal Scan1 connected to the same clock line CL is 1. From the fifth stage to the eighth stage, the number of first shift register units 22 with overlapping effective times of the first scan signal Scan1 connected to the same clock line CL is 2. During at least a portion of the time period of the fourth sub-refresh stage TF04, the load of clock line CL is greater than the load of clock line CL during at least a portion of the time period of the third sub-refresh stage TF03.

[0150] When M=6, from the first stage to the sixth stage, the number of first shift register units 22 with overlapping effective times of the first scan signal Scan1 connected to the same clock line CL is 1. From the seventh stage to the twelfth stage, the number of first shift register units 22 with overlapping effective times of the first scan signal Scan1 connected to the same clock line CL is 2. During at least a portion of the fourth sub-refresh stage TF04, the load of clock line CL is greater than the load of clock line CL during at least a portion of the third sub-refresh stage TF03.

[0151] By setting the third sub-refresh stage TF03 to include the data write pulse S1 output by the first shift register unit 22 from the first stage to the Mth stage, and the fourth sub-refresh stage TF04 to include the data write pulse S1 output by the first shift register unit 22 from the M+1th stage to the 2×Mth stage, and setting the ninth transition duration △t9 to the tenth transition duration △t10, the transition speed of the data write pulse S1 of multiple first scan signals Scan1 from the effective level to the ineffective level under different loads of the clock line CL can be balanced. It is also beneficial to increase the effective duration of the clock signal, thereby increasing the effective duration of the data write pulse S1 of the first scan signal Scan1 and improving the charging rate of the data signal.

[0152] Optionally, the number of first shift register units 22 with overlapping effective times of the first scan signal Scan1 connected to the same clock line CL is less than or equal to 2.

[0153] For example, referring to Figure 17, for the display time DF of one frame, the first shift register unit 22 can output three valid pulses of the first scan signal Scan1. The first valid pulse is the data write pulse S1, and the latter two valid pulses are virtual write pulses S0. The number of first shift register units 22 connected to the same clock line CL and whose output first scan signal Scan1 has overlapping valid times is a maximum of 3 and a minimum of 1. The maximum difference in the load of the clock line CL is large, resulting in more cases where the load of the clock line CL is small. The refresh time of the uneven load of the clock line CL is also long, resulting in more areas where abnormal display brightness is likely to occur.

[0154] In an optional implementation, FIG18 is a structural schematic diagram and timing schematic diagram of another driving circuit provided in the embodiment of the present application. Referring to FIG18, during the display time DF of a frame, the first scan signal Scan1 includes a data write pulse S1 and a virtual write pulse S0.

[0155] For the display time DF of one frame, the first shift register unit 22 can output two valid pulses of the first scan signal Scan1. The first valid pulse is a data write pulse S1 and the second valid pulse is a virtual write pulse S0, or the first valid pulse is a virtual write pulse S0 and the second valid pulse is a data write pulse S1 (not shown in the figure). When the first shift register unit 22 outputs the data write pulse S1 in the first four stages or the last four stages (not shown in the figure), the number of first shift register units 22 connected to the same clock line CL and whose output first scan signal Scan1 has overlapping valid times is 1. When the first shift register unit 22 of other stages outputs the data write pulse S1, the number of first shift register units 22 connected to the same clock line CL and whose output first scan signal Scan1 has overlapping valid times is 2. The maximum difference in the load of the clock line CL is small, so the case where the load of the clock line CL is small is less frequent. The refresh time of the clock line CL with uneven load is shorter, and there are fewer areas where abnormal display brightness is likely to occur.

[0156] By setting the maximum number of first shift register units 22 whose effective times overlap with the first scan signal Scan1 output from the same clock line CL during the display time DF of a frame, the following advantages are achieved: Firstly, the load on clock line CL is relatively small, and the signal delay of the clock signal output by the first shift register unit 22 as the first scan signal Scan1 is also relatively small. Thus, the thrust of the voltage edge of the clock signal can be set to be relatively small, which is beneficial to reducing power consumption. Secondly, the maximum difference in the load variation of clock line CL can be reduced, and the situation where the load of clock line CL is relatively small can also be reduced, thereby shortening the refresh time of uneven load on clock line CL and reducing the area where abnormal display brightness is likely to occur. In addition, the period during which the transition time of the second voltage edge J needs to be increased can be shortened, thereby reducing the impact on the clock signal in other periods, which is beneficial to increasing the effective time of the clock signal and the effective time of the data write pulse S1 of the first scan signal Scan1, and improving the charging rate of the data signal.

[0157] Based on the above implementation, taking the pixel circuit 11 as the 7T1C circuit shown in Figure 8 as an example, during the display time DF of one frame, the first shift register unit 22 can output two valid pulses of the first scan signal Scan1, and the first valid pulse is the data write pulse S1 and the second valid pulse is the virtual write pulse S0. In an optional implementation, the virtual write pulse S0 can be located after the write stage t2 and after the light emission stage t3, as shown in Figure 19. After the pixel P displays and emits light, the bias of the driving transistor M3 is adjusted to improve the performance of the driving transistor M3.

[0158] In another alternative implementation, the virtual write pulse S0 can also be located after the write stage t2 and before the light emission stage t3, as shown in Figure 20. The bias adjustment of the driving transistor M3 is performed before the pixel P emits light for display. This implementation is suitable for cases where the compensation transistor M5 and the write transistor M2 receive different scan signals (not shown in the figure). During the effective time of the virtual write pulse S0, when the bias adjustment of the driving transistor M3 is performed before the pixel P emits light for display, the compensation transistor M5 needs to be turned off to prevent data signals of other rows used for bias adjustment from being written to the gate of the driving transistor M3 during the effective time of the virtual write pulse S0, thus affecting the display grayscale.

[0159] Optionally, during the display time DF of one frame, the first scan signal Scan1 includes a first virtual write pulse S01, a data write pulse S1, and a second virtual write pulse S02; wherein, during the display time DF of one frame, the data write pulse S1 is located between the first virtual write pulse S01 and the second virtual write pulse S02.

[0160] For example, Figure 21 is a schematic diagram of the structure and timing of another driving circuit provided in an embodiment of this application. Referring to Figure 21, the driving circuit 20 includes four clock lines CL. When the first shift register unit 22 outputs the data writing pulse S1, the number of first shift register units 22 connected to the same clock line CL and whose effective time overlaps with the output first scan signal Scan1 is at most 3 and at least 2. On the one hand, it can reduce the maximum difference in the load change of the clock line CL and reduce the situation where the load of the clock line CL is too small. Therefore, when increasing the transition duration of the second voltage along J2 of the clock signal during a portion of the display time DF of a frame, it is not necessary to increase it too much, which can reduce the impact on the effective duration and increase the charging rate of the data signal. It is also not necessary to design too much transition duration of the second voltage along J2 according to the situation where the load is too small, which can simplify the timing design. On the other hand, performing a bias adjustment before and after data writing can better adjust the state of the driving transistor, which is beneficial to extending the service life of the driving transistor and improving the display quality.

[0161] Based on the above embodiments, taking the pixel circuit 11 as the 7T1C circuit shown in FIG8 as an example, FIG22 is a timing diagram of another pixel circuit provided in the embodiment of this application. Referring to FIG22, the first virtual write pulse S01 can be located before the initialization stage t1, and the second virtual write pulse S02 can be located after the light emission stage t3. In this way, the bias adjustment of the driving transistor M3 can be performed before the pixel P is initialized, and the bias adjustment of the driving transistor M3 can be performed again after the pixel P displays light emission. This can prevent the driving transistor M3 of the pixel circuit 11 from being at a certain potential for a long time, which would affect the performance of the driving transistor M3.

[0162] In other embodiments, the second virtual write pulse S02 may also be located before the light emission stage t3, as shown in FIG23. Before pixel P emits light, the bias adjustment of the driving transistor M3 is performed again. This embodiment is applicable to the case where the compensation transistor M5 and the write transistor M2 receive different scan signals (not shown in the figure). During the effective time of the second virtual write pulse S02, when the bias adjustment of the driving transistor M3 is performed before pixel P emits light, the compensation transistor M5 needs to be turned off to avoid the data signals of other rows used for bias adjustment being written to the gate of the driving transistor M3 during the effective time of the second virtual write pulse S02, which would affect the display grayscale.

[0163] This application also provides a display device. FIG24 is a schematic diagram of the structure of a display device provided in this application embodiment. As shown in FIG24, the display device 02 includes a display panel 01 and a housing 03 provided in any embodiment of this application. The display device 02 provided in this application embodiment can be a mobile phone as shown in FIG24, or any electronic product with display function, including but not limited to the following categories: television, laptop, desktop monitor, tablet computer, digital camera, smart bracelet, smart glasses, vehicle display, medical device, industrial control equipment, touch interactive terminal, etc. This application embodiment does not make any special limitation in this regard.

Claims

1. A display panel, comprising: The driving circuit, multiple pixels arranged in an array, multiple first scan lines, and multiple clock lines; At least some of the pixels located in the same row are electrically connected to the same first scan line; The driving circuit is electrically connected to multiple first scan lines respectively; the driving circuit includes N cascaded first shift register units; the clock line is electrically connected to multiple first shift register units; the first shift register units are configured to receive at least an input signal and a clock signal on the clock line, and control the clock signal on the clock line to be provided to the first scan line as a first scan signal; The effective times of the first scan signals of at least a portion of the first shift register units connected to the same clock line overlap. The process of the clock signal transitioning from an invalid level to an effective level is the first voltage edge, and the process of transitioning from the effective level to the invalid level is the second voltage edge; During at least a portion of the display time of a frame, the transition duration of the second voltage edge of the clock signal is greater than or equal to a second preset duration.

2. The display panel according to claim 1, wherein, The second preset duration is greater than or equal to 600ns and less than or equal to 700ns.

3. The display panel according to claim 1, wherein, The second preset duration is greater than or equal to 26% of the duration of the effective level of the clock signal, and less than or equal to 30% of the duration of the effective level.

4. The display panel according to claim 1, wherein, During at least a portion of the display time of a frame, the second voltage edge of the clock signal includes at least two second sub-voltage edges; Wherein, the second sub-voltage edge is the process of the clock signal transitioning from the first sub-level to the second sub-level; at least one of the first sub-level and the second sub-level is located between the invalid level and the valid level; the absolute value of the difference between the first sub-level and the valid level is less than the absolute value of the difference between the second sub-level and the valid level; the absolute value of the difference between the second sub-level and the invalid level is less than the absolute value of the difference between the first sub-level and the invalid level.

5. The display panel according to claim 1, wherein, During at least a portion of the display time of a frame, the thrust of the second voltage edge of the clock signal is less than the first preset thrust.

6. The display panel according to claim 1, wherein, During the display time of one frame, the first scan signal includes a data write pulse and at least one virtual write pulse; The data write pulse of the first scan signal Scan1(i) output by a portion of the first shift register unit overlaps with the virtual write pulse of the first scan signal Scan1(j) output by other first shift register units, where i and j are both positive integers less than or equal to N, and i ≠ j.

7. The display panel according to claim 1, wherein, The first scan signal includes a data write pulse and a virtual write pulse; the data write pulse output by each stage of the first shift register unit is shifted sequentially; During the display time of one frame, at least one of the virtual write pulses of the same first scan signal is located before the data write pulse; The display time of a single frame includes the first refresh period and the second refresh period; During the first refresh period, the first shift register unit of the first stage to the (X-1)th stage first shift register unit sequentially outputs the data write pulse; During the second refresh period, the data write pulses are sequentially output from the first shift register unit of the Xth stage to the first shift register unit of the Nth stage; N / 2 < X ≤ N, and X is an integer; At least during the second refresh period, the transition duration of the second voltage edge of the clock signal is greater than or equal to the second preset duration.

8. The display panel according to claim 7, wherein, During at least a portion of the first refresh period, the number of first shift register units whose effective times overlap with the first scan signal output from the same clock line is a first number. During at least a portion of the second refresh period, the number of first shift register units whose effective times overlap with the first scan signal output from the same clock line is the second number. The first quantity is greater than the second quantity.

9. The display panel according to claim 7, wherein, During at least a portion of the first refresh period, the transition duration of the second voltage edge of the clock signal is the first transition duration; During the second refresh period, the transition duration of the second voltage edge of the clock signal is the second transition duration; The duration of the second transition is greater than the duration of the first transition.

10. The display panel according to claim 7, wherein, The second refresh period includes a first sub-refresh phase and a second sub-refresh phase; the first sub-refresh phase is located before the second sub-refresh phase; During the first sub-refresh phase, the transition duration of the second voltage edge of the clock signal is the third transition duration; During the second sub-refresh phase, the transition duration of the second voltage edge of the clock signal is the fourth transition duration; The duration of the third transition is less than or equal to the duration of the fourth transition.

11. The display panel according to claim 10, wherein, The driving circuit includes M clock lines; M≥2, and M is an even number; During the display time of one frame, for the same first scan signal, Q virtual write pulses are located before the data write pulse; Q ≥ 1, and Q is an integer; N / 2<X≤N+1-Q×M.

12. The display panel according to claim 11, wherein, Q＝2； During the first sub-refresh phase, the first shift register unit of the Xth stage to the first shift register unit of the NMth stage sequentially outputs the data write pulse; during the second sub-refresh phase, the first shift register unit of the N-M+1th stage to the first shift register unit of the Nth stage sequentially outputs the data write pulse. The duration of the third transition is less than the duration of the fourth transition.

13. The display panel of claim 11, further comprising a plurality of second scan lines; at least a portion of the pixels located in the same row are electrically connected to the same second scan line; the second scan line is configured to transmit a second scan signal; The second scan line corresponds one-to-one with the first scan line, and at least some of the pixels located in the same row are electrically connected to the corresponding second scan line and the first scan line; The s-th first scan line corresponds to the s-th second scan line; the s-th first scan line is electrically connected to the s+k-th second scan line; 1≤s≤Nk, 1≤k≤Ns, and s and k are both integers; in, X = NQ × M - k + 1.

14. The display panel according to claim 13, wherein, Q＝2； The second refresh period includes the first sub-phase, the second sub-phase, the third sub-phase, the fourth sub-phase, and the fifth sub-phase; In the first sub-stage, the data write pulses are sequentially output from the first shift register unit of the Xth stage to the first shift register unit of the N-2×Mth stage; In the second sub-stage, the first shift register unit of the N-2×M+1th stage to the first shift register unit of the NMkth stage sequentially outputs the data write pulse; In the third sub-stage, the first shift register unit of the N-M+1-kth stage to the first shift register unit of the NMth stage sequentially outputs the data write pulse; In the fourth sub-stage, the first shift register unit of the N-M+1th stage to the first shift register unit of the Nkth stage sequentially outputs the data write pulse; In the fifth sub-stage, the data write pulses are sequentially output from the first shift register unit of the N-k+1th stage to the first shift register unit of the Nth stage. In the a-th stage, the transition duration of the second voltage edge of the clock signal is the fifth transition duration; in the b-th refresh stage, the transition duration of the second voltage edge of the clock signal is the sixth transition duration; 1≤a<b≤5, and a and b are both integers; The duration of the fifth transition is shorter than the duration of the sixth transition.

15. The display panel according to claim 1, wherein, The first scan signal includes a data write pulse and a virtual write pulse; the data write pulse output by each stage of the first shift register unit is shifted sequentially; During the display time of one frame, at least one of the virtual write pulses of the same first scan signal is located after the data write pulse; The display time of one frame includes the third refresh period and the fourth refresh period; During the third refresh period, the data write pulses are sequentially output from the first shift register unit of the first stage to the first shift register unit of the Zth stage; 1≤Z<N / 2, and Z is an integer; During the fourth refresh period, the first shift register unit of the Z+1th stage to the first shift register unit of the Nth stage sequentially output the data write pulse; At least during the third refresh period, the transition duration of the second voltage edge of the clock signal is greater than or equal to the second preset duration.

16. The display panel according to claim 15, wherein, During at least a portion of the third refresh period, the number of first shift register units whose effective times overlap with the first scan signal output from the same clock line is the third number. During at least a portion of the fourth refresh period, the number of first shift register units whose effective times overlap with the first scan signal output from the same clock line is the fourth number. The third quantity is less than the fourth quantity.

17. The display panel according to claim 15, wherein, During the third refresh period, the transition duration of the second voltage edge of the clock signal is the seventh transition duration; During at least a portion of the fourth refresh period, the transition duration of the second voltage edge of the clock signal is the eighth transition duration; The duration of the seventh transition is greater than the duration of the eighth transition.

18. The display panel according to claim 15, wherein, The third refresh period includes a third sub-refresh phase and a fourth sub-refresh phase; the third sub-refresh phase is located before the fourth sub-refresh phase. In the third sub-refresh phase, the transition duration of the second voltage edge of the clock signal is the ninth transition duration; In the fourth sub-refresh stage, the transition duration of the second voltage edge of the clock signal is the tenth transition duration; The duration of the ninth transition is greater than or equal to the duration of the tenth transition.

19. The display panel according to claim 18, wherein, The driving circuit includes M clock lines; M≥2, and M is an even number; During the display time of one frame, with the same first scan signal, P virtual write pulses are located after the data write pulse; P≥1, and P is an integer; P×M≤z<N / 2.

20. The display panel according to claim 19, wherein, P＝2； In the third sub-refresh stage, the first shift register unit of the first stage to the first shift register unit of the Mth stage sequentially outputs the data write pulse; in the fourth sub-refresh stage, the first shift register unit of the M+1th stage to the first shift register unit of the 2×Mth stage sequentially outputs the data write pulse. The duration of the ninth transition is greater than the duration of the tenth transition.

21. The display panel according to claim 1, wherein, During at least a portion of the display time of a frame, the transition duration of the first voltage edge of the clock signal is greater than or equal to a first preset duration.

22. The display panel according to claim 1, wherein, The number of first shift register units whose effective times overlap and are connected to the same clock line is less than or equal to 2.

23. The display panel according to claim 22, wherein, During the display time of one frame, the first scan signal includes a data write pulse and a virtual write pulse.

24. The display panel according to claim 1, wherein, During the display time of one frame, the first scan signal includes a first virtual write pulse, a data write pulse, and a second virtual write pulse; During the display time of one frame, the data write pulse is located between the first virtual write pulse and the second virtual write pulse.

25. A display device, comprising: The display panel and housing according to any one of claims 1-24.

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