Total variation analog-to-digital converter for collecting electroencephalogram

Abstract

Provided in the present invention is a total variation analog-to-digital converter for collecting an electroencephalogram. Firstly, a total variation operator is used to calculate second-order delta encoding, such that the sparsity of an electroencephalogram signal can be more effectively utilized, thereby significantly improving the compression ratio of the electroencephalogram signal. Secondly, a non-switching double-buffer module is designed, such that a second-order delta encoding value can be generated in a simple and efficient manner. Finally, a serialized bitstream generator is designed, such that serialized packaging can be performed on second-order delta data collected by a plurality of parallel channels, which not only exhibits high scalability and is applicable to multi-channel collection, but also enables reliable interfacing with a subsequent synchronous clock wireless transmission system, thus avoiding overheads and latency of synchronous-asynchronous interface coordination, and further improving the signal collection efficiency.

Description

A total variation analog-to-digital converter for electroencephalogram (EEG) acquisition

[0001] Cross-references to related applications

[0002] This application claims priority to Chinese Patent Application No. 2025104617776, filed on April 14, 2025, entitled “A Total Variation Analog-to-Digital Converter for Electroencephalogram Acquisition,” the entire contents of which are incorporated herein by reference. Technical Field

[0003] This invention belongs to the field of brain-computer interfaces, and in particular relates to a total variation analog-to-digital converter for electroencephalogram (EEG) acquisition. Background Technology

[0004] Brain-computer interfaces (BCIs), as a cutting-edge technology connecting the brain to external electronic devices, are revolutionizing neurotherapy, neuroscience research, and human-computer interaction. By monitoring and analyzing brain activity in real time, BCIs offer hope for the recovery of partial function for patients with severe disabilities (such as paralysis and locked-in syndrome). With the help of BCI technology, patients can control external devices through their thoughts, improving their quality of life. Furthermore, BCIs play a crucial role in neuroscience research, helping researchers delve deeper into the neurodynamics of the brain and advancing the understanding and development of treatments for neurological diseases. The widespread application of BCIs has driven innovation across multiple dimensions, from basic neuroscience to clinical treatment.

[0005] Among various sensing technologies in brain-computer interfaces, electroencephalography (EEG) has become the most commonly used signal acquisition method due to its advantages of being non-invasive, convenient, and having high temporal and spatial resolution. EEG can reflect the electrical activity of neuronal populations in the cerebral cortex in real time and is widely used in clinical and research fields. However, with the continuous increase in the number of EEG channels, the acquisition and transmission of EEG signals face unprecedented challenges. With each additional acquisition channel, the amount of data to be transmitted increases dramatically, thus placing higher demands on the system's transmission bandwidth, energy consumption, and processing capabilities.

[0006] Modern brain-computer interface (BCI) systems generally employ wireless data transmission to ensure users' freedom of movement and minimize disruption to their daily lives. However, with the dramatic increase in data volume, wireless transmission bandwidth has become a bottleneck. Reducing the amount of data transmitted while maintaining data integrity has become crucial to solving this problem. Traditional EEG acquisition systems typically use an architecture combining analog front-end sensors (including a preamplifier stage) and a Nyquist analog-to-digital converter (ADC) to convert analog signals into digital signals for subsequent processing and analysis. However, this traditional architecture suffers from severe energy efficiency issues, especially in scenarios where BCIs require prolonged use and frequent data transmission, where energy efficiency is paramount.

[0007] Due to limitations in wireless data transmission and battery capacity, traditional Nyquist ADC architectures have not been effectively optimized for energy consumption, resulting in high power consumption and transmission latency. Traditional analog-to-digital conversion methods, based on the Nyquist sampling theorem, require sufficiently high sampling rates to accurately capture the frequency information of EEG signals. Because the spectrum of EEG signals is relatively limited, especially in the high-frequency range, traditional Nyquist sampling methods often generate a large amount of redundant data, increasing the transmission burden and wasting significant power resources. Furthermore, the sparsity characteristics of EEG signals are not fully utilized.

[0008] Electroencephalogram (EEG) signals exhibit significant sparsity over time, meaning that signal changes are minimal for most of the time, with large fluctuations occurring only at a few moments. To address this redundancy issue, researchers have proposed analog-to-digital converter (ADC) designs based on signal incremental coding (e.g., Delta-ADCs). These designs aim to reduce data transmission overhead and improve system energy efficiency through compressed sampling. Delta-ADCs effectively avoid unnecessary data acquisition during signal silence periods by sampling incremental information only when the input signal crosses a preset threshold, thus saving energy while still efficiently recovering the signal.

[0009] However, despite the theoretically significant improvement in acquisition efficiency offered by Delta-ADCs, current implementations still face several key challenges. First, the incremental coding method used in Delta-ADCs is not always superior to traditional Nyquist-based analog-to-digital converters (ADCs). In certain applications, especially those with frequent or complex signal variations, Delta-ADCs may actually outperform traditional successive approximation ADCs. Furthermore, existing Delta-ADCs generally employ first-order differential computation to generate first-order incremental codes. However, first-order incremental coding does not fully utilize the sparsity of EEG signals, resulting in limited compression and insufficient acquisition efficiency. Finally, most existing Delta-ADC systems use asynchronous sampling, while wireless brain-computer interface systems typically employ synchronous digital processing. This leads to significant overhead and latency in coordination between system interfaces, further impacting overall performance and energy efficiency.

[0010] Therefore, to meet the demands of modern brain-computer interfaces for efficient data acquisition, low-power transmission, and high-quality signal recovery, it is crucial to design a novel analog-to-digital converter (ADC) capable of effectively compressing EEG signals, improving acquisition efficiency, and adapting to wireless transmission requirements. This design not only needs to fully exploit the sparsity characteristics of EEG signals but also consider the system's power consumption, sampling efficiency, and compatibility with subsequent processing modules. Summary of the Invention

[0011] To overcome the low efficiency of EEG signal acquisition in existing technologies, this invention provides a Total Variation Analog-to-Digital Converter (TV-ADC) for EEG acquisition, which comprehensively improves signal acquisition efficiency while maintaining the simplicity of the circuit topology. First, a total variation operator is designed to calculate second-order incremental encoding, which, compared to existing first-order incremental encoding, can more effectively utilize the sparsity of EEG signals, significantly improving the EEG signal compression rate. Second, a fixed double-buffered module is designed, avoiding the circuit complexity caused by the need for switching between existing double-buffered modules, and generating second-order incremental encoded values ​​in a simple and efficient manner. Finally, a serialized bitstream generator is designed, which can serialize and package second-order incremental data acquired from multiple parallel channels. This not only has high scalability, applicable to multiple channel acquisitions, but also reliably interfaces with subsequent synchronous clock wireless transmission systems, avoiding the overhead and latency of synchronous-asynchronous interface coordination, further improving signal acquisition efficiency.

[0012] This invention relates to a total variational analog-to-digital converter (ADC) for electroencephalogram (EEG) acquisition. The circuit comprises a multiplexer, a fixed double-buffered module, a DAC controller, a DAC, a comparator, an increment counter, and a serialized bitstream generator. The multiplexer is controlled by the global clock CLK of the TV-ADC. ADC The system controls the switching of acquisition channels every clock cycle and stabilizes the current EEG acquisition signal to support multi-channel parallel acquisition.

[0013] Furthermore, the fixed double-buffered module is affected by the global clock CLK of the TV-ADC. ADC The control module is responsible for storing and outputting the last acquired value for each channel to support the calculation of second-order incremental encoding, while avoiding the complexity of traditional double-buffered structures.

[0014] Furthermore, the DAC controller reads the previous acquisition value from the fixed double-buffered module and combines it with the output of the incremental counter to generate DAC control code.

[0015] Furthermore, the DAC reads the DAC control code output by the DAC controller, converts it into the EEG signal to be compared, and after multiple comparisons, stores the final DAC output as the current acquisition value of the current channel in the fixed double buffer module.

[0016] Furthermore, the comparator is used to compare the EEG signal to be acquired output from the multiplexer with the EEG signal to be compared output from the DAC, and inputs the comparison result into the increment counter for increment counting.

[0017] Furthermore, the increment counter is affected by the global clock CLK of the TV-ADC. ADC The control system reads the comparator's output in each clock cycle, calculates the second-order increment between the current acquired EEG signal and the previous acquired value, and transmits the increment to the DAC controller and the serialized bit stream generator.

[0018] Furthermore, the serialized bitstream generator is controlled by the global clock CLK of the TV-ADC. ADC The control system stores and converts the signal increment output by the increment counter into a bit stream in each clock cycle, compresses the data, and serializes and packages it to ensure the synchronization of data transmission, generating the final bit stream output by the TV-ADC.

[0019] This invention employs a total variational operator to compute second-order incremental coding, which, compared to existing first-order incremental coding, more effectively utilizes the sparsity of EEG signals and significantly improves the EEG signal compression rate. Secondly, it utilizes a fixed double-buffered module, avoiding the circuit complexity caused by the switching required in existing double-buffered modules, and generating second-order incremental coding values ​​in a simple and efficient manner. Finally, a serialized bitstream generator is designed to serialize and package second-order incremental data acquired from multiple parallel channels. This not only has high scalability, applicable to multiple channel acquisitions, but also reliably interfaces with subsequent synchronous clock wireless transmission systems, avoiding the overhead and latency of synchronous-asynchronous interface coordination, further improving signal acquisition efficiency. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 shows the overall architecture of the total variational analog-to-digital converter for EEG acquisition proposed in this invention;

[0022] Figure 2 is a schematic diagram of a fixed double buffer module;

[0023] Figure 3 is a schematic diagram of the working principle of the DAC controller;

[0024] Figure 4 shows the DAC structure diagram;

[0025] Figure 5 shows the comparator structure diagram;

[0026] Figure 6 is a schematic diagram of the working principle of the increment counter;

[0027] Figure 7 shows an example timing diagram of the increment counter;

[0028] Figure 8 is a schematic diagram of the working principle of the serialized bit stream generator;

[0029] Figure 9 shows the data results acquired by the two ADCs;

[0030] Figure 10 shows the results of normalizing the data acquired by the two ADCs;

[0031] Figure 11 shows the results of converting the data acquired by the two ADCs into bit streams;

[0032] Figure 12 shows the number of 0s and 1s in the bit stream and the total number of binary values. Detailed Implementation

[0033] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of the invention. However, those skilled in the art will understand that the invention can be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods are omitted so as not to obscure the description of the invention with unnecessary detail.

[0034] For an N-point EEG time series signal X = [x1, x2, ..., x...] N ] T Its total variation increment and total variation operator are defined as follows:

[0035] Where D = [d1, d2, ..., d N ] T For total variation increments, It is a total variation operator. For each collected data point x t Its total variation increment is d t =x t -(2x t-1 -x t-2 Therefore, when calculating the total variation increment of the current data point, it is necessary to obtain the values ​​of the previous two data points. Thus, the total variation increment is a second-order increment, and the total variation operator is a second-order difference operator.

[0036] To achieve second-order incremental acquisition, this invention proposes a total variational analog-to-digital converter (ADC) for EEG acquisition, the overall architecture of which is shown in Figure 1. The device consists of a multiplexer, a fixed double-buffered module, a DAC controller, a DAC, a comparator, an incremental counter, and a serialized bitstream generator.

[0037] The multiplexer is powered by the global clock CLK of the TV-ADC. ADC The control switches the acquisition channel every clock cycle and stabilizes the current acquisition signal after the channel switch, thus supporting multi-channel parallel acquisition. The multiplexer in this circuit adopts a standard time-division multiplexing structure, allowing L channels of signals to share a single physical channel for transmission, and stabilizing the signal at different clock cycles (CLK). ADC The channel is occupied sequentially within the cycle to achieve efficient data acquisition.

[0038] In this invention, the time-division multiplexing structure is implemented through a multiplexer circuit. The switch position changes once per clock cycle to select different acquisition channels. After the multiplexer, the signal enters the sample-and-hold circuit, where a switched capacitor circuit physically holds the signal, ensuring signal stability during acquisition and guaranteeing the accuracy and reliability of subsequent acquisitions.

[0039] As shown in Figure 2, the fixed double-buffered module is controlled by the global clock CLK of the TV-ADC. ADC The control module is responsible for storing and outputting the last acquired value for each channel to support the calculation of second-order incremental encoding, while avoiding the complexity of traditional double-buffered structures.

[0040] Specifically, the module comprises two equal-length First-In-First-Out (FIFO) queues, the length of which is related to the number of channels to be acquired. Taking L channels as an example, each FIFO needs to store at least L data points. To prevent queue overflow, a certain margin must be maintained; therefore, in this invention, the FIFO length is set to 1.5L. The two FIFOs are arranged side-by-side, and each FIFO can read data independently. The input of FIFO1 can only be obtained from the output of FIFO2 and cannot be input from the outside; the input of FIFO2 can directly receive external input. Thus, this fixed double-buffered module forms a single-input dual-output structure. This structure is designed to work with the subsequent DAC controller to read data in a fixed manner, thereby avoiding increased circuit complexity and power consumption due to frequent switching of the readout port.

[0041] As shown in Figure 3, the DAC controller is used to read the previous acquisition value of the fixed double buffer module and, in combination with the output of the incremental counter, generate DAC control code.

[0042] Specifically, affected by the global clock CLK ADC Under control, the TV-ADC will sequentially acquire data from L channels, one channel per clock cycle. First, it will acquire data from the first channel to obtain the acquired value. The DAC controller's workflow is as follows:

[0043] Assume the data stored in the current fixed double buffer module are as follows:

[0044] Step 1: Extract the previous two acquisition values ​​of the first channel from FIFO1 and FIFO2 in the fixed double buffer module. and The former is obtained by inverting the input in the inverting module. The latter is input into the doubling module for doubling. Add the two together to get the initial comparison value. The inverting module uses an inverter circuit to invert the sign bit of the input data and output it. The doubling module uses a shift register circuit to shift the input data left by one bit, thereby achieving the doubling effect.

[0045] Step 2: The increment counter inputs the increment value kΔ, adds it to the initial comparison value, and obtains the value to be compared. Where Δ is the smallest quantization unit of the TV-ADC. The initial value of the increment is 0Δ.

[0046] Step 3: Compare the values ​​to be compared As the DAC control code, it is input into the DAC and converted into the corresponding signal to be compared.

[0047] Step 4: Input the signal to be compared into the comparator and compare it with the signal to be acquired. If the signal to be acquired is greater than the signal to be compared, the increment counter is incremented by 1Δ, and the increment value becomes (k+1)Δ; otherwise, it is decremented by 1Δ, and the increment value becomes (k-1)Δ.

[0048] Step 5: Repeat steps 2 through 4 until the difference between the signal to be acquired and the signal to be compared is less than 1Δ. At this point, stop the loop and use the DAC output as the acquired value.

[0049] Step 6: Input into FIFO1, and The data stored in the fixed double-buffered module at this time, after inputting into FIFO2, are as follows:

[0050] The process described above can then be repeated to acquire data from channels 2 to L. After acquiring data from channel L, return to acquiring data from channel 1.

[0051] As shown in Figure 4, the DAC reads the DAC control code output by the DAC controller, converts it into a signal to be compared, and after multiple comparisons, stores the final DAC output as the current acquisition value of the current channel in the fixed double buffer module.

[0052] Specifically, the DAC employs an 8-bit capacitor divider structure, consisting of an array of eight weighted capacitors with sizes C, 2C, 4C, 8C, C, 2C, 4C, and 8C respectively. Before conversion begins, the Reset switch is closed, grounding the upper plates of all capacitors and discharging the capacitor array. During conversion, the Reset switch is opened, and the lower plates of the eight binary weighted capacitors are connected to V according to the control code. ref Alternatively, a 1.067C attenuation capacitor is added to divide the capacitor array into two parts, thereby reducing the variety of capacitors. The rightmost part of the DAC forms a voltage follower structure through an operational amplifier with negative feedback, isolating the capacitor array from the DAC output to reduce output impedance and enhance load-driving capability.

[0053] As shown in Figure 5, the comparator compares the signal to be acquired from the multiplexer output with the signal to be compared from the DAC output, and inputs the comparison result into the increment counter for increment counting. To reduce power consumption, the TV-ADC uses a dynamic comparator. The signal to be acquired is V... inp The input signal to be compared is V. inn The input is V, and the comparison result is given by V. out Terminal output.

[0054] As shown in Figure 6, the increment counter is controlled by the global clock CLK of the TV-ADC. ADC The control system reads the comparator's output in each clock cycle, calculates the second-order increment between the current acquired EEG signal and the previous acquired value, and transmits the increment to the DAC controller and the serialized bit stream generator.

[0055] Specifically, the increment counter contains two modules: a sign register consisting of a 1-bit register circuit to store the sign of the increment value, and an 8-bit binary counter consisting of 8 D flip-flops to store the magnitude of the increment value.

[0056] The increment counter operates as follows: The initial value of the increment is 0Δ. When the comparator output is positive, it is determined that the EEG signal to be acquired is greater than the EEG signal to be compared. The increment counter is incremented by 1Δ, the sign register is positive, and the increment value becomes (0+1)Δ. When the comparator output is negative, it is determined that the EEG signal to be acquired is less than the EEG signal to be compared. The increment counter is decremented by 1Δ, the sign register is negative, and the increment value becomes (0-1)Δ. After each judgment, the increment value is output to the DAC controller to generate the DAC control code. This judgment process is repeated until the difference between the EEG signal to be acquired and the EEG signal to be compared is less than 1Δ. At this point, the loop stops, and the sign in the sign register is concatenated with the value in the 8-bit binary counter to obtain the final second-order increment value.

[0057] Figure 7 shows an example timing diagram for an increment counter. At each global clock CLK... ADC One channel is sampled at a time within each clock cycle. The output of the multiplexer remains stable within each clock cycle, allowing the incremental counter to perform analog-to-digital conversion.

[0058] During the first cycle, the increment counter performs analog-to-digital conversion on channel CH1. In CLK... ADC During the low-level period, both the EEG signal to be acquired and the DAC output signal remain stable. At this time, the DAC output signal is the EEG signal to be compared from channel CH1. In CLK... ADCDuring the high-level period, the increment counter begins analog-to-digital conversion. The first comparison reveals that the EEG signal to be compared is less than the EEG signal to be acquired. Therefore, the increment is increased by 1Δ, and the comparison continues. After six increments of 1Δ, the difference between the EEG signal to be compared and the EEG signal to be acquired is less than 1Δ, at which point the conversion is complete. In the next CLK... ADC At the start of the cycle, the increment counter outputs the increment value of channel CH1, which is +6Δ.

[0059] During the second cycle, the increment counter performs analog-to-digital conversion on the CH2 channel. (CLK) ADC During the low-level period, both the EEG signal to be acquired and the DAC output signal remain stable. At this time, the DAC output signal is the EEG signal to be compared from channel CH2. In CLK... ADC During the high-level period, the increment counter begins analog-to-digital conversion. The first comparison reveals that the difference between the EEG signal to be compared and the EEG signal to be acquired is less than 1Δ, at which point the conversion is complete. In the next CLK... ADC At the start of the cycle, the increment counter outputs the increment value of the CH2 channel, which is 0Δ. At this point, it is assumed that there is no increment between the current acquisition and the previous acquisition of the CH2 channel.

[0060] During the third cycle, the increment counter performs analog-to-digital conversion on channel CH3. In CLK... ADC During the low-level period, both the EEG signal to be acquired and the DAC output signal remain stable. At this time, the DAC output signal is the EEG signal to be compared from channel CH3. In CLK... ADC During the high-level period, the increment counter begins analog-to-digital conversion. The first comparison reveals that the EEG signal to be compared is greater than the EEG signal to be acquired. Therefore, the increment is decreased by 1Δ, and the comparison continues. After four decrements of 1Δ, the difference between the EEG signal to be compared and the EEG signal to be acquired is less than 1Δ, at which point the conversion is complete. In the next CLK... ADC At the start of the cycle, the increment counter outputs the increment value of channel CH3, which is -4Δ.

[0061] Other channels will undergo analog-to-digital conversion cycle by cycle, following the above conversion rules.

[0062] As shown in Figure 8, the serialized bitstream generator is controlled by the global clock CLK of the TV-ADC. ADC The control system stores and converts the signal increment output by the increment counter into a bit stream in each clock cycle, compresses the data, and serializes and packages it to ensure the synchronization of data transmission, generating the final bit stream output by the TV-ADC.

[0063] Specifically, in each global clock CLK ADCOn the rising edge of the EEG, the event judge reads the increment value from the increment counter and determines whether the increment value constitutes a second-order increment event. When the increment value is not 0Δ, it indicates that the currently acquired EEG signal is different from the EEG signal to be compared, and it can be determined as a second-order increment event. At this time, the increment value is stored in the event register.

[0064] Each second-order incremental event requires 9 + log2 L bits of storage space, where log2 L bits are used for the numbering of L channels, 1 bit is used for the increment value sign, and 8 bits are used to store the increment value magnitude. In addition, the system is equipped with a 9 + log2 L bit replica memory for parallel data caching and processing to improve data throughput efficiency.

[0065] After all L channels have completed one acquisition cycle, a complete data acquisition frame is formed. Upon completion of each acquisition frame, the finite state machine generates an enable signal ENA and inputs it to the bitstream clock generator. This clock generator has a built-in ring oscillator specifically designed to provide the clock CLK for bitstream packetization. BIT .

[0066] Subsequently, the finite state machine scans the data in the event register and, based on CLK... BIT The clock is used to pack the bit stream, ultimately generating a TV-ADC data bit stream.

[0067] This invention compares the proposed TV-ADC with the state-of-the-art Nyquist ADC. The experimental setup is as follows: subjects wore EEG caps and sat quietly in front of a computer. Two electrode channels were extended from the EEG caps; channel 1 used a Nyquist ADC for data acquisition, and channel 2 used a TV-ADC. The acquired data was transmitted to the computer via a wired connection for analysis.

[0068] Figure 9 shows the data collected by the two ADCs. It can be seen that the data collected by the Nyquist ADC has greater fluctuations and larger amplitudes, while the data collected by the TV-ADC has smaller fluctuations. Most of the collected values ​​are very close to 0, and only a few collected values ​​are relatively large, showing higher sparsity.

[0069] The data acquired by the two ADCs were sorted in descending order and normalized, as shown in Figure 10. It can be seen that the sparsity of the data acquired by the TV-ADC is significantly higher than that of the data acquired by the Nyquist ADC.

[0070] The data acquired by the two ADCs were converted into bitstreams, as shown in Figure 11. It can be seen that the bitstream of the TV-ADC is sparser than that of the Nyquist ADC.

[0071] The data acquired by the two ADCs were converted into bitstreams, and the number of 0s and 1s and the total number of binary values ​​in the bitstreams were counted, as shown in Figure 12. It can be concluded that the data volume of the TV-ADC bitstream is 39.7% of that of the Nyquist ADC bitstream.

[0072] The above demonstrates that the amount of data that a TV-ADC needs to transmit is significantly less than that that of a Nyquist ADC, thus resulting in higher energy efficiency.

[0073] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0074] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is merely an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit. Furthermore, the specific names of the functional units and modules are only for easy differentiation and are not intended to limit the scope of protection of this application. The specific working process of the units and modules in the above system can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0075] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0076] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0077] In the embodiments provided by this invention, it should be understood that the disclosed apparatus / terminal devices and methods can be implemented in other ways. For example, the apparatus / terminal device embodiments described above are merely illustrative. For instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0078] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0079] Furthermore, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0080] If the integrated module / unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, all or part of the processes in the methods of the above embodiments can also be implemented by a computer program instructing related hardware. The computer program can be stored in a computer-readable storage medium, and when executed by a processor, it can implement the steps of the various method embodiments described above. The computer program includes computer program code, which can be in the form of source code, object code, executable files, or certain intermediate forms. The computer-readable medium can include: any entity or device capable of carrying the computer program code, recording media, USB flash drives, portable hard drives, magnetic disks, optical disks, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signals, telecommunication signals, and software distribution media, etc. It should be noted that the content included in the computer-readable medium can be appropriately added or removed according to the requirements of legislation and patent practice in the jurisdiction. For example, in some jurisdictions, according to legislation and patent practice, computer-readable media do not include electrical carrier signals and telecommunication signals.

[0081] The above-described embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included within the protection scope of the present invention.

Claims

1. A total variation analog-to-digital converter (TV-ADC) for electroencephalogram (EEG) acquisition, characterized in that: The total variational analog-to-digital converter consists of a multiplexer, a fixed double-buffered module, a DAC controller, a DAC, a comparator, an incremental counter, and a serialized bit stream generator, and is used to acquire electroencephalogram (EEG) signals. The multiplexer, fixed double-buffered module, incremental counter, and serialized bitstream generator are all affected by the TV-ADC's global clock CLK. ADC control; The multiplexer switches the acquisition channel in each clock cycle and stabilizes the current EEG acquisition signal to support multi-channel parallel acquisition; The fixed double buffer module is responsible for storing and outputting the previous acquisition value of each channel to support the calculation of second-order incremental coding; The DAC controller is used to read the previous acquisition value of the fixed double-buffered module and, in combination with the output of the incremental counter, generate DAC control code; The DAC reads the DAC control code output by the DAC controller, converts it into the EEG signal to be compared, and after multiple comparisons, stores the final DAC output as the current acquisition value of the current channel in the fixed double buffer module. The comparator is used to compare the EEG signal to be acquired output from the multiplexer with the EEG signal to be compared output from the DAC, and input the comparison result into the increment counter for increment counting; In each clock cycle, the increment counter reads the output of the comparator, calculates the second-order increment between the current acquired EEG signal and the previous acquired value, and transmits the increment to the DAC controller and the serialized bit stream generator. The serialized bitstream generator stores and converts the signal increment output by the increment counter into a bitstream in each clock cycle, generating the final bitstream output by the TV-ADC.

2. A fully variable analog-to-digital converter according to claim 1, wherein the multiplexer adopts a standard time-division multiplexing structure, the time-division multiplexing structure is implemented by a multiplexer circuit, and the switch position is switched once in each clock cycle to select different acquisition channels.

3. A fully variational analog-to-digital converter according to claim 1, wherein the DAC controller comprises an inverting module and a doubling module; the inverting module is implemented using an inverter circuit to invert the sign bit of the input data and output it; the doubling module is implemented using a shift register circuit to shift the input data left by 1 bit, thereby achieving the doubling effect.

4. A fully variable analog-to-digital converter according to claim 3, wherein the DAC controller operates as follows: Assume the data stored in the current fixed double buffer module are as follows: Step 1: Extract the previous two acquisition values ​​of the first channel from FIFO1 and FIFO2 in the fixed double buffer module. and The former is obtained by inverting the input in the inverting module. The latter is input into the doubling module for doubling. Add the two together to get the initial comparison value. Step 2: The increment counter inputs the increment value kΔ, adds it to the initial comparison value, and obtains the value to be compared. Where Δ is the smallest quantization unit of the TV-ADC; and the initial value of the increment is 0Δ. Step 3: Compare the values ​​to be compared As the DAC control code, it is input into the DAC and converted into the corresponding signal to be compared; Step 4: Input the signal to be compared into the comparator and compare it with the signal to be acquired; if the signal to be acquired is greater than the signal to be compared, the increment counter is incremented by 1Δ, and the increment value becomes (k+1)Δ; otherwise, it is decremented by 1Δ, and the increment value becomes (k-1)Δ. Step 5: Repeat steps 2 through 4 until the difference between the signal to be acquired and the signal to be compared is less than 1Δ. At this point, stop the loop and use the DAC output as the acquired value. Step 6: Input into FIFO1, and The data stored in the fixed double-buffered module at this time, after inputting into FIFO2, are as follows:

5. A fully variable analog-to-digital converter according to claim 1, wherein the DAC is implemented using an 8-bit capacitor voltage divider structure; and the comparator is a dynamic comparator.

6. A fully variational analog-to-digital converter according to claim 1, wherein the increment counter comprises two modules: a sign register and an 8-bit binary counter; wherein the sign register is composed of a 1-bit register circuit for storing the sign of the increment value, and the 8-bit binary counter is composed of 8 D flip-flops for storing the magnitude of the increment value.

7. A total variational analog-to-digital converter according to claim 6, wherein the increment counter operates as follows: the initial value of the increment is 0Δ; when the comparator output is positive, it is determined that the EEG signal to be acquired is greater than the EEG signal to be compared, then the increment counter is incremented by 1Δ, the sign register is positive, and the increment value becomes (0+1)Δ; when the comparator output is negative, it is determined that the EEG signal to be acquired is less than the EEG signal to be compared, then the increment counter is decremented by 1Δ, the sign register is negative, and the increment value becomes (0-1)Δ; after each judgment, the increment value is output to the DAC controller to generate DAC control code; the above judgment steps are repeated until the difference between the EEG signal to be acquired and the EEG signal to be compared is less than 1Δ, at which point the loop stops, and the sign in the sign register and the value in the 8-bit binary counter are concatenated to obtain the final second-order increment value.

8. A fully variational analog-to-digital converter according to claim 1, wherein the serialized bitstream generator comprises an event judge, an event register, a finite state machine, a bitstream clock generator, and a bitstream packer.

9. A fully variational analog-to-digital converter according to claim 8, wherein the serialized bitstream generator operates at each global clock CLK. ADC On the rising edge, the event judge reads the increment value from the increment counter and determines whether the increment value forms a second-order increment event. When the increment value is not 0Δ, it is determined to be a second-order increment event, and the increment value is stored in the event register. After all L channels have completed one acquisition, a complete data acquisition frame is formed; After each acquisition frame is completed, the finite state machine generates an enable signal ENA and inputs it to the bitstream clock generator; this clock generator has a built-in ring oscillator specifically designed to provide the clock CLK for bitstream packetization. BIT ; The finite state machine scans the data in the event register and uses CLK as a basis. BIT The clock is used to pack the bit stream, ultimately generating a TV-ADC data bit stream.

10. A fully variational analog-to-digital converter according to claim 9, wherein in the serialized bit stream generator, each second-order incremental event requires 9 + log2 L bits of storage space, wherein log2 L bits are used for numbering the L channels, 1 bit is used for the incremental value sign, and 8 bits are used to store the magnitude of the incremental value.

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