Fractional-order difference analog-to-digital converter for collecting neural spike potential

Abstract

Provided in the present invention is a fractional-order difference analog-to-digital converter for collecting a neural spike potential. Firstly, a fractional-order difference operator is designed to calculate arbitrary fractional-order delta encoding, such that the sparsity of a neural spike potential can be more effectively utilized, thereby significantly improving the compression ratio of the neural spike potential; moreover, the fractional-order difference analog-to-digital converter has higher flexibility by means of tunable differential orders, and can adapt to a wider range of neural spike potential collection scenarios. Secondly, a fractional-order buffer module is designed, such that an arbitrary fractional-order delta encoding value can be generated in a simple and efficient manner. Finally, a serialized bitstream generator is designed, such that serialized packaging can be performed on fractional-order delta data collected by a plurality of parallel channels, which not only exhibits high scalability and is applicable to multi-channel collection, but also enables reliable interfacing with a subsequent synchronous clock wireless transmission system, thus avoiding overheads and latency of synchronous-asynchronous interface coordination, and further improving the efficiency of neural spike potential collection.

Description

A fractional-order differential analog-to-digital converter for acquiring neural peak potentials

[0001] Cross-reference to related applications

[0002] This application claims priority to Chinese Patent Application No. 2025104659478, filed on April 14, 2025, entitled "A Fractional-Order Differential Analog-to-Digital Converter for Acquiring Neural Peak Potentials", the entire contents of which are incorporated herein by reference. Technical Field

[0003] This invention belongs to the field of brain-computer interfaces, and in particular relates to a fractional-order differential analog-to-digital converter for acquiring neural peak potentials. Background Technology

[0004] As a disruptive technology at the intersection of neuroscience and engineering, invasive brain-computer interfaces (BCIs) are reshaping the paradigm of rehabilitation for paralyzed patients and treatment for neurological diseases by directly capturing electrical activity in the cerebral cortex through implanted electrode arrays. This technology can not only interpret motor intention signals, helping spinal cord injury patients control robotic arms to perform grasping actions, but also intervene in abnormal brain electrical rhythms through closed-loop electrical stimulation, providing precise treatment options for tremor control in Parkinson's disease. Its high spatiotemporal resolution signal decoding capabilities enable researchers to explore the neural circuit mechanisms of cognitive function with single-neuron precision, accelerating the deep integration of brain-computer interface theory and clinical translational research.

[0005] In invasive systems, neural spike potentials, as core bioelectrical signals reflecting the firing of single neurons, directly determine the decoding efficiency of brain-computer interfaces through their acquisition quality. These signals are generated by the conduction of neuronal action potentials and have millivolt-level amplitudes and millisecond-level durations. To accurately capture their firing timing, microelectrode arrays need to penetrate the cortex to reach the target neuron, using high-impedance probes and adaptive threshold detection technology to separate the action potential waveform. Because spike potential amplitudes are easily affected by changes in cell membrane impedance, the system needs to integrate a dynamic gain compensation module and a multi-channel signal alignment algorithm to maintain coding consistency. However, this cell-level electrophysiological recording places more stringent requirements on electrode tip morphology, tissue interface stability, and signal crosstalk suppression; any distortion of the action potential waveform will lead to misinterpretation of the neuronal cluster coding information.

[0006] Traditional acquisition architectures typically employ Nyquist analog-to-digital converters (ADCs) for uniform sampling of neural spike potentials across the entire frequency band. This design faces significant energy efficiency challenges when achieving high-density, multi-channel neural spike potential recording. Since neural spike potentials are characteristic signals of single-neuron action potentials, their effective information is concentrated in the 500Hz-8kHz high-frequency band and exhibits sub-millisecond transient discharge characteristics. Using a fixed-rate broadband sampling strategy leads to signal sparsity issues—approximately 85% of the sampled data only records baseline noise. This not only results in inefficient use of ADC resources but also causes an exponential increase in the power density of the implanted system. When the number of microelectrode channels expands to 256, the static power consumption of the front-end sampling module may exceed the 20mW safety threshold. The resulting local tissue thermal deposition effect not only accelerates electrode-tissue interface impedance drift but may also affect the normal firing patterns of adjacent neurons.

[0007] To overcome energy efficiency barriers, event-driven incremental coding analog-to-digital conversion technologies (such as Delta-ADC) have emerged. This solution innovatively introduces a dynamic threshold comparison mechanism, triggering quantization only when the signal amplitude exceeds a preset threshold. This adaptive sampling strategy fully utilizes the sparsity of neural spike potentials over time, resulting in data throughput reductions of over 82% in scenarios such as Parkinson's disease monitoring and rhythm acquisition. By constructing a multi-level differential coding tree, the system can simultaneously extract signal amplitude abrupt changes and slope variations, significantly reducing single-channel power consumption and extending the battery life of implanted devices while maintaining action potential waveform details.

[0008] However, despite the theoretically significant improvement in acquisition efficiency offered by Delta-ADCs, current implementations still face several key challenges. First, the incremental coding method used in Delta-ADCs is not always superior to traditional Nyquist-based analog-to-digital converters (ADCs). In certain applications, especially those with frequent or complex signal variations, Delta-ADCs may actually outperform traditional successive approximation ADCs. Furthermore, existing Delta-ADCs generally employ first-order differential computation to generate first-order incremental codes. However, first-order incremental coding does not fully utilize the sparsity of neural peak potentials, resulting in limited compression and insufficient acquisition efficiency. Finally, most existing Delta-ADC systems use asynchronous sampling, while wireless brain-computer interface systems typically employ synchronous digital processing. This leads to significant overhead and latency in coordination between system interfaces, further impacting overall performance and energy efficiency.

[0009] Therefore, to meet the demands of modern brain-computer interfaces for efficient acquisition, low-power transmission, and high-quality signal recovery, it is crucial to design a novel analog-to-digital converter (ADC) capable of effectively compressing neural peak potential signals, improving acquisition efficiency, and adapting to wireless transmission requirements. This design not only needs to fully exploit the sparsity characteristics of neural peak potentials but also consider the system's power consumption, sampling efficiency, and compatibility with subsequent processing modules. Summary of the Invention

[0010] To overcome the low acquisition efficiency of neural spike potentials in existing technologies, this invention provides a fractional order difference analog-to-digital converter (FOD-ADC) for neural spike potential acquisition, which comprehensively improves signal acquisition efficiency while maintaining the simplicity of the circuit topology. First, a fractional order differential operator is designed to calculate arbitrary fractional order incremental codes. Compared to existing first-order incremental codes, this not only more effectively utilizes the sparsity of neural spike potentials and significantly improves the neural spike potential compression ratio, but also offers greater flexibility, with an adjustable differential order to adapt to more neural spike potential acquisition application scenarios. Second, a fractional order buffer module is designed to generate arbitrary fractional order incremental code values ​​in a simple and efficient manner. Finally, a serialized bitstream generator is designed to serialize and package fractional order incremental data acquired from multiple parallel channels. This not only has high scalability, applicable to multiple channel acquisitions, but also reliably interfaces with subsequent synchronous clock wireless transmission systems, avoiding the overhead and latency of synchronous-asynchronous interface coordination, further improving the neural spike potential acquisition efficiency.

[0011] This invention relates to a fractional-order differential analog-to-digital converter (ADC) for acquiring neural peak potentials. The circuit comprises a multiplexer, a fractional-order buffer module, a DAC controller, a DAC, a comparator, an increment counter, and a serialized bitstream generator. The multiplexer is controlled by the global clock CLK of the FOD-ADC. ADC The system controls the switching of acquisition channels every clock cycle and stabilizes the current acquisition signal to support multi-channel parallel acquisition.

[0012] Furthermore, the fractional-order buffer module is controlled by the global clock CLK of the FOD-ADC. ADC The control unit is responsible for storing and outputting the last acquired value for each channel to support the calculation of arbitrary fractional-order incremental encoding.

[0013] Furthermore, the DAC controller reads the previous acquisition value from the fractional buffer module and combines it with the output of the increment counter to generate DAC control code.

[0014] Furthermore, the DAC reads the DAC control code output by the DAC controller, converts it into a signal to be compared, and after multiple comparisons, stores the final DAC output as the current acquisition value of the current channel in the fractional buffer module.

[0015] Furthermore, the comparator is used to compare the signal to be acquired output from the multiplexer with the signal to be compared output from the DAC, and inputs the comparison result into the increment counter for increment counting.

[0016] Furthermore, the increment counter is controlled by the global clock CLK of the FOD-ADC. ADC The control system reads the comparator's output in each clock cycle, calculates the fractional increment between the current acquired signal and the previous acquired value, and transmits the increment to the DAC controller and the serialized bit stream generator.

[0017] Furthermore, the serialized bitstream generator is controlled by the global clock CLK of the FOD-ADC. ADC The control system stores and converts the signal increment output by the increment counter into a bit stream in each clock cycle, compresses the data, and serializes and packages it to ensure the synchronization of data transmission, generating the final bit stream output by the FOD-ADC.

[0018] This invention provides a fractional-order differential analog-to-digital converter (ADC) for neural spike potential acquisition. First, a fractional-order differential operator is designed to calculate arbitrary fractional-order incremental codes, which more effectively utilizes the sparsity of neural spike potentials, significantly improving the compression ratio while offering greater flexibility with an adjustable differential order to adapt to more neural spike potential acquisition application scenarios. Second, a fractional-order buffer module is designed to generate arbitrary fractional-order incremental code values ​​in a concise and efficient manner. Finally, a serialized bitstream generator is designed to serialize and package fractional-order incremental data acquired from multiple parallel channels. This not only offers high scalability, applicable to multiple channel acquisitions, but also allows for reliable interfacing with subsequent synchronous clock wireless transmission systems, avoiding the overhead and latency of synchronous-asynchronous interface coordination, further improving the efficiency of neural spike potential acquisition. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 shows the overall architecture of the fractional-order differential analog-to-digital converter for acquiring neural peak potentials proposed in this invention.

[0021] Figure 2 is a schematic diagram of the fractional buffer module;

[0022] Figure 3 shows the execution process of the fractional buffer module;

[0023] Figure 4 shows the working principle diagram of the DAC controller;

[0024] Figure 5 shows the DAC structure diagram;

[0025] Figure 6 shows the comparator structure diagram;

[0026] Figure 7 shows the working principle diagram of the increment counter;

[0027] Figure 8 is an example timing diagram of an increment counter;

[0028] Figure 9 is a schematic diagram of the working principle of the serialized bit stream generator;

[0029] Figure 10 shows the data acquisition results of the two ADCs;

[0030] Figure 11 shows the results of normalizing the data acquired by the two ADCs;

[0031] Figure 12 shows the results of converting the data acquired by the two ADCs into bit streams;

[0032] Figure 13 shows the number of 0s and 1s in the bit stream and the total number of binary values. Detailed Implementation

[0033] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of the invention. However, those skilled in the art will understand that the invention can be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods are omitted so as not to obscure the description of the invention with unnecessary detail.

[0034] For a neural peak time series signal X = [x1, x2, ..., xn] at N points, N ] T Its f-th order difference operator is defined as:

[0035] Where x i Let f be the i-th element in signal X, f be any fraction greater than 0, j! denote the factorial of j, Γ(·) denote the GAMMA function, and D f It is an f-order difference operator, where Y is the increment of signal X after f-order difference calculation. Fractional-order differences involve infinite series, but in practical applications, due to the finite length of neural peak signals, truncation is necessary; therefore, it is truncated to... In this case, the f-th order difference operator is defined as:

[0036] As can be seen from the above formula, when calculating the f-th order increment of the current data point, it is necessary to obtain the values ​​of the previous g data points.

[0037] Taking the 1.3rd order difference operator as an example, its matrix form is:

[0038] To calculate the 1.3rd order differential increment value of the currently acquired neural peak potential data point, it is first necessary to obtain the values ​​of the previous two acquired neural peak potential data points. The 1.3rd order minuend y is then calculated from these values. i =1.3x i-1 -0.195x i-2 Then use the currently collected data point x i Subtract y i The 1.3rd order difference increment value z is obtained. i =x i -y i =x i -(1.3x i-1 -0.195x i-2 ).

[0039] Taking the 2.5th order difference operator as an example, its matrix form is:

[0040] To calculate the 2.5th order differential increment value of the current acquired neural peak potential data point, it is first necessary to obtain the values ​​of the previous three acquired data points. The 2.5th order minuend y is then calculated. i =3.5x i-1 -4.375x i-2 +2.1875x i-3 Then use the currently collected data point x i Subtract y i The 2.5th order difference increment value z is obtained. i =x i -y i =x i -(3.5x i-1 -4.375x i-2 +2.1875x i-3 ).

[0041] To achieve f-order incremental acquisition, this invention proposes a fractional-order differential analog-to-digital converter (ADC) for acquiring neural peak potentials, the overall architecture of which is shown in Figure 1. The device consists of a multiplexer, a fractional-order buffer module, a DAC controller, a DAC, a comparator, an incremental counter, and a serialized bitstream generator.

[0042] The multiplexer is powered by the global clock CLK of the FOD-ADC. ADC The control switches the acquisition channel every clock cycle and stabilizes the current acquisition signal after the channel switch, thus supporting multi-channel parallel acquisition. The multiplexer in this circuit adopts a standard time-division multiplexing structure, allowing L channels of signals to share a single physical channel for transmission, and stabilizing the signal at different clock cycles (CLK). ADC The channel is occupied sequentially within the cycle to achieve efficient data acquisition.

[0043] In this invention, the time-division multiplexing structure is implemented through a multiplexer circuit. The switch position changes once per clock cycle to select different acquisition channels. After the multiplexer, the signal enters the sample-and-hold circuit, where a switched capacitor circuit physically holds the signal, ensuring signal stability during acquisition and guaranteeing the accuracy and reliability of subsequent acquisitions.

[0044] As shown in Figure 2, the fractional-order buffer module is controlled by the global clock CLK of the FOD-ADC. ADC The control module is responsible for storing and outputting the values ​​of the previous g data points for each channel to support the calculation of the f-th order minuend, while avoiding the complexity of the traditional first-in-first-out buffer structure.

[0045] Specifically, the module comprises three parts: a storage matrix, a computation matrix, and an adder tree. The storage matrix has g rows and L columns. In each clock cycle, data from the DAC input is fed into the left side of the g-th row. Data from the rightmost edge of each row is shifted out of the storage matrix and input into the computation matrix for calculation. Simultaneously, the data in the storage matrix moves in a circular fashion; data shifted out of the lower row is simultaneously shifted into the left side of the upper row. Except for the g-th row, which can receive data from the DAC, data in other rows can only be shifted in from the corresponding lower row and cannot receive input data from outside the module. Therefore, the storage matrix forms a 1-input, g-output structure. This structure is designed to work in conjunction with the computation matrix to read data in a fixed manner, thereby avoiding increased circuit complexity and power consumption due to frequent switching of read ports.

[0046] The computation matrix consists of a series of multiplication units. Data retrieved from the storage matrix is ​​multiplied by the corresponding difference operator coefficients, and then input into the adder tree. The adder tree accumulates the data that has been multiplied by coefficients to obtain the f-order minuend, and outputs the f-order minuend to the DAC controller, thus completing the task of the fractional buffer module.

[0047] The fractional-order buffer module is controlled by the global clock CLK of the FOD-ADC. ADCThe control process involves receiving one data point, reading from the storage matrix, performing one calculation, and accumulating the data in each cycle. Taking a 2.5-order FOD-ADC as an example, assuming the current cycle is i-th, and the first channel is being sampled to obtain the sampled value... At this point, the 2.5 order minuend is The execution process is shown in Figure 3, and the details are as follows:

[0048] Assume the data stored in the current storage matrix is:

[0049] Step 1: Extract the first 3 acquisition values ​​of the first channel from the 3 output terminals of the storage matrix. and The three collected values ​​were input into the calculation matrix and the calculations were performed respectively.

[0050] Step 2: Activate three multiplication units in the computation matrix, numbered 1, 2, and 3 respectively. In input multiplication unit 1, multiply by the coefficient 2.1875 to obtain... Will In input multiplication unit 2, multiply by the coefficient -4.375 to obtain... Will In input multiplication unit 3, multiply by the coefficient 3.5 to obtain...

[0051] The third step involves inputting the results of the three multiplication units into the adder tree for accumulation, resulting in a 2.5 order minuend.

[0052] As shown in Figure 4, the DAC controller is used to read the f-th order minuend output by the fractional buffer module and, in combination with the output of the increment counter, generate the DAC control code.

[0053] Specifically, affected by the global clock CLK ADC Under the control of the FOD-ADC, data will be acquired sequentially from L channels, one channel at a time, with each clock cycle acquiring data from one channel. Assuming we are currently acquiring data from the first channel, the acquired value will be... The DAC controller's workflow is as follows:

[0054] The first step is to calculate the f-th order minuend y using the fractional buffer module. i .

[0055] Step 2: The increment counter inputs the increment value kΔ, and modulates it with the f-order minuend y. i Add them together to get the value to be compared, y. i +kΔ, where Δ is the smallest quantization unit of the FOD-ADC. The initial value of the increment is 0Δ.

[0056] Step 3: Compare the value y to be compared i +kΔ is used as the DAC control code, input to the DAC, and converted into the corresponding signal to be compared.

[0057] Step 4: Input the signal to be compared into the comparator and compare it with the signal to be acquired. If the signal to be acquired is greater than the signal to be compared, the increment counter is incremented by 1Δ, and the increment value becomes (k+1)Δ; otherwise, it is decremented by 1Δ, and the increment value becomes (k-1)Δ.

[0058] Step 5: Repeat steps 2 through 4 until the difference between the signal to be acquired and the signal to be compared is less than 1Δ. At this point, stop the loop and use the DAC output as the acquired value.

[0059] Step 6: Store the data in the fractional buffer module and update the value of each row in the fractional buffer module.

[0060] The process described above can then be repeated to acquire data from channels 2 to L. After acquiring data from channel L, return to acquiring data from channel 1.

[0061] As shown in Figure 5, the DAC reads the DAC control code output by the DAC controller, converts it into a signal to be compared, and after multiple comparisons, stores the final DAC output as the current acquisition value of the current channel in the fractional buffer module.

[0062] Specifically, the DAC employs an 8-bit capacitor divider structure, consisting of an array of eight weighted capacitors with sizes C, 2C, 4C, 8C, C, 2C, 4C, and 8C respectively. Before conversion begins, the Reset switch is closed, grounding the upper plates of all capacitors and discharging the capacitor array. During conversion, the Reset switch is opened, and the lower plates of the eight binary weighted capacitors are connected to V according to the control code. ref Alternatively, a 1.067C attenuation capacitor is added to divide the capacitor array into two parts, thereby reducing the variety of capacitors. The rightmost part of the DAC forms a voltage follower structure through an operational amplifier with negative feedback, isolating the capacitor array from the DAC output to reduce output impedance and enhance load-driving capability.

[0063] As shown in Figure 6, the comparator compares the signal to be acquired from the multiplexer output with the signal to be compared from the DAC output, and inputs the comparison result into the increment counter for increment counting. To reduce power consumption, the FOD-ADC uses a dynamic comparator. The signal to be acquired is determined by V... inp The input signal to be compared is V. inn The input is V, and the comparison result is given by V. out Terminal output.

[0064] As shown in Figure 7, the increment counter is controlled by the global clock CLK of the FOD-ADC. ADC The control system reads the comparator's output in each clock cycle, calculates the fractional increment between the current acquired signal and the previous acquired value, and transmits the increment to the DAC controller and the serialized bit stream generator.

[0065] Specifically, the increment counter contains two modules: a sign register consisting of a 1-bit register circuit to store the sign of the increment value, and an 8-bit binary counter consisting of 8 D flip-flops to store the magnitude of the increment value.

[0066] The increment counter operates as follows: The initial value of the increment is 0Δ. When the comparator output is positive, it is determined that the signal to be acquired is greater than the signal to be compared, so the increment counter is incremented by 1Δ, the sign register is positive, and the increment value becomes (0+1)Δ. When the comparator output is negative, it is determined that the signal to be acquired is less than the signal to be compared, so the increment counter is decremented by 1Δ, the sign register is negative, and the increment value becomes (0-1)Δ. After each judgment, the increment value is output to the DAC controller to generate DAC control code. The above judgment steps are repeated until the difference between the signal to be acquired and the signal to be compared is less than 1Δ. At this point, the loop stops, and the sign in the sign register is concatenated with the value in the 8-bit binary counter to obtain the final fractional increment value.

[0067] Figure 8 shows an example timing diagram for an increment counter. At each global clock CLK... ADC One channel is sampled at a time within each clock cycle. The output of the multiplexer remains stable within each clock cycle, allowing the incremental counter to perform analog-to-digital conversion.

[0068] During the first cycle, the increment counter performs analog-to-digital conversion on channel CH1. In CLK... ADC During the low-level period of CLK, both the signal to be acquired and the DAC output signal remain stable. At this time, the DAC output signal is the signal to be compared from channel CH1. ADC During the high-level period, the increment counter begins analog-to-digital conversion. The first comparison finds that the signal to be compared is less than the signal to be acquired, so the increment is increased by 1Δ, and the comparison continues. After six increments of 1Δ, the difference between the signal to be compared and the signal to be acquired is less than 1Δ, at which point the conversion is complete. In the next CLK... ADC At the start of the cycle, the increment counter outputs the increment value of channel CH1, which is +6Δ.

[0069] During the second cycle, the increment counter performs analog-to-digital conversion on the CH2 channel. (CLK) ADCDuring the low-level period of CLK, both the signal to be acquired and the DAC output signal remain stable. At this time, the DAC output signal is the signal to be compared from channel CH2. ADC During the high-level period, the increment counter begins analog-to-digital conversion. The first comparison finds that the difference between the signal to be compared and the signal to be acquired is less than 1Δ, at which point the conversion is complete. In the next CLK... ADC At the start of the cycle, the increment counter outputs the increment value of the CH2 channel, which is 0Δ. At this point, it is assumed that there is no increment between the current acquisition and the previous acquisition of the CH2 channel.

[0070] During the third cycle, the increment counter performs analog-to-digital conversion on channel CH3. In CLK... ADC During the low-level period, both the signal to be acquired and the DAC output signal remain stable. At this time, the DAC output signal is the signal to be compared from channel CH3. In CLK... ADC During the high-level period, the increment counter begins analog-to-digital conversion. The first comparison finds that the signal to be compared is greater than the signal to be acquired, so the increment is decreased by 1Δ, and the comparison continues. After four decrements of 1Δ, the difference between the signal to be compared and the signal to be acquired is less than 1Δ, at which point the conversion is complete. In the next CLK... ADC At the start of the cycle, the increment counter outputs the increment value of channel CH3, which is -4Δ.

[0071] Other channels will undergo analog-to-digital conversion cycle by cycle, following the above conversion rules.

[0072] As shown in Figure 9, the serialized bitstream generator is controlled by the global clock CLK of the FOD-ADC. ADC The control system stores and converts the signal increment output by the increment counter into a bit stream in each clock cycle, compresses the data, and serializes and packages it to ensure the synchronization of data transmission, generating the final bit stream output by the FOD-ADC.

[0073] Specifically, in each global clock CLK ADC On the rising edge of the signal, the event detector reads the increment value from the increment counter and determines whether the increment value constitutes a fractional increment event. When the increment value is not 0Δ, it indicates that the currently acquired signal is different from the signal to be compared, and thus it can be determined as a fractional increment event. At this time, the increment value is stored in the event register.

[0074] Each fractional-order incremental event requires 9 + log2 L bits of storage space, where log2 L bits are used for the numbering of L channels, 1 bit is used for the sign of the incremental value, and 8 bits are used to store the magnitude of the incremental value. In addition, the system is equipped with a 9 + log2 L bit replica memory for parallel data caching and processing to improve data throughput efficiency.

[0075] After all L channels have completed one acquisition cycle, a complete data acquisition frame is formed. Upon completion of each acquisition frame, the finite state machine generates an enable signal ENA and inputs it to the bitstream clock generator. This clock generator has a built-in ring oscillator specifically designed to provide the clock CLK for bitstream packetization. BIT .

[0076] Subsequently, the finite state machine scans the data in the event register and, based on CLK... BIT The clock is used to pack the bit stream, ultimately generating the FOD-ADC data bit stream.

[0077] This invention compares the proposed FOD-ADC with the state-of-the-art Nyquist ADC. The experimental setup is as follows: Animals were anesthetized and held still in their cages. Electrodes were implanted in the head, leading to two electrode channels. Each electrode channel contained the same neural spike potential. Channel 1 was acquired using a Nyquist ADC, and channel 2 was acquired using the FOD-ADC. The difference orders of the FOD-ADC were selected as 1.3, 2.5, and 3.7 for comprehensive comparison. The acquired data were transmitted to a computer via wired connection for analysis.

[0078] Figure 10 shows the data collected by the two ADCs. It can be seen that the data collected by the Nyquist ADC has greater fluctuations and larger amplitudes, while the data collected by the FOD-ADC has smaller fluctuations. Most of the collected values ​​are very close to 0, and only a few collected values ​​are relatively large, showing higher sparsity.

[0079] The data acquired by the two ADCs were sorted in descending order and normalized, as shown in Figure 11. It can be seen that the sparsity of the data acquired by the FOD-ADC is significantly higher than that of the data acquired by the Nyquist ADC.

[0080] The data acquired by the two ADCs were converted into bitstreams, as shown in Figure 12. It can be seen that the bitstream of the FOD-ADC is sparser than that of the Nyquist ADC.

[0081] The data acquired by the two ADCs were converted into bitstreams, and the number of 0s and 1s and the total number of binary values ​​in the bitstreams were counted, as shown in Figure 13. It can be concluded that the data volume of the 1.3-order FOD-ADC bitstream is 18.1% of the Nyquist ADC bitstream data volume, the 2.5-order FOD-ADC bitstream data volume is 24.6% of the Nyquist ADC bitstream data volume, and the 3.7-order FOD-ADC bitstream data volume is 18.2% of the Nyquist ADC bitstream data volume.

[0082] The above demonstrates that the amount of data that FOD-ADC needs to transmit is significantly less than that that that Nyquist ADC needs to transmit, thus resulting in higher energy efficiency.

[0083] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0084] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is merely an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit. Furthermore, the specific names of the functional units and modules are only for easy differentiation and are not intended to limit the scope of protection of this application. The specific working process of the units and modules in the above system can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0085] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0086] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0087] In the embodiments provided by this invention, it should be understood that the disclosed apparatus / terminal devices and methods can be implemented in other ways. For example, the apparatus / terminal device embodiments described above are merely illustrative. For instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0088] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0089] Furthermore, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0090] If the integrated module / unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, all or part of the processes in the methods of the above embodiments can also be implemented by a computer program instructing related hardware. The computer program can be stored in a computer-readable storage medium, and when executed by a processor, it can implement the steps of the various method embodiments described above. The computer program includes computer program code, which can be in the form of source code, object code, executable files, or certain intermediate forms. The computer-readable medium can include: any entity or device capable of carrying the computer program code, recording media, USB flash drives, portable hard drives, magnetic disks, optical disks, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signals, telecommunication signals, and software distribution media, etc. It should be noted that the content included in the computer-readable medium can be appropriately added or removed according to the requirements of legislation and patent practice in the jurisdiction. For example, in some jurisdictions, according to legislation and patent practice, computer-readable media do not include electrical carrier signals and telecommunication signals.

[0091] The above-described embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included within the protection scope of the present invention.

Claims

1. A fractional order difference analog-to-digital converter (FOD-ADC) for acquiring neural peak potentials, characterized in that, The device consists of a multiplexer, a fractional-order buffer module, a DAC controller, a DAC, a comparator, an increment counter, and a serialized bit stream generator, and is used to acquire neural peak potential signals. The multiplexer, fractional-order buffer module, increment counter, and serialized bitstream generator are all controlled by the global clock CLK of the FOD-ADC. ADC Control is used to achieve the corresponding function; The multiplexer switches the acquisition channel in each clock cycle and stabilizes the current acquisition signal to support multi-channel parallel acquisition; The fractional-order buffer module is responsible for storing and outputting the previous acquisition value of each channel to support the calculation of arbitrary fractional-order incremental encoding; The DAC controller is used to read the previous acquisition value from the fractional buffer module and, in conjunction with the output of the increment counter, generate DAC control code. The DAC reads the DAC control code output by the DAC controller, converts it into a signal to be compared, and after multiple comparisons, stores the final DAC output as the current acquisition value of the current channel in the fractional buffer module. The comparator is used to compare the signal to be acquired output from the multiplexer with the signal to be compared output from the DAC, and inputs the comparison result into the increment counter for increment counting; In each clock cycle, the increment counter reads the output of the comparator, calculates the fractional increment between the current acquired signal and the previous acquired value, and transmits the increment to the DAC controller and the serialized bit stream generator. The serialized bitstream generator stores and converts the signal increment output by the increment counter into a bitstream in each clock cycle, generating the final bitstream output by the FOD-ADC.

2. The fractional-order differential analog-to-digital converter according to claim 1, wherein the multiplexer adopts a time-division multiplexing structure, and the time-division multiplexing structure is implemented by a multiplexer circuit, wherein the switch position is switched once in each clock cycle to select different acquisition channels.

3. The fractional-order differential analog-to-digital converter according to claim 1, wherein the fractional-order buffer module consists of three parts: a storage matrix, a computation matrix, and an adder tree; The storage matrix contains g rows and L columns; in each clock cycle, the data input from the DAC is fed to the left side of the g-th row, and the rightmost data of each row is shifted out of the storage matrix and input into the calculation matrix for calculation; the data in the storage matrix is ​​moved in a circular motion. The computation matrix multiplies the data retrieved from the storage matrix with the corresponding difference operator coefficients, and then inputs the result into the adder tree; The adder tree accumulates the data that has already been multiplied by coefficients to obtain the f-order minuend, and outputs the f-order minuend to the DAC controller, thus completing the task of the fractional buffer module.

4. The fractional-order differential analog-to-digital converter according to claim 1, wherein the DAC controller operates as follows: The first step is to calculate the f-th order minuend y using the fractional buffer module. i ; Step 2: The increment counter inputs the increment value kΔ, and modulates it with the f-order minuend y. i Add them together to get the value to be compared, y. i +kΔ, where Δ is the smallest quantization unit of the FOD-ADC; and the initial value of the increment is 0Δ; Step 3: Compare the value y to be compared i +kΔ is used as the DAC control code, input to the DAC, and converted into the corresponding signal to be compared. Step 4: Input the signal to be compared into the comparator and compare it with the signal to be acquired; if the signal to be acquired is greater than the signal to be compared, the increment counter is incremented by 1Δ, and the increment value becomes (k+1)Δ; otherwise, it is decremented by 1Δ, and the increment value becomes (k-1)Δ. Step 5: Repeat steps 2 through 4 until the difference between the signal to be acquired and the signal to be compared is less than 1Δ. At this point, stop the loop and use the DAC output as the acquired value. Step 6: Store the data in the fractional buffer module and update the value of each row in the fractional buffer module.

5. The fractional-order differential analog-to-digital converter according to claim 1, wherein the increment counter includes a sign register and an 8-bit binary counter, the sign register being composed of a 1-bit register circuit for storing the sign of the increment value, and the 8-bit binary counter being composed of 8 D flip-flops for storing the magnitude of the increment value.

6. The fractional-order differential analog-to-digital converter according to claim 5, wherein the increment counter operates as follows: the initial value of the increment is 0Δ; when the comparator output is positive, it is determined that the signal to be acquired is greater than the signal to be compared, then the increment counter is incremented by 1Δ, the sign register is positive, and the increment value becomes (0+1)Δ; when the comparator output is negative, it is determined that the signal to be acquired is less than the signal to be compared, then the increment counter is decremented by 1Δ, the sign register is negative, and the increment value becomes (0-1)Δ; after each judgment, the increment value is output to the DAC controller to generate DAC control code; the above judgment steps are repeated until the difference between the signal to be acquired and the signal to be compared is less than 1Δ, at which point the loop stops, and the sign in the sign register and the value in the 8-bit binary counter are concatenated to obtain the final fractional-order increment value.

7. The fractional-order differential analog-to-digital converter according to claim 1, wherein the serialized bitstream generator comprises an event judge, an event register, a finite state machine, a bitstream clock generator, and a bitstream packer.

8. The fractional-order differential analog-to-digital converter according to claim 7, wherein the serialized bitstream generator operates at each global clock CLK. ADC On the rising edge, the event judge reads the increment value from the increment counter and determines whether the increment value forms a fractional increment event. When the increment value is not 0Δ, it indicates that the currently acquired signal is different from the signal to be compared, and it can be determined as a fractional increment event; at this time, the increment value is stored in the event register. After all L channels have completed one acquisition, a complete data acquisition frame is formed; After each acquisition frame is completed, the finite state machine generates an enable signal ENA and inputs it to the bitstream clock generator; this clock generator has a built-in ring oscillator specifically designed to provide the clock CLK for bitstream packetization. BIT ; Subsequently, the finite state machine scans the data in the event register and, based on CLK... BIT The clock is used to pack the bit stream, ultimately generating the FOD-ADC data bit stream.

9. The fractional-order differential analog-to-digital converter according to claim 1, wherein the DAC is implemented using an 8-bit capacitor voltage divider structure; and the comparator is implemented using a dynamic comparator.

10. The fractional-order differential analog-to-digital converter according to claim 1, wherein the computation matrix consists of a series of multiplication units.

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