Filter and filter manufacturing method

Abstract

Disclosed in the present invention are a filter and a filter manufacturing method. A piezoelectric layer is provided with an opening in a connection region between a series bulk acoustic wave resonator and a parallel bulk acoustic wave resonator that are adjacent to each other. A dielectric layer of a capacitor is filled in the opening. The series bulk acoustic wave resonator further comprises a first lower electrode located on the side of the piezoelectric layer close to a substrate and a first upper electrode located on the side of the piezoelectric layer away from the substrate. The parallel bulk acoustic wave resonator comprises a second lower electrode located on the side of the piezoelectric layer close to the substrate and a second upper electrode located on the side of the piezoelectric layer away from the substrate. The capacitor comprises a third lower electrode and a third upper electrode, which are located in the connection region. The third upper electrode is electrically connected to the first upper electrode and the second upper electrode, and the third lower electrode is electrically connected to the second lower electrode. In this way, by means of connecting the capacitor in parallel in the connection region between the adjacent series bulk acoustic wave resonator and parallel bulk acoustic wave resonator, the in-band insertion loss and out-of-band suppression of the filter can be effectively improved; moreover, no additional chip space is occupied.

Description

A filter and a method for fabricating the filter.

[0001] Cross-reference to related applications

[0002] This application claims priority to Chinese Patent Application No. 202411555701.1, filed on November 1, 2024, entitled "A Filter and a Method for Preparing a Filter", the entire contents of which are incorporated herein by reference. Technical Field

[0003] This application relates to the field of radio frequency filtering technology, and more specifically, to a filter and a method for fabricating the filter. Background Technology

[0004] Radio frequency (RF) filters are key components in 5G and 6G wireless communication and signal processing systems, used to select or suppress signals within a specific frequency range. Film bulk acoustic resonators (FBARs) are fundamental components in RF filters. Generally, by connecting at least two FBARs of different frequencies in a ladder or lattice configuration, a filter with bandpass filtering capabilities can be constructed.

[0005] While adding external matching circuits can improve filter performance in existing technologies, it also introduces several drawbacks: First, the additional circuitry occupies substrate space, increasing the package size of the filter chip. Second, conventional methods in existing technologies can generally broaden bandwidth and improve out-of-band rejection, but these typically sacrifice some of the filter's insertion loss.

[0006] Application content

[0007] This invention provides a filter and a method for fabricating the filter. By connecting a capacitor in parallel in the connection region of adjacent series acoustic resonators and parallel acoustic resonators, the in-band insertion loss and out-of-band rejection of the filter can be effectively improved, while not occupying extra chip space.

[0008] In a first aspect, embodiments of the present invention provide a filter, including a substrate, and at least one parallel solid acoustic wave resonator, at least one series solid acoustic wave resonator, and at least one capacitor located on one side of the substrate; both the series solid acoustic wave resonator and the parallel solid acoustic wave resonator include a piezoelectric layer, the piezoelectric layer having an opening in the connection region of adjacent series and parallel solid acoustic wave resonators; the capacitor includes a dielectric layer filling the opening; the series solid acoustic wave resonator further includes a first lower electrode located on the side of the piezoelectric layer near the substrate and a first upper electrode located on the side of the piezoelectric layer away from the substrate, the parallel solid acoustic wave resonator includes a second lower electrode located on the side of the piezoelectric layer near the substrate and a second upper electrode located on the side of the piezoelectric layer away from the substrate, and the capacitor includes a third lower electrode and a third upper electrode located in the connection region; the third upper electrode is electrically connected to the first upper electrode and the second upper electrode respectively, and the third lower electrode is electrically connected to the second lower electrode.

[0009] Optionally, the first upper electrode, the second upper electrode, and the third upper electrode are all disposed in the same layer and integrally formed; the first lower electrode, the second lower electrode, and the third lower electrode are all disposed in the same layer, and the third lower electrode is integrally formed with the second lower electrode.

[0010] Optionally, along the thickness direction of the substrate, the opening penetrates the piezoelectric layer. Let the thickness of the dielectric layer be D1 and the surface area of ​​the dielectric layer be S1. By setting the thickness and surface area of ​​the dielectric layer to satisfy a first relationship, the capacitance value of the capacitor is set within a first preset range. The first relationship includes: C = (ε1 × S1) / D1, where ε1 is the dielectric constant of the dielectric layer and C is the capacitance value of the capacitor. Alternatively, along the thickness direction of the substrate, the opening partially penetrates the piezoelectric layer. Let the maximum thickness of the piezoelectric layer be D2. By setting the thickness, surface area, and maximum thickness of the dielectric layer to satisfy a second relationship, the capacitance value of the capacitor is set within the first preset range. The second relationship includes: C = (ε1 × S1) / D1 + (ε2 × S1) / (D2 - D1), where ε2 is the dielectric constant of the piezoelectric layer. The first preset range includes 0 pf - 100 pf.

[0011] Optionally, the filter includes a trapezoidal topology filter; the trapezoidal topology filter includes a first minimum repeating unit consisting of a parallel solid acoustic resonator, a series solid acoustic resonator, and a capacitor disposed in the connection region.

[0012] Optionally, the filter includes a lattice topology filter; the lattice topology filter includes a second minimum repeating unit composed of two parallel acoustic resonators, two series acoustic resonators, and a capacitor; wherein the two parallel acoustic resonators include a first parallel acoustic resonator and a second parallel acoustic resonator, and the two series acoustic resonators include a first series acoustic resonator and a second series acoustic resonator; the connection region between the first parallel acoustic resonator and the first series acoustic resonator is a first connection region, the connection region between the second parallel acoustic resonator and the second series acoustic resonator is a second connection region, and the capacitor is disposed in the overlapping region of the first connection region and the second connection region.

[0013] Secondly, embodiments of the present invention also provide a method for fabricating a filter, used to fabricate any of the filters described in the first aspect. The fabrication method includes: providing a substrate; fabricating at least one parallel solid acoustic wave resonator, at least one series solid acoustic wave resonator, and at least one capacitor on one side of the substrate; wherein the series solid acoustic wave resonator and the parallel solid acoustic wave resonator each include a piezoelectric layer, the piezoelectric layer having an opening in the connection region between adjacent series and parallel solid acoustic wave resonators; the capacitor includes a dielectric layer filling the opening; the series solid acoustic wave resonator further includes a first lower electrode located on the side of the piezoelectric layer near the substrate and a first upper electrode located on the side of the piezoelectric layer away from the substrate; the parallel solid acoustic wave resonator includes a second lower electrode located on the side of the piezoelectric layer near the substrate and a second upper electrode located on the side of the piezoelectric layer away from the substrate; the capacitor includes a third lower electrode and a third upper electrode located in the connection region; the third upper electrode is electrically connected to the first upper electrode and the second upper electrode respectively, and the third lower electrode is electrically connected to the second lower electrode.

[0014] Optionally, providing the substrate includes: preparing a plurality of cavities in the substrate and filling the cavities with a first sacrificial layer, wherein the cavities at least partially overlap with the first lower electrode or the second lower electrode along the thickness direction of the substrate; and preparing a seed layer on the side of the cavities away from the substrate.

[0015] Optionally, the step of fabricating at least one parallel solid acoustic wave resonator, at least one series solid acoustic wave resonator, and at least one capacitor on one side of the substrate includes: fabricating a full-layer lower electrode layer on one side of the seed layer, and patterning the full-layer lower electrode layer to form a first lower electrode layer, a second lower electrode layer, and a third lower electrode layer, wherein the second lower electrode layer and the third lower electrode layer are integrally disposed; fabricating the piezoelectric layer on the side of the full-layer lower electrode layer away from the substrate, and etching the opening in the connection region of the piezoelectric layer, wherein the opening penetrates at least a portion of the piezoelectric layer along the thickness direction of the substrate; filling the opening with the dielectric layer; fabricating a second sacrificial layer on the side of the piezoelectric layer away from the substrate, and patterning the second sacrificial layer; etching the piezoelectric layer downward to form a first via and a second via on the piezoelectric layer, wherein the first via and the second via are both offset from the cavity along the thickness direction of the substrate, and the first via at least partially overlaps with the first lower electrode, and the second via at least partially overlaps with the second lower electrode.

[0016] Optionally, after etching the piezoelectric layer downwards to form the first via and the second via in the piezoelectric layer, the method further includes: depositing a thickening layer on the side of the second sacrificial layer away from the substrate, and patterning the thickening layer so that the thickening layer at least covers the second sacrificial layer, the dielectric layer, the first via, and the second via; and depositing an integral top electrode layer on the side of the thickening layer away from the substrate to form an integrally disposed first top electrode layer, second top electrode layer, and third top electrode layer.

[0017] Optionally, after depositing an entire upper electrode layer on the side of the thickened layer away from the substrate, the method further includes: preparing a mass load layer on the side of the second upper electrode away from the substrate, wherein the mass load layer at least partially overlaps with the second lower electrode layer along the thickness direction of the substrate; depositing an entire passivation layer on the side of the mass load layer away from the substrate, and patterning the entire passivation layer to expose a portion of the piezoelectric layer in the first region and a portion of the piezoelectric layer in the second region; drilling a third via downwards into the portion of the piezoelectric layer in the first region, and drilling a fourth via downwards into the portion of the piezoelectric layer in the second region, wherein the third via at least partially overlaps with the first lower electrode, and the fourth via at least partially overlaps with the second lower electrode; preparing a protective layer on the first via and the second via; and releasing the cavity and the first sacrificial layer to prepare at least one parallel bulk acoustic resonator, at least one series bulk acoustic resonator, and at least one capacitor.

[0018] The filter in this embodiment of the invention includes at least one parallel PAS resonator, at least one series PAS resonator, and at least one capacitor located on one side of a substrate. Both the series and parallel PAS resonators include a piezoelectric layer, with an opening in the connection region between adjacent series and parallel PAS resonators. The capacitor includes a dielectric layer filling the opening. The series PAS resonator further includes a first lower electrode located on the side of the piezoelectric layer near the substrate and a first upper electrode located on the side of the piezoelectric layer away from the substrate. The parallel PAS resonator includes a second lower electrode located on the side of the piezoelectric layer near the substrate and a second upper electrode located on the side of the piezoelectric layer away from the substrate. The capacitor includes a third lower electrode and a third upper electrode located in the connection region. The third upper electrode is electrically connected to both the first and second upper electrodes, and the third lower electrode is electrically connected to the second lower electrode. Thus, by connecting capacitors in parallel in the connection area of ​​adjacent series acoustic resonators and parallel acoustic resonators, the in-band insertion loss and out-of-band rejection of the filter can be effectively improved. On the other hand, setting capacitors in the connection area will not occupy extra chip space, which is conducive to the miniaturization of the filter. Attached Figure Description

[0019] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 is a schematic diagram of a filter provided in an embodiment of the present invention;

[0021] Figure 2 is the equivalent circuit diagram of the filter provided in Figure 1;

[0022] Figure 3 is a schematic cross-section of Figure 1 along the A-A' direction;

[0023] Figure 4 is a schematic diagram of another filter structure provided in an embodiment of the present invention;

[0024] Figure 5 is the equivalent circuit diagram of the filter provided in Figure 4;

[0025] Figure 6 is a schematic flowchart of a filter fabrication method provided in an embodiment of the present invention;

[0026] Figure 7 is a flowchart illustrating another method for fabricating a filter according to an embodiment of the present invention;

[0027] Figure 8 is a schematic diagram of a preparation process provided by an embodiment of the present invention. Detailed Implementation

[0028] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, the accompanying drawings show only the parts relevant to the present invention, and not all of the structures.

[0029] Figure 1 is a schematic diagram of a filter provided in an embodiment of the present invention, Figure 2 is an equivalent circuit diagram of the filter provided in Figure 1, and Figure 3 is a cross-sectional schematic diagram along the A-A' direction in Figure 1. Referring to Figures 1-3, the filter includes a substrate 01, and at least one parallel solid acoustic wave resonator 20, at least one series solid acoustic wave resonator 10, and at least one capacitor 30 located on one side of the substrate 01. Both the series solid acoustic wave resonator 10 and the parallel solid acoustic wave resonator 20 include a piezoelectric layer 40, and the piezoelectric layer 40 has an opening 410 in the connection region B1 of adjacent series solid acoustic wave resonators 10 and parallel solid acoustic wave resonators 20. The capacitor 30 includes a dielectric layer 310, which fills the opening 410. The series solid acoustic wave resonator 10 also includes a first lower electrode 110 located on the side of the piezoelectric layer 40 near the substrate 01 and a first upper electrode 120 located on the side of the piezoelectric layer 40 away from the substrate 01. The parallel acoustic resonator 20 includes a second lower electrode 210 located on the side of the piezoelectric layer 40 closer to the substrate 01 and a second upper electrode 220 located on the side of the piezoelectric layer 40 away from the substrate 01. The capacitor 30 includes a third lower electrode 320 and a third upper electrode 330 located in the connection region B1. The third upper electrode 330 is electrically connected to the first upper electrode 120 and the second upper electrode 220, respectively, and the third lower electrode 320 is electrically connected to the second lower electrode 220.

[0030] Specifically, referring to Figures 1-3, the filter includes at least one parallel acoustic wave resonator 20, at least one series acoustic wave resonator 10, and at least one capacitor 30. For example, Figure 1 illustrates a trapezoidal topology, where the filter comprises multiple parallel acoustic wave resonators 20 and multiple series acoustic wave resonators 10. Adjacent parallel acoustic wave resonators 20 and series acoustic wave resonators 10 share the same piezoelectric layer 40, and the upper electrodes of the parallel and series acoustic wave resonators 10 are electrically connected. This connection of adjacent parallel and series acoustic wave resonators 20 and series acoustic wave resonators 10 forms a minimum repeating unit of the filter, ensuring that the filter can achieve bandpass filtering functionality.

[0031] In existing technologies, widening the bandwidth of filters is typically achieved by adding external matching circuits, such as connecting independent capacitors or inductors in series or parallel. However, on the one hand, independently placed capacitors or inductors occupy chip space, increasing the filter's package size; on the other hand, while independently placed capacitors or inductors can widen the bandwidth and improve out-of-band rejection, they sacrifice some of the filter's insertion loss, thus negatively impacting the filter's performance.

[0032] To this end, embodiments of the present invention connect a capacitor 10 in parallel within the connection region B1 of adjacent series acoustic wave resonators 10 and parallel acoustic wave resonators 20. Specifically, since adjacent series acoustic wave resonators 10 and parallel acoustic wave resonators 20 share the same piezoelectric layer 40, an opening 410 is provided in the connection region B1 of the series acoustic wave resonators 10 and parallel acoustic wave resonators 20 within the piezoelectric layer 40, and a dielectric layer is filled in the opening 410 to form the dielectric layer 310 of the capacitor 30. Furthermore, the series acoustic wave resonator 10 also includes a first lower electrode 110 and a first upper electrode 120. The first lower electrode 110 is located on the side of the piezoelectric layer 40 in the series acoustic wave resonator 10 closer to the substrate 01, and the first upper electrode 120 is located on the side of the piezoelectric layer 40 in the series acoustic wave resonator 10 farther from the substrate 01. The parallel acoustic wave resonator 20 also includes a second lower electrode 210 and a second upper electrode 220. In this embodiment, the second lower electrode 210 is located on the side of the piezoelectric layer 40 in the parallel acoustic resonator 20 closer to the substrate 01, and the second upper electrode 220 is located on the side of the piezoelectric layer 40 in the parallel acoustic resonator 20 away from the substrate 01. In one embodiment, the first upper electrode 120 and the second upper electrode 220 can be integrally formed, i.e., formed in the same process. Furthermore, the portion of the first upper electrode 120 and the second upper electrode 220 in the connection region B1 can be used as the third upper electrode 230 of the capacitor 30, thus achieving electrical connection between the first upper electrode 120, the second upper electrode 220, and the third upper electrode 330. The first lower electrode 110 and the second lower electrode 210 are independent, meaning that the first lower electrode 110 and the second lower electrode 210 are insulated from each other. This allows for the fabrication of the third lower electrode 320 of the capacitor 30 on the side of the dielectric layer 310 near the substrate 01 in the connection region B1. The third lower electrode 320 is electrically connected to the second lower electrode 210, thus allowing the capacitor 30 to be connected in parallel in the connection region B1 of the adjacent series acoustic resonator 10 and parallel acoustic resonator 20. In this way, the capacitor 30 is based on the existing film layer in the connection region B1; that is, the capacitor 30 utilizes the existing film layer to create an inductive region, rather than introducing a new independent device (a physical capacitor). Since no independent capacitor or inductor is introduced, the in-band insertion loss and out-of-band rejection of the filter can be effectively improved, while avoiding the need for additional chip space, thereby facilitating the miniaturization of the filter.

[0033] It should be noted that, in this embodiment of the invention, since the substrate is disposed in the filter, and a cavity is also disposed in the substrate 01, the normal operation of the filter can be guaranteed.

[0034] It should also be noted that Figures 1-3 are only illustrated using a trapezoidal topology filter as an example, but this is not a limitation. In other embodiments, the filter can be other types of topology, which can be set by those skilled in the art as needed.

[0035] In summary, the filter in this embodiment of the invention includes at least one parallel PAS resonator, at least one series PAS resonator, and at least one capacitor located on one side of the substrate. Both the series and parallel PAS resonators include a piezoelectric layer, with an opening in the connection region between adjacent series and parallel PAS resonators. The capacitor includes a dielectric layer filling the opening. The series PAS resonator further includes a first lower electrode located on the side of the piezoelectric layer near the substrate and a first upper electrode located on the side of the piezoelectric layer away from the substrate. The parallel PAS resonator includes a second lower electrode located on the side of the piezoelectric layer near the substrate and a second upper electrode located on the side of the piezoelectric layer away from the substrate. The capacitor includes a third lower electrode and a third upper electrode located in the connection region. The third upper electrode is electrically connected to both the first and second upper electrodes, and the third lower electrode is electrically connected to the second lower electrode. Thus, by connecting capacitors in parallel in the connection area of ​​adjacent series acoustic resonators and parallel acoustic resonators, the in-band insertion loss and out-of-band rejection of the filter can be effectively improved. On the other hand, setting capacitors in the connection area will not occupy extra chip space, which is conducive to the miniaturization of the filter.

[0036] Optionally, based on the above embodiments, referring to Figure 3, the first upper electrode 120, the second upper electrode 220, and the third upper electrode 330 are all integrally formed on the same layer. During fabrication, the first upper electrode 120, the second upper electrode 220, and the third upper electrode 330 can be formed using the same mask in the same fabrication process, eliminating the need to fabricate separate masks for each electrode, thus saving costs, reducing the number of processes, and improving production efficiency. The first lower electrode 110, the second lower electrode 210, and the third lower electrode 320 are all integrally formed on the same layer, and the third lower electrode 320 is integrally formed with the second lower electrode 210. During fabrication, the first lower electrode 110, the second lower electrode 210, and the third lower electrode 320 can be formed using the same mask in the same fabrication process, eliminating the need to fabricate separate masks for each electrode, thus saving costs, reducing the number of processes, and improving production efficiency.

[0037] Optionally, based on the above embodiments, referring to Figure 3, an opening 410 penetrates the piezoelectric layer 40 along the thickness direction of the substrate 01. The thickness of the dielectric layer 310 is denoted as D1, and its surface area as S1. By setting the thickness and surface area of ​​the dielectric layer 310 to satisfy a first relationship, the capacitance value of the capacitor 30 is set within a first preset range. The first relationship includes: C = (ε1 × S1) / D1, where ε1 is the dielectric constant of the dielectric layer 310, and C is the capacitance value of the capacitor 30. Specifically, when the opening 410 penetrates the piezoelectric layer 40, the capacitance value of the capacitor 30 is related to the thickness D1 and surface area S1 of the dielectric layer 310. That is, by adjusting the thickness and surface area of ​​the dielectric layer 310 to satisfy the first relationship, the capacitance value of the capacitor 30 can be made within the range of 0pf-100pf, thereby ensuring that when the capacitor 30 is connected in parallel in the connection region B1, the in-band insertion loss and out-of-band rejection of the filter are effectively improved.

[0038] In another embodiment, an opening 410 penetrates a portion of the piezoelectric layer 40 along the thickness direction of the substrate 01. The maximum thickness of the piezoelectric layer 40 is denoted as D2. By setting the thickness of the dielectric layer 310, the surface area of ​​the dielectric layer 310, and the maximum thickness of the piezoelectric layer 40 to satisfy a second relationship, the capacitance value of the capacitor 30 is set within a first preset range. The second relationship includes: C = (ε1 × S1) / D1 + (ε2 × S1) / (D2 - D1), where ε2 is the dielectric constant of the piezoelectric layer 40. Specifically, when the opening 410 penetrates part of the piezoelectric layer 40, the area between the third upper electrode 320 and the third lower electrode 330 includes not only the dielectric layer 310 but also part of the piezoelectric layer 40. Consequently, the capacitance value of the capacitor 30 is related to the thickness D1 and surface area S1 of the dielectric layer 310, as well as the thickness (D2-D1) and surface area (S1) of the piezoelectric layer 40 overlapping with the opening 410. That is, the thickness D1 and surface area S1 of the dielectric layer 310, as well as the thickness (D2-D1) and surface area (S1) of the piezoelectric layer 40 overlapping with the opening 410, can be adjusted to satisfy the second relationship, thereby setting the capacitance value of the capacitor 30 within the range of 0pf-100pf. This ensures that when the capacitor 30 is connected in parallel in the connection area B1, the in-band insertion loss and out-of-band rejection of the filter are effectively improved.

[0039] Optionally, based on the above embodiments, referring to Figures 1-3, the filter includes a trapezoidal topology filter. The trapezoidal topology filter includes a first minimum repeating unit composed of a parallel solid acoustic resonator 20, a series solid acoustic resonator 10, and a capacitor 30 disposed in the connection region B1. Specifically, as shown in Figure 1, a capacitor 30 is connected in parallel in the connection region B1 of adjacent parallel solid acoustic resonators 20 and series solid acoustic resonators 10 to form a first minimum repeating unit. The trapezoidal topology filter includes multiple first minimum repeating units. This improves the in-band insertion loss and out-of-band rejection of the trapezoidal topology filter while maintaining its original characteristics.

[0040] Optionally, Figure 4 is a schematic diagram of another filter structure provided in an embodiment of the present invention, and Figure 5 is an equivalent circuit diagram of the filter provided in Figure 4. Referring to Figures 4 and 5, the filter includes a lattice topology filter. The lattice topology filter includes a second minimum repeating unit composed of two parallel acoustic resonators 20, two series acoustic resonators 10, and a capacitor 30. The two parallel acoustic resonators 20 include a first parallel acoustic resonator 201 and a second parallel acoustic resonator 202, and the two series acoustic resonators 10 include a first series acoustic resonator 101 and a second series acoustic resonator 102. The connection region B1 between the first parallel acoustic resonator 201 and the first series acoustic resonator 101 is a first connection region B11, and the connection region B1 between the second parallel acoustic resonator 202 and the second series acoustic resonator 102 is a second connection region B12. The capacitor 30 is disposed in the overlapping region of the first connection region B11 and the second connection region B12.

[0041] Specifically, as shown in Figures 4 and 5, the lattice topology filter includes two series acoustic resonators 10 on the upper side, namely a first series acoustic resonator 101 and a second series acoustic resonator 102, and two parallel acoustic resonators 20 on the lower side, namely a first parallel acoustic resonator 201 and a second parallel acoustic resonator 202. The two series acoustic resonators 10 on the upper side and the two parallel acoustic resonators 20 on the lower side are cross-connected electrically, that is, the connection area B1 between the first parallel acoustic resonator 201 and the first series acoustic resonator 101 is the first connection area B11, and the connection area B1 between the second parallel acoustic resonator 202 and the second series acoustic resonator 102 is the second connection area B12. The capacitor 30 is disposed in the overlapping area of ​​the first connection area B11 and the second connection area B12. Thus, by having two parallel acoustic resonators 20 and two series acoustic resonators 10 share the same capacitor 30 in the second minimum repeating unit, the in-band insertion loss and out-of-band rejection of the trapezoidal topology filter are improved while ensuring the original characteristics of the lattice topology filter.

[0042] Based on the same inventive concept, this invention also provides a method for fabricating a filter. Figure 6 is a schematic flowchart of a filter fabrication method provided by this invention. Referring to Figure 6, the fabrication method includes:

[0043] S110 provides a substrate.

[0044] Specifically, the substrate material can be sapphire (Al2O3), silicon carbide (SiC), silicon (Si), etc. This invention does not limit the specific substrate material; those skilled in the art can set it as needed.

[0045] S120. At least one parallel solid acoustic resonator, at least one series solid acoustic resonator, and at least one capacitor are fabricated on one side of the substrate.

[0046] Specifically, both the series and parallel bulk acoustic wave resonators include a piezoelectric layer, with openings in the connection regions of adjacent series and parallel bulk acoustic wave resonators. The capacitor includes a dielectric layer filling the openings. The series bulk acoustic wave resonator also includes a first lower electrode located on the side of the piezoelectric layer closest to the substrate and a first upper electrode located on the side of the piezoelectric layer furthest from the substrate. The parallel bulk acoustic wave resonator includes a second lower electrode located on the side of the piezoelectric layer closest to the substrate and a second upper electrode located on the side of the piezoelectric layer furthest from the substrate. The capacitor includes a third lower electrode and a third upper electrode located in the connection region. The third upper electrode is electrically connected to both the first and second upper electrodes, and the third lower electrode is electrically connected to the second lower electrode.

[0047] For example, a trapezoidal topology is used, where the filter comprises multiple parallel and multiple series acoustic wave resonators. In this embodiment, a capacitor is connected in parallel to the connection region of adjacent series and parallel acoustic wave resonators. Specifically, since adjacent series and parallel acoustic wave resonators share the same piezoelectric layer, an opening can be formed in the connection region of the series and parallel resonators within the piezoelectric layer, and a dielectric layer can be filled into the opening to form the dielectric layer of the capacitor. Furthermore, the series acoustic wave resonator also includes a first lower electrode and a first upper electrode. The first lower electrode is located on the side of the piezoelectric layer closer to the substrate, and the first upper electrode is located on the side of the piezoelectric layer farther from the substrate. The parallel acoustic wave resonator also includes a second lower electrode and a second upper electrode. The second lower electrode is located on the side of the piezoelectric layer closer to the substrate, and the second upper electrode is located on the side of the piezoelectric layer farther from the substrate. In one embodiment, the first upper electrode and the second upper electrode can be integrally formed, i.e., formed in the same process. The portion of the first and second upper electrodes in the connection region can then serve as the third upper electrode of the capacitor, achieving electrical connection between the first, second, and third upper electrodes. The first and second lower electrodes are independent, i.e., insulated from each other. The third lower electrode of the capacitor can then be fabricated on the side of the dielectric layer near the substrate in the connection region, and electrically connected to the second lower electrode. This allows the capacitor to be connected in parallel in the connection region of adjacent series and parallel bulk acoustic wave resonators. Thus, the capacitor is based on the existing film layer in the connection region; the capacitor utilizes the existing film layer to create an inductive region, rather than introducing a new independent device (a physical capacitor). Since no independent capacitor or inductor is introduced, it effectively improves the in-band insertion loss and out-of-band rejection of the filter, while not occupying extra chip space, thereby facilitating the miniaturization of the filter.

[0048] In summary, in this embodiment of the invention, the piezoelectric layer has an opening in the connection region of adjacent series and parallel PAS resonators. The dielectric layer of the capacitor fills the opening. The series PAS resonator also includes a first lower electrode located on the side of the piezoelectric layer closer to the substrate and a first upper electrode located on the side of the piezoelectric layer farther from the substrate. The parallel PAS resonator includes a second lower electrode located on the side of the piezoelectric layer closer to the substrate and a second upper electrode located on the side of the piezoelectric layer farther from the substrate. The capacitor includes a third lower electrode and a third upper electrode located in the connection region. The third upper electrode is electrically connected to the first upper electrode and the second upper electrode, respectively, and the third lower electrode is electrically connected to the second lower electrode. Thus, by connecting a capacitor in parallel in the connection region of adjacent series and parallel PAS resonators, the in-band insertion loss and out-of-band rejection of the filter can be effectively improved on the one hand, and the extra chip space is not occupied on the other hand.

[0049] Optionally, Figure 7 is a schematic flowchart of another filter fabrication method provided by an embodiment of the present invention, and Figure 8 is a schematic flowchart of a fabrication process provided by an embodiment of the present invention. Referring to Figures 7 and 8, the fabrication method includes:

[0050] S210. Multiple cavities are prepared in the substrate, and a first sacrificial layer is filled in the cavities. A seed layer is prepared on the side of the cavity away from the substrate.

[0051] Specifically, holes are drilled in the substrate 01 to form cavities in the regions of the substrate 01 corresponding to the series PAS resonator 10 and the parallel PAS resonator 20, respectively. For example, along the thickness direction of the substrate 01, when the cavity at least partially overlaps with the first lower electrode 110, the cavity corresponds to the series PAS resonator 10; and when the cavity at least partially overlaps with the second lower electrode 210, the cavity corresponds to the parallel PAS resonator 20. A first sacrificial layer 510 is then filled into the cavity. The sacrificial layer 510 material can include SiO2, silicate glass PSG, Si3N4, etc. A seed layer 520 is then deposited on the side of the cavity (first sacrificial layer 510) away from the substrate 01. The seed layer 520 ensures that the subsequently formed piezoelectric thin film has good crystal orientation.

[0052] S220. Prepare a full-layer lower electrode layer on one side of the seed layer and pattern the full-layer lower electrode layer to form a first lower electrode layer, a second lower electrode layer and a third lower electrode layer. Prepare a piezoelectric layer on the side of the full-layer lower electrode layer away from the substrate and etch an opening in the connection region of the piezoelectric layer and fill the opening with a dielectric layer.

[0053] Specifically, a full-layer lower electrode layer is deposited on the side of the seed layer 520 away from the substrate 01. The material of this full-layer lower electrode layer can be at least one of the following metals: molybdenum (Mo), aluminum (Al), copper (Cu), tungsten (W), tantalum (Ta), platinum (Pt), ruthenium (Ru), rhodium (Rh), iridium (Ir), chromium (Cr), titanium (Ti), gold (Au), osmium (Os), rhenium (Re), and palladium (Pd). The full-layer lower electrode layer is then patterned to form a first lower electrode 110 at the corresponding position of the series bulk acoustic wave resonator 10, a second lower electrode 210 at the corresponding position of the parallel bulk acoustic wave resonator 20, and a third lower electrode 320 at the corresponding position of the capacitor 30. It is understood that, in the embodiment shown in FIG8, the second lower electrode 210 and the third lower electrode 320 are integrally formed. Next, a full-length piezoelectric layer 40 is fabricated on one side of the first lower electrode 110 and the second lower electrode 210, and an opening 410 is etched in the connection region B1 of the piezoelectric layer 40, extending through at least a portion of the piezoelectric layer 40 along the thickness direction of the substrate 01. The material of the piezoelectric layer 40 can be at least one of aluminum nitride (AlN), lithium niobate (LiNbO3), lithium tantalate (LiTaO3), lead zirconate titanate (PZT), zinc oxide (ZnO), scandium-doped aluminum nitride (ScAlN), quartz crystal (Quatz), lead magnesium niobate (PMN), and lead fluoride (PbTiO3). Finally, a dielectric layer material is filled into the opening 410 to form the dielectric layer 310 of the capacitor 30 within the opening 410.

[0054] S230. A second sacrificial layer is prepared on the side of the piezoelectric layer away from the substrate, and the second sacrificial layer is patterned. The piezoelectric layer is etched downward to form a first via and a second via in the piezoelectric layer.

[0055] Specifically, a second sacrificial layer 530 is deposited on the side of the piezoelectric layer 40 away from the substrate 01, and the second sacrificial layer 530 is patterned to form symmetrical second sacrificial layer patterns on the series bulk acoustic wave resonator 10 and the parallel bulk acoustic wave resonator 20, respectively. Then, a first via 540 is formed in the piezoelectric layer 40 at a position corresponding to the series bulk acoustic wave resonator 10, offset from the cavity along the thickness direction of the substrate 01; and a second via 550 is formed in the piezoelectric layer 40 at a position corresponding to the parallel bulk acoustic wave resonator 20, offset from the cavity along the thickness direction of the substrate 01. The first via 540 and the second via 550 expose the first lower electrode 110 and the second lower electrode 210, respectively.

[0056] S240, a thickening layer is deposited on the side of the second sacrificial layer away from the substrate, and the thickening layer is patterned. An entire top electrode layer is deposited on the side of the thickening layer away from the substrate to form an integrally disposed first top electrode layer, second top electrode layer, and third top electrode layer.

[0057] Specifically, a thickening layer 560 is deposited on the side of the second sacrificial layer 530 away from the substrate 01, and the thickening layer 560 is patterned so that the thickening layer 560 at least covers the second sacrificial layer 530, the dielectric layer 310, the first via 540, and the second via 550. Thus, the Q value of the filter is improved by setting the thickening layer 560. Then, a whole-layer top electrode layer is deposited on the side of the thickening layer 560 away from the substrate, and the whole-layer top electrode layer is patterned to form an integrally formed first top electrode layer 120, second top electrode layer 220, and third top electrode layer 330. The material of the whole-layer top electrode layer can be at least one of the following metals: molybdenum (Mo), aluminum (Al), copper (Cu), tungsten (W), tantalum (Ta), platinum (Pt), ruthenium (Ru), rhodium (Rh), iridium (Ir), chromium (Cr), titanium (Ti), gold (Au), osmium (Os), rhenium (Re), and palladium (Pd).

[0058] S250. A mass load layer is prepared on the side of the second upper electrode away from the substrate. A full passivation layer is deposited on the side of the mass load layer away from the substrate. The full passivation layer is patterned so that the passivation layer exposes a portion of the piezoelectric layer in the first region and a portion of the piezoelectric layer in the second region. A third via is formed by drilling holes downward in the portion of the piezoelectric layer in the first region, and a fourth via is formed by drilling holes downward in the portion of the piezoelectric layer in the second region.

[0059] Specifically, a mass load layer 570 is prepared on the side of the second upper electrode 220 away from the substrate 01. Along the thickness direction of the substrate 01, the mass load layer 570 at least partially overlaps with the second lower electrode layer 210, i.e., the mass load layer 570 is disposed on the corresponding parallel bulk acoustic wave resonator 20 to adjust the frequency of the parallel bulk acoustic wave resonator 20. Then, a full-layer passivation layer is deposited on the side of the mass load layer 570 away from the substrate 01 to protect the surface-mounted device from oxidation. The full-layer passivation layer is patterned so that the patterned passivation layer 580 exposes a portion of the piezoelectric layer in the first region and a portion of the piezoelectric layer in the second region. A third via 610 is formed by drilling downwards into the portion of the piezoelectric layer in the first region, and a fourth via 620 is formed by drilling downwards into the portion of the piezoelectric layer in the second region. The third via 610 and the fourth via 640 are release vias. For example, the third via 610 at least partially overlaps with the first lower electrode 110, that is, the third via 610 corresponds to the series acoustic resonator 10, and the fourth via 620 at least partially overlaps with the second lower electrode 210, that is, the fourth via 620 corresponds to the parallel acoustic resonator 20. This embodiment of the invention does not limit the specific process sequence of the release holes; those skilled in the art can configure it as needed.

[0060] S260. A protective layer is prepared on the first via and the second via, and a cavity and a first sacrificial layer are released to prepare at least one parallel acoustic resonator, at least one series acoustic resonator, and at least one capacitor.

[0061] In summary, in this embodiment of the invention, the piezoelectric layer has an opening in the connection region of adjacent series and parallel PAS resonators. The dielectric layer of the capacitor fills the opening. The series PAS resonator further includes a first lower electrode located on the side of the piezoelectric layer closer to the substrate and a first upper electrode located on the side of the piezoelectric layer farther from the substrate. The parallel PAS resonator includes a second lower electrode located on the side of the piezoelectric layer closer to the substrate and a second upper electrode located on the side of the piezoelectric layer farther from the substrate. The capacitor includes a third lower electrode and a third upper electrode located in the connection region. The third upper electrode is electrically connected to the first upper electrode and the second upper electrode, respectively, and the third lower electrode is electrically connected to the second lower electrode. Thus, by connecting a capacitor in parallel in the connection region of adjacent series and parallel PAS resonators, the in-band insertion loss and out-of-band rejection of the filter can be effectively improved, while not occupying extra chip space.

[0062] Note that the above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions can be made without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of the present invention, the scope of which is determined by the scope of the appended claims. Industrial applicability

[0063] The filter in this embodiment of the invention includes at least one parallel PAS resonator, at least one series PAS resonator, and at least one capacitor located on one side of a substrate. Both the series and parallel PAS resonators include a piezoelectric layer, with an opening in the connection region between adjacent series and parallel PAS resonators. The capacitor includes a dielectric layer filling the opening. The series PAS resonator further includes a first lower electrode located on the side of the piezoelectric layer near the substrate and a first upper electrode located on the side of the piezoelectric layer away from the substrate. The parallel PAS resonator includes a second lower electrode located on the side of the piezoelectric layer near the substrate and a second upper electrode located on the side of the piezoelectric layer away from the substrate. The capacitor includes a third lower electrode and a third upper electrode located in the connection region. The third upper electrode is electrically connected to both the first and second upper electrodes, and the third lower electrode is electrically connected to the second lower electrode. Thus, by connecting capacitors in parallel in the connection area of ​​adjacent series acoustic resonators and parallel acoustic resonators, the in-band insertion loss and out-of-band rejection of the filter can be effectively improved. On the other hand, setting capacitors in the connection area will not occupy extra chip space, which is conducive to the miniaturization of the filter.

Claims

1. A filter, characterized in that, It includes a substrate, and at least one parallel solid acoustic wave resonator, at least one series solid acoustic wave resonator, and at least one capacitor located on one side of the substrate. Both the series acoustic resonator and the parallel acoustic resonator include a piezoelectric layer, and the piezoelectric layer has an opening in the connection region of adjacent series and parallel acoustic resonators; the capacitor includes a dielectric layer that fills the opening; the series acoustic resonator further includes a first lower electrode located on the side of the piezoelectric layer near the substrate and a first upper electrode located on the side of the piezoelectric layer away from the substrate; the parallel acoustic resonator includes a second lower electrode located on the side of the piezoelectric layer near the substrate and a second upper electrode located on the side of the piezoelectric layer away from the substrate; the capacitor includes a third lower electrode and a third upper electrode located in the connection region; the third upper electrode is electrically connected to the first upper electrode and the second upper electrode respectively, and the third lower electrode is electrically connected to the second lower electrode.

2. The filter according to claim 1, characterized in that, The first upper electrode, the second upper electrode, and the third upper electrode are all disposed in the same layer and integrally formed; the first lower electrode, the second lower electrode, and the third lower electrode are all disposed in the same layer, and the third lower electrode is integrally formed with the second lower electrode.

3. The filter according to claim 1, characterized in that, Along the thickness direction of the substrate, the opening penetrates the piezoelectric layer. Let the thickness of the dielectric layer be D1, and the surface area of ​​the dielectric layer be S1. By setting the thickness and surface area of ​​the dielectric layer to satisfy a first relationship, the capacitance value of the capacitor is set within a first preset range. The first relationship includes: C = (ε1 × S1) / D1, where ε1 is the dielectric constant of the dielectric layer, and C is the capacitance value of the capacitor. Alternatively, along the thickness direction of the substrate, the opening partially penetrates the piezoelectric layer. Let the maximum thickness of the piezoelectric layer be D2. By setting the thickness, surface area, and maximum thickness of the dielectric layer to satisfy a second relationship, the capacitance value of the capacitor is set within the first preset range. The second relationship includes: C = (ε1 × S1) / D1 + (ε2 × S1) / (D2 - D1), where ε2 is the dielectric constant of the piezoelectric layer. The first preset range includes 0 pf - 100 pf.

4. The filter according to claim 1, characterized in that, The filter includes a trapezoidal topology filter; the trapezoidal topology filter includes a first minimum repeating unit consisting of a parallel solid acoustic resonator, a series solid acoustic resonator, and a capacitor disposed in the connection region.

5. The filter according to claim 1, characterized in that, The filter includes a lattice topology filter; the lattice topology filter includes a second minimum repeating unit composed of two parallel acoustic resonators, two series acoustic resonators, and a capacitor; wherein the two parallel acoustic resonators include a first parallel acoustic resonator and a second parallel acoustic resonator, and the two series acoustic resonators include a first series acoustic resonator and a second series acoustic resonator; the connection region between the first parallel acoustic resonator and the first series acoustic resonator is a first connection region, the connection region between the second parallel acoustic resonator and the second series acoustic resonator is a second connection region, and the capacitor is disposed in the overlapping region of the first connection region and the second connection region.

6. A method for fabricating a filter, characterized in that, Used to manufacture the filter according to any one of claims 1-5; The preparation method includes: Provide substrate; At least one parallel solid acoustic wave resonator, at least one series solid acoustic wave resonator, and at least one capacitor are fabricated on one side of the substrate; wherein, both the series solid acoustic wave resonator and the parallel solid acoustic wave resonator include a piezoelectric layer, and the piezoelectric layer has an opening in the connection region of adjacent series solid acoustic wave resonators and parallel solid acoustic wave resonators; the capacitor includes a dielectric layer, and the dielectric layer fills the opening; the series solid acoustic wave resonator further includes a first lower electrode located on the side of the piezoelectric layer near the substrate and a first upper electrode located on the side of the piezoelectric layer away from the substrate, the parallel solid acoustic wave resonator includes a second lower electrode located on the side of the piezoelectric layer near the substrate and a second upper electrode located on the side of the piezoelectric layer away from the substrate, and the capacitor includes a third lower electrode and a third upper electrode located in the connection region; the third upper electrode is electrically connected to the first upper electrode and the second upper electrode respectively, and the third lower electrode is electrically connected to the second lower electrode.

7. The preparation method according to claim 6, characterized in that, The substrate provided includes: A plurality of cavities are formed in the substrate and a first sacrificial layer is filled in the cavities, wherein the cavities at least partially overlap with the first lower electrode or the second lower electrode along the thickness direction of the substrate; A seed layer is prepared on the side of the cavity away from the substrate.

8. The preparation method according to claim 7, characterized in that, The fabrication of at least one parallel bulk acoustic resonator, at least one series bulk acoustic resonator, and at least one capacitor on one side of the substrate includes: A whole-layer lower electrode layer is prepared on one side of the seed layer, and the whole-layer lower electrode layer is patterned to form a first lower electrode layer, a second lower electrode layer and a third lower electrode layer, wherein the second lower electrode layer and the third lower electrode layer are integrally disposed; The piezoelectric layer is prepared on the side of the lower electrode layer away from the substrate, and the opening is etched in the connection region of the piezoelectric layer, wherein the opening penetrates at least a portion of the piezoelectric layer along the thickness direction of the substrate. The dielectric layer is filled into the opening; A second sacrificial layer is prepared on the side of the piezoelectric layer away from the substrate, and the second sacrificial layer is patterned. The piezoelectric layer is etched downwards to form a first via and a second via in the piezoelectric layer. Along the thickness direction of the substrate, the first via and the second via are both offset from the cavity, and the first via at least partially overlaps with the first lower electrode, and the second via at least partially overlaps with the second lower electrode.

9. The preparation method according to claim 8, characterized in that, After etching the piezoelectric layer downwards to form the first and second vias in the piezoelectric layer, the process further includes: A thickening layer is deposited on the side of the second sacrificial layer away from the substrate, and the thickening layer is patterned such that the thickening layer at least covers the second sacrificial layer, the dielectric layer, the first via, and the second via; An integral top electrode layer is deposited on the side of the thickened layer away from the substrate to form an integrally formed first top electrode layer, second top electrode layer, and third top electrode layer.

10. The preparation method according to claim 9, characterized in that, After depositing the entire top electrode layer on the side of the thickened layer away from the substrate, the method further includes: A mass load layer is formed on the side of the second upper electrode away from the substrate, and the mass load layer overlaps at least partially with the second lower electrode layer along the thickness direction of the substrate; A full passivation layer is deposited on the side of the mass load layer away from the substrate, and the full passivation layer is patterned to expose a portion of the piezoelectric layer in the first region and a portion of the piezoelectric layer in the second region. A third via is formed by drilling a hole downward in the portion of the piezoelectric layer in the first region, and a fourth via is formed by drilling a hole downward in the portion of the piezoelectric layer in the second region. The third via overlaps at least partially with the first lower electrode, and the fourth via overlaps at least partially with the second lower electrode. A protective layer is prepared on the first via and the second via; Release the cavity and the first sacrificial layer to prepare at least one parallel acoustic resonator, at least one series acoustic resonator, and at least one capacitor.

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