Shift register and driving method therefor, gate driving circuit, and display device

Abstract

The present application relates to the technical field of display, and provides a shift register and a driving method therefor, a gate driving circuit, and a display device. The shift register comprises: an input circuit, a first control circuit, and an output circuit; the input circuit is separately connected to an input signal line and a first node, and is configured to write an input signal into the first node under the control of an input signal of the input signal line; the first control circuit is separately electrically connected to the first node and a first power signal line, and is configured to disconnect the first power signal line from the first node in a touch stage; and the output circuit is separately electrically connected to the first node, a clock signal line, and an output signal line, and is configured to write a clock signal of the clock signal line into the output signal line under the control of a voltage of the first node. The horizontal stripe defects of display panels can be ameliorated, and the image quality of the display panels can be improved.

Description

Shift registers and their driving methods, gate driving circuits and display devices

[0001] Cross-references to related applications

[0002] This application claims priority to Chinese Patent Application No. 202411535959.5, filed on October 30, 2024, entitled "Shift Register and Driving Method Thereof, Gate Driving Circuit and Display Device", the entire contents of which are incorporated herein by reference. Technical Field

[0003] This application relates to the field of display technology, and in particular to a shift register and its driving method, gate driving circuit and display device. Background Technology

[0004] As users increasingly demand more diverse functions from computer products such as laptops (Notebooks, NBs), and as the application of functions such as finger touch and active pen touch becomes more widespread, the advantages of embedded touch, such as In-cell Touch display panels, are becoming increasingly prominent.

[0005] Embedded touch typically employs an in-frame touch (LHB) mode that alternates between a display phase and a touch phase. During the touch phase, the pull-up node (PU) voltage of the outgoing row needs to be kept high until the end of the touch phase, so that the shift register can output signals normally.

[0006] However, due to transistor leakage in the PU nodes of the current shift register, the voltage of the PU node in the row that enters the pit is lower than that of the PU node in the row that does not enter the pit when it leaves the pit. This causes the output signal of the shift register to decrease, resulting in insufficient charging of the corresponding pixel row and causing poor horizontal stripe quality on the display panel. Summary of the Invention

[0007] This application provides a shift register and its driving method, gate driving circuit and display device, which can solve the problem of horizontal lines on the display panel caused by voltage drop at the PU node of the shift register during the touch stage.

[0008] In a first aspect, this application provides a shift register, which includes: an input circuit, a first control circuit, and an output circuit;

[0009] The input circuit is connected to the input signal line and the first node respectively, and is configured to write the input signal into the first node under the control of the input signal on the input signal line;

[0010] The first control circuit is electrically connected to the first node and the first power signal line respectively, and is configured to disconnect the connection between the first power signal line and the first node during the touch phase.

[0011] The output circuit is electrically connected to the first node, the clock signal line, and the output signal line, respectively, and is configured to write the clock signal of the clock signal line into the output signal line under the control of the voltage of the first node.

[0012] Optionally, the first control circuit includes a reset module and a pull-down module;

[0013] The reset module is electrically connected to the reset signal line, the first node, and the first power signal line, and is configured to control the connection and disconnection between the first power signal line and the first node under the control of the reset signal of the reset signal line.

[0014] The pull-down module is electrically connected to the second node, the first node, and the first power signal line, respectively, and is configured to control the connection and disconnection of the first power signal line and the first node under the control of the voltage of the second node.

[0015] Optionally, the reset module includes a first transistor;

[0016] The control electrode of the first transistor is electrically connected to the first sub-signal line, the first electrode is electrically connected to the first node, and the second electrode is electrically connected to the first power signal line; the reset signal line includes the first sub-signal line.

[0017] The first sub-signal line is the signal line connected to the output control terminal of the target register; the target register is a register cascaded with the shift register, and the target register is located at the next level of the shift register.

[0018] Optionally, the reset module includes a second transistor;

[0019] The control electrode of the second transistor is electrically connected to the second sub-signal line, the first electrode is electrically connected to the first node, and the second electrode is electrically connected to the first power signal line; the reset signal line includes the second sub-signal line.

[0020] Optionally, the second node includes a first drop-down node and a second drop-down node, and the drop-down module includes a first drop-down unit and a second drop-down unit;

[0021] The first pull-down unit is electrically connected to the first pull-down node, the first node, and the first power signal line, respectively, and is configured to control the on / off state of the first power signal line and the first node under the control of the voltage of the first pull-down node;

[0022] The second pull-down unit is electrically connected to the second pull-down node, the first node, and the first power signal line, respectively, and is configured to control the on / off state of the first power signal line and the first node under the control of the voltage of the second pull-down node.

[0023] Optionally, the first pull-down unit includes a third transistor;

[0024] The control electrode of the third transistor is electrically connected to the first pull-down node, the first electrode is electrically connected to the first node, and the second electrode is electrically connected to the first power signal line.

[0025] Optionally, the second pull-down unit includes a fourth transistor;

[0026] The control electrode of the fourth transistor is electrically connected to the second pull-down node, the first electrode is electrically connected to the first node, and the second electrode is electrically connected to the first power signal line.

[0027] Optionally, the shift register further includes a first noise reduction circuit;

[0028] The first noise reduction circuit is electrically connected to the first power signal line, the second node, and the second power signal line, respectively, and is configured to write the second power signal of the second power signal line into the second node under the control of the first power signal during the touch phase.

[0029] Optionally, the second node includes a first drop-down node and a second drop-down node, and the first noise reduction circuit includes a first noise reduction module and a second noise reduction module;

[0030] The first noise reduction module is electrically connected to the first power signal line, the first pull-down node, and the second power signal line, respectively, and is configured to write the second power signal into the first pull-down node under the control of the first power signal during the touch phase.

[0031] The second noise reduction module is electrically connected to the first power signal line, the second pull-down node, and the second power signal line respectively, and is configured to write the second power signal into the second pull-down node under the control of the first power signal during the touch phase.

[0032] Optionally, the first noise reduction module includes a fifth transistor;

[0033] The control electrode of the fifth transistor is electrically connected to the first power signal line, the first electrode is electrically connected to the first pull-down node, and the second electrode is electrically connected to the second power signal line.

[0034] Optionally, the second noise reduction module includes a sixth transistor;

[0035] The control electrode of the sixth transistor is electrically connected to the first power signal line, the first electrode is electrically connected to the second pull-down node, and the second electrode is electrically connected to the second power signal line.

[0036] Optionally, the shift register further includes a second noise reduction circuit;

[0037] The second noise reduction circuit is electrically connected to the first power signal line, the second power signal line, and the output signal line, respectively, and is configured to, during the touch phase, write the second power signal of the second power signal line into the output signal line under the control of the first power signal.

[0038] Optionally, the second noise reduction circuit includes a seventh transistor;

[0039] The control electrode of the seventh transistor is electrically connected to the first power signal line, the first electrode is electrically connected to the output signal line, and the second electrode is electrically connected to the second power signal line.

[0040] Optionally, the shift register further includes an output control circuit and a third noise reduction circuit;

[0041] The output control circuit is electrically connected to the first node, the clock signal line, and the output control line, respectively, and is configured to write the clock signal into the output control line under the control of the voltage of the first node.

[0042] The third noise reduction circuit is electrically connected to the first power signal line, the second power signal line, and the output control line, respectively, and is configured to write the second power signal of the second power signal line into the output control line under the control of the first power signal during the touch phase.

[0043] Optionally, the third noise reduction circuit includes an eighth transistor;

[0044] The control electrode of the eighth transistor is electrically connected to the first power signal line, the first electrode is electrically connected to the output control line, and the second electrode is electrically connected to the second power signal line.

[0045] In a second aspect, this application provides a gate driving circuit, which includes a plurality of cascaded shift registers as described in the first aspect.

[0046] Thirdly, this application provides a display device, the display device including the gate driving circuit as described in the second aspect.

[0047] Fourthly, this application provides a driving method for controlling a shift register as described in the first aspect, the driving method comprising:

[0048] In the first display stage, an input signal with a first level is written to the input signal line so that the input circuit writes the input signal with the first level to the first node;

[0049] During the touch control phase, a first power signal with a first level is written to the first power signal line, and the first control circuit is controlled to disconnect the connection between the first power signal line and the first node; wherein, the first level is the same as the level of the input signal.

[0050] Optionally, after the touch phase, the method further includes:

[0051] In the second display stage, a first power signal with a second level is written to the first power signal line, and a clock signal is written to the clock signal line so that the output circuit writes the clock signal to the output signal line.

[0052] The first display stage also includes:

[0053] Write the first power signal with the second level to the first power signal line; wherein the signals corresponding to the first level and the second level are out of phase.

[0054] Optionally, the shift register further includes a pull-up circuit, which is electrically connected to the third power supply signal line and the second node respectively;

[0055] The first display stage also includes:

[0056] Write a third power signal with a first level to the third power signal line so that the pull-up circuit can connect the second node and the third power signal line, and write the third power signal with the first level to the second node.

[0057] The second display stage also includes:

[0058] Write the third power signal with a first level to the third power signal line so that the pull-up circuit conducts the connection between the second node and the third power signal line, and write the third power signal with a first level to the second node;

[0059] The touch phase also includes:

[0060] Write a third power signal with a second level to the third power signal line to cause the pull-up circuit to disconnect the connection between the second node and the third power signal line;

[0061] Wherein, the time point at which the first power signal transitions from the second level to the first level is delayed by a first duration relative to the time point at which the third power signal transitions from the first level to the second level; the time point at which the first power signal transitions from the first level to the second level is advanced by a first duration relative to the time point at which the third power signal transitions from the second level to the first level.

[0062] Wherein, the first duration is greater than or equal to the line scan duration, and less than or equal to twice the line scan duration; the line scan duration represents the time required to scan one line of pixels.

[0063] This application provides a shift register, its driving method, gate driving circuit, and display device, which have at least the following advantages: The shift register includes an input circuit, a first control circuit, and an output circuit. Since the input circuit is connected to both the input signal line and the first node, it is configured to write the input signal to the first node under the control of the input signal on the input signal line. This allows the input signal to be written to the first node, thereby changing the voltage level of the first node. Since the first control circuit is electrically connected to both the first node and the first power signal line, it is configured to disconnect the connection between the first power signal line and the first node during the touch phase. Thus, during the touch phase, the first node and the first power signal line are disconnected. By writing an input signal with a first voltage level to the input signal line and a first power signal with a first voltage level to the first power signal line, both the first node and the first power signal line are in a first voltage level state. This improves the problem of voltage drop at the first node due to leakage current through the first control circuit, thereby maintaining the voltage level of the first node unchanged. Since the output circuit is electrically connected to the first node, the clock signal line, and the output signal line respectively, it is configured to write the clock signal of the clock signal line into the output signal line under the control of the voltage of the first node. Because the voltage of the first node can maintain a constant level during the touch phase, the output circuit can output the clock signal normally under the control of the voltage of the first node, avoiding the problem of insufficient charging of the corresponding pixel row of the shift register, which can improve the horizontal stripe defects of the display panel and improve the image quality of the display panel.

[0064] The above description is only an overview of the technical solution of this application. In order to better understand the technical means of this application and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this application more obvious and understandable, the following are specific embodiments of this application. Attached Figure Description

[0065] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0066] Figure 1 illustrates, by way of example, a schematic diagram of the structure of a shift register provided in an embodiment of this application;

[0067] Figure 2 illustrates, by way of example, a schematic diagram of another shift register provided in an embodiment of this application;

[0068] Figure 3 illustrates, by way of example, a state diagram of a first control circuit provided in an embodiment of this application;

[0069] Figure 4 illustrates, by way of example, a schematic diagram of another shift register provided in an embodiment of this application;

[0070] Figure 5 illustrates, by way of example, a state diagram of a first noise reduction circuit provided in an embodiment of this application;

[0071] Figure 6 illustrates, by way of example, the states of the second and third noise reduction circuits provided in the embodiments of this application;

[0072] Figure 7 illustrates, exemplarily, a flowchart of the steps of a driving method provided in an embodiment of this application;

[0073] Figure 8 illustrates, exemplarily, a schematic diagram of voltage variation at the pull-up node of the sink row in the related art;

[0074] Figure 9 illustrates, by way of example, a waveform diagram of the output signal of a shift register provided in an embodiment of this application;

[0075] Figure 10 illustrates, by way of example, a waveform diagram of the output signal of another shift register provided in an embodiment of this application;

[0076] Figure 11 illustrates, by way of example, a schematic diagram of the signal level changes before and after the touch phase in an embodiment of this application;

[0077] Figure 12 illustrates an exemplary overall timing diagram of a display device provided in an embodiment of this application. Specific Implementation

[0078] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0079] In some embodiments, multiple signals have a first level and a second level. The first level and the second level only represent that the signal level has two states, and do not represent that the first level or the second level has a specific value.

[0080] In some embodiments, the transistor may be a thin-film transistor (TFT) or a metal-oxide-semiconductor (MOS) field-effect transistor. The control electrode of the transistor may be the gate, the first electrode may be the source or drain, and the second electrode may be the drain or source. For example, it may be an N-type TFT or a P-type TFT, but this application does not limit this.

[0081] Figure 1 illustrates a schematic diagram of the structure of a shift register 10 provided in an embodiment of this application. The shift register 10 includes: an input circuit 101, a first control circuit 102, and an output circuit 103.

[0082] The input circuit 101 is connected to the input signal line Input and the first node PU respectively, and is configured to write the input signal to the first node PU under the control of the input signal of the input signal line Input.

[0083] The first control circuit 102 is electrically connected to the first node PU and the first power signal line LVGL1 respectively, and is configured to disconnect the connection between the first power signal line LVGL1 and the first node PU during the touch phase.

[0084] The output circuit 103 is electrically connected to the first node PU, the clock signal line CLK, and the output signal line Gout(n), respectively, and is configured to write the clock signal of the clock signal line CLK into the output signal line Gout(n) under the control of the voltage of the first node PU.

[0085] In some embodiments, shift register 10 can be applied to the gate drive circuit of an embedded touch panel, such as an Incell Touch display panel. Shift register 10 can serve as a Gate Driver On Array (GOA) circuit in the gate drive circuit, also known as a GOA circuit, to provide gate drive signals to the embedded touch panel.

[0086] In some embodiments, the control terminal and input terminal of the input circuit 101 can be electrically connected to the input signal line Input and receive the input signal transmitted by the input signal line Input. The output terminal of the input circuit 101 can be electrically connected to the first node PU. When the input circuit 101 conducts the connection between the input signal line Input and the first node PU under the control of the input signal, the input circuit 101 can write the input signal into the first node PU, thereby charging the first node PU so that the first node PU and the input signal maintain the same level.

[0087] In some embodiments, the control terminal of the output circuit 103 can be electrically connected to the first node PU, the input terminal can be electrically connected to the clock signal line CLK, and the output terminal can be electrically connected to the output signal line Gout(n). When the output circuit 103 conducts the connection between the clock signal line CLK and the output signal line Gout(n) under the control of the voltage of the first node PU, the output circuit 103 can write the clock signal transmitted by the clock signal line CLK into the output signal line Gout(n), thereby outputting a clock signal.

[0088] In some embodiments, an in-frame touch (LHB) mode, alternating between display and touch phases, can be used to drive the embedded touch panel. LHB mode divides a frame of screen time into multiple display and touch phases, with the touch phase positioned between adjacent display phases to achieve a higher touch frequency. Specifically, when a pixel row is scanned, row scanning is temporarily stopped for touch recognition, and then scanning resumes from the paused pixel row. This alternation of display and touch phases continues multiple times until a frame is finished. During the touch phase, the clock signal is pulled low, keeping the display panel in a hold state.

[0089] In some embodiments, the first control circuit 102 connected to the first node PU in the shift register 10 is configured to disconnect the connection between the first power signal line LVGL1 and the first node PU during the touch phase. In this way, the first power signal of the first power signal line LVGL1 cannot change the voltage of the first node PU. Furthermore, during the touch phase, by writing a first power signal with the same level as the input signal to the first power signal line LVGL1, the voltage levels at both ends of the first control circuit 102 can be made the same. This can improve the problem of the first node PU voltage dropping due to leakage from the first control circuit 102 to the first power signal line LVGL1. Thus, during the touch phase, the voltage of the first node PU can be maintained at the level state after the input signal with the first level is written.

[0090] Specifically, before the touch phase, an input signal with a first level can be written to the input signal line Input, and the input circuit 101 writes the input signal with the first level to the first node PU, charging the first node PU so that the voltage of the first node PU is at the first level. During the touch phase, a first power signal with the first level can be written to the first power signal line LVGL1, and the first control circuit 102 controls the disconnection between the first power signal line LVGL1 and the first node PU. In this way, at both ends of the first control circuit 102, the voltage of the first node PU and the first power signal of the first power signal line LVGL1 are at the same first level, thereby eliminating the leakage path of the first node PU and allowing the voltage of the first node PU to remain at the first level during the touch phase.

[0091] Therefore, the problem of voltage drop in the first node PU of shift register 10 during the touch phase can be improved, the abnormal output signal of shift register 10 caused by voltage drop in the first node PU can be avoided, the output signal difference between different shift registers 10 can be reduced, the horizontal line defects caused by intra-frame touch mode to embedded touch panel can be improved, the touch display effect of display panel can be improved, and the product image quality can be enhanced.

[0092] In this embodiment, the shift register 10 includes an input circuit 101, a first control circuit 102, and an output circuit 103. Since the input circuit 101 is connected to the input signal line Input and the first node PU respectively, it is configured to write the input signal to the first node PU under the control of the input signal on the input signal line Input. This allows the input signal to be written to the first node PU through the input circuit 101, thereby changing the voltage state of the first node PU. Since the first control circuit 102 is electrically connected to the first node PU and the first power signal line LVGL1 respectively, it is configured to disconnect the connection between the first power signal line LVGL1 and the first node PU during the touch phase. Thus, during the touch phase, the first node PU and the first power signal line LVGL1 are disconnected. By writing an input signal with a first level to the input signal line Input and a first power signal with a first level to the first power signal line LVGL1, both the first node and the first power signal line are in a first level state. This improves the problem of voltage drop in the first node PU caused by leakage through the first control circuit 102, thereby maintaining the voltage state of the first node PU unchanged. Since the output circuit 103 is electrically connected to the first node PU, the clock signal line CLK, and the output signal line Gout(n) respectively, it is configured to write the clock signal of the clock signal line CLK into the output signal line Gout(n) under the control of the voltage of the first node PU. Because the voltage of the first node PU can maintain a constant level during the touch phase, the output circuit 103 can output the clock signal normally under the control of the voltage of the first node PU, avoiding the problem of insufficient charging of the corresponding pixel row of the shift register 10, which can improve the horizontal stripe defects of the display panel and improve the image quality of the display panel.

[0093] Optionally, the first control circuit 102 includes a reset module 1021 and a pull-down module 1022;

[0094] The reset module 1021 is electrically connected to the reset signal line, the first node PU, and the first power signal line LVGL1, respectively, and is configured to control the on / off state of the first power signal line LVGL1 and the first node PU under the control of the reset signal of the reset signal line.

[0095] The pull-down module 1022 is electrically connected to the second node PD, the first node PU, and the first power signal line LVGL1, respectively, and is configured to control the on / off state of the first power signal line LVGL1 and the first node PU under the control of the voltage of the second node PD.

[0096] In some embodiments, the control terminal of the reset module 1021 can be electrically connected to the reset signal line and receive the reset signal transmitted by the reset signal line. The reset module 1021 is also connected to the first node PU and the first power signal line LVGL1 respectively. When the reset module 1021 connects the first node PU and the first power signal line LVGL1 under the control of the reset signal, the voltage of the first node PU can be reset through the first power signal of the first power signal line LVGL1.

[0097] In some embodiments, the control terminal of the pull-down module 1022 can be electrically connected to the second node PD, and the pull-down module 1022 is also electrically connected to the first node PU and the first power signal line LVGL1 respectively. When the pull-down module 1022 conducts the connection between the first node PU and the first power signal line LVGL1 under the control of the voltage of the second node PD, it can write the first power signal of the first power signal line LVGL1 into the first node PU, thereby making the voltage level of the first node PU consistent with the voltage level of the first power signal.

[0098] In some embodiments, the touch phase can be positioned between the first display phase and the second display phase. During the touch phase, a reset signal and the voltage of the second node PD can be used to disconnect the connection between the reset module 1021 and the pull-down module 1022 from the first node PU and the first power signal line LVGL1. Furthermore, a first power signal with a first level can be written to the first power signal line LVGL1. This first power signal with a first level has the same level as the input signal with a first level, thereby preventing the voltage of the first node PU from dropping due to leakage during the touch phase and changing its level. During both the first and second display phases, a first power signal with a second level opposite to the first level can be written to the first power signal line LVGL1. When the reset module 1021 and the pull-down module 1022 reconnect the first node PU and the first power signal line LVGL1, a first power signal with a second level can be written to the first node PU to change the voltage level of the first node PU.

[0099] Optionally, the reset module 1021 includes a first transistor M2;

[0100] The control electrode of the first transistor M2 is electrically connected to the first sub-signal line Out_C(n+1), the first electrode is electrically connected to the first node PU, and the second electrode is electrically connected to the first power signal line LVGL1; the reset signal line includes the first sub-signal line Out_C(n+1);

[0101] Among them, the first sub-signal line Out_C(n+1) is the signal line connected to the output control terminal of the target register; the target register is a register cascaded with shift register 10, and the target register is located at the next level of shift register 10.

[0102] In some embodiments, shift register 10 may be a stage of a plurality of shift registers 10 cascaded with gate drive circuits. The next stage register of shift register 10 is the target register in this embodiment. The output control signal written to the output control signal line of the target register's output control terminal can be used as the reset signal of shift register 10. The output control signal line connected to the output control terminal of the target register is the first sub-signal line Out_C(n+1) in this embodiment.

[0103] In some embodiments, the first transistor M2 can serve as the reset transistor for the first node PU. When the first transistor M2 is turned on, the voltage of the first node PU is reset by the first power signal on the first power signal line LVGL1. When the first transistor M2 is turned off, the connection between the first node PU and the first power signal line LVGL1 is disconnected. During the touch phase, the connection between the first node PU and the first power signal line LVGL1 can be disconnected by controlling the first transistor M2 to be turned off. In addition, by writing a first power signal with the same first level as the input signal to the first power signal line LVGL1, the problem of the voltage drop of the first node PU caused by leakage current through the first transistor M2 can be improved, thereby maintaining the voltage level of the first node PU during the touch phase.

[0104] For example, the first transistor M2 is an N-type TFT. When a high-level reset signal is received, the first transistor M2 turns on, and when a low-level reset signal is received, the first transistor M2 turns off. The control electrode of the first transistor M2 can be the gate of the TFT, the first electrode can be the drain of the TFT, and the second electrode can be the source of the TFT. When the TFT is on, the source and drain are connected, and the first node PU is connected to the first power signal line LVGL1. When the TFT is off, the source and drain are disconnected, and the first node PU is disconnected from the first power signal line LVGL1.

[0105] Optionally, the reset module 1021 includes a second transistor M15;

[0106] The control electrode of the second transistor M15 is electrically connected to the second sub-signal T_RST, the first electrode is electrically connected to the first node PU, and the second electrode is electrically connected to the first power signal line LVGL1; the reset signal line includes the second sub-signal T_RST.

[0107] In some embodiments, the second sub-signal T_RST can be connected to a reset signal line of an external driving circuit. The external driving circuit provides a reset signal to the shift register 10, and controls the turning on or off of the second transistor M15 through the reset signal, thereby controlling whether the voltage of the first node PU is reset by the first power signal of the first power signal line LVGL1.

[0108] Similarly, the second transistor M15 can also serve as the reset transistor for the first node PU. During the touch phase, the connection between the first node PU and the first power signal line LVGL1 can be disconnected by controlling the second transistor M15 to be turned off. Referring to the aforementioned description of the first transistor M2, the voltage level of the first node PU can be kept unchanged during the touch phase; this will not be elaborated further here. For example, the second transistor M15 can be an N-type TFT. This is merely an example, and the embodiments of this application do not impose any limitations on this.

[0109] Optionally, the second node PD includes a first drop-down node PD_A and a second drop-down node PD_B, and the drop-down module 1022 includes a first drop-down unit and a second drop-down unit;

[0110] The first pull-down unit is electrically connected to the first pull-down node PD_A, the first node PU, and the first power signal line LVGL1, respectively, and is configured to control the on / off state of the first power signal line LVGL1 and the first node PU under the control of the voltage of the first pull-down node PD_A.

[0111] The second pull-down unit is electrically connected to the second pull-down node PD_B, the first node PU, and the first power signal line LVGL1, respectively, and is configured to control the on / off state of the first power signal line LVGL1 and the first node PU under the control of the voltage of the second pull-down node PD_B.

[0112] In some embodiments, the pull-down module 1022 includes a first pull-down unit controlled by the voltage of a first pull-down node PD_A, and a second pull-down unit controlled by the voltage of a second pull-down node PD_B. By adjusting the voltages of the first pull-down node PD_A and the second pull-down node PD_B respectively, the on / off state between the first node PU and the first power signal line LVGL1 can be controlled by the first pull-down unit and / or the second pull-down unit.

[0113] In some embodiments, during the touch phase, the connection between the first node PU and the first power signal line LVGL1 can be disconnected via the first pull-down unit and the second pull-down unit. This prevents the first power signal on the first power signal line LVGL1 from changing the voltage level of the first node PU. Furthermore, during the touch phase, a first power signal with the same level as the input signal can be written to the first power signal line LVGL1. This improves the problem of voltage drop in the first node PU due to leakage through the first and second pull-down units, thus maintaining the voltage level of the first node PU during the touch phase.

[0114] Optionally, the first pull-down unit includes a third transistor M8A;

[0115] The control electrode of the third transistor M8A is electrically connected to the first pull-down node PD_A, the first electrode is electrically connected to the first node PU, and the second electrode is electrically connected to the first power signal line LVGL1.

[0116] In some embodiments, the third transistor M8A can serve as a pull-down transistor for the first node PU. When the third transistor M8A is turned on, a first power signal on the first power signal line LVGL1 is written to the first node PU. When the third transistor M8A is turned off, the connection between the first node PU and the first power signal line LVGL1 is disconnected. During the touch phase, the connection between the first node PU and the first power signal line LVGL1 can be disconnected by controlling the third transistor M8A to be turned off. In addition, by writing a first power signal with the same first level as the input signal to the first power signal line LVGL1, the problem of voltage drop in the first node PU due to leakage current through the third transistor M8A can be improved, thereby maintaining the voltage level of the first node PU during the touch phase.

[0117] For example, the third transistor M8A is an N-type TFT. When the voltage of the first pull-down node PD_A is high, the third transistor M8A is turned on, and when the voltage of the first pull-down node PD_A is low, the third transistor M8A is turned off. The control electrode of the third transistor M8A can be the gate of the TFT, the first electrode can be the drain of the TFT, and the second electrode can be the source of the TFT. This is merely an example, and the embodiments of this application do not impose limitations.

[0118] Optionally, the second pull-down unit includes a fourth transistor M8B;

[0119] The control electrode of the fourth transistor M8B is electrically connected to the second pull-down node PD_B, the first electrode is electrically connected to the first node PU, and the second electrode is electrically connected to the first power signal line LVGL1.

[0120] In some embodiments, similarly, the fourth transistor M8B can also serve as a pull-down transistor for the first node PU. During the touch phase, the connection between the first node PU and the first power signal line LVGL1 can be disconnected by controlling the fourth transistor M8B to be turned off. Referring to the aforementioned description of the third transistor M8A, the voltage level of the first node PU can be kept unchanged during the touch phase; this will not be repeated here. For example, the fourth transistor M8B is an N-type TFT. This is merely an illustrative example, and the embodiments of this application do not impose limitations.

[0121] Figure 2 exemplarily illustrates a schematic diagram of another shift register 10 provided in an embodiment of this application. As shown in Figure 2, the input circuit 101 may include transistor M1, the output circuit 103 may include transistor M3 and capacitor C1, and the first control circuit 102 may include a first transistor M2, a second transistor M15, a third transistor M8A, and a fourth transistor M8B. In the shift register 10 shown in Figure 2, the transistors may be N-type TFTs, the control electrode of the transistor may be the gate of the TFT, the first electrode may be the drain of the TFT, and the second electrode may be the source of the TFT. The first node PU may be a pull-up node (PU), the first power signal line LVGL1 may be an LVGL1 signal line, and the second node PD is a pull-down node (PD), which includes a first pull-down node PD_A and a second pull-down node PD_B.

[0122] As shown in Figure 2, the gate and drain of transistor M1 are electrically connected to the input signal line Input, and the source is electrically connected to the first node PU. The input signal line Input can be the signal line Out_C, which is cascaded with shift register 10 and located at the level above shift register 10, connected to the output control terminal. The gate of transistor M3 is electrically connected to the first node PU and the first terminal of capacitor C1, the drain is electrically connected to the clock signal line CLK, and the source is electrically connected to the output signal line Gout(n). The drains of transistors M2 / M8A / M8B / M15 are electrically connected to the first node PU, and the sources are electrically connected to the first power signal line LVGL1. During the touch control phase, transistors M2 / M8A / M8B / M15 can be turned off, thus disconnecting the first node PU from the first power signal line LVGL1.

[0123] As shown in Figure 3, in the first display stage before the touch stage, an input signal with a first level (high level) can be input to the input signal line Input. For example, a high voltage signal (VGH) can be input to the input signal line Input, where the voltage range of the VGH signal is typically 12–25 volts (V). This high-level input signal can charge the first node PU. For instance, the first node PU can be pulled high to VGH by the input signal, allowing its voltage to remain high under the control of the input signal with the first level. Then, during the touch stage, a first power signal with the first level can be written to the first power signal line LVGL1. This ensures that the source and drain of transistors M2 / M8A / M8B / M15 are all in a high-level state, mitigating the problem of voltage drop in the first node PU due to leakage from transistors M2 / M8A / M8B / M15. Furthermore, since the source and drain of transistor M1 are both in a high-level state, the problem of voltage drop in the first node PU due to leakage from transistor M1 can also be mitigated.

[0124] Specifically, when the voltage value of the first node PU is equal to the voltage value of the first power signal in the first power signal line LVGL1, the voltage of the first node PU cannot leak to the first power signal line LVGL1 through the first control circuit 102. In this way, there is no leakage path for the first node PU during the touch phase, and the voltage of the first node PU can remain at a high level until the touch phase ends.

[0125] Optionally, the shift register 10 also includes a first noise reduction circuit 104;

[0126] The first noise reduction circuit 104 is electrically connected to the first power signal line LVGL1, the second node PD, and the second power signal line LVGL / VGL, respectively, and is configured to write the second power signal of the second power signal line LVGL / VGL into the second node PD under the control of the first power signal during the touch phase.

[0127] In some embodiments, to prevent leakage of current from the first node PU through the first control circuit 102 during the touch phase, it is necessary to disconnect the connection between the first node PU and the first power signal line LVGL1 through the first control circuit 102 during the touch phase. This requires the reset module 1021 and the pull-down module 1022 in the first control circuit 102 to disconnect the connection between the first node PU and the first power signal line LVGL1. Specifically, for the pull-down module 1022, the voltage of the second node PD needs to remain at a constant level during the touch phase, so that the pull-down module 1022 can disconnect the connection between the first node PU and the first power signal line LVGL1 during the touch phase.

[0128] As shown in Figure 2, during the touch phase, a third power signal with a second level can be written to the third power signal lines VDD_A / VDD_B. This second level can be low, in which case transistors M5A / M5B are turned off. Furthermore, since the voltage of the first node PU is high during the touch phase, transistors M6A / M6B are turned on under the voltage control of the first node PU. This causes the first pull-down node PD_A and the second pull-down node PD_B to conduct with the second power signal lines LVGL / VGL. Since the second power signal on the second power signal lines LVGL / VGL can be a low-level power signal, the voltages of both the first pull-down node PD_A and the second pull-down node PD_B are pulled low, causing transistors M8A / M8B to turn off.

[0129] For example, a low-voltage signal (VGL) can be written to the third power signal lines VDD_A / VDD_B. The voltage range of the VGL signal is typically -6 to -15V. The low-level second power signal can also be the VGL signal. When the first pull-down node PD_A and the second pull-down node PD_B are connected to the second power signal lines LVGL / VGL respectively, the node voltage is pulled low to VGL, and both the voltage of the first pull-down node PD_A and the voltage of the second pull-down node PD_B are in a low-level state.

[0130] However, for non-in-the-slot rows, although a low-level third power signal is written to the third power signal line VDD_A / VDD_B during the touch phase, the voltage of the second node PD may also be in a high-level state due to the presence of residual charge. This will prevent transistors M8A / M8B from being turned off. When transistors M8A / M8B are turned on, the first node PU and the first power signal line LVGL1 are connected, which will pull the first node PU high. This will affect some first node PUs that have been reset / pulled down to a low level, causing noise in the output signal of non-in-the-slot rows.

[0131] In some embodiments, the shift register 10 further includes a first noise reduction circuit 104, which is used to reduce the voltage noise of the second node PD. Specifically, the first noise reduction circuit 104 is electrically connected to the first power signal line LVGL1, the second node PD, and the second power signal line LVGL / VGL. During the touch phase, a first power signal with a first level can be written to the first power signal line LVGL1. Under the control of the first power signal, the first noise reduction circuit 104 writes the second power signal of the second power signal line LVGL / VGL to the second node PD. By reducing the voltage noise of the second node PD through the second power signal, the voltage of the second node PD during the touch phase can control the pull-down module 1022 to disconnect the connection between the first node PU and the first power signal line LVGL1.

[0132] Optionally, the second node PD includes a first drop-down node PD_A and a second drop-down node PD_B, and the first noise reduction circuit 104 includes a first noise reduction module and a second noise reduction module;

[0133] The first noise reduction module is electrically connected to the first power signal line LVGL1, the first pull-down node PD_A, and the second power signal line LVGL / VGL, respectively, and is configured to write the second power signal into the first pull-down node PD_A under the control of the first power signal during the touch phase.

[0134] The second noise reduction module is electrically connected to the first power signal line LVGL1, the second pull-down node PD_B, and the second power signal line LVGL / VGL, respectively, and is configured to write the second power signal into the second pull-down node PD_B under the control of the first power signal during the touch phase.

[0135] In some embodiments, the voltage of the first pull-down node PD_A controls the first pull-down unit, and the voltage of the second pull-down node PD_B controls the second pull-down unit. To control the first pull-down unit to disconnect the first node PU from the first power signal line LVGL1 during the touch phase, the voltage of the first pull-down node PD_A can be denoised using a first noise reduction module. Similarly, to control the second pull-down unit to disconnect the first node PU from the first power signal line LVGL1 during the touch phase, the voltage of the second pull-down node PD_B can be denoised using a second noise reduction module.

[0136] In some embodiments, during the touch control phase, a first power signal with a first level can be written to the first power signal line LVGL1, so that the first noise reduction module can connect the second power signal line LVGL / VGL and the first pull-down node PD_A, and the second power signal of the second power signal line LVGL / VGL can be written to the first pull-down node PD_A, and the voltage of the first pull-down node PD_A can be reduced by the second power signal.

[0137] Optionally, the first noise reduction module includes a fifth transistor M16A;

[0138] The control electrode of the fifth transistor M16A is electrically connected to the first power signal line LVGL1, the first electrode is electrically connected to the first pull-down node PD_A, and the second electrode is electrically connected to the second power signal line LVGL / VGL.

[0139] In some embodiments, the fifth transistor M16A can serve as a noise reduction transistor for the first pull-down node PD_A. When the fifth transistor M16A is turned on, the second power signal of the second power signal line LVGL / VGL is written to the first pull-down node PD_A. When the fifth transistor M16A is turned off, the connection between the first pull-down node PD_A and the second power signal line LVGL / VGL is disconnected. For example, the fifth transistor M16A is an N-type TFT. When the first power signal is a high-level power signal, the fifth transistor M16A is turned on, and when the first power signal is a low-level power signal, the fifth transistor M16A is turned off. The control electrode of the fifth transistor M16A can be the gate of the TFT, the first electrode can be the drain of the TFT, and the second electrode can be the source of the TFT. The high-level first power signal can be the VGH signal, and the low-level first power signal can be the VGL signal. The voltage ranges of the VGH and VGL signals are described in the foregoing embodiments.

[0140] In some embodiments, during the touch control phase, a first power signal with a first level can be written to the first power signal line LVGL1, causing the fifth transistor M16A to conduct the connection between the second power signal line LVGL / VGL and the second pull-down node PD_B, and the second power signal of the second power signal line LVGL / VGL can be written to the second pull-down node PD_B, thereby reducing the noise of the voltage of the second pull-down node PD_B through the second power signal.

[0141] Optionally, the second noise reduction module includes a sixth transistor M16B;

[0142] The control electrode of the sixth transistor M16B is electrically connected to the first power signal line LVGL1, the first electrode is electrically connected to the second pull-down node PD_B, and the second electrode is electrically connected to the second power signal line LVGL / VGL.

[0143] In some embodiments, the sixth transistor M16B can serve as a noise reduction transistor for the second pull-down node PD_B. When the sixth transistor M16B is turned on, the second power signal of the second power signal line LVGL / VGL is written to the second pull-down node PD_B. When the sixth transistor M16B is turned off, the connection between the second pull-down node PD_B and the second power signal line LVGL / VGL is disconnected. For example, the sixth transistor M16B is an N-type TFT. Similarly, the description of the fifth transistor M16A can be referred to, and will not be repeated here. This is merely an example, and the embodiments of this application do not limit the scope of the invention.

[0144] In this embodiment, the shift register 10 further includes a first noise reduction circuit 104. The first noise reduction circuit 104 is electrically connected to the first power signal line LVGL1, the second node PD, and the second power signal line LVGL / VGL, respectively. It is configured to write the second power signal of the second power signal line LVGL / VGL to the second node PD under the control of the first power signal during the touch phase. In this way, the voltage of the second node PD can be reduced by the second power signal, so that the voltage of the second node PD can control the pull-down module 1022 to disconnect the connection between the first node PU and the first power signal line LVGL1 during the touch phase. This can improve the problem of the voltage of the first node PU decreasing due to leakage through the pull-down module 1022, and can keep the voltage state of the first node PU unchanged.

[0145] Optionally, the shift register 10 also includes a second noise reduction circuit 105;

[0146] The second noise reduction circuit 105 is electrically connected to the first power signal line LVGL1, the second power signal line LVGL / VGL, and the output signal line Gout(n), respectively, and is configured to write the second power signal of the second power signal line LVGL / VGL into the output signal line Gout(n) under the control of the first power signal during the touch phase.

[0147] In some embodiments, as shown in FIG2, a first power signal with a first level can be written to the first power signal line LVGL1 during the touch stage. The first level is a high level. For non-slot rows, even if some first node PUs that have been reset / pulled down to a low level are disconnected from the first power signal line LVGL1, the voltage of the first node PU may be slightly pulled up at the moment when the first power signal jumps from the second level to the first level, i.e., at the moment when the first power signal is pulled up, due to the presence of the transistor coupling capacitor in the first control circuit 102. This causes noise in the output signal of the non-slot rows.

[0148] In some embodiments, the shift register 10 further includes a second noise reduction circuit 105, which is used to reduce the noise of the output signal of the output circuit 103. Specifically, the second noise reduction circuit 105 is electrically connected to the first power signal line LVGL1, the second power signal line LVGL / VGL, and the output signal line Gout(n). During the touch control phase, a first power signal with a first level can be written to the first power signal line LVGL1. Under the control of the first power signal, the second noise reduction circuit 105 can write the second power signal of the second power signal line LVGL / VGL to the output signal line Gout(n). By reducing the noise of the output signal of the output circuit 103 through the second power signal, noise can be avoided from being generated by the non-input row output signal.

[0149] Optionally, the second noise reduction circuit 105 includes a seventh transistor M18;

[0150] The control electrode of the seventh transistor M18 is electrically connected to the first power supply signal line LVGL1, the first electrode is electrically connected to the output signal line Gout(n), and the second electrode is electrically connected to the second power supply signal line LVGL / VGL.

[0151] In some embodiments, the seventh transistor M18 can serve as a noise reduction transistor in the output circuit 103. When the seventh transistor M18 is turned on, the second power signal of the second power signal line LVGL / VGL is written into the output signal line Gout(n) connected to the output terminal of the output circuit 103. When the seventh transistor M18 is turned off, the connection between the output signal line Gout(n) and the second power signal line LVGL / VGL is disconnected. For example, the seventh transistor M18 is an N-type TFT. When the first power signal is a high-level power signal, the seventh transistor M18 is turned on, and when the first power signal is a low-level power signal, the seventh transistor M18 is turned off. The control electrode of the seventh transistor M18 can be the gate of the TFT, the first electrode can be the drain of the TFT, and the second electrode can be the source of the TFT.

[0152] In some embodiments, during the touch control phase, a first power signal with a first level can be written to the first power signal line LVGL1, causing the seventh transistor M18 to conduct the connection between the second power signal line LVGL / VGL and the second pull-down node PD_B. The second power signal of the second power signal line LVGL / VGL is written to the second pull-down node PD_B, and the voltage of the second pull-down node PD_B is reduced by the second power signal, which can avoid noise from the non-input row output signal.

[0153] In this embodiment, the shift register 10 further includes a second noise reduction circuit 105. The second noise reduction circuit 105 is electrically connected to the first power signal line LVGL1, the second power signal line LVGL / VGL, and the output signal line Gout(n), respectively. It is configured to write the second power signal of the second power signal line LVGL / VGL to the output signal line Gout(n) under the control of the first power signal during the touch phase. In this way, the second power signal can be written as an output signal to the output signal line Gout(n) during the touch phase, thereby reducing the noise of the output signal of the output circuit 103.

[0154] Optionally, the shift register 10 also includes an output control circuit 106 and a third noise reduction circuit 107;

[0155] The output control circuit 106 is electrically connected to the first node PU, the clock signal line CLK, and the output control line Out_C(n), respectively, and is configured to write the clock signal into the output control line Out_C(n) under the control of the voltage of the first node PU.

[0156] The third noise reduction circuit 107 is electrically connected to the first power signal line LVGL1, the second power signal line LVGL / VGL, and the output control line Out_C(n), respectively, and is configured to write the second power signal of the second power signal line LVGL / VGL into the output control line Out_C(n) under the control of the first power signal during the touch phase.

[0157] In some embodiments, the shift register 10 further includes an output control circuit 106, which controls the switching between the clock signal line CLK and the output control line Out_C(n) under the control of the voltage of the first node PU. As shown in Figure 2, the output control circuit 106 includes a transistor M2, which is an N-type TFT. The gate of the transistor M2 is electrically connected to the first node PU, the drain is electrically connected to the clock signal line CLK, and the source is electrically connected to the output control line Out_C(n). When the voltage of the first node PU is high, the transistor M2 is turned on, and the clock signal is written to the output control line Out_C(n). When the voltage of the first node PU is low, the transistor M2 is turned off, and the clock signal line CLK is disconnected from the output control line Out_C(n). The voltage of the first node PU is high, for example, when the voltage of the first node PU is pulled up to VGH.

[0158] However, for non-slotted rows, referring to the description in the previous embodiment that the voltage of the second node PD may be at a high level due to the presence of residual charge, causing the first node PU to be pulled high, the output control signal of the output control circuit 106 may also generate noise because the first node PU is pulled high. Therefore, in this embodiment, the output control signal of the output control circuit 106 is denoised by the third noise reduction circuit 107 to avoid noise in the output control signal of non-slotted rows.

[0159] In some embodiments, the shift register 10 includes a third noise reduction circuit 107, which is used to reduce the noise of the output control signal of the output control circuit 106. Specifically, the third noise reduction circuit 107 is electrically connected to the first power signal line LVGL1, the second power signal line LVGL / VGL, and the output control line Out_C(n). During the touch control phase, a first power signal with a first level can be written to the first power signal line LVGL1. Under the control of the first power signal, the third noise reduction circuit 107 writes the second power signal of the second power signal line LVGL / VGL to the output control line Out_C(n), thereby reducing the noise of the output control signal through the second power signal.

[0160] Optionally, the third noise reduction circuit 107 includes an eighth transistor M17;

[0161] The control electrode of the eighth transistor M17 is electrically connected to the first power supply signal line LVGL1, the first electrode is electrically connected to the output control line Out_C(n), and the second electrode is electrically connected to the second power supply signal line LVGL / VGL.

[0162] In some embodiments, the eighth transistor M17 can serve as a noise reduction transistor in the output control circuit 106. When the eighth transistor M17 is turned on, the second power signal of the second power signal line LVGL / VGL is written into the output control line Out_C(n) connected to the output control terminal of the output control circuit 106. When the eighth transistor M17 is turned off, the connection between the output control line Out_C(n) and the second power signal line LVGL / VGL is disconnected. For example, the eighth transistor M17 is an N-type TFT. When the first power signal is a high-level power signal, the eighth transistor M17 is turned on, and when the first power signal is a low-level power signal, the eighth transistor M17 is turned off. The control electrode of the eighth transistor M17 can be the gate of the TFT, the first electrode can be the drain of the TFT, and the second electrode can be the source of the TFT.

[0163] In this embodiment, the shift register 10 further includes an output control circuit 106 and a third noise reduction circuit 107. The output control circuit 106 is electrically connected to the first node PU, the clock signal line CLK, and the output control line Out_C(n), and is configured to write the clock signal to the output control line Out_C(n) under the control of the voltage of the first node PU. The third noise reduction circuit 107 is electrically connected to the first power signal line LVGL1, the second power signal line LVGL / VGL, and the output control line Out_C(n), and is configured to write the second power signal of the second power signal line LVGL / VGL to the output control line Out_C(n) under the control of the first power signal during the touch phase. In this way, the second power signal can be written as the output control signal to the output control line Out_C(n) during the touch phase, thereby reducing the noise of the output control signal of the output control circuit 106.

[0164] Figure 4 exemplarily illustrates a schematic diagram of another shift register 10 provided in an embodiment of this application. Compared to the circuit structure of the shift register 10 shown in Figure 2, the shift register 10 shown in Figure 4 further includes a first noise reduction circuit 104, a second noise reduction circuit 105, and a third noise reduction circuit 107. The first noise reduction circuit 104 may include a fifth transistor M16A and a sixth transistor M16B, the second noise reduction circuit 105 may include a seventh transistor M18, the output control circuit 106 may include a transistor M11, and the third noise reduction circuit 107 may include an eighth transistor M17. In the shift register 10 shown in Figure 4, the transistors may be N-type TFTs, the control electrode of the transistor may be the gate of the TFT, the first electrode may be the drain of the TFT, and the second electrode may be the source of the TFT.

[0165] As shown in Figure 4, the gate of the fifth transistor M16A is electrically connected to the first power signal line LVGL1, the drain is electrically connected to the first pull-down node PD_A, and the source is electrically connected to the second power signal line LVGL / VGL. The gate of the sixth transistor M16B is electrically connected to the first power signal line LVGL1, the drain is electrically connected to the second pull-down node PD_B, and the source is electrically connected to the second power signal line LVGL / VGL. The gate of the seventh transistor M18 is electrically connected to the first power signal line LVGL1, the drain is electrically connected to the output signal line Gout(n), and the source is electrically connected to the second power signal line LVGL / VGL. The gate of the eighth transistor M17 is electrically connected to the first power signal line LVGL1, the drain is electrically connected to the output control line Out_C(n), and the source is electrically connected to the second power signal line LVGL / VGL.

[0166] As shown in Figure 5, during the touch phase, a first power signal with a first level (high) can be written to the first power signal line LVGL1, and a second power signal with a second level (low) can be written to the second power signal line LVGL / VGL. M16 in Figure 5 includes M16A / M16B, and the second node PD includes a first pull-down node PD_A and a second pull-down node PD_B. Thus, the fifth transistor M16A and the sixth transistor M16B are turned on, and the low-level second power signal is written to the second node PD, that is, the second power signal is written to the first pull-down node PD_A and the second pull-down node PD_B, thereby pulling down the level of the second node PD. This allows the voltage of the second node PD to remain low during the touch phase, enabling the voltage of the second node PD to control the reset module 1021 and the pull-down module 1022 to disconnect the connection between the first node PU and the first power signal line LVGL1 during the touch phase.

[0167] As shown in Figure 6, during the touch phase, a first power signal with a first level (high) can be written to the first power signal line LVGL1, and a second power signal with a second level (low) can be written to the second power signal line LVGL / VGL. This turns on the seventh transistor M18 and the eighth transistor M17, and the low-level second power signal is written to the output control line Out_C(n) and the output signal line Gout(n), thereby lowering the level of the output control signal of the output control circuit 106 and the output signal of the output circuit 103. This reduces noise at the output control terminal of the output control circuit 106 and the output terminal of the output circuit 103, preventing noise from being generated in the output control signal and the output signal.

[0168] This application also provides a gate driving circuit, which includes a plurality of cascaded shift registers 10 as described in the foregoing embodiments.

[0169] In some embodiments, the input circuit 101 of the shift register 10 can be connected to the output control terminal of the previous-level register via the input signal line Input, using the output control signal of the previous-level register as the input signal of the shift register 10. The control terminal of the pull-down module 1022 of the first control circuit 102 in the shift register 10 can be electrically connected to the output control terminal of the next-level register via the reset signal line, using the output control signal of the next-level register as the reset signal of the shift register 10.

[0170] For example, as shown in Figure 4, transistor M1 can be connected to the output control terminal of the previous stage register via the Input signal line, and the first transistor M2 can be connected to the output control terminal of the next stage register via the reset signal line. Furthermore, the gate of transistor M4 in Figure 4 can be connected to the next stage register, allowing the output signal of the next stage register to be used as the reset signal for this stage, controlling the on / off state of transistor M4. Similarly, transistor M3 of the shift register 10 in this stage can also be connected to the previous stage register, using the output signal of this stage as the reset signal for the previous stage register; further details are omitted here.

[0171] The gate drive circuit has the same advantages as the shift register 10 in the aforementioned embodiment compared to related technologies, and will not be described again here.

[0172] This application also provides a display device, which includes the gate driving circuit as described in the foregoing embodiments.

[0173] This display device has the same advantages as the shift register 10 in the aforementioned embodiments compared to related technologies, and will not be repeated here.

[0174] Figure 7 illustrates an exemplary flowchart of a driving method provided in an embodiment of this application. This driving method is used to control the shift register 10 as described in the foregoing embodiment. As shown in Figure 7, the driving method includes:

[0175] Step S1, first display stage: write an input signal with a first level to the input signal line Input, so that the input circuit 101 writes the input signal with the first level to the first node PU;

[0176] Step S2, the touch control stage, writes a first power signal with a first level to the first power signal line LVGL1, and controls the first control circuit 102 to disconnect the connection between the first power signal line LVGL1 and the first node PU; wherein, the first level is the same as the level of the input signal.

[0177] In some embodiments, for the gate driving circuit of an embedded touch panel driven in the intra-frame touch (LHB) mode, during the touch phase, the first node PU in the shift register 10 corresponding to the row entering the pit needs to remain at a high level after exiting the pit until the end of the touch phase in order for the shift register 10 to output a signal normally. Otherwise, if the voltage of the first node PU decays after exiting the pit during the touch phase, the output signal of the shift register 10 will decrease, resulting in insufficient charging of the corresponding pixel row and causing poor horizontal lines on the display panel. These horizontal lines are called LHB horizontal lines. For example, as shown in Figure 4, the voltage of the first node PU in the shift register 10 needs to remain at a high level until the end of the touch phase.

[0178] In related technologies, as shown in the circuit structure in Figure 4, if there is no first power signal line LVGL1, the source of transistors M2 / M8A / M8B / M15 is connected to the second power signal line LVGL / VGL. During the touch phase, the second power signal of the second power signal line LVGL / VGL is in a low-level state. The signal connected to the gate of transistors M2 / M8A / M8B / M15 and the PD node are also in a low-level state. Then the Vgs of transistors M2 / M8A / M8B / M15 is 0V. The TFT leakage current is large at 0V. During the touch phase, the PU node may continuously leak current to transistors M2 / M8A / M8B / M15, which will cause the voltage of the PU node to be lower than that of the non-drilled row at the end of the touch phase. This will result in a decrease in the output signal after the pit, insufficient charging of the corresponding pixel row, and the LHB horizontal stripe problem.

[0179] Figure 8 illustrates, for example, the voltage change of the PU node in the related technology. As shown in Figure 8, during the touch stage, the voltage of the PU node is difficult to maintain a high voltage due to leakage. The simulated voltage drop in Figure 8 reaches about 11V.

[0180] In some embodiments, during the first display stage before the touch stage, for the indentation row, an input signal with a first level can be written to the input signal line Input. Under the control of the input signal with the first level, the input circuit 101 can write the input signal with the first level to the first node PU. For example, as shown in FIG4, the shift register 10 can write a high-level input signal, such as a VGH signal, to the input signal line Input, controlling the transistor M1 to turn on. The high-level input signal is written to the first node PU, causing the voltage of the first node PU to be pulled up to a high level.

[0181] In some embodiments, upon entering the touch phase, the first control circuit 102 disconnects the connection between the first power signal line LVGL1 and the first node PU, and writes a first power signal with the same level as the input signal to the first power signal line LVGL1. That is, during the first display phase, an input signal with the first level is first written to the input signal line Input, making the voltage of the first node PU a first level state. Then, upon entering the touch phase, a first power signal with the first level is written to the first power signal line LVGL1. In this way, on the one hand, the first control circuit 102 disconnects the connection between the first node PU and the first power signal line LVGL1; on the other hand, the first power signal in the first power signal line LVGL1 has the same level as the voltage of the first node PU. This can improve the problem of the first node PU voltage decreasing due to leakage from the first control circuit 102 to the first power signal line LVGL1, thus maintaining the voltage of the first node PU at the first level state during the touch phase. Furthermore, when the voltage value of the first node PU is equal to the voltage value of the first power supply signal, the leakage path of the first node PU can be eliminated, which can avoid the reduction of the output signal of the shift register 10 and the resulting horizontal stripe defects on the display panel, thereby improving the display effect of the display panel.

[0182] Figure 9 exemplarily illustrates the waveform diagram of the output signal of the shift register 10 in the embodiment of this application. As shown in Figure 9, the voltage of the first node PU can remain at a level for a long time during the touch phase. When the direct touch phase ends, the voltage drop of the first node PU shown in the voltage waveform of the first node PU in Figure 9 is only 2.13V, which is a significant improvement compared to the voltage drop of the first node PU in Figure 8. This can also reduce the abnormal output signal of the shift register 10 and improve the poor horizontal lines on the display panel.

[0183] In some embodiments, for non-in-slot rows, a first power signal with a first level can be written to the first power signal line LVGL1 during the touch phase, and a second power signal with a second level can be written to the second power signal line LVGL / VGL, with the first and second level signals having opposite phases. Thus, under the control of the first power signal, the second power signal of the second power signal line LVGL / VGL is written to the second node PD, the output signal line Gout(n), and the output control line Out_C(n) respectively through the first noise reduction circuit 104, the second noise reduction circuit 105, and the third noise reduction circuit 107. This reduces noise in the voltage of the second node PD, the output signal of the output circuit 103, and the output control signal of the output control circuit 106, preventing noise from being generated in the output signal and output control signal.

[0184] Figure 10 exemplarily illustrates the waveform diagram of the output signal of the shift register 10 in the non-slot row of this application embodiment. As shown in Figure 10, by reducing noise in the voltage of the second node PD, the output signal of the output circuit 103, and the output control signal of the output control circuit 106 during the touch stage, the shift register 10 in the non-slot row can output signals normally, which can avoid noise in the output signal and the output control signal, reduce the difference between different shift registers 10, improve the touch display effect of the display panel, and enhance the product image quality.

[0185] In this embodiment, during the first display stage, an input signal is written to the input signal line Input, causing the input circuit 101 to write the input signal to the first node PU. During the touch stage, a first power signal with a first level is written to the first power signal line LVGL1, and the first control circuit 102 is controlled to disconnect the connection between the first power signal line LVGL1 and the first node PU. The first level is the same as the level of the input signal. In this way, the voltage of the first node PU can be maintained at the first level during the touch stage, allowing the output circuit 103 to output the clock signal normally under the voltage control of the first node PU. This avoids the problem of insufficient charging of the corresponding pixel row of the shift register 10, improves the horizontal stripe defects of the display panel, and enhances the image quality of the display panel.

[0186] Optionally, after the touch phase, the method further includes:

[0187] Step S3, the second display stage, writes a first power signal with a second level to the first power signal line LVGL1 and writes a clock signal to the clock signal line CLK, so that the output circuit 103 writes the clock signal to the output signal line Gout(n).

[0188] The first display phase also includes:

[0189] Write a first power signal with a second level to the first power signal line LVGL1; wherein the signals corresponding to the first level and the second level are out of phase.

[0190] In some embodiments, the touch phase can be set between the first display phase and the second display phase. In the first display phase and the second display phase, a first power signal with a second level opposite to the first level can be written to the first power signal line LVGL1, so that the reset module 1021 and the pull-down module 1022 in the first control circuit 102 conduct the connection between the first node PU and the first power signal line LVGL1. The reset module 1021 and the pull-down module 1022 can write the first power signal with the second level to the first node PU to change the voltage level of the first node PU.

[0191] In some embodiments, since scanning of the infeed row is paused and touch recognition is performed during the touch phase, the clock signal line CLK can be pulled low for the shift register 10 shown in Figure 4, so that the clock signal of the clock signal line CLK remains low during the touch phase. In the second display phase after the touch phase ends, a normal clock signal can be written to the clock signal line CLK for the infeed row, so that the output circuit 103 writes the clock signal to the output signal line Gout(n), and resumes scanning from the paused pixel row.

[0192] Optionally, the shift register 10 further includes a pull-up circuit 108, which is electrically connected to the third power supply signal lines VDD_A / VDD_B and the second node PD, respectively.

[0193] The first display phase also includes:

[0194] Write a third power signal with a first level to the third power signal line VDD_A / VDD_B so that the pull-up circuit 108 turns on the connection between the second node PD and the third power signal line VDD_A / VDD_B, and write the third power signal with the first level to the second node PD.

[0195] The second display phase also includes:

[0196] Write a third power signal with a first level to the third power signal line VDD_A / VDD_B so that the pull-up circuit 108 turns on the connection between the second node PD and the third power signal line VDD_A / VDD_B, and write the third power signal with the first level to the second node PD.

[0197] The touch phase also includes:

[0198] Write a third power signal with a second level to the third power signal line VDD_A / VDD_B to cause the pull-up circuit 108 to disconnect the connection between the second node PD and the third power signal line VDD_A / VDD_B;

[0199] Wherein, the time point when the first power signal transitions from the second level to the first level is delayed by a first time interval relative to the time point when the third power signal transitions from the first level to the second level; the time point when the first power signal transitions from the first level to the second level is advanced by a first time interval relative to the time point when the third power signal transitions from the second level to the first level.

[0200] The first duration is greater than or equal to the line scan duration, and less than or equal to twice the line scan duration; the line scan duration represents the time required to scan one line of pixels.

[0201] In some embodiments, the pull-up circuit 108 may include transistors M5A and M5B in the shift register 10 shown in FIG4. Transistors M5A and M5B may be N-type TFTs. The gate and drain of transistors M5A and M5B are electrically connected to the third power supply signal lines VDD_A / VDD_B, respectively. The source of transistors M5A and M5B is electrically connected to the first pull-down node PD_A and the second pull-down node PD_B, respectively.

[0202] In some embodiments, during the touch phase, a third power signal with a second level can be written to the third power signal lines VDD_A / VDD_B to cause the pull-up circuit 108 to disconnect the connection between the second node PD and the third power signal lines VDD_A / VDD_B. For example, a low-level third power signal can control transistors M5A and M5B to turn off. During the first and second display phases, a third power signal with a first level can be written to the third power signal lines VDD_A / VDD_B to cause the pull-up circuit 108 to turn on the connection between the second node PD and the third power signal lines VDD_A / VDD_B. This allows the pull-up circuit 108 to write the third power signal with the first level to the second node PD. For example, a high-level third power signal can control transistors M5A and M5B to turn on, allowing the high-level third power signal to be written to the first pull-down node PD_A and the second pull-down node PD_B.

[0203] The high-level third power supply signal can be the VGH signal, which can control the N-type transistors M5A and M5B to turn on. The low-level third power supply signal can be the VGL signal, which can control the N-type transistors M5A and M5B to turn off. The voltage ranges of VGH and VGL are described in the relevant descriptions in the foregoing embodiments.

[0204] In some embodiments, for non-in-the-slot rows, although a low-level third power signal is written to the third power signal line VDD_A / VDD_B during the touch phase, the voltage of the second node PD may also be in a high-level state due to the presence of residual charge, which will prevent transistors M8A / M8B from being turned off. When transistors M8A / M8B are turned on, the first node PU and the first power signal line LVGL1 are connected, which will cause the first node PU to be raised too high, resulting in the risk of multiple outputs and screen flickering.

[0205] Therefore, upon entering the touch phase, a third power signal with a second level can be written to the third power signal line VDD_A / VDD_B first, and after a first delay, a first power signal with a first level can be written to the first power signal line LVGL1. This ensures that the first power signal transitions from the second level to the first level after a first delay when entering the touch phase. Similarly, before exiting the touch phase, a first power signal with a second level can be written to the first power signal line LVGL1 first, and after a first delay, a third power signal with a first level can be written to the third power signal line VDD_A / VDD_B.

[0206] This ensures that upon entering the touch phase, at the moment the first power signal transitions from the second level to the first level, the pull-down module 1022 in the first control circuit 102 has already disconnected the connection between the first node PU and the first power signal line LVGL1 under the control of the voltage of the second node PD. Furthermore, before exiting the touch phase, at the moment the third power signal transitions from the second level to the first level, the first power signal of the first power signal line LVGL1 has already changed to the second level state.

[0207] Figure 11 exemplarily illustrates the signal level changes before and after the touch phase in this embodiment of the application. As shown in Figure 11, for the shift register 10 shown in Figure 4, in the first display phase, the third power signal of the third power signal line VDD_A / VDD_B is at a high level, the second power signal of the second power signal line LVGL / VGL is at a low level, and the first power signal of the first power signal line LVGL1 is at a low level. The level states of each signal in the second display phase are the same as in the first display phase, and will not be described again here. After entering the touch phase, the third power signal of the third power signal line VDD_A / VDD_B first becomes low, and after a first delay, the first power signal of the first power signal line LVGL1 becomes high. Before exiting the touch phase, the first power signal of the first power signal line LVGL1 first becomes low, and after a first delay, the third power signal of the third power signal line VDD_A / VDD_B becomes high.

[0208] In other words, the time when the first power signal transitions from the second level to the first level is delayed by a first duration relative to the time when the third power signal transitions from the first level to the second level; the time when the first power signal transitions from the first level to the second level is advanced by a first duration relative to the time when the third power signal transitions from the second level to the first level. Here, the first duration is 1 to 2H, meaning the first duration is greater than or equal to the line scan duration and less than or equal to twice the line scan duration, where H represents the time required to scan one line of pixels.

[0209] Figure 12 exemplarily illustrates an overall timing diagram of a display device according to an embodiment of this application. As shown in Figure 12, in LHB mode, the frame time may include at least a first display time, a touch time, and a second display time. The first power signal may be a signal labeled LVGL1, the clock signal may include signals labeled CLK1 to 8, the second power signal may include signals labeled VGL / LVGL, the third power signal may include signals labeled VDDO / VDDE, and Out1 to 4 represent output signals. In addition, Figure 12 also shows the frame start signal STV, the reset signal Treset, and the source drive signal output by the source drive circuit in the display device.

[0210] Current embedded touch panels, such as In-cell Touch display panels, are increasingly pursuing higher refresh rates while supporting active pen touch. This places higher demands on the voltage retention capability of the PU node during the touch phase. Because a higher refresh rate means a shorter charging time for each pixel—for example, increasing the refresh rate from 60 Hz to 120 Hz halves the pixel charging time—the leakage time of the PU node relatively increases, having a greater impact on the shift register output. Especially when the shift register operates at high temperatures, the drift of transistors M2 / M6 / M8 becomes more severe, leading to more severe leakage at the PU node. This can result in insufficient shift register output, causing horizontal lines to appear on the display panel.

[0211] While adjusting the process to positively shift the transistor's threshold voltage Vth can reduce 0V leakage current, the improvement is minimal and reduces the noise immunity of the shift register. Alternatively, reducing the duration of the touch phase, such as a typical 180µs touch phase, is effective, but this significantly limits the application of active pen touch, as a shorter phase cannot meet the requirements of mainstream active pens, which generally require around 400µs. Therefore, existing improvements cannot meet the touch display requirements of high refresh rate embedded touch panels.

[0212] The shift register 10 provided in this application embodiment allows the voltage of the first node PU to remain constant during the touch phase, enabling the shift register 10 to output a clock signal normally. This avoids insufficient charging of the corresponding pixel row, improves horizontal stripe defects on the display panel, and enhances the image quality, especially for high refresh rate embedded touch panels such as In-cell Touch display panels. Furthermore, although the shift register 10 provided in this application embodiment increases the number of components, the manufacturing process remains unchanged, and the number of masks is not increased, so the cost remains the same. Therefore, the shift register 10 provided in this application embodiment, while maintaining the original process and cost, effectively solves the problem of voltage drop at the first node PU after the pit by eliminating the leakage path of the first node PU. This avoids abnormal display problems caused by excessively long touch phase time in embedded touch panels, and can be applied to products such as mobile terminals, notebooks, and tablet PCs (TPCs).

[0213] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0214] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0215] Although preferred embodiments of the present application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of the embodiments of the present application.

[0216] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or terminal device that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or terminal device. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or terminal device that includes the element.

[0217] The shift register, its driving method, gate driving circuit, and display device provided in this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A shift register, wherein, The shift register includes: an input circuit, a first control circuit, and an output circuit; The input circuit is connected to the input signal line and the first node respectively, and is configured to write the input signal into the first node under the control of the input signal on the input signal line; The first control circuit is electrically connected to the first node and the first power signal line respectively, and is configured to disconnect the connection between the first power signal line and the first node during the touch phase. The output circuit is electrically connected to the first node, the clock signal line, and the output signal line, respectively, and is configured to write the clock signal of the clock signal line into the output signal line under the control of the voltage of the first node.

2. The shift register according to claim 1, wherein, The first control circuit includes a reset module and a pull-down module; The reset module is electrically connected to the reset signal line, the first node, and the first power signal line, and is configured to control the connection and disconnection between the first power signal line and the first node under the control of the reset signal of the reset signal line. The pull-down module is electrically connected to the second node, the first node, and the first power signal line, respectively, and is configured to control the connection and disconnection of the first power signal line and the first node under the control of the voltage of the second node.

3. The shift register according to claim 2, wherein, The reset module includes a first transistor; The control electrode of the first transistor is electrically connected to the first sub-signal line, the first electrode is electrically connected to the first node, and the second electrode is electrically connected to the first power signal line; the reset signal line includes the first sub-signal line. The first sub-signal line is the signal line connected to the output control terminal of the target register; the target register is a register cascaded with the shift register, and the target register is located at the next level of the shift register.

4. The shift register according to claim 2, wherein, The reset module includes a second transistor; The control electrode of the second transistor is electrically connected to the second sub-signal line, the first electrode is electrically connected to the first node, and the second electrode is electrically connected to the first power signal line; the reset signal line includes the second sub-signal line.

5. The shift register according to claim 2, wherein, The second node includes a first drop-down node and a second drop-down node, and the drop-down module includes a first drop-down unit and a second drop-down unit; The first pull-down unit is electrically connected to the first pull-down node, the first node, and the first power signal line, respectively, and is configured to control the on / off state of the first power signal line and the first node under the control of the voltage of the first pull-down node; The second pull-down unit is electrically connected to the second pull-down node, the first node, and the first power signal line, respectively, and is configured to control the on / off state of the first power signal line and the first node under the control of the voltage of the second pull-down node.

6. The shift register according to claim 5, wherein, The first pull-down unit includes a third transistor; The control electrode of the third transistor is electrically connected to the first pull-down node, the first electrode is electrically connected to the first node, and the second electrode is electrically connected to the first power signal line.

7. The shift register according to claim 5, wherein, The second pull-down unit includes a fourth transistor; The control electrode of the fourth transistor is electrically connected to the second pull-down node, the first electrode is electrically connected to the first node, and the second electrode is electrically connected to the first power signal line.

8. The shift register according to any one of claims 1-7, wherein, The shift register also includes a first noise reduction circuit; The first noise reduction circuit is electrically connected to the first power signal line, the second node, and the second power signal line, respectively, and is configured to write the second power signal of the second power signal line into the second node under the control of the first power signal during the touch phase.

9. The shift register according to claim 8, wherein, The second node includes a first drop-down node and a second drop-down node, and the first noise reduction circuit includes a first noise reduction module and a second noise reduction module; The first noise reduction module is electrically connected to the first power signal line, the first drop-down node, and the second power signal line, respectively, and is configured to write the second power signal into the first drop-down node under the control of the first power signal during the touch phase. The second noise reduction module is electrically connected to the first power signal line, the second pull-down node, and the second power signal line respectively, and is configured to write the second power signal into the second pull-down node under the control of the first power signal during the touch phase.

10. The shift register according to claim 9, wherein, The first noise reduction module includes a fifth transistor; The control electrode of the fifth transistor is electrically connected to the first power signal line, the first electrode is electrically connected to the first pull-down node, and the second electrode is electrically connected to the second power signal line.

11. The shift register according to claim 9, wherein, The second noise reduction module includes a sixth transistor; The control electrode of the sixth transistor is electrically connected to the first power signal line, the first electrode is electrically connected to the second pull-down node, and the second electrode is electrically connected to the second power signal line.

12. The shift register according to any one of claims 1-7, wherein, The shift register also includes a second noise reduction circuit; The second noise reduction circuit is electrically connected to the first power signal line, the second power signal line, and the output signal line, respectively, and is configured to, during the touch phase, write the second power signal of the second power signal line into the output signal line under the control of the first power signal.

13. The shift register according to claim 12, wherein, The second noise reduction circuit includes a seventh transistor; The control electrode of the seventh transistor is electrically connected to the first power signal line, the first electrode is electrically connected to the output signal line, and the second electrode is electrically connected to the second power signal line.

14. The shift register according to any one of claims 1-7, wherein, The shift register also includes an output control circuit and a third noise reduction circuit; The output control circuit is electrically connected to the first node, the clock signal line, and the output control line, respectively, and is configured to write the clock signal into the output control line under the control of the voltage of the first node. The third noise reduction circuit is electrically connected to the first power signal line, the second power signal line, and the output control line, respectively, and is configured to write the second power signal of the second power signal line into the output control line under the control of the first power signal during the touch phase.

15. The shift register according to claim 14, wherein, The third noise reduction circuit includes an eighth transistor; The control electrode of the eighth transistor is electrically connected to the first power signal line, the first electrode is electrically connected to the output control line, and the second electrode is electrically connected to the second power signal line.

16. A gate driving circuit, wherein, The gate drive circuit includes a plurality of cascaded shift registers as described in any one of claims 1-15.

17. A display device, wherein, The display device includes the gate driving circuit as described in claim 16.

18. A driving method, wherein, The driving method for controlling the shift register as described in any one of claims 1-15 includes: In the first display stage, an input signal with a first level is written to the input signal line so that the input circuit writes the input signal with the first level to the first node; During the touch phase, a first power signal with a first level is written to the first power signal line, and the first control circuit is controlled to disconnect the connection between the first power signal line and the first node.

19. The driving method according to claim 18, wherein, After the touch phase, the method further includes: In the second display stage, a first power signal with a second level is written to the first power signal line, and a clock signal is written to the clock signal line so that the output circuit writes the clock signal to the output signal line. The first display stage also includes: Write the first power signal with the second level to the first power signal line; wherein the signals corresponding to the first level and the second level are out of phase.

20. The driving method according to claim 19, wherein, The shift register also includes a pull-up circuit, which is electrically connected to the third power signal line and the second node respectively. The first display stage also includes: Write a third power signal with a first level to the third power signal line so that the pull-up circuit can connect the second node and the third power signal line, and write the third power signal with the first level to the second node. The second display stage also includes: Write the third power signal with a first level to the third power signal line so that the pull-up circuit conducts the connection between the second node and the third power signal line, and write the third power signal with a first level to the second node; The touch phase also includes: Write a third power signal with a second level to the third power signal line to cause the pull-up circuit to disconnect the connection between the second node and the third power signal line; Wherein, the time point at which the first power signal transitions from the second level to the first level is delayed by a first duration relative to the time point at which the third power signal transitions from the first level to the second level; the time point at which the first power signal transitions from the first level to the second level is advanced by a first duration relative to the time point at which the third power signal transitions from the second level to the first level. Wherein, the first duration is greater than or equal to the line scan duration, and less than or equal to twice the line scan duration; the line scan duration represents the time required to scan one line of pixels.

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