Display panel and display apparatus

Abstract

Disclosed in the present disclosure are a display panel and a display apparatus. The display panel comprises a base substrate (10), a thin-film transistor layer (20) and a shielding layer (30), wherein the thin-film transistor layer (20) comprises a first source-drain sub-layer (21), the orthographic projection of the shielding layer (30) on the base substrate (10) serves as a first projection area, the orthographic projection of the first source-drain sub-layer (21) on the base substrate (10) serves as a second projection area, the orthographic projection of a second electrode of a target transistor (112) on the base substrate (10) serves as a third projection area, and at least a portion of the third projection area does not overlap with the first projection area and / or the second projection area.

Description

Display panel and display device Cross-references to related applications

[0001] This disclosure claims priority to Chinese patent application No. 2024115470605, filed on October 31, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure relates to the field of display technology, and in particular to a display panel and display device. Background Technology

[0003] Currently, most display panels use GOA (Gate On Array) instead of Gate IC (Gate Integrated Circuit) for display scanning drive, which can save costs, shorten process time, and achieve the effect of narrow bezels.

[0004] However, the display panel used may experience abnormal display issues due to static electricity. Using a BSM (Bottom Shelter Metal) to shield the TFTs (Thin Film Transistors) in the GOA can solve the static electricity problem, but it will increase the power consumption of the GOA. Summary of the Invention

[0005] This disclosure provides a display panel and display device designed to at least partially address the problem of increased power consumption in a GOA (Power On-Demand) system.

[0006] In a first aspect of this disclosure, a display panel is provided, the display panel comprising: a substrate having a display area and a non-display area located on one side of the display area; a thin-film transistor layer located on the substrate for forming a gate driving circuit in the non-display area; the gate driving circuit including a plurality of cascaded shift registers, the shift registers including a plurality of thin-film transistors, at least one of the plurality of thin-film transistors being a target transistor; the thin-film transistor layer including a first source-drain layer for forming a first electrode of the thin-film transistor; and a shielding layer located between the thin-film transistor layer and the substrate; the orthographic projection of the shielding layer on the substrate being a first projection region, the orthographic projection of the first source-drain layer on the substrate being a second projection region, and the orthographic projection of the second electrode of the target transistor on the substrate being a third projection region, the third projection region not overlapping at least partially with the first projection region and / or the second projection region.

[0007] In some embodiments, the target transistor may include the thin-film transistor with the largest aspect ratio among the plurality of thin-film transistors.

[0008] In some embodiments, the gate drive circuit further includes a square wave signal line, and the second terminal of the target transistor can be connected to the square wave signal line.

[0009] In some embodiments, the orthographic projection of the second electrode of the target transistor onto the substrate may at least partially not overlap with the orthographic projection of the shielding layer onto the substrate.

[0010] In some embodiments, the orthographic projection of the second electrode of the target transistor onto the substrate may not intersect with the orthographic projection of the shielding layer onto the substrate.

[0011] In some embodiments, the orthographic projection of the first electrode of the target transistor onto the substrate may at least partially not overlap with the orthographic projection of the shielding layer onto the substrate.

[0012] In some embodiments, each of the plurality of thin-film transistors other than the target transistor is a conventional transistor; the orthographic projection of the shielding layer on the substrate may include the orthographic projection of the conventional transistor on the substrate.

[0013] In some embodiments, the first source-drain layer may also be used to form the electrode transition portion of the target transistor, the electrode transition portion of the target transistor being connected to the active layer of the same target transistor through a via; the thin-film transistor layer may further include: a second source-drain layer located on the side of the first source-drain layer away from the substrate; the second source-drain layer is used to form the second electrode of the target transistor, the second electrode of the target transistor being connected to the electrode transition portion of the same target transistor through a via.

[0014] In some embodiments, the orthographic projection of the electrode junction of the target transistor onto the substrate may overlap with the orthographic projection of the second electrode of the same target transistor onto the substrate.

[0015] In some embodiments, the two ends of the second electrode of the target transistor can be connected to the electrode transition portion of the same target transistor through a through-hole, and the electrode transition portions connected to the two ends of the second electrode of the target transistor are different.

[0016] In some embodiments, the orthographic projections of the two ends of the second electrode of the target transistor onto the substrate may respectively include the orthographic projections of the respective connected electrode transition portions onto the substrate.

[0017] In some embodiments, the electrode junction of the target transistor can be connected to the active layer of the same target transistor via two vias.

[0018] In some embodiments, the target transistor has two second electrodes, each end of each second electrode of the target transistor being connected to an electrode junction of the same target transistor via a via.

[0019] In some embodiments, the thin-film transistor layer may further include: a semiconductor sublayer located on the side of the first source-drain layer near the substrate; the semiconductor sublayer being used to form the active layer of the thin-film transistor; and a gate sublayer located between the semiconductor sublayer and the first source-drain layer; the gate sublayer being used to form the gate of the thin-film transistor.

[0020] In some embodiments, the gate driving circuit further includes a square wave signal line, and the first source-drain layer is also used to form the square wave signal line; the gate sublayer can also be used to form a signal switching section, which is connected to the square wave signal line and the second electrode of the target transistor through vias.

[0021] In some embodiments, each of the plurality of thin-film transistors other than the target transistor is a conventional transistor; the first source-drain layer can also be used to form the second electrode of the conventional transistor, and the second electrode of the conventional transistor is connected to the active layer of the same conventional transistor through a via.

[0022] In a second aspect of this disclosure, a display device is provided, which may include a display panel as provided in the first aspect.

[0023] A display panel and display device according to one or more embodiments of the present disclosure include a substrate, a thin-film transistor layer, and a shielding layer. The substrate has a display area and a non-display area located on one side of the display area. The thin-film transistor layer is located on the substrate and is used to form a gate driving circuit in the non-display area. The gate driving circuit includes a plurality of cascaded shift registers, each shift register including a plurality of thin-film transistors. The shielding layer is located between the thin-film transistor layer and the substrate and can shield the TFTs in the GOA (Gate of Assembly) to prevent abnormal display problems caused by static electricity in the display panel. The thin-film transistor layer includes a first source-drain layer, which is used to form the first electrode of the thin-film transistor. The orthographic projection of the first source / drain layer onto the substrate is the first projection region, the orthographic projection of the shielding layer onto the substrate is the second projection region, and the orthographic projection of the second electrode of the target transistor onto the substrate is the third projection region. The third projection region at least partially does not overlap with the first and / or second projection regions. This reduces the overlap area between the region where the target transistor's second electrode transmits signals to the active layer and the orthographic projection of the shielding layer onto the substrate, thereby avoiding the increased capacitance caused by the overlap of signals transmitted through the signal lines and the shielding layer in the GOA, and thus reducing the power consumption of the GOA. Furthermore, since at least one of the multiple thin-film transistors is the target transistor, only the thin-film transistor with a larger increase in capacitance can be selected as the target transistor. This effectively reduces the power consumption of the GOA, and the shielding layer can also block most of the thin-film transistors, effectively improving abnormal display problems caused by static electricity in the display panel. Attached Figure Description

[0024] To more clearly illustrate the technical solutions in the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0025] Figure 1 shows a partial layout diagram of GOA in the related technology;

[0026] Figure 2 shows a schematic diagram of the structure of a display panel according to some embodiments of the present disclosure.

[0027] Figure 3 shows a top view of the substrate shown in Figure 2.

[0028] Figure 4 shows a schematic diagram of the shift register in Figure 3.

[0029] Figure 5 shows a schematic diagram of one circuit layout for the shift register in Figure 4.

[0030] Figure 6 shows a partial structural schematic diagram of the display panel in Figure 2.

[0031] Figure 7 shows a schematic diagram of the semiconductor sublayer distribution in Figure 6.

[0032] Figure 8 shows a schematic diagram of the distribution of a gate sublayer in Figure 6.

[0033] Figure 9 shows a schematic diagram of the distribution of another gate sublayer in Figure 6.

[0034] Figure 10 shows a schematic diagram of the distribution of the first source leak layer in Figure 6.

[0035] Figure 11 shows a schematic diagram of the distribution of the shielding layer in Figure 6.

[0036] Figure 12 shows another circuit layout diagram of the shift register in Figure 4.

[0037] Figure 13 shows another circuit layout diagram of the shift register in Figure 4.

[0038] Figure 14 shows a schematic diagram of the distribution of the first source leak layer in Figure 13.

[0039] Figure 15 shows a schematic diagram of the distribution of the second source leak layer in Figure 13.

[0040] Figure 16 shows another circuit layout diagram of the shift register in Figure 4.

[0041] Explanation of reference numerals in the attached figures: 10': Substrate; 21': Active layer; 22': Gate; 23': First electrode; 24': Second electrode; 30': Shielding layer; 10: Substrate; 11: Display area; 12: Non-display area; 20: Thin film transistor layer; 21: First source / drain layer; 22: Second source / drain layer; 23: Semiconductor sublayer; 24: Gate sublayer; 30: Shielding layer; 100: Gate drive circuit; 110: Shift register; 111: Thin film transistor; 112: Target transistor; 113: Ordinary transistor; 120: Square wave signal line. Detailed Implementation

[0042] To enable those skilled in the art to more clearly understand this disclosure, the technical solutions in the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. Based on the embodiments of this disclosure, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this disclosure.

[0043] Display panels using GOA (Glass Outer Array) all fail electrostatic discharge (ESD) tests. This is because static electricity accumulates on the back of the panel after the test, forming an electric field that causes the electrical characteristics of the TFTs in the GOA to drift, resulting in abnormal output waveforms and abnormal display problems caused by ESD. Currently, the most effective solution to the ESD problem is to add a BSM (Browser Shielding System) to shield the TFTs in the GOA. Figure 1 shows a partial layout diagram of the GOA in related technologies. Referring to Figure 1, the TFTs located on the substrate 10' have an active layer 21', a gate 22', a first electrode 23', and a second electrode 24'. The gate 22' of the TFT is disposed on the active layer 21' of the TFT, and the first electrode 23' and the second electrode 24' of the TFT are connected to the active layer 21' of the TFT through vias. A shielding layer 30' is located between the substrate 10' and the TFTs. The orthographic projection of the shielding layer 30' onto the substrate 10' includes the orthographic projection of each TFT onto the substrate 10'. While this can solve the ESD problem, it also increases the power consumption of the GOA.

[0044] To address the issue of increased power consumption in the GOA (Gateway for Aspect Ratio) in related technologies, the inventors analyzed the power consumption of the GOA when the BSM (Body Shielding System) blocks different areas of the TFT (Thin Film Frame), as shown in Table 1 below:

[0045] Table 1. Power consumption of GOA when it is blocked by BSM in different regions.

[0046] In some embodiments, the GOA may include a Gate GOA and an EM GOA. Exemplarily, the Gate GOA may be connected at least to the TFT gate of the data writing sub-circuit in the pixel circuit, and may also be connected to the TFT gate of the compensation sub-circuit in the pixel circuit. The EM GOA may be connected to the TFT gate of the light emission control sub-circuit in the pixel circuit.

[0047] As shown in Table 1, after the BSM blocks the Gate GOA, the power consumption of the GOA increases by 16mW. Blocking the EM GOA with the BSM does not significantly increase the power consumption of the GOA. Therefore, the power consumption increase caused by the BSM blocking the Gate GOA accounts for the majority of the increase in GOA power consumption, while the power consumption increase caused by the BSM blocking the EM GOA is relatively small.

[0048] Based on the above, the inventors further analyzed the load of different TFTs in Gate GOA when there is no BSM obstruction and found that among the capacitance generated by the square wave signal and different TFTs, the capacitance generated by the TFT with the largest aspect ratio is mainly generated (accounting for nearly 50%).

[0049] Then, the capacitance change of the TFT after BSM blocking is analyzed, as shown in Table 2 below:

[0050] Table 2: Capacitance variations in different regions of the TFT

[0051] Table 2 shows that the capacitance change generated by the square wave signal of Gate GOA increased from 200pF to 287pF after BSM blocking, mainly due to the capacitance between BSM and the active layer. This indicates that the capacitance increase between BSM and the active layer of the TFT with the largest aspect ratio is the greatest. The capacitance between the active layer of the TFT with the largest aspect ratio and BSM accounts for approximately 35% (50% × 67.4%). In contrast, the capacitance change generated by the square wave signal of EM GOA after BMS blocking is smaller (22pF), and the capacitance between BSM and the active layer accounts for a smaller proportion.

[0052] Comparing EM GOA and Gate GOA, the main difference lies in the input signal of the TFT with the largest aspect ratio (200μm~500μm) in Gate GOA. This square wave signal has a longer trace length through the active layer in this TFT, resulting in a significant increase in capacitance after BMS blocking, and consequently, a larger increase in power consumption. In contrast, the input signal of the TFT with the largest aspect ratio in EM GOA is a constant voltage signal, resulting in a smaller increase in capacitance after BMS blocking, and thus a smaller increase in power consumption.

[0053] In summary, the main reason for the increased power consumption of the GOA is that the square wave signal of the TFT with the largest aspect ratio in the Gate GOA overlaps more with the BSM.

[0054] Based on the above analysis, a first aspect of this disclosure provides a display panel. Figure 2 is a schematic diagram of the structure of a display panel in one or more embodiments of this disclosure. Referring to Figure 2, the display panel includes a substrate 10, a thin-film transistor layer 20, and a shielding layer 30. The thin-film transistor layer 20 is located on the substrate 10, and the shielding layer 30 is located between the thin-film transistor layer 20 and the substrate 10.

[0055] Figure 3 is a top view of the substrate of Figure 2. Referring to Figure 3, the substrate 10 has a display area 11 and a non-display area 12 located on one side of the display area 11. A thin-film transistor layer 20 is used to form a gate driving circuit 100 in the non-display area 12. The gate driving circuit 100 includes a plurality of cascaded shift registers 110.

[0056] Figure 4 is a schematic diagram of the shift register in Figure 3. Please refer to Figure 4. The shift register 110 includes multiple thin-film transistors 111, and at least one of the multiple thin-film transistors 111 is the target transistor 112.

[0057] Figure 5 is a schematic diagram of the circuit layout of the shift register in Figure 4. Referring to Figure 5, the thin-film transistor layer 20 includes a first source-drain layer 21, which forms the first electrode of the thin-film transistor 111. The orthogonal projection of the shielding layer 30 onto the substrate 10 is the first projection region, the orthogonal projection of the first source-drain layer 21 onto the substrate 10 is the second projection region, and the orthogonal projection of the second electrode of the target transistor 112 onto the substrate 10 is the third projection region. The third projection region does not overlap with the first projection region and / or the second projection region at least partially. That is, the third projection region may not overlap with the first projection region at least partially, and the second projection region may contain the third projection region; the third projection region may not overlap with the second projection region at least partially, and the first projection region may contain the third projection region; or the third projection region may not overlap with the first projection region at least partially, and the third projection region may not overlap with the second projection region at least partially.

[0058] The aforementioned display panel includes a substrate 10, a thin-film transistor layer 20, and a shielding layer 30. The substrate 10 has a display area 11 and a non-display area 12 located on one side of the display area 11. The thin-film transistor layer 20 is located on the substrate 10 and is used to form a gate driving circuit 100 in the non-display area 12. The gate driving circuit 100 includes a plurality of cascaded shift registers 110, each shift register including a plurality of thin-film transistors 111. The shielding layer 30 is located between the thin-film transistor layer 20 and the substrate 10, and can shield the TFTs in the GOA (Gate of Assembly) to prevent abnormal display problems caused by static electricity in the display panel. The thin-film transistor layer 20 includes a first source / drain layer 21, which is used to form the first electrode of the thin-film transistors 111. The orthographic projection of the shielding layer 30 onto the substrate 10 is the first projection region, the orthographic projection of the first source / drain layer 21 onto the substrate 10 is the second projection region, and the orthographic projection of the second electrode of the target transistor 112 onto the substrate 10 is the third projection region. The third projection region at least partially does not overlap with the first and / or second projection regions. This reduces the overlap area between the region where the target transistor 112 transmits signals to the active layer and the orthographic projection of the shielding layer 30 onto the substrate 10, thereby avoiding the increased capacitance caused by the overlap between the signal transmitted by the signal lines in the GOA (such as a square wave signal) and the signal transmitted by the shielding layer 30 (i.e., the BSM), thus reducing the power consumption of the GOA. Furthermore, if at least one of the multiple thin-film transistors 111 is the target transistor 112 (such as the TFT with the largest aspect ratio), only the thin-film transistor 111 with a larger capacitance increase can be selected as the target transistor 112. This effectively reduces the power consumption of the GOA. Additionally, the shielding layer 30 can also block most of the thin-film transistors, effectively improving abnormal display problems caused by static electricity in the display panel.

[0059] For example, the gate drive circuit 100 can be a Gate GOA.

[0060] Exemplarily, the thin-film transistor 111 has an active layer, a gate, a first electrode, and a second electrode. The gate of the thin-film transistor 111 is disposed on the active layer of the same thin-film transistor 111, and the first electrode and the second electrode of the thin-film transistor 111 are respectively connected to the active layer of the same thin-film transistor 111 through vias. The orthographic projections of the gate, the first electrode, and the second electrode of the thin-film transistor 111 onto the substrate 10 at least partially overlap with the orthographic projections of the active layer of the thin-film transistor 111 onto the substrate 10.

[0061] For example, referring to Figure 4, the shift register 110 may also include at least one capacitor and multiple signal lines.

[0062] Taking Figure 4 as an example, the shift register 110 includes eight thin-film transistors 111, two capacitors, and four signal lines. The eight thin-film transistors 111 are transistor T1, transistor T2, transistor T3, transistor T4, transistor T5, transistor T6, transistor T7, and transistor T8. The two capacitors 120 are capacitor C1 and capacitor C2. The four signal lines are clock signal line CK, clock signal line CB, power supply signal line VGH, and power supply signal line VGL.

[0063] The gate of the first transistor T1 is connected to the first clock signal line CK, the second terminal of the first transistor T1 is connected to the signal input terminal STV of the shift register 110, and the first terminal of the first transistor T1 is connected to the first node N1. The gate of the second transistor T2 is connected to the first node N1, the second terminal of the second transistor T2 is connected to the first clock signal line CK, and the first terminal of the second transistor T2 is connected to the second node N2. The gate of the third transistor T3 is connected to the first clock signal line CK, the second terminal of the third transistor T3 is connected to the second power supply signal line VGL, and the first terminal of the third transistor T3 is connected to the second node N2.

[0064] The gate of the sixth transistor T6 is connected to the second node N2, the second terminal of the sixth transistor T6 is connected to the first power supply connection line VGH, and the first terminal of the sixth transistor T6 is connected to the third node N3. The gate of the seventh transistor T7 is connected to the second clock signal line CB, the second terminal of the seventh transistor T7 is connected to the first node N1, and the first terminal of the seventh transistor T7 is connected to the third node N3. The gate of the eighth transistor T8 is connected to the second power supply signal line VGL, the second terminal of the eighth transistor T8 is connected to the first node N1, and the first terminal of the eighth transistor T8 is connected to the fourth node N4.

[0065] The gate of the fourth transistor T4 is connected to the second node N2, the second terminal of the fourth transistor T4 is connected to the first power supply signal line VGH, and the first terminal of the fourth transistor T4 is connected to the signal output terminal OUT of the shift register 110. The first terminal of the first capacitor C1 is connected to the first power supply signal line VGH, and the second terminal of the first capacitor C1 is connected to the signal output terminal OUT of the shift register 110. The gate of the fifth transistor T5 is connected to the fourth node N4, the second terminal of the fifth transistor T5 is connected to the second clock signal terminal CB, and the first terminal of the fifth transistor T5 is connected to the signal output terminal OUT of the shift register 110.

[0066] For example, the first node N1, the second node N2, the third node N3, and the fourth node N4 are common connection points of at least two thin-film transistors 111. Taking Figure 4 as an example, the first node N1 is the common connection point of the second terminal of the first transistor T1, the gate of the second transistor T2, the first terminal of the seventh transistor T7, and the first terminal of the eighth transistor T8. The second node N2 is the common connection point of the second terminal of the second transistor T2, the second terminal of the third transistor T3, the gate of the fourth transistor T4, and the gate of the sixth transistor T6. The third node N3 is the common connection point of the second terminal of the sixth transistor T6,

[0067] Thin-film transistor 111 can be either an N-type TFT or a P-type TFT. When TFT 111 is a P-type TFT, the first electrode is the drain and the second electrode is the source. When TFT 111 is an N-type TFT, the first electrode is the source and the second electrode is the drain. The signals transmitted on the first clock signal line CK and the second clock signal line CB can be complementary square wave signals. The signals on the first power signal line VGH and the second power signal line VGL can be constant voltage signals with different voltages, such as a high-level signal transmitted on the first power signal line VGH and a low-level signal transmitted on the second power signal line VGL.

[0068] In some embodiments, referring to FIG4, the target transistor 112 may include the thin-film transistor 111 with the largest aspect ratio among a plurality of thin-film transistors 111. Taking FIG4 as an example, the fifth transistor T5 is the target transistor 112.

[0069] As mentioned earlier, the main reason for the increased power consumption of the GOA is the significant overlap between the square wave signal of the TFT with the largest aspect ratio in the gate drive circuit and the BSM. The target transistor 112 includes the thin-film transistor 111 with the largest aspect ratio among multiple thin-film transistors 111, i.e., the thin-film transistor 111 with the greatest impact on GOA power consumption is selected as the target transistor 112. The orthographic projection of the shielding layer 30 on the substrate 10 is the first projection region, the orthographic projection of the first source / drain layer 21 on the substrate 10 is the second projection region, and the orthographic projection of the second electrode of the target transistor 112 on the substrate 10 is the third projection region. Since the third projection region does not overlap with the first projection region and / or the second projection region at least partially, the increase in capacitance due to the overlap between the square wave signal of the target transistor 112 and the signal of the shielding layer 30 is less, and the power consumption increase due to the addition of the BSM is lower, thereby effectively reducing the power consumption of the GOA.

[0070] For example, referring to Figure 4, the gate drive circuit 100 also includes a square wave signal line 120, and the second terminal of the target transistor 112 is connected to the square wave signal line 120. Taking Figure 4 as an example, the second clock signal line CB is the square wave signal line 120.

[0071] As mentioned earlier, the main reason for the increased power consumption of the GOA is the significant overlap between the square wave signal of the TFT with the largest aspect ratio in the gate drive circuit and the BSM. The target transistor 112, as the TFT with the largest aspect ratio in the gate drive circuit, has its second electrode connected to the square wave signal line 120, meaning the input signal of the target transistor 112 is a square wave signal. The orthographic projection of the shielding layer 30 onto the substrate 10 is the first projection region, the orthographic projection of the first source / drain layer 21 onto the substrate 10 is the second projection region, and the orthographic projection of the second electrode of the target transistor 112 onto the substrate 10 is the third projection region. By ensuring that the third projection region does not overlap with at least part of the first and / or second projection regions, the increased capacitance due to the overlap between the square wave signal of the target transistor 112 and the signal of the shielding layer 30 can be reduced, effectively lowering the increased power consumption caused by the addition of the BSM.

[0072] The following describes in detail how the orthographic projection of the second electrode of the target transistor 112 on the substrate 10 does not at least partially overlap with the orthographic projection of the shielding layer 30 on the substrate 10. At this time, the orthographic projection of the first source / drain layer 21 on the substrate 10 may at least partially overlap with the orthographic projection of the second electrode of the target transistor 112 on the substrate 10, or it may not intersect with the orthographic projection of the second electrode of the target transistor 112 on the substrate 10.

[0073] To facilitate identification of the active layer, gate, first electrode, and second electrode distribution of each thin-film transistor 111 in Figure 5, a brief introduction to each sublayer within the thin-film transistor layer 20 is provided first. Figure 6 is a partial structural schematic diagram of the display panel in Figure 2. Referring to Figure 6, in some embodiments, the thin-film transistor layer 20 may further include a semiconductor sublayer 23 and a gate sublayer 24. The semiconductor sublayer 23, gate sublayer 24, and first source / drain layer 21 are sequentially stacked on the side of the shielding layer 30 away from the substrate 10. Insulating layers are provided between the shielding layer 30 and the semiconductor sublayer 23, between the semiconductor sublayer 23 and the gate sublayer 24, and between the gate sublayer 24 and the first source / drain layer 21. Through holes can be provided in the insulating layers to achieve connections between different layers on both sides of the insulating layer.

[0074] Figure 7 is a schematic diagram of the semiconductor sublayer distribution in Figure 6. Referring to Figure 7, semiconductor sublayer 23 is used to form the active layer of thin-film transistor 111. Figure 8 is a schematic diagram of the distribution of one gate sublayer in Figure 6, and Figure 9 is a schematic diagram of the distribution of another gate sublayer in Figure 6. Referring to Figures 8 and 9, thin-film transistor layer 20 may include two gate sublayers 24. One gate sublayer 24 is used to form the gate of thin-film transistor 111, and the two gate sublayers 24 are used to form the two electrodes of a capacitor, respectively. Figure 10 is a schematic diagram of the distribution of the first source-drain sublayer in Figure 6. Referring to Figure 10, the first source-drain sublayer 21 can be used to form the first and second electrodes of thin-film transistor 111, as well as some signal lines (such as the first clock signal line CK and the second clock signal line CB). Figure 11 is a schematic diagram of the distribution of the shielding layer in Figure 6. Referring to Figure 11, shielding layer 30 is used to form BSM and some signal lines (such as the second power signal line VGL).

[0075] In some embodiments, referring to FIG5, the orthographic projection of the second electrode of the target transistor 112 on the substrate 10 may at least partially not overlap with the orthographic projection of the shielding layer 30 on the substrate 10. That is, the orthographic projection of the second electrode of the target transistor 112 on the substrate 10 may partially overlap with the orthographic projection of the shielding layer 30 on the substrate 10, and another portion may not overlap with the orthographic projection of the shielding layer 30 on the substrate 10, or it may not intersect with the portion of the orthographic projection of the shielding layer 30 on the substrate 10. By ensuring that the orthographic projection of the second electrode of the target transistor 112 on the substrate 10 at least partially does not overlap with the orthographic projection of the shielding layer 30 on the substrate 10, it is possible to achieve that the orthographic projection of the second electrode of the target transistor 112 on the substrate 10 is at least partially not overlapping with the orthographic projection of the shielding layer 30 on the substrate 10.

[0076] For example, referring to FIG5, the orthographic projection of the second electrode of the target transistor 112 on the substrate 10 may not intersect with the orthographic projection of the shielding layer 30 on the substrate 10.

[0077] In one possible embodiment, referring to FIG5, the orthographic projection of the shielding layer 30 on the substrate 10 may include the orthographic projection of the gate and first electrode of the target transistor 112 on the substrate 10.

[0078] Compared with Figure 1, Figure 5 shows that the capacitance caused by the overlap of the square wave signal and the shielding layer 30 signal is reduced by 93%, and the power consumption of the GOA rise is reduced by 93%.

[0079] Figure 12 is a schematic diagram of another circuit layout for the shift register in Figure 4. Referring to Figure 12, in another possible embodiment, the orthographic projection of the first electrode of the target transistor 112 on the substrate 10 may at least partially not overlap with the orthographic projection of the shielding layer 30 on the substrate 10. That is, the orthographic projection of the first electrode of the target transistor 112 on the substrate 10 may partially overlap with the orthographic projection of the shielding layer 30 on the substrate 10, and another part may not overlap with the orthographic projection of the shielding layer 30 on the substrate 10, or it may not intersect with the portion of the orthographic projection of the shielding layer 30 on the substrate 10.

[0080] For example, referring to FIG12, the orthographic projection of the shielding layer 30 on the substrate 10 may include the orthographic projection of the gate of the target transistor 112 on the substrate 10.

[0081] The shielding layer 30, by obscuring the gate of the thin-film transistor 111, affects the number of charge carriers in the thin-film transistor 111, directly impacting the active layer characteristics of the shielding layer 30. Therefore, the effect of the shielding layer 30 obscuring the gate of the thin-film transistor 111 is greater than the effect of obscuring the source and drain of the thin-film transistor 111. In both possible embodiments, the orthographic projection of the shielding layer 30 onto the substrate 10, including the orthographic projection of the gate of the target transistor 112 onto the substrate 10, can effectively control the electrical characteristic drift of the thin-film transistor 111, ensuring the improvement effect of abnormal displays caused by static electricity.

[0082] In some embodiments, referring to FIG4, each of the plurality of thin-film transistors 111, excluding the target transistor 112, is a conventional transistor 113. Referring to FIG5, the orthographic projection of the shielding layer 30 on the substrate 10 may include the orthographic projection of the conventional transistor 113 on the substrate 10. That is, the orthographic projection of the shielding layer 30 on the substrate 10 includes the orthographic projection of the active layer, gate, first electrode, and second electrode of the conventional transistor 113 on the substrate 10.

[0083] In the above embodiments, each thin-film transistor 111 except for the target transistor 112 can be completely shielded by the shielding layer 30, which can effectively improve the static electricity problem of the display panel, while having little impact on the increase of GOA power consumption.

[0084] The following describes in detail how the orthographic projection of the second electrode of the target transistor 112 on the substrate 10 does not at least partially overlap with the orthographic projection of the first source / drain layer 21 on the substrate 10. At this time, the orthographic projection of the shielding layer 30 on the substrate 10 may at least partially overlap with the orthographic projection of the second electrode of the target transistor 112 on the substrate 10, or it may not intersect with the orthographic projection of the second electrode of the target transistor 112 on the substrate 10.

[0085] Figure 13 is another circuit layout diagram of the shift register in Figure 4, Figure 14 is a layout diagram of the first source-drain layer in Figure 13, and Figure 15 is a circuit layout diagram of the second source-drain layer in Figure 13. Please refer to Figures 13, 14 and 15. In a certain embodiment, the first source-drain layer 21 can also be used to form the electrode transition portion of the target transistor 112. The electrode transition portion of the target transistor 112 is connected to the active layer of the same target transistor 112 through a via.

[0086] The thin-film transistor layer 20 also includes a second source / drain layer 22, which is located on the side of the first source / drain layer 21 away from the substrate 10. The second source / drain layer 22 is used to form the second electrode of the target transistor 112, which is connected to the electrode junction of the same target transistor 112 through a via.

[0087] By forming the electrode transfer portion of the target transistor 112 through the first source-drain layer 21, the second electrode of the target transistor 112 can be transferred from the first source-drain layer 21 to the second source-drain layer 22. The second electrode of the target transistor 112 located in the second source-drain layer 22 can be connected to the active layer of the same target transistor 112 through the electrode transfer portion located in the first source-drain layer 21. In this way, the orthographic projection of the second electrode of the target transistor 112 on the substrate 10 can be realized, at least partially, without overlapping with the orthographic projection of the first source-drain layer 21 on the substrate 10.

[0088] In some embodiments, referring to FIG13, the orthographic projection of the electrode transition portion of the target transistor 112 on the substrate 10 can overlap with the orthographic projection portion of the second electrode of the same target transistor 112 on the substrate 10, so that the second electrode of the target transistor 112 can be connected to the electrode transition portion of the same target transistor 112 through the through hole.

[0089] For example, referring to FIG13, the two ends of the second electrode of the target transistor 112 can be connected to the electrode transition portion of the same target transistor 112 through a through hole, and the electrode transition portions connected to the two ends of the second electrode of the target transistor 112 are different.

[0090] For example, referring to FIG13, the orthographic projections of the two ends of the second pole of the target transistor 112 on the substrate 10 respectively include the orthographic projections of their respective connected electrode transition portions on the substrate 10, so that the second pole of the target transistor 112 can be connected to the electrode transition portion of the same target transistor 112 through the through hole.

[0091] For example, referring to Figure 13, the electrode junction of the target transistor 112 is connected to the active layer of the same target transistor 112 through two vias. By reducing the number of vias from six to two, the contact area between the first source / drain sublayer 21 and the semiconductor sublayer 23 can be reduced, preventing the square wave signal input to the target transistor 112 from entering the active layer from the source and overlapping with the signal in the shielding layer 30 to generate capacitance, thereby reducing the power consumption of the GOA.

[0092] For example, referring to FIG13, the target transistor 112 has two second poles, and each end of each second pole of the target transistor 112 is connected to the electrode transition portion of the same target transistor 112 through a through hole.

[0093] In some embodiments, referring to FIG13, the thin-film transistor layer 20 may further include a semiconductor sublayer 23 and a gate sublayer 24. The semiconductor sublayer 23 is located on the side of the first source-drain layer 21 near the substrate 10. The semiconductor sublayer 23 is used to form the active layer of the thin-film transistor 111. The gate sublayer 24 is located between the semiconductor sublayer 23 and the first source-drain layer 21. The gate sublayer 24 is used to form the gate of the thin-film transistor 111.

[0094] For example, referring to FIG13, the gate drive circuit 100 may further include a square wave signal line 120, and the first source-drain layer 21 is also used to form the square wave signal line 120. The gate sublayer 24 is also used to form a signal transition section, which is connected to the square wave signal line 120 and the second terminal of the target transistor 112 through vias.

[0095] In some embodiments, referring to FIG4, each of the plurality of thin-film transistors 111, except for the target transistor 112, is a conventional transistor 113. Referring to FIG13, the first source-drain layer 21 can also be used to form the second electrode of the conventional transistor 113, and the second electrode of the conventional transistor 113 is connected to the active layer of the same conventional transistor 113 through a via.

[0096] Compared with Figure 1, Figure 13 shows that the capacitance caused by the overlap of the square wave signal and the shielding layer 30 signal is reduced by 76%, and the power consumption of the GOA rise is reduced by 76%.

[0097] Figure 16 is a schematic diagram of another circuit distribution of the shift register in Figure 4. Referring to Figure 16, in some embodiments, the orthographic projection of the second pole of the target transistor 112 on the substrate 10 does not overlap at least partially with the orthographic projection of the shielding layer 30 on the substrate 10, and does not overlap at least partially with the orthographic projection of the first source-drain layer 21 on the substrate 10.

[0098] Compared with Figure 1, Figure 16 shows that the capacitance caused by the overlap of the square wave signal and the shielding layer 30 signal is reduced by 99%, and the power consumption of the GOA rise is reduced by 99%.

[0099] A second aspect of this disclosure provides a display device that includes a display panel as provided in the first aspect embodiment.

[0100] In this disclosure, unless otherwise expressly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0101] In the description of this disclosure, it should be understood that the terms “center,” “longitudinal,” “lateral,” “length,” “width,” “thickness,” “upper,” “lower,” “front,” “rear,” “left,” “right,” “vertical,” “horizontal,” “top,” “bottom,” “inner,” “outer,” “clockwise,” and “counterclockwise” indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this disclosure and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this disclosure.

[0102] In this disclosure, unless otherwise expressly specified and limited, the terms "connection," "fixed," etc., should be interpreted broadly. For example, "fixed" can mean a fixed connection, a detachable connection, or an integral part; it can mean a mechanical connection or an electrical connection; it can mean a direct connection or an indirect connection through an intermediate medium; it can mean the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this disclosure according to the specific circumstances.

[0103] Furthermore, the use of terms such as "first" and "second" in this disclosure is for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, features defined with "first" or "second" may explicitly or implicitly include one or more features. In the description of this disclosure, "multiple" means two or more, unless otherwise explicitly specified.

[0104] Although embodiments of the present disclosure have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the present disclosure, the scope of which is defined by the claims and their equivalents.

Claims

1. A display panel, comprising: The substrate (10) has a display area (11) and a non-display area (12) located on one side of the display area (11); A thin-film transistor layer (20), located on the substrate (10), is used to form a gate driving circuit (100) in the non-display area (12); the gate driving circuit (100) includes a plurality of cascaded shift registers (110), each shift register (110) including a plurality of thin-film transistors (111), at least one of the plurality of thin-film transistors (111) being a target transistor (112); the thin-film transistor layer (20) includes a first source-drain layer (21), the first source-drain layer (21) being used to form the first electrode of the thin-film transistor (111); and A shielding layer (30) is located between the thin film transistor layer (20) and the substrate (10); the orthographic projection of the shielding layer (30) on the substrate (10) is a first projection region, the orthographic projection of the first source-drain layer (21) on the substrate (10) is a second projection region, and the orthographic projection of the second electrode of the target transistor (112) on the substrate (10) is a third projection region, and the third projection region does not overlap with the first projection region and / or the second projection region at least partially.

2. The display panel according to claim 1, wherein, The target transistor (112) includes the thin-film transistor (111) with the largest aspect ratio among the plurality of thin-film transistors (111).

3. The display panel according to claim 2, wherein, The gate drive circuit (100) further includes a square wave signal line (120), and the second pole of the target transistor (112) is connected to the square wave signal line (120).

4. The display panel according to any one of claims 1-3, wherein, The orthographic projection of the second pole of the target transistor (112) onto the substrate (10) is at least partially not overlapping with the orthographic projection of the shielding layer (30) onto the substrate (10).

5. The display panel according to claim 4, wherein, The orthographic projection of the second pole of the target transistor (112) onto the substrate (10) does not intersect with the orthographic projection of the shielding layer (30) onto the substrate (10).

6. The display panel according to claim 4, wherein, The orthographic projection of the first pole of the target transistor (112) onto the substrate (10) is at least partially not overlapping with the orthographic projection of the shielding layer (30) onto the substrate (10).

7. The display panel according to claim 4, wherein, Each of the plurality of thin-film transistors (111) except for the target transistor (112) is a common transistor (113); the orthographic projection of the shielding layer (30) on the substrate (10) includes the orthographic projection of the common transistor (113) on the substrate (10).

8. The display panel according to any one of claims 1-3, wherein, The first source drain layer (21) is also used to form the electrode transition portion of the target transistor (112), and the electrode transition portion of the target transistor (112) is connected to the active layer of the same target transistor (112) through a through hole; The thin-film transistor layer (20) further includes: The second source drain layer (22) is located on the side of the first source drain layer (21) away from the substrate (10); the second source drain layer (22) is used to form the second electrode of the target transistor (112), and the second electrode of the target transistor (112) is connected to the electrode transition portion of the same target transistor (112) through a through hole.

9. The display panel according to claim 8, wherein, The orthographic projection of the electrode junction of the target transistor (112) on the substrate (10) overlaps with the orthographic projection of the second electrode of the same target transistor (112) on the substrate (10).

10. The display panel according to claim 9, wherein, The two ends of the second electrode of the target transistor (112) are respectively connected to the electrode transition portion of the same target transistor (112) through a through hole, and the electrode transition portions connected to the two ends of the second electrode of the target transistor (112) are different.

11. The display panel according to claim 10, wherein, The two ends of the second pole of the target transistor (112) are projected onto the substrate (10) respectively, including the projected onto the substrate (10) of the respective connected electrode adapter.

12. The display panel according to claim 11, wherein, The electrode junction of the target transistor (112) is connected to the active layer of the same target transistor (112) through two through holes.

13. The display panel according to claim 10, wherein, The target transistor (112) has two second poles, and each end of each second pole of the target transistor (112) is connected to the electrode transition portion of the same target transistor (112) through a through hole.

14. The display panel according to claim 8, wherein, The thin-film transistor layer (20) further includes: A semiconductor sublayer (23) is located on the side of the first source / drain layer (21) near the substrate (10); the semiconductor sublayer (23) is used to form the active layer of the thin-film transistor (111); and A gate sublayer (24) is located between the semiconductor sublayer (23) and the first source-drain sublayer (21); the gate sublayer (24) is used to form the gate of the thin film transistor (111).

15. The display panel according to claim 8, wherein, The gate drive circuit (100) further includes a square wave signal line (120), and the first source-drain layer (21) is also used to form the square wave signal line (120); the gate sublayer (24) is also used to form a signal switching section, and the signal switching section is connected to the square wave signal line (120) and the second pole of the target transistor (112) through a through hole.

16. The display panel according to claim 8, wherein, Each of the plurality of thin-film transistors (111) except for the target transistor (112) is a common transistor (113); the first source-drain layer (21) is also used to form the second electrode of the common transistor (113), and the second electrode of the common transistor (113) is connected to the active layer of the same common transistor (113) through a via.

17. A display device comprising a display panel as claimed in any one of claims 1-16.

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