Signal transmission method and apparatus

Abstract

The present application provides a signal transmission method and an apparatus, which can support signal transmission at higher rates and improve the reliability of transmission. The method comprises: acquiring a first signal; on the basis of a 10-bit symbol granularity, performing interleaving processing on the first signal to obtain a second signal; and sending the second signal, wherein the first signal comprises 32 logical channel signals, for example, the first signal may be generated by eight 100 Gbit / s, or four 200 Gbit / s, or two 400 Gbit / s, or one 800 Gbit / s OTN signal, the first signal has undergone first FEC processing, and the second signal comprises 4 physical channel signals.

Description

A signal transmission method and apparatus

[0001] This application claims priority to Chinese Patent Application No. 202411562466.0, filed on November 1, 2024, entitled "A Signal Transmission Method and Apparatus", and Chinese Patent Application No. 202511309095.X, filed on September 12, 2025, entitled "A Signal Transmission Method and Apparatus", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of optical communication, and more specifically, to a signal transmission method and apparatus. Background Technology

[0003] Optical networks are gradually evolving towards ultra-high-speed transmission technologies, such as optical transport network (OTN) technologies with speeds of 100G, 400G, or 800G, which are gradually becoming the main choice for transmission networks.

[0004] OTN is a wavelength division multiplexing (WDM) transmission network based on fiber optic interconnection. For a single high-speed optical port, time division multiplexing (TDM) can be used to divide time slots, supporting multiple sub-channels to carry different services. For example, the FlexO-8-RS frame structure is suitable for multi-channel parallel interfaces using eight physical channels with a transmission rate of 112 Gbit / s, such as the FOIC 8.8-RS interface. With the improvement of device manufacturing capabilities, how to provide higher-speed signal transmission is a pressing issue. Summary of the Invention

[0005] This application provides a signal transmission method and apparatus that can support higher-speed signal transmission and improve transmission reliability.

[0006] Firstly, a signal transmission method is provided. This method can be executed by a transmitting device. Unless otherwise specified, the term "transmitting device" in this application can refer to the transmitting device itself, or a component within the transmitting device (e.g., a communication module, processor, circuit, chip, or chip system), or a logic module or software capable of implementing all or part of the functions of the transmitting device. This application does not limit the definition of such a device.

[0007] The method includes: acquiring a first signal, which comprises 32 logical channel signals, generated from 8 100Gbit / s, or 4 200Gbit / s, or 2 400Gbit / s, or 1 800Gbit / s optical transport network (OTN) signals, and the first signal undergoing first Hamming forward error correction (FEC) processing; interleaving the first signal based on a 10-bit symbol granularity to obtain a second signal, which comprises 4 physical channel signals, and transmitting the second signal.

[0008] Based on the above scheme, the second signal is obtained by interleaving the first signal with a 10-bit symbol granularity. Specifically, 32 logical channel signals are interleaved in groups of 8 with a 10-bit symbol granularity, resulting in 4 physical channel signals. For example, if the first signal has a rate of 800 Gbit / s and is generated from 8 100 Gbit / s OTN signals, then each logical channel signal has a rate of 25 Gbit / s. After interleaving, each physical channel signal has a rate of 200 Gbit / s. A 4*200G optical module can support higher signal transmission rates, achieving generational upgrades and cost reduction. Furthermore, interleaving with a 10-bit symbol granularity ensures that the signal distribution granularity and interleaving granularity are consistent (both 10 bits), guaranteeing symbol integrity, facilitating subsequent FEC encoding, and improving transmission reliability.

[0009] For example, the 32 logical channel signals can be flexible OTN interface (FOIC) signals, such as the FOIC8.32 signal, where 8 indicates that the FlexO interface generating the FOIC8.32 signal has a rate of 800G, and 32 indicates the number of FOIC channels split from the FlexO interface. This logical channel can be a logical channel within the Framer.

[0010] For example, the four physical channel signals can be FOIC signals or FOIC8.4-RS signals, such as FOIC8.4 signals.

[0011] It should be noted that the above-mentioned 8 channels of 100Gbit / s, or 4 channels of 200Gbit / s, or 2 channels of 400Gbit / s, or 1 channel of 800Gbit / s all refer to the rate class. The higher the rate class, the faster the signal transmission rate, which can meet the needs of higher transmission performance.

[0012] In conjunction with the first aspect, in some implementations of the first aspect, the method further includes: performing a second FEC process on the second signal to obtain a third signal, and sending the third signal.

[0013] It is understandable that the second FCE processing in the technical solution of this application is Hamming FEC encoding processing.

[0014] In conjunction with the first aspect, in some implementations of the first aspect, the first signal is a flexible OTN (Flexible OTN, FlexO) frame.

[0015] In conjunction with the first aspect, in some implementations of the first aspect, the second signal is a FOIC-RS signal after 10-bit symbol interleaving.

[0016] In conjunction with the first aspect, in some implementations of the first aspect, the third signal is a signal after FEC encoding (combining RS and hamming FEC, FOIC-RSH).

[0017] It is understood that the names of the first, second, and third signals above are merely examples for ease of understanding, and this application does not limit their specific names.

[0018] In conjunction with the first aspect, in some implementations of the first aspect, the second signal is padded with information after being processed by the second FEC.

[0019] In conjunction with the first aspect, in some implementations of the first aspect, the size of the padding information is 8×128b.

[0020] In conjunction with the first aspect, in some implementations of the first aspect, the insertion interval between two adjacent padding information is 8704×128b or 8×4096×128b.

[0021] In other words, the insertion period for the padding information can be either 8704×128b or 8×4096×128b. That is, after the second signal undergoes second FEC processing, an 8×128b padding information can be inserted every 8704×128b, or an 8×128b padding information can be inserted every 8×4096×128b; there is no limitation on this. By setting different insertion intervals, different transmission rates can be determined to meet different signal transmission requirements.

[0022] In conjunction with the first aspect, in some implementations of the first aspect, the transmission rate of each physical channel signal included in the second signal is 223.618 Gbit / s.

[0023] In conjunction with the first aspect, in some implementations of the first aspect, the bit rate of each physical channel signal included in the third signal is 238.746 Gbit / s or 238.585 Gbit / s.

[0024] It is understood that bit rate can also be replaced with transmission rate or speed, and there is no limitation thereto. The bit rate values ​​of each physical channel signal included in the second signal and the bit rate values ​​of each physical channel signal included in the third signal are merely illustrative examples for ease of understanding and are not intended to be limiting.

[0025] In conjunction with the first aspect, in some implementations of the first aspect, when the insertion interval between two adjacent padding information is 8704×128b, the bit rate of each physical channel signal contained in the third signal can be approximately 238.746 Gbit / s. Specifically, the bit rate of each physical channel signal contained in the third signal (e.g., FlexO-8-RSH) satisfies: FlexO-8-RSH bit rate / 4=2×119373056.541kbit / s=238746 113.083kbit / s.

[0026] In conjunction with the first aspect, in some implementations of the first aspect, when the insertion interval between two adjacent padding information is 8×4096×128b, the bit rate of each physical channel signal contained in the third signal can be approximately 238.585Gbit / s. Specifically, the bit rate of each physical channel signal contained in the third signal (e.g., FlexO-8-RSH) satisfies: FlexO-8-RSH bit rate / 4=2×4063 / 3390×99532800kbit / s=238585112.92kbit / s.

[0027] In conjunction with the first aspect, in some implementations of the first aspect, before obtaining the first signal, the method further includes: generating two 400 Gbit / s FlexO signals and performing Reed-Solomon (RS) encoding on the two 400 Gbit / s FlexO signals to obtain the first signal.

[0028] In conjunction with the first aspect, in certain implementations of the first aspect, generating two 400 Gbit / s FlexO signals includes: mapping optical transport unit (OTU) signals, such as OTUC8 signals, to flexible optical transport network (FlexO) signals. The FlexO signals include eight FlexO instance signals, each with a bit rate of 100 Gbit / s. The eight FlexO instance signals are then interleaved to obtain two 400 Gbit / s FlexO signals.

[0029] Secondly, a method for transmitting data frames is provided. This method can be executed by a receiving device. Unless otherwise specified, the term "receiving device" in this application can refer to the transmitting device itself, or a component in the receiving device (e.g., a communication module, processor, circuit, chip, or chip system), or a logic module or software that can implement all or part of the functions of the receiving device. This application does not limit the scope of the term.

[0030] The method includes: receiving a second signal, the second signal comprising 4 physical channel signals; deinterleaving the second signal based on a 10-bit symbol granularity to obtain a first signal, the first signal comprising 32 logical channel signals; the first signal being generated from 8 100Gbit / s, or 4 200Gbit / s, or 2 400Gbit / s, or 1 800Gbit / s optical transport network (OTN) signals; and the first signal undergoing a first FEC processing.

[0031] In conjunction with the second aspect, in some implementations of the second aspect, the method further includes: receiving a third signal and performing a third FEC process on the third signal to obtain the second signal.

[0032] In the embodiments of this application, the third FEC process can be understood as the reverse process of the second FEC process, wherein the second FEC process is an encoding process and the third FEC process is a decoding process.

[0033] In conjunction with the second aspect, in some implementations of the second aspect, the first signal is a FlexO frame.

[0034] In conjunction with the second aspect, in some implementations of the second aspect, the second signal is a FOIC-RS signal after 10-bit symbol interleaving.

[0035] In conjunction with the second aspect, in some implementations of the second aspect, the third signal is the FOIC-RSH signal after FEC encoding.

[0036] In conjunction with the second aspect, in some implementations of the second aspect, the second signal is padded with information after being processed by the second FEC.

[0037] In conjunction with the second aspect, in some implementations of the second aspect, the size of the padding information is 8×128b.

[0038] In conjunction with the second aspect, in some implementations of the second aspect, the insertion interval between two adjacent padding information is 8704×128b or 8×4096×128b.

[0039] In conjunction with the second aspect, in some implementations of the second aspect, the transmission rate of each physical channel signal included in the second signal is 223.618 Gbit / s.

[0040] In conjunction with the second aspect, in some implementations of the second aspect, the third signal contains a bit rate of 238.746 Gbit / s or 238.585 Gbit / s for each physical channel signal.

[0041] In conjunction with the second aspect, in some implementations of the second aspect, when the insertion interval between two adjacent padding information is 8704×128b, the bit rate of each physical channel signal contained in the third signal is 238.746Gbit / s.

[0042] In conjunction with the second aspect, in some implementations of the second aspect, when the insertion interval between two adjacent padding information is 8×4096×128b, the bit rate of each physical channel signal contained in the third signal is 238.585Gbit / s.

[0043] In conjunction with the second aspect, in some implementations of the second aspect, the method further includes: performing RS decoding on the first signal to obtain two 400Gbit / s FlexO signals.

[0044] In conjunction with the second aspect, in some implementations of the second aspect, the method further includes: deinterleaving two 400 Gbit / s Flexible Optical Transport Network (FlexO) signals to obtain eight FlexO instance signals, each with a bit rate of 100 Gbit / s. The optical transmission unit (OTUC8) signal is then demapped from the eight FlexO instance signals.

[0045] The beneficial effects of some implementation methods of the second aspect mentioned above can be referred to the relevant descriptions in the first aspect, and will not be repeated here.

[0046] Thirdly, a signal transmission method is provided. This method can be executed by a transmitting device. Unless otherwise specified, the term "transmitting device" in this application can refer to the transmitting device itself, or a component within the transmitting device (e.g., a communication module, processor, circuit, chip, or chip system), or a logic module or software capable of implementing all or part of the functions of the transmitting device. This application does not limit the scope of the term.

[0047] The method includes: a transmitting device acquiring a first signal, the first signal being generated from m x*25Gbit / s optical transport network (OTN) signals, the first signal undergoing first FEC processing; interleaving the first signal based on a 10*n bit symbol granularity to obtain a second signal, the second signal including (m*x) / 8 physical channel signals; and transmitting the second signal.

[0048] For example, m is an integer greater than 1, and x is an integer greater than or equal to 1. For example, m can be equal to 8, 16, or 64, etc., or m can be an integer multiple of 8. For example, x can be equal to 1, 2, or 4, etc.

[0049] For example, m*x can be a multiple of 8, such as 8, 16, 32, or 64.

[0050] For example, n is an integer greater than or equal to 1. For instance, n = 2.

[0051] Understandably, m channels of x*25Gbit / s OTN signals can be understood as: there are m OTN signals, each with a bit rate of x*25Gbit / s. For example, if the rate of the first signal is 800Gbit / s, m=8, and x=4, then the first signal can be generated from eight 100Gbit / s OTN signals, with each logical channel signal having a rate of 25Gbit / s.

[0052] In conjunction with the third aspect, in some implementations of the third aspect, the method further includes: the transmitting device performing a second FEC process on the second signal to obtain a third signal; and transmitting the third signal.

[0053] In conjunction with the third aspect, in some implementations of the third aspect, the second signal is padded with information after being processed by the second FEC.

[0054] In conjunction with the third aspect, in some implementations of the third aspect, the size of the padding information is 8×128b.

[0055] In conjunction with the third aspect, in some implementations of the third aspect, the insertion interval between two adjacent padding information is 8704×128b or 8×4096×128b.

[0056] In conjunction with the third aspect, in some implementations of the third aspect, the bit rate of each physical channel signal contained in the second signal is 223.618 Gbit / s, or 213.865 Gbit / s, or 214.304 Gbit / s, or 213.836 Gbit / s.

[0057] In conjunction with the third aspect, in some implementations of the third aspect, the bit rate of each physical channel signal contained in the third signal is 238.746 Gbit / s, or 238.585 Gbit / s, or 228.332 Gbit / s, or 228.800 Gbit / s, or 228.301 Gbit / s.

[0058] In conjunction with the third aspect, in some implementations of the third aspect, when the insertion interval between two adjacent padding information is 8704×128b, the bit rate of each physical channel signal contained in the third signal is 238.746Gbit / s.

[0059] In conjunction with the third aspect, in some implementations of the third aspect, when the insertion interval between two adjacent padding information is 8×4096×128b, the bit rate of each physical channel signal contained in the third signal is 238.585Gbit / s.

[0060] In conjunction with the third aspect, in some implementations of the third aspect, before the transmitting device acquires the first signal, the method further includes: the transmitting device generating at least one y*100Gbit / s FlexO signal, and performing RS encoding on the at least one y*100bit / s FlexO signal to obtain the first signal.

[0061] For example, y is an integer greater than or equal to 1. For instance, assuming the rate level of the first signal is 800 Gbit / s, the receiving device performs RS decoding on the first signal to obtain two FlexO signals with y = 4 * 100 Gbit / s.

[0062] In conjunction with the third aspect, in some implementations of the third aspect, the transmitting device generates at least one y*100Gbit / s FlexO signal, including: the transmitting device mapping the optical transmission unit OTUCy signal to the flexible optical transport network FlexO signal, the FlexO signal including at least y FlexO instance signals, each FlexO instance signal having a bit rate of 100Gbit / s; and interleaving the at least y FlexO instance signals to obtain at least one y*100Gbit / s FlexO signal.

[0063] In conjunction with the third aspect, in some implementations of the third aspect, the first signal is a FlexO frame from a flexible optical transport network.

[0064] In conjunction with the third aspect, in some implementations of the third aspect, n = 2.

[0065] Fourthly, a method for transmitting data frames is provided. This method can be executed by a receiving device. Unless otherwise specified, the term "receiving device" in this application can refer to the transmitting device itself, or a component in the receiving device (e.g., a communication module, processor, circuit, chip, or chip system), or a logic module or software that can implement all or part of the functions of the receiving device. This application does not limit the scope of the term.

[0066] The method includes: a receiving device receiving a second signal, the second signal including (m*x) / 8 physical channel signals; and deinterleaving the second signal based on a 10*n bit symbol granularity to obtain a first signal, the first signal being generated from m x*25Gbit / s optical transport network OTN signals, and the first signal undergoing a first FEC processing.

[0067] For example, m is an integer greater than 1, and x is an integer greater than or equal to 1. For example, m can be equal to 8, 16, or 64, etc., or m can be an integer multiple of 8. For example, x can be equal to 1, 2, or 4, etc.

[0068] For example, m*x can be a multiple of 8, such as 8, 16, 32, or 64.

[0069] For example, n is an integer greater than or equal to 1. For instance, n = 2.

[0070] In conjunction with the fourth aspect, in some implementations of the fourth aspect, the method further includes: the receiving device receiving a third signal; and performing a third FEC process on the third signal to obtain a second signal.

[0071] In conjunction with the fourth aspect, in some implementations of the fourth aspect, the second signal is padded with information after being processed by the second FEC.

[0072] In conjunction with the fourth aspect, in some implementations of the fourth aspect, the size of the padding information is 8×128b.

[0073] In conjunction with the fourth aspect, in some implementations of the fourth aspect, the insertion interval between two adjacent padding information is 8704×128b or 8×4096×128b.

[0074] In conjunction with the fourth aspect, in some implementations of the fourth aspect, the bit rate of each physical channel signal contained in the second signal is 223.618 Gbit / s, or 213.865 Gbit / s, or 214.304 Gbit / s, or 213.836 Gbit / s.

[0075] In conjunction with the fourth aspect, in some implementations of the fourth aspect, the bit rate of each physical channel signal contained in the third signal is 238.746 Gbit / s, or 238.585 Gbit / s, or 228.332 Gbit / s, or 228.800 Gbit / s, or 228.301 Gbit / s.

[0076] In conjunction with the fourth aspect, in some implementations of the fourth aspect, when the insertion interval between two adjacent padding information is 8704×128b, the bit rate of each physical channel signal contained in the third signal is 238.746Gbit / s.

[0077] In conjunction with the fourth aspect, in some implementations of the fourth aspect, when the insertion interval between two adjacent padding information is 8×4096×128b, the bit rate of each physical channel signal contained in the third signal is 238.585Gbit / s.

[0078] In conjunction with the fourth aspect, in some implementations of the fourth aspect, the method further includes: the receiving device performing RS decoding on the first signal to obtain at least one y*100Gbit / s FlexO signal.

[0079] For example, y is an integer greater than or equal to 1. For instance, assuming the rate level of the first signal is 800 Gbit / s, the receiving device performs RS decoding on the first signal to obtain two FlexO signals with y = 4 * 100 Gbit / s.

[0080] In conjunction with the fourth aspect, in some implementations of the fourth aspect, the method further includes: the receiving device performing deinterleaving processing on at least one y*100Gbit / s Flexible Optical Transport Network (FlexO) signal to obtain at least y FlexO instance signals, each FlexO instance signal having a bit rate of 100Gbit / s; and demapping from the at least y FlexO instance signals to obtain the Optical Transmission Unit (OTUCy) signal.

[0081] In conjunction with the fourth aspect, in some implementations of the fourth aspect, the first signal is a FlexO frame of a flexible optical transport network.

[0082] In conjunction with the fourth aspect, in some implementations of the fourth aspect, n = 2.

[0083] The beneficial effects of certain implementation methods of the third or fourth aspect mentioned above can be referred to the relevant descriptions of the first or second aspect, and will not be repeated here.

[0084] Fifthly, embodiments of this application provide a signal transmission apparatus. This apparatus is used to execute the methods provided in the first or second aspect, or to execute the methods provided in the third or fourth aspect. Specifically, the apparatus may include units and / or modules for executing the methods provided in the first aspect or any of the above-described implementations of the first aspect; or, the apparatus may include units and / or modules for executing the methods provided in the second aspect or any of the above-described implementations of the second aspect; or, the apparatus may include units and / or modules for executing the methods provided in the third aspect or any of the above-described implementations of the third aspect; or, the apparatus may include units and / or modules for executing the methods provided in the fourth aspect or any of the above-described implementations of the fourth aspect, such as a processing module and a transceiver module.

[0085] In one implementation, the signal transmission device may include units and / or modules for performing the method provided by the first aspect or any of the above-described implementations of the first aspect, or may include units and / or modules for performing the method provided by the third aspect or any of the above-described implementations of the third aspect, serving as a transmitting end device. The transceiver module may be a transceiver, or an input / output interface. The processing module may be at least one processor. Optionally, the transceiver may be a transceiver circuit. Optionally, the input / output interface may be an input / output circuit.

[0086] Alternatively, the signal transmission device may be a chip, chip system, or circuit in the transmitting device. The transceiver module may be an input / output interface, interface circuit, output circuit, input circuit, pin, or related circuit on the chip, chip system, or circuit. The processing module may be at least one processor, processing circuit, or logic circuit.

[0087] In another implementation, the signal transmission device may include units and / or modules for performing the methods provided in the second aspect or any of the above-described implementations of the second aspect, or may include units and / or modules for performing the methods provided in the fourth aspect or any of the above-described implementations of the fourth aspect, serving as a receiving device. The transceiver module may be a transceiver, or an input / output interface. The processing module may be at least one processor. Optionally, the transceiver may be a transceiver circuit. Optionally, the input / output interface may be an input / output circuit.

[0088] Alternatively, the signal transmission device can be a chip, chip system, or circuit in the receiving device. The transceiver module can be an input / output interface, interface circuit, output circuit, input circuit, pin, or related circuit on the chip, chip system, or circuit. The processing module can be at least one processor, processing circuit, or logic circuit.

[0089] Sixthly, an optical module is provided, including a signal processor and an optical transmitting component. The signal processor is used to acquire a second signal, wherein each physical channel signal contained in the second signal has a transmission rate of 223.618 Gbit / s. The signal processor is also used to perform FEC processing on the second signal to obtain a third signal, wherein each physical channel signal contained in the third signal has a bit rate of 238.746 Gbit / s or 238.585 Gbit / s. The optical transmitting component is used to transmit the third signal.

[0090] In a seventh aspect, an optical module is provided, including a signal processor and an optical receiving component. The optical receiving component is used to receive a third signal, wherein the bit rate of each physical channel signal contained in the third signal is 238.746 Gbit / s or 238.585 Gbit / s. The signal processor is used to perform third FEC processing on the third signal to obtain a second signal, wherein the transmission rate of each physical channel signal contained in the second signal is 223.618 Gbit / s.

[0091] Eighthly, a processor is provided for executing the methods provided in the above aspects.

[0092] Unless otherwise specified, or if it does not contradict its actual function or internal logic in the relevant description, the transmission and acquisition / reception operations involved in the processor can be understood as processor output and reception, input and other operations, or as transmission and reception operations performed by radio frequency circuits and antennas. This application does not limit them in this regard.

[0093] A ninth aspect provides an optical module comprising a signal processor and an optical transmitting component. The signal processor is used to execute the method provided in the first aspect or any of the above implementations of the first aspect. The optical transmitting component is used to transmit optical signals.

[0094] In a tenth aspect, an optical module is provided, comprising a signal processor and an optical receiving component. The optical receiving component is used to receive a second signal; the signal processor is used to execute the method provided in the second aspect or any of the above-described implementations of the second aspect.

[0095] Eleventhly, an optical module is provided, comprising a signal processor and an optical transmitting component. The signal processor is used to execute the method provided in the third aspect or any of the above-described implementations of the third aspect; the optical transmitting component is used to transmit optical signals.

[0096] In a twelfth aspect, an optical module is provided, comprising a signal processor and an optical receiving component. The optical receiving component is used to receive a second signal; the signal processor is used to execute the method provided in the fourth aspect or any of the above-described implementations of the fourth aspect.

[0097] In a thirteenth aspect, embodiments of this application provide a network device comprising: at least one processor and an input / output interface, for executing the method provided by any implementation of any of the first to fourth aspects described above, wherein the input / output interface is used to transmit and receive a second signal, and the at least one processor is used to process the second signal.

[0098] In a fourteenth aspect, a computer-readable storage medium is provided. This computer-readable storage medium stores program code for execution by a device, the program code including methods for performing any implementation of any of the first to fourth aspects described above.

[0099] In a fifteenth aspect, a computer program product comprising instructions is provided. When the computer program product is run on a computer or processor, it causes the computer or processor to perform a method provided by any implementation of any of the first to fourth aspects described above.

[0100] In a sixteenth aspect, a chip is provided. The chip includes at least one processor, which reads instructions stored in a memory via a communication interface and executes the method provided by any implementation of any of the first to fourth aspects described above.

[0101] Optionally, as one implementation, the chip further includes a memory and / or a communication interface, the memory storing computer programs or instructions, and at least one processor for executing the computer programs or instructions stored in the memory. When the computer programs or instructions are executed, at least one processor is used to execute the method provided by any implementation of any of the first to fourth aspects described above.

[0102] The beneficial effects of the fifth to sixteenth aspects mentioned above can be specifically referred to in the description of the beneficial effects of any of the first to fourth aspects, and will not be repeated here. Attached Figure Description

[0103] Figure 1 is a schematic diagram of an OTN optical network system applicable to an embodiment of this application.

[0104] Figure 2 is a schematic diagram of the hardware structure of an OTN device applicable to an embodiment of this application.

[0105] Figure 3 is a schematic diagram of the hardware structure of an optical module applicable to an embodiment of this application.

[0106] Figure 4 is a schematic flowchart of a data signal transmission method provided in an embodiment of this application.

[0107] Figure 5 is a schematic flowchart of an 800G FlexO-8-RS interface transmission signal provided in an embodiment of this application.

[0108] Figure 6 is a schematic diagram of a second signal and a third signal after FEC processing provided in an embodiment of this application.

[0109] Figure 7 is a schematic diagram of the structure of a Hamming FEC functional block provided in an embodiment of this application.

[0110] Figure 8 is a schematic block diagram of a communication device provided in an embodiment of this application.

[0111] Figure 9 is a schematic block diagram of another communication device provided in an embodiment of this application.

[0112] Figure 10 is a schematic diagram of a chip system provided in an embodiment of this application.

[0113] Figure 11 is a schematic flowchart of another data signal transmission method provided in an embodiment of this application. Detailed Implementation

[0114] The following description is provided to facilitate understanding of the embodiments of this application.

[0115] (1) In this application, unless otherwise specified or logically conflicting, the terms and / or descriptions of different embodiments are consistent and can be referenced by each other. The technical features of different embodiments can be combined to form new embodiments according to their inherent logical relationship.

[0116] (2) In this application, "at least one" means one or more, and "more than one" means two or more. "And / or" describes the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist simultaneously, or B exists alone, where A and B can be singular or plural. In the textual description of this application, the character " / " generally indicates that the related objects before and after are in an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, and c can mean: a, or, b, or, c, or, a and b, or, a and c, or, b and c, or, a, b, and c. Where a, b, and c can be single or multiple.

[0117] (3) In this application, the terms "first," "second," and various numerical designations are used for convenience of description and are not intended to limit the scope of the embodiments of this application. For example, they are used to distinguish different messages, rather than to describe a specific order or sequence. It should be understood that such descriptions can be interchanged where appropriate to describe solutions other than those in the embodiments of this application.

[0118] (4) In this application, “instruction” or “for instruction” can include both direct instruction and indirect instruction. When describing an instruction as being used to instruct A, it can include whether the instruction directly instructs A or indirectly instructs A, but does not necessarily mean that the instruction carries A.

[0119] The indication methods involved in the embodiments of this application should be understood to cover various methods that enable the party to be indicated to obtain the information to be indicated. The information to be indicated can be sent as a whole or divided into multiple sub-information and sent separately. Moreover, the sending period and / or sending time of these sub-information can be the same or different. This application does not limit the sending method, for example.

[0120] (5) In this application, the words “exemplary,” “for example,” etc., are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as an “example” in this application should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of the word “example” is intended to present the concept in a concrete manner. In the embodiments of this application, “of,” “corresponding, relevant,” “corresponding,” and “associate” may sometimes be used interchangeably, and it should be noted that their intended meanings are consistent unless their distinctions are emphasized.

[0121] (6) In this application, "send" and "receive" indicate the direction of signal transmission. For example, "receiving information from YY" can be understood as the source of the information being YY, which may include receiving directly from YY through a communication interface (or input / output interface), or receiving indirectly from YY through a communication interface from other units or modules. "Send" can also be understood as the "output" of the chip interface, and "receive" can also be understood as the "input" of the chip interface. In other words, sending and receiving can be performed between devices, such as between OTN device #1 and OTN device #2, or they can be performed within a device, for example, by sending or receiving between components, modules, chips, software modules, or hardware modules within the device via a bus, trace, or interface.

[0122] (7) In this application, "data frame" may also be referred to as "frame" or "signal". For example, an OTN frame may be referred to as an OTN signal, an OTN frame, or an OTN data frame. It should be noted that both "frame" and "signal" in this application are used to carry service data. When used to describe the data structure carrying service data, it is generally understood as "frame" such as an ODU frame; when used to describe the carrier carrying service data, or to describe the transmission of service data, it is generally understood as "signal". In the following description, this application does not make a special distinction between "frame" and "signal".

[0123] Specifically, the OTN signal can be any of the following: optical payload unit (OPU) signal, ODU signal (such as ODUk, ODUflex, etc.), optical transport unit (OTU) signal (such as OTUk, OTUCn, where k represents different rate levels and Cn represents variable rate), FlexO signal, or FOICx.k. The FlexO signal can be any of the following: FlexO instance, FlexO interface signal (e.g., FlexO-n, FlexO-n(e), FlexO-x, FlexO-x(e), FlexO-x-FEC, FlexO-x-FEC-m), and other FlexO interface signals with rates exceeding 100 Gbit / s defined by future OTN signals. In FOICx.k, x represents a FlexO interface rate x, and k represents the number of channels derived from the FlexO interface rate. For example, in the FOIC8.32 signal, 8 represents the FlexO interface rate that generates the FOIC8.4 signal, i.e., 800 Gbit / s, and 4 represents the number of FOIC channels derived from the FlexO interface. In one example, FOICx.k can be viewed as a multiplexed channel obtained by splitting FlexO-x. It should be understood that this application also applies to other data frames, such as metro transport network (MTN) frames, or to new types of OTN and MTN frames that may be defined as OTN and MTN technologies develop.

[0124] (8) In this application, the transmitting device and the receiving device are used as the main entities for illustrative purposes. A device may be called a node or a node device, and a transmitting device may be called a transmitting node, a transmitting end, or a source node. Similarly, in this application, a receiving device may be called a receiving device, a receiving end, or a destination node. Exemplarily, a transmitting device may be called a transmitting end device, a transmitting end node, or a transmitting node, etc., and similarly, in this application, a receiving device may be called a receiving end device, a receiving end node, or a receiving node, etc. For example, the transmitting device may be an OTN device (such as OTN device A shown in Figure 1) that receives service data from a client device (such as the client device shown in Figure 1). Alternatively, the transmitting device may be any other device capable of implementing an OTN device. The specific form of the transmitting or receiving device in the embodiments of this application is not limited, as long as it can achieve the corresponding communication function.

[0125] (9) In this application, "*" represents multiplication and can also be described as "×" or "·". In addition, " / " represents division in formulas or numbers and can also be described as "-" or "÷", without limitation.

[0126] The technical solution of this application will be described in detail below with reference to the accompanying drawings.

[0127] The embodiments of this application are applicable to optical networks, such as OTN. An OTN is typically composed of multiple devices connected by optical fibers, and can be configured into different topologies such as linear, ring, and mesh, depending on specific needs.

[0128] Figure 1 is a schematic diagram of an OTN optical network system applicable to an embodiment of this application. As shown in Figure 1, OTN 100 includes eight interconnected OTN devices 101, namely devices AH. 102 indicates an optical fiber used to connect two devices; 103 indicates a customer service interface used to receive or send customer service data. As shown in Figure 1, OTN 100 is used to transmit service data for customer devices 1-3. Customer devices 1-3 can be Ethernet devices, and the service data can be Ethernet service data. The customer devices are connected to the OTN devices through the customer service interface. For example, in Figure 1, customer devices 1-3 are connected to OTN devices A, H, and F respectively.

[0129] Depending on the specific needs, an OTN device may possess different functions. Generally speaking, OTN devices are categorized into optical layer devices, electrical layer devices, and hybrid optoelectronic devices. Optical layer devices refer to those capable of processing optical layer signals, such as optical amplifiers and optical add-drop multiplexers. Optical amplifiers amplify optical signals to support longer transmission distances while maintaining specific optical signal performance. Optical add-drop multiplexers perform spatial transformations on optical signals, allowing them to be output from different output ports (sometimes referred to as directions). Electrical layer devices refer to those capable of processing electrical layer signals, such as devices capable of processing OTN signals. Hybrid optoelectronic devices refer to devices capable of processing both optical and electrical layer signals. It should be noted that, depending on specific integration requirements, an OTN device can integrate multiple different functions. The technical solutions provided in this application are applicable to OTN devices with different forms and integration levels that include electrical layer functions.

[0130] Figure 2 is a schematic diagram of the hardware structure of an OTN device applicable to an embodiment of this application. Specifically, the OTN device may include one or more of a tributary board, a line board, and a cross-connect board, and may also include one or more of a system control board, a power supply, a fan, and auxiliary boards.

[0131] The circuit board can also be an optical layer processing board. Depending on specific needs, the type and number of boards included in each device may differ. For example, an OTN device acting as a core node may not have tributary boards. An OTN device acting as an edge node may have multiple tributary boards. Power supply boards are used to power the OTN device and may include primary and backup power supplies. Fan boards are used for heat dissipation. Auxiliary boards provide auxiliary functions such as external alarms or access to external clocks. Tributary boards, cross-connect boards, and circuit boards are primarily used to process OTN electrical layer signals (also known as OTN frames). Tributary boards are used to receive and transmit various client signals (also known as client services). Client signals can include constant bit rate (CBR) signals (e.g., synchronous digital hierarchy (SDH) signals) and packet signals (e.g., Ethernet signals). Furthermore, tributary boards can include client-side optical modules and signal processors. Client-side optical modules are used to receive and / or transmit client signals. Signal processors are used to perform mapping and demapping processing of client signals to OTN frames. The signal processor can be located inside or outside the customer-side optical module. If the signal processor is a combination of multiple chips, one (or some) of the chips can be inside the customer-side optical module, while the others are outside. The cross-connect board is used to implement the switching of OTN frames, for example, to perform the switching of one or more types of OTN frames. The line board mainly implements the processing of line-side OTN frames. Specifically, the line board can include a line-side optical module and a signal processor. The line-side optical module, which can be called an optical transceiver, is used to receive and / or transmit optical signals carrying OTN frames. The signal processor is used to implement multiplexing and demultiplexing, or mapping and demapping processing of line-side OTN frames. The signal processor can be located inside or outside the line-side optical module. If the signal processor is a combination of multiple chips, one (or some) of the chips can be inside the line-side optical module, while the others are outside. The customer-side optical module or the line-side optical module can also be collectively referred to as an optical module or an optical transceiver. The signal processors in either the customer-side or line-side optical modules can be optical digital signal processors (oDSPs) or framers, or a combination of framers and oDSPs. System control boards are used for system control. Specifically, the system control board can collect information from different boards or send control commands to the corresponding boards.

[0132] It should be noted that, unless otherwise specified, a specific component (such as a tributary board) may be one or more, and this application does not impose any restrictions. This application also does not impose any restrictions on the type of boards included in the device, or on the functional design and number of the boards. It should also be noted that, in a specific implementation, the two boards mentioned above may also be designed as a single board. Furthermore, network devices may also include backup power supplies, fans for device cooling, auxiliary boards for providing external alarms or accessing external clocks, etc.

[0133] Figure 3 is a schematic diagram of the hardware structure of an optical module applicable to an embodiment of this application. As shown in Figure 3, the optical module may include a signal processor, an optical transmitting component, and an optical receiving component. As mentioned above, the signal processor may include a Framer or an oDSP, or a combination of a Framer and an oDSP. The optical module can be a unidirectional optical module, that is, it includes one of an optical transmitting component and an optical receiving component. The optical module can also be a bidirectional optical module, that is, it includes both an optical transmitting component and an optical receiving component.

[0134] Framer, also known as a service chip or physical layer (PHY) chip, is primarily used to perform OTN electrical layer encapsulation / decapsulation (or mapping / demapping). Framers encapsulate client signals into OTN frames or decapsulate OTN frames to obtain client signals. For example, a framer can encapsulate client signals into ODUs, encapsulate low-rate ODUs into high-rate ODUs, encapsulate ODUs into flexible OTN (FlexO) frames, or directly encapsulate client signals into FlexO frames. Decapsulation is the reverse process of encapsulation.

[0135] The oDSP is used to perform digital signal processing on OTN frames generated by the Framer, or on electrical signals obtained from the optical receiving component. The oDSP is used to perform one or more of the following processing operations: forward error correction (FEC), clock recovery, equalization, sequence detection, and signal decision.

[0136] FEC is an error control method that refers to pre-encoding the signal according to a certain algorithm before it is sent into the transmission channel, adding redundant data with the characteristics of the signal itself, and then decoding the received signal at the receiving end according to the corresponding algorithm to find and correct the error codes generated during transmission.

[0137] Optical transmitting module (TOSA), also known as a transmitter optical subassembly, is used to convert electrical signals into optical signals. A TOSA may include a light source, a driver chip, and a modulator. The light source can be a semiconductor laser (also known as a laser diode (LD)) or a light emitting diode (LED). The driver chip processes the electrical signals generated by the oDSP and drives the light source to emit modulated optical signals. The modulated optical signals are transmitted to the fiber optic line via an optical fiber interface.

[0138] Optical receiver assembly (ROSA), also known as a receiver optical subassembly, is used to convert optical signals into electrical signals. ROSA may include photodetectors, amplifiers, etc. The photodetector can be an avalanche photodiode (APD) or a PIN photodiode. The amplifier may include a preamplifier and a post-amplifier. After the optical signal enters from the fiber optic interface, it is converted into an electrical signal by the photodetector, and then amplified by the amplifier to output an amplified electrical signal.

[0139] It should be noted that the client signal involved in the embodiments of this application can refer to the service carried by the optical transport network or metropolitan area transport network, such as Ethernet service, packet service, or wireless backhaul service. The client signal can also be referred to as client-side signal, client signal, service signal, service data, client data, or client service data, etc.

[0140] Figures 1 to 3 above are merely illustrative examples for ease of understanding, and other structural schemes are not excluded.

[0141] Optical networks (ONNs) are a type of transmission network capable of transmitting, multiplexing, routing, and monitoring service data. OTN technology is gradually becoming the primary choice for transmission networks. OTN is a wavelength division multiplexing (WDM) transmission network based on fiber optic interconnection. For a single high-speed optical port, multiple sub-channels can be used to carry different services through TDM time slot partitioning. For example, a 100G optical port can be divided into 80 1.25G time slots, carrying 80 ODU0s or 10 ODU2s. For instance, the FlexO-8-RS frame structure is suitable for multi-channel parallel interfaces using eight physical channels with a transmission rate of 112 Gbit / s, such as the FOIC 8.8-RS interface. With advancements in device manufacturing capabilities, providing even higher signal transmission rates is a pressing issue.

[0142] In view of this, embodiments of this application provide a signal transmission method and apparatus, which obtains a second signal from a first signal with a 10-bit symbol granularity. Specifically, 32 logic channel signals are interleaved with 8 logic channel signals at a 10-bit symbol granularity to obtain 4 physical channel signals, so as to support higher-speed signal transmission, achieve generational upgrade, and reduce costs.

[0143] The signal transmission method provided by the embodiments of this application will be described in detail below with reference to Figures 4 to 7, and can be applied to the communication system shown in Figure 1 above. It should be understood that the embodiments of this application can be applied to scenarios where a transmitting device and a receiving device communicate.

[0144] It should also be understood that the embodiments shown below do not specifically limit the structure of the execution subject of the method provided in the embodiments of this application. As long as communication can be performed according to the method provided in the embodiments of this application by running the code or program that records the method provided in the embodiments of this application. For example, the method provided in the embodiments of this application can be executed by a transmitting device and a receiving device. Unless otherwise specified, the device in this application, such as the transmitting device and the receiving device, can refer to the device itself (e.g., an OTN device), or a component in the device (e.g., a communication module, processor, circuit, chip (such as a modem chip, also known as a baseband chip, or a SoC chip or SIP chip containing a modem core), or a chip system, etc.), or it can be a logic module or software that can implement all or part of the device functions.

[0145] Figure 4 is a schematic flowchart of a data signal transmission method provided in an embodiment of this application. As shown in Figure 4, the method includes the following steps.

[0146] S410, the transmitting device acquires or generates the first signal.

[0147] The first signal includes 32 logic channel signals. The first signal is generated by 8 OTN signals of 100Gbit / s, or 4 of 200Gbit / s, or 2 of 400Gbit / s, or 1 of 800Gbit / s. The first signal has been processed by the first FEC.

[0148] For example, the first signal can be a flexible OTN (Flexible OTN, FlexO) frame. For instance, the 32 logical channel signal can be a FOIC8.32 signal, where 8 indicates that the FlexO interface generating the FOIC8.32 signal has a rate of 800G, and 32 indicates the number of FOIC channels split from the FlexO interface. This logical channel can be a logical channel within the framer. Understandably, in one example, the FlexO signal can contain the FOIC8.32 signal, or in other words, the FlexO signal is split into 32 FOIC signals.

[0149] For example, the OTN signal can be either OTUCn or FlexO, without limitation.

[0150] It should be noted that the above-mentioned 8 channels of 100Gbit / s, or 4 channels of 200Gbit / s, or 2 channels of 400Gbit / s, or 1 channel of 800Gbit / s all refer to the rate class. The higher the rate class, the faster the signal transmission rate, which can meet the requirements of higher transmission performance.

[0151] In this embodiment, the first signal undergoes first FEC processing, which can be understood as the transmitting device performing first FEC processing, i.e., RS encoding processing, before acquiring or generating the first signal. This application does not limit the specific implementation of the first FEC processing; reference can be made to relevant descriptions of current FEC processing, which will not be elaborated here.

[0152] Optionally, before performing step S410, i.e. before acquiring the first signal, the method 400 further includes: the transmitting device generating two 400 Gbit / s FlexO signals, and performing RS encoding on the two 400 Gbit / s FlexO signals to obtain the first signal.

[0153] In one implementation, the transmitting device maps the OTUC8 signal to a FlexO signal. The FlexO signal includes eight FlexO instance signals, each with a bit rate of 100 Gbit / s. These eight FlexO instance signals are then interleaved to obtain two 400 Gbit / s FlexO signals. RS encoding is then performed on these two 400 Gbit / s FlexO signals to obtain a first signal. Correspondingly, the receiving device performs RS decoding on the first signal to obtain two 400 Gbit / s FlexO signals. It then deinterleaves these two 400 Gbit / s Flexible Optical Transport Network (FlexO) signals to obtain eight FlexO instance signals, each with a bit rate of 100 Gbit / s. The OTUC8 signal is then demapped from these eight FlexO instance signals. The processing at the receiving device is the reverse of the mapping and interleaving process compared to the transmitting device.

[0154] S420, the transmitting device performs interleaving processing on the first signal based on 10-bit symbol granularity to obtain the second signal.

[0155] The second signal includes four physical channel signals.

[0156] For example, the bit rate of each physical channel signal included in the second signal can be approximately 223.618 Gbit / s.

[0157] For example, the second signal can be a FOIC-RS signal after 10-bit symbol interleaving or a FOIC8.4-RS signal. For instance, the four physical channel signals can be FOIC8.4 signals.

[0158] In this application, bit rate can be replaced with rate or transmission rate, and there is no limitation thereto. The bit rate value of each physical channel signal included in the second signal is merely an illustrative example for ease of understanding and is not limited thereto. For example, the specific numerical values ​​of transmission rate or bit rate involved in this application can be actual values ​​or approximate values ​​of actual values. Furthermore, the number of decimal places after the decimal point of a specific numerical value can be one, two, or other numbers, or the number of decimal places can be omitted. When the number of decimal places is omitted, the specific numerical value of the bit rate can be determined by rounding, and there is no limitation thereto.

[0159] Understandably, the transmitting device interleaves the 32 logical channel signals contained in the first signal, grouping them into sets of eight logical channel signals at a 10-bit symbol granularity (or interleaving granularity), thus obtaining four physical channel signals. For example, if the first signal has a rate level of 800 Gbit / s and is generated from eight 100 Gbit / s OTN signals, then each logical channel signal has a rate level of 25 Gbit / s. After interleaving, the resulting second signal contains four physical channel signals, with each physical channel signal having a rate level of 200 Gbit / s. This enables higher signal transmission rates and reduces costs. The rate level indicates that the actual rate is approximately within the specified range.

[0160] It should also be understood that interleaving with a 10-bit symbol granularity ensures that the signal distribution granularity and the interleaving granularity are consistent at 10 bits, which guarantees the integrity of the symbols and facilitates subsequent Hamming FEC encoding. For details, please refer to step S440 below, which will not be explained here.

[0161] S430, the transmitting device sends a second signal to the receiving device; correspondingly, the receiving device receives the second signal from the transmitting device.

[0162] S440, the receiving device performs deinterleaving processing on the second signal based on 10-bit symbol granularity to obtain the first signal.

[0163] This application does not limit the specific method of transmitting the second signal or the specific implementation method of deinterleaving the second signal.

[0164] The following example, with reference to Figure 5, illustrates the specific implementation of the signal transmission method.

[0165] Figure 5 is a schematic flowchart of an 800G FlexO-8-RS interface transmission signal provided in an embodiment of this application. As shown in Figure 5, for example, for an 800G OTUC8 signal (e.g., OTUC#1 to OTUC#8), the transmitting device first maps the OTUC#1 to OTUC#8 signals to FlexO signals respectively. The FlexO signals include 8 FlexO instance signals (e.g., FlexO#1 to FlexO#8), each with a bit rate of 100Gbit / s. Then, FlexO OH insertion, 10-bit symbol granularity interleaving, scrambling, and alignment marker (AM) insertion for framing are performed on these 8 FlexO instance signals to obtain 2 400Gbit / s FlexO signals. RS encoding (RS) is then performed on the 2 400bit / s FlexO signals. The system performs operations such as encoding and signal distribution to obtain the first signal, which is a 32-channel logical channel signal. Then, based on a 10-bit symbol granularity, the first signal undergoes interleaving and multiplexing operations to obtain four 200-bit / s physical channel signals, i.e., the second signal. Specifically, during RS encoding of the two 400-bit / s FlexO signals, FlexO#1 and FlexO#3 are FEC encoded, FlexO#2 and FlexO#4 are FEC encoded, FlexO#5 and FlexO#7 are FEC encoded, and FlexO#6 and FlexO#8 are FEC encoded, thus obtaining four 200-bit / s FlexO signals.

[0166] It should be noted that when multiplexing 32 logical channel signals into 4 physical channel signals, the signal distribution granularity and interleaving granularity remain consistent, both using 10-bit symbols as the granularity. This ensures the integrity of the symbols and facilitates subsequent FEC encoding processing.

[0167] Correspondingly, the receiving device performs deinterleaving on the second signal, that is, deinterleaving the four 200-bit / s physical channel signals to obtain 32 logical channel signals, i.e., the first signal. Then, RS decoding is performed on the first signal to obtain two 400-Gbit / s FlexO signals. These two 400-Gbit / s FlexO signals are then deinterleaved to obtain eight 100-Gbit / s FlexO instance signals. Finally, the eight FlexO instance signals (e.g., FlexO#1 to FlexO#8) are demapped to obtain the OTUC8 signals (e.g., OTUC#1 to OTUC#8), thereby acquiring the valid data. It can be understood that the processing procedures on the transmitting and receiving sides are the inverse of each other.

[0168] Optionally, for the second signal determined above, the transmitting device may also perform Hamming FEC encoding processing on the second signal, that is, the method 400 further includes the following step S450.

[0169] S450, the transmitting device performs a second FEC process on the second signal to obtain a third signal, and then sends the third signal to the receiving device.

[0170] Correspondingly, the receiving device receives the third signal and performs a third FEC process on it to obtain the second signal. It can be understood that, relative to the transmitting device, the third FEC process on the receiving device side is the reverse of the second FEC process.

[0171] In this embodiment, the second FCE processing can be Hamming FEC encoding processing. The third signal can be a FOIC-RSH signal after inner FEC encoding.

[0172] In one implementation, the second signal is padded with information after being processed by the second FEC.

[0173] For example, the size of the padding information is 8×128b.

[0174] For example, the insertion interval between two adjacent padding messages is 8704×128b or 8×4096×128b. In other words, the insertion period of the padding message can be 8704×128b or 8×4096×128b. That is, in this embodiment of the application, after the second signal is processed by the second FEC, a padding message of size 8×128b can be inserted every 8704×128b, or a padding message of size 8×128b can be inserted every 8×4096×128b, without limitation. By setting different insertion intervals, different transmission rates can be determined accordingly, which can meet different transmission requirements.

[0175] For example, the third signal contains a bit rate of 238.746 Gbit / s or 238.585 Gbit / s for each physical channel signal.

[0176] For example, when the insertion interval between two adjacent padding information is 8704×128b, the bit rate of each physical channel signal contained in the third signal can be approximately 238.746 Gbit / s. Specifically, the bit rate of each physical channel signal contained in the third signal (e.g., FlexO-8-RSH) satisfies: FlexO-8-RSH bit rate / 4=2×119373056.541kbit / s=238746113.083kbit / s.

[0177] For example, when the insertion interval between two adjacent padding information is 8×4096×128b, the bit rate of each physical channel signal contained in the third signal can be approximately 238.585Gbit / s. Specifically, the bit rate of each physical channel signal contained in the third signal (e.g., FlexO-8-RSH) satisfies: FlexO-8-RSH bit rate / 4=2×4063 / 3390×99532800kbit / s=238585112.92kbit / s.

[0178] In this application, bit rate can also be replaced with transmission rate or speed, and there is no limitation thereto. The bit rate value of each physical channel signal included in the above-mentioned third signal is only an example given for ease of understanding and is not limited. For example, the specific value of transmission rate or bit rate involved in this application can be a real value or an approximation of a real value. In addition, the number of decimal places after the specific value can be one, two, or other numbers, or the number of decimal places can be omitted. When the number of decimal places is omitted, the specific value of bit rate can be determined by the principle of rounding, and there is no limitation thereto.

[0179] The following is an example illustrating the specific implementation of FEC processing for the second signal, with reference to Figures 6 and 7.

[0180] Figure 6 is a schematic diagram illustrating FEC processing between a second signal and a third signal according to an embodiment of this application. As shown in Figure 6(a), the transmitting device can perform a second FEC processing on the second signal (e.g., FOIC8.4-RS), that is, perform Hamming FEC encoding processing on the interleaved second signal to obtain the third signal (e.g., FOIC8.4-RSH). As shown in Figure 6(b), after receiving the third signal (e.g., FOIC8.4-RSH), the receiving device can perform a third FEC processing on the third signal, that is, perform Hamming FEC decoding processing on the third signal to obtain the second signal (e.g., FOIC8.4-RS). It can be understood that the third FEC processing and the second FEC processing are inverse processes of each other.

[0181] Optionally, the transmitting device may also perform a second FEC processing on the second signal (e.g., FOIC16o.8-RS), that is, perform Hamming FEC encoding on the interleaved second signal to obtain the third signal (e.g., FOIC16o.8-RSH). Correspondingly, the receiving device may also perform a third FEC processing on the third signal (e.g., FOIC16o.8-RSH) after receiving it, that is, perform Hamming FEC decoding on the third signal to obtain the second signal (e.g., FOIC16o.8-RS). It is understood that this third FEC processing and the second FEC processing are inverse processes of each other.

[0182] Figure 7 is a schematic diagram of the structure of a Hamming FEC functional block provided in an embodiment of this application. As shown in Figure 7, the left side is the processing flow on the transmitting device side, with n = 4 input lanes, and the right side is the processing flow on the receiving device side, with n = 4 output lanes. For example, the transmitting device performs the following operations sequentially on the second signal (e.g., n = 4 channels of 200 bit / s FOIC8.4-RS signal, or n = 8 channels of 200 bit / s FOIC16o.8-RS signal) to obtain the third signal (e.g., n = 4 channels of 200 bit / s FOIC8.4-RSH signal, or n = 8 channels of 200 bit / s FOIC16o.8-RSH signal). These operations include convolutional interleaver, 1:8 120 bit data block separation, circular shift, inner FEC encoding, 8:1 bit-pair interleaver, 8×128b pad insertion, and PAM4 encoding. Correspondingly, the receiving device receives the third signal (e.g., n = 4 channels of 200 bit / s FOIC8.4-RSH signals, or n = 8 channels of 200 bit / s FOIC16o.8-RSH signals), and sequentially performs PAM decoding, FEC synchronization (inner FEC sync), 8×128b pad removal, 1:8 bit-pair deinterleaver, Hamming FEC decoding, inverse circular shift, 8:1 120 bit data block collection, and convolutional deinterleaver to obtain the second signal (e.g., n = 4 channels of 200 bit / s FOIC8.4-RS signals, or n = 8 channels of 200 bit / s FOIC16o.8-RS signals). Correspondingly, it can be understood that the processing procedures on the sending device side and the receiving device side are the inverse of each other.

[0183] It is understandable that the Hamming FEC functional block shown in Figure 7 can be deployed independently or integrated into the optical module or OTN device. This application does not limit the deployment method of the Hamming FEC functional block.

[0184] As shown in Figure 7, after the second signal is encoded by Hamming FEC (i.e., the second FEC processing), padding information of size 8×128b is inserted. In the technical solution of this application, since the insertion interval of the padding information is not unique, for example, the insertion interval can be 8704×128b or 8×4096×128b, the corresponding signal transmission rate will also be different, thereby meeting the transmission requirements of different signals.

[0185] Table 1 below shows the correspondence between various FOIC interfaces, nominal bit rate, and bit rate tolerance.

[0186] Table 1

[0187] Specifically, Table 1 shows the nominal bit rates of the FlexO-8-RS, FOIC8.4-RS, FlexO-8-RSH, and FOIC8.4-RSH channels. Furthermore, multiple FOIC interfaces or channels have the same frequency offset range, for example, ±20ppm. The signal bit rate transmitted through the FlexO-8-RS (i.e., the second signal) interface can be 8×30592 / 27233×99532800 kbit / s, and the nominal bit rate of the FOIC8.4-RS channel is approximately: FlexO-8-RS bit rate / 4 = 2×111 809 474.446 kbit / s = 223618948.893 kbit / s. When the insertion interval for padding information is 8704×128b, the signal bit rate transmitted through the FlexO-8-RSH (i.e., the third signal) interface can be 8×30592 / 27233×99532800 kbit / s. The nominal bit rate of the FOIC8.4-RSH channel is approximately: FlexO-8-RSH bit rate / 4 = 2 × 119 373056.541 kbit / s = 238746113.083 kbit / s.

[0188] In the embodiments of this application, the above-mentioned interfaces, such as FlexO-8, can also be described as FlexO-8o, FlexO-8-RS can also be described as FlexO-8o-RS, FOIC8.4-RS can also be described as FOIC8o.4-RS, FlexO-8-RSH can also be described as FlexO-8o-RSH, FOIC8.4-RSH can also be described as FOIC8o.4-RSH, etc., and their specific names are not limited.

[0189] Tables 2 and 3 below show the correspondence between multiple FOIC interfaces and transmission rates for optical module transmission rates of 800 Gbps (gigabits per second) and 1.6 Tbps (terabits per second), respectively.

[0190] Table 2

[0191] Table 3

[0192] In Table 2 or Table 3 above, Rate 1 can be seen as reserving support for 2-layer FlexO channel layer multiplexing, and the FlexO channel layer frame structure is 10*16 byte overhead area + 5130*16 byte payload area. Rate 2 can be seen as reserving support for 3-layer FlexO channel layer multiplexing, and the FlexO channel layer frame structure is 10*16 byte overhead area + 5130*16 byte payload area. Rate 3 can be seen as reserving support for 3-layer FlexO channel layer multiplexing, and the FlexO channel layer frame structure is 6*16 byte overhead area + 5130*16 byte payload area.

[0193] It should be understood that the rates provided in Table 2 or Table 3 above are merely illustrative examples to facilitate understanding of the scheme, and other possible implementation methods are not excluded.

[0194] Based on the above scheme, the second signal is obtained by interleaving the first signal with a 10-bit symbol granularity. Specifically, the 32 logical channel signals are interleaved in groups of 8 with a 10-bit symbol granularity, resulting in 4 physical channel signals. For example, if the first signal has a rate of 800 Gbit / s and is generated from 8 100 Gbit / s OTN signals, then each logical channel signal has a rate of 25 Gbit / s. After interleaving, each physical channel signal has a rate of 200 Gbit / s. A 4*200G optical module can support higher-speed signal transmission, achieving generational upgrades and cost reduction. Furthermore, interleaving with a 10-bit symbol granularity ensures that the signal distribution granularity and interleaving granularity are consistent at 10 bits, guaranteeing symbol integrity and facilitating subsequent FEC encoding.

[0195] Figure 11 is a schematic flowchart of another data signal transmission method provided in an embodiment of this application. As shown in Figure 11, the method includes the following steps. For details not covered herein, please refer to the relevant description in Figure 4 above. For the sake of brevity, these details will not be repeated here.

[0196] S1110, The transmitting device acquires or generates the first signal.

[0197] For example, the first signal can be a FlexO frame, and the OTN signal can be either OTUCn or FlexO, without limitation.

[0198] The first signal is generated from m channels of x*25Gbit / s OTN signals and has undergone the first FEC processing.

[0199] For example, m can be an integer greater than 1, and x can be an integer greater than or equal to 1. For example, m can be equal to 8, 16, or 64, etc., or m can be an integer multiple of 8. For example, x can be equal to 1, 2, or 4, etc.

[0200] For example, m*x can be a multiple of 8, such as 8, 16, 32, or 64.

[0201] For example, the first signal can be generated from m = 8 OTN signals with x = 1 * 25 Gbit / s, or the first signal can be generated from m = 16 OTN signals with x = 1 * 25 Gbit / s, or the first signal can be generated from m = 32 OTN signals with x = 1 * 25 Gbit / s, or the first signal can be generated from m = 16 OTN signals with x = 2 * 25 Gbit / s, or the first signal can be generated from m = 16 OTN signals with x = 4 * 25 Gbit / s, or the first signal can be generated from m = 64 OTN signals with x = 4 * 25 Gbit / s, without limitation.

[0202] Understandably, m channels of x*25Gbit / s OTN signals can be understood as: there are m OTN signals, each with a bit rate of x*25Gbit / s. For example, if the rate of the first signal is 800Gbit / s, m=8, and x=4, then the first signal can be generated from eight 100Gbit / s OTN signals, with each logical channel signal having a rate of 25Gbit / s.

[0203] Optionally, before performing step S1110, i.e. before the transmitting device acquires the first signal, the method 1100 further includes: the transmitting device generating at least one y*100Gbit / s FlexO signal, and performing RS encoding on the at least one y*100Gbit / s FlexO signal to obtain the first signal, where y is an integer greater than or equal to 1.

[0204] In one possible implementation, the transmitting device maps the OTUCy signal to a FlexO signal, the FlexO signal comprising at least y FlexO instance signals, each with a bit rate of 100 Gbit / s. Then, the at least y FlexO instance signals are interleaved to obtain at least one y*100 Gbit / s FlexO signal. Next, RS encoding is performed on the at least one y*100 Gbit / s FlexO signal to obtain a first signal, which is then transmitted to the receiving device. Correspondingly, the receiving device receives the first signal and performs RS decoding on it to obtain at least one y*100 Gbit / s FlexO signal. Then, the at least one y*100 Gbit / s FlexO signal is deinterleaved to obtain at least y FlexO instance signals, each with a bit rate of 100 Gbit / s. The optical transmission unit OTUCy signal is demapped from the at least y FlexO instance signals. The processing at the receiving device is the reverse of the mapping and interleaving process relative to the transmitting device.

[0205] S1120, the transmitting device performs interleaving processing on the first signal based on a 10*n bit symbol granularity to obtain the second signal.

[0206] The second signal includes (m*x) / 8 physical channel signals.

[0207] For example, n is an integer greater than or equal to 1. For instance, n = 2.

[0208] For example, the bit rate of each physical channel signal included in the second signal is 223.618 Gbit / s, or 213.865 Gbit / s, or 214.304 Gbit / s, or 213.836 Gbit / s.

[0209] For example, the second signal can be a FOIC-RS signal after 10*n bit symbol interleaving. For instance, the (m*x) / 8 physical channel signal can be a FOIC8o.4-RS signal or a FOIC16o.8-RS signal.

[0210] For example, the rate level of the first signal can be 800 Gbit / s. The first signal is generated by 8 OTN signals of 100 Gbit / s each. Then the rate level of each logical channel signal is 25 Gbit / s. After interleaving, the second signal containing 4 physical channel signals is obtained. Then the rate level of each physical channel signal is 200 Gbit / s, which can achieve higher signal transmission speed and reduce costs.

[0211] For example, the rate level of the first signal can be 1.6Tbit / s. The first signal is generated by 16 OTN signals of 100Gbit / s each. Then the rate level of each logical channel signal is 25Gbit / s. After interleaving, the second signal containing 8 physical channel signals is obtained. Then the rate level of each physical channel signal is 200Gbit / s, which can achieve higher signal transmission speed and reduce costs.

[0212] It should be understood that interleaving with a 10*n bit symbol granularity ensures that the signal distribution granularity and the interleaving granularity are consistent, both being 10*n bits. This guarantees the integrity of the symbols and facilitates subsequent Hamming FEC encoding. For details, please refer to step S1140 below, which will not be explained here.

[0213] S1130, the transmitting device sends a second signal to the receiving device; correspondingly, the receiving device receives the second signal from the transmitting device.

[0214] S1140, the receiving device performs deinterleaving processing on the second signal based on a 10*n bit symbol granularity to obtain the first signal.

[0215] This application does not limit the specific method of transmitting the second signal or the specific implementation method of deinterleaving the second signal.

[0216] Optionally, for the second signal determined above, the transmitting device may also perform Hamming FEC encoding processing on the second signal, that is, the method 1100 further includes the following step S1150.

[0217] S1150, the transmitting device performs a second FEC process on the second signal to obtain a third signal, and then sends the third signal to the receiving device.

[0218] Correspondingly, the receiving device receives the third signal and performs third FEC processing on the third signal to obtain the second signal.

[0219] Understandably, the third FEC treatment is the reverse process of the second FEC treatment.

[0220] For example, the second FCE processing can be Hamming FEC encoding processing. The second signal can be the FOIC-RS signal, and the third signal can be the FOIC-RSH signal after FEC encoding. For example, the second signal can be the FOIC8o.4-RS signal, and the third signal can be the FOIC8o.4-RSH signal; or the second signal can be the FOIC16o.8-RS signal, and the third signal can be the FOIC16o.8-RSH signal, without limitation.

[0221] In one implementation, the second signal is padded with information after being processed by the second FEC.

[0222] For example, the size of the padding information is 8×128b.

[0223] For example, the insertion interval between two adjacent padding messages is 8704×128b or 8×4096×128b. In other words, the insertion period of the padding message can be 8704×128b or 8×4096×128b. That is, in this embodiment of the application, after the second signal is processed by the second FEC, a padding message of size 8×128b can be inserted every 8704×128b, or a padding message of size 8×128b can be inserted every 8×4096×128b, without limitation. By setting different insertion intervals, different transmission rates can be determined accordingly, which can meet different transmission requirements.

[0224] For example, the bit rate of each physical channel signal included in the third signal is 238.746 Gbit / s, or 238.585 Gbit / s, or 228.332 Gbit / s, or 228.800 Gbit / s, or 228.301 Gbit / s.

[0225] For example, when the insertion interval between two adjacent padding information is 8704×128b, the bit rate of each physical channel signal contained in the third signal can be approximately 238.746 Gbit / s. Specifically, the bit rate of each physical channel signal contained in the third signal (e.g., FlexO-8-RSH) satisfies: FlexO-8-RSH bit rate / 4=2×119373056.541kbit / s=238746113.083kbit / s, or 228.332Gbit / s, or 228.800Gbit / s, or 228.301Gbit / s.

[0226] For example, when the insertion interval between two adjacent padding information is 8×4096×128b, the bit rate of each physical channel signal contained in the third signal can be approximately 238.585Gbit / s. Specifically, the bit rate of each physical channel signal contained in the third signal (e.g., FlexO-8-RSH) satisfies: FlexO-8-RSH bit rate / 4=2×4063 / 3390×99532800kbit / s=238585112.92kbit / s.

[0227] Based on the above scheme, the second signal is obtained by interleaving the first signal with a granularity of 10*n bits. For example, the rate level of the first signal can be 1.6Tbit / s, generated by 16 channels of 100Gbit / s OTN signals, with each physical channel signal having a rate level of 200Gbit / s. Higher-speed signal transmission can be supported through 8*200G optical modules, achieving generational upgrade and cost reduction.

[0228] It should be understood that the specific examples shown in the embodiments of this application are only for the purpose of helping those skilled in the art to better understand the embodiments of this application, and are not intended to limit the scope of the embodiments of this application.

[0229] It should also be understood that, in the various embodiments of this application, unless otherwise specified or in case of logical conflict, the terms and / or descriptions between different embodiments are consistent and can be referenced by each other, and the technical features in different embodiments can be combined to form new embodiments according to their inherent logical relationships.

[0230] It should also be understood that in some of the above embodiments, the examples are mainly based on devices in existing network architectures (such as OTN devices), and this application does not limit the specific form of the devices in the embodiments. For example, any device that can achieve the same function in the future is applicable to this application.

[0231] The signal transmission method provided by the embodiments of this application has been described above with reference to Figures 1 to 7 and Figure 11. In the various embodiments of this application, unless otherwise specified or logically conflicting, the terms and / or descriptions between the various embodiments are consistent and can be referenced by each other. The technical features in different embodiments can be combined to form new embodiments according to their inherent logical relationship.

[0232] The signal transmission method apparatus, device, and chip system provided in the embodiments of this application are described in detail below with reference to Figures 8 to 10. It should be understood that the descriptions of the apparatus embodiments correspond to the descriptions of the method embodiments. Therefore, for details not described in detail, please refer to the above method embodiments; for brevity, some details are omitted.

[0233] Figure 8 is a schematic block diagram of a communication device 1000 provided in an embodiment of this application. As shown in Figure 8, the device 1000 can be disposed in the OTN device 101 shown in Figure 1, or the device 1000 can also be disposed in the OTN device shown in Figure 2. The device 1000 includes a transceiver module 1001, which can be used to implement corresponding transceiver functions. The transceiver module 1001 can also be referred to as a transceiver unit.

[0234] The device 1000 also includes a processing module 1002 (or processing unit), which can be used to implement corresponding processing functions.

[0235] Optionally, the device 1000 further includes a storage unit, which can be used to store instructions and / or data. The processing module 1002 can read the instructions and / or data in the storage unit so that the device can perform the operation of the relevant devices in the foregoing method embodiments.

[0236] The device 1000 can be used to perform the actions performed by the transmitting or receiving device in the above method embodiments. In this case, the device 1000 can be a component of the transmitting or receiving device. The transceiver module 1001 is used to perform the transmission and reception related operations of the transmitting or receiving device in the above method embodiments, and the processing module 1002 is used to perform the processing related operations of the transmitting or receiving device in the above method embodiments.

[0237] It should be understood that the specific process of each module performing the above-mentioned corresponding steps has been described in detail in the above method embodiments, and will not be repeated here for the sake of brevity.

[0238] Figure 9 is a schematic diagram of a signal transmission method apparatus provided in an embodiment of this application. As shown in Figure 9, the apparatus 2000 includes a processor 2001 and an optical transceiver 2002. This apparatus can be applied to both transmitting and receiving devices. The apparatus shown in Figure 9 may include any of the OTN devices 101 shown in Figure 1, or the apparatus shown in Figure 9 may also include the OTN device shown in Figure 2.

[0239] For example, processor 2001 is used to implement S410, S420, and S440 in method 400 shown in FIG. 4, or to implement S1110, S1120, and S1140 in method 1100 shown in FIG. 11. Optical transceiver 2002 is used to implement S430 in method 400 shown in FIG. 4, or to implement S1130 in method 1100 shown in FIG. 11. During implementation, each step of the processing flow can be completed by the integrated logic circuitry of the hardware in processor 2001 or by instructions in the form of software, thus fulfilling the method executed by the transmitting or receiving device.

[0240] In this application embodiment, the processor 2001 can be a general-purpose processor, digital signal processor, application-specific integrated circuit, field-programmable gate array or other programmable logic device, discrete gate or transistor logic device, or discrete hardware component, capable of implementing or executing the methods, steps, and logic block diagrams disclosed in this application embodiment. The general-purpose processor can be a microprocessor or any conventional processor, etc. The steps of the methods disclosed in the embodiments of this application can be directly manifested as being executed by a hardware processor, or executed by a combination of hardware and software units within the processor.

[0241] Furthermore, the device 2000 may include one or more processors 2001.

[0242] Optionally, the device 2000 may further include a memory 2003, wherein the program code executed by the processor 2001 to implement the above methods can be stored in the memory 2003. The device 2000 may include one or more memories 2003.

[0243] Specifically, the memory 2003 can be coupled to the processor 2001. The coupling in this embodiment is an indirect coupling or communication connection between devices, units, or modules, and can be electrical, mechanical, or other forms, used for information exchange between devices, units, or modules. Alternatively, the processor 2001 can operate in conjunction with the memory 2003. The memory 2003 can be non-volatile memory, such as a hard disk drive (HDD), or volatile memory, such as random-access memory (RAM). The memory 2003 can be any other medium capable of carrying or storing desired program code in the form of instructions or data structures, and accessible by a computer, but is not limited thereto. It should be noted that the device described in FIG9 can also be used to perform the method steps involved in the aforementioned variations of the embodiments shown in the figures, which will not be repeated here.

[0244] Figure 10 is a schematic diagram of a chip system provided in an embodiment of this application. As shown in Figure 10, the chip system 3000 (or processing system) includes logic circuitry 3010 and input / output interface 3020.

[0245] The logic circuit 3010 can be a processing circuit in the chip system 3000. The logic circuit 3010 can be coupled to a memory unit, calling instructions from the memory unit, enabling the chip system 3000 to implement the methods and functions of the embodiments of this application. The input / output interface 3020 can be an input / output circuit in the chip system 3000, outputting processed information from the chip system 3000, or inputting data or signaling information to be processed into the chip system 3000 for processing.

[0246] Optionally, the logic circuit 3010 may be implemented by one or more processors, including the one or more processors or the processing portion of the one or more processors.

[0247] Optionally, the input / output interface 3020 may include transceiver circuitry, a transceiver, input / output circuitry, or a communication interface.

[0248] As one approach, the chip system 3000 is used to implement the operations performed by the transmitting or receiving device in the various method embodiments described above.

[0249] Specifically, the logic circuit 3010 is used to implement the processing-related operations performed by the transmitting device or the receiving device in the above method embodiments; the input / output interface 3020 is used to implement the sending and / or receiving-related operations performed by the transmitting device or the receiving device in the above method embodiments.

[0250] This application embodiment also provides an optical module, which includes a signal processor and an optical transmitting component. The signal processor is used to: acquire a first signal, the first signal comprising 32 logical channel signals, generated from 8 OTN signals of 100 Gbit / s, or 4 of 200 Gbit / s, or 2 of 400 Gbit / s, or 1 of 800 Gbit / s, and the first signal undergoing first FEC processing; the signal processor is also used to: interleave the first signal based on a 10-bit symbol granularity to obtain a second signal, the second signal comprising 4 physical channel signals; the optical transmitting component is used to: transmit the second signal.

[0251] This application embodiment also provides an optical module, which includes a signal processor and an optical transmitting component. The signal processor is used to: acquire a first signal, which is generated from m x*25Gbit / s OTN signals and has undergone first FEC processing; the signal processor is also used to: interleave the first signal based on a 10*n bit symbol granularity to obtain a second signal, which includes (m*x) / 8 physical channel signals; the optical transmitting component is used to: transmit the second signal.

[0252] This application embodiment also provides an optical module, which includes a signal processor and an optical receiving component. The optical receiving component is used to receive a second signal, which includes four physical channel signals. The signal processor is used to deinterleave the second signal at a 10-bit symbol granularity to obtain a first signal, which includes 32 logical channel signals. The first signal is generated from eight 100Gbit / s, or four 200Gbit / s, or two 400Gbit / s, or one 800Gbit / s Optical Transport Network (OTN) signals, and the first signal has undergone first FEC processing.

[0253] This application also provides an optical module, which includes a signal processor and an optical transmitting component. The optical receiving component is used to receive a second signal, which includes (m*x) / 8 physical channel signals. The signal processor is used to deinterleave the second signal based on a 10*n bit symbol granularity to obtain a first signal, which is generated from m x*25Gbit / s optical transport network (OTN) signals and has undergone first FEC processing.

[0254] Based on the above embodiments, this application also provides a computer-readable storage medium. This storage medium stores a software program, which, when read and executed by one or more processors, can implement the methods provided in any one or more of the above embodiments. The computer-readable storage medium may include various media capable of storing program code, such as a USB flash drive, portable hard drive, read-only memory, random access memory, magnetic disk, or optical disk.

[0255] Based on the above embodiments, this application provides a computer program product containing instructions. When this computer program product is run on a computer or processor, it can implement the methods provided in any one or more of the above embodiments.

[0256] Based on the above embodiments, this application also provides a chip. The chip includes a processor for implementing the functions involved in any one or more of the above embodiments, such as acquiring or processing OTN frames involved in the above methods. Optionally, the chip further includes a memory for storing necessary program instructions and data executed by the processor. The chip may be composed of a single chip or may include chips and other discrete devices.

[0257] Obviously, those skilled in the art can make various modifications and variations to the embodiments of this application without departing from the scope of the embodiments of this application. Therefore, if these modifications and variations to the embodiments of this application fall within the scope of the claims of this application and their equivalents, this application also intends to include these modifications and variations.

[0258] It should be understood that the processor mentioned in the embodiments of this application can be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor can be a microprocessor or any conventional processor.

[0259] It should also be understood that the memory mentioned in the embodiments of this application can be volatile memory and / or non-volatile memory. Non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. Volatile memory can be random access memory (RAM). For example, RAM can be used as an external cache. By way of example and not limitation, RAM can include a variety of forms, such as: static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous linked dynamic random access memory (SLDRAM), and direct rambus RAM (DR RAM).

[0260] It should be noted that when the processor is a general-purpose processor, DSP, ASIC, FPGA or other programmable logic device, discrete gate or transistor logic device, or discrete hardware component, the memory (storage module) can be integrated into the processor.

[0261] Those skilled in the art will recognize that the units and steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application; such implementations should not be considered beyond the scope of protection of this application.

[0262] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces, and the indirect coupling or communication connection of apparatus or units may be electrical, mechanical, or other forms.

[0263] In the above embodiments, implementation can be achieved entirely or partially through software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented entirely or partially in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. For example, the computer can be a personal computer, a server, or a network device, etc. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available media can be magnetic media (e.g., floppy disks, hard disks, magnetic tapes), optical media (e.g., DVDs), or semiconductor media (e.g., solid-state disks, SSDs). For example, the aforementioned available media can include, but are not limited to, various media capable of storing program code, such as USB flash drives, portable hard drives, ROM, RAM, magnetic disks, or optical disks.

[0264] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A signal transmission method, characterized in that, include: The first signal is obtained. The first signal is generated by m x*25Gbit / s optical transport network OTN signals. The first signal has been processed by the first FEC. m is an integer greater than 1 and x is an integer greater than or equal to 1. Based on a 10*n bit symbol granularity, the first signal is interleaved to obtain the second signal, which includes (m*x) / 8 physical channel signals, where n is an integer greater than or equal to 1; Send the second signal.

2. The method according to claim 1, characterized in that, The method further includes: The second signal is processed by a second FEC to obtain a third signal; Send the third signal.

3. The method according to claim 2, characterized in that, The second signal is padded with information after being processed by the second FEC.

4. The method according to claim 3, characterized in that, The size of the padding information is 8×128b.

5. The method according to claim 3 or 4, characterized in that, The insertion interval between two adjacent padding messages is 8704×128b or 8×4096×128b.

6. The method according to any one of claims 1 to 5, characterized in that, The second signal contains a bit rate of 223.618 Gbit / s, or 213.865 Gbit / s, or 214.304 Gbit / s, or 213.836 Gbit / s for each physical channel signal.

7. The method according to any one of claims 2 to 6, characterized in that, The third signal contains a bit rate of 238.746 Gbit / s, or 238.585 Gbit / s, or 228.332 Gbit / s, or 228.800 Gbit / s, or 228.301 Gbit / s for each physical channel signal.

8. The method according to any one of claims 3 to 7, characterized in that, When the insertion interval between two adjacent padding messages is 8704×128b, the bit rate of each physical channel signal contained in the third signal is 238.746Gbit / s.

9. The method according to any one of claims 3 to 7, characterized in that, When the insertion interval between two adjacent padding messages is 8×4096×128b, the bit rate of each physical channel signal contained in the third signal is 238.585Gbit / s.

10. The method according to any one of claims 1 to 9, characterized in that, Before acquiring the first signal, the method further includes: Generate at least one y*100Gbit / s FlexO signal, and perform RS encoding on the at least one y*100bit / s FlexO signal to obtain the first signal, where y is an integer greater than or equal to 1.

11. The method according to claim 10, characterized in that, The generation of at least one y*100Gbit / s FlexO signal includes: The optical transmission unit OTUCy signal is mapped to the flexible optical transport network FlexO signal, the FlexO signal including at least y FlexO instance signals, each FlexO instance signal having a bit rate of 100 Gbit / s; The at least y-channel FlexO instance signals are interleaved to obtain the at least one y*100Gbit / s FlexO signal.

12. The method according to any one of claims 1 to 11, characterized in that, The first signal is a FlexO frame from a flexible optical transport network.

13. The method according to any one of claims 1 to 12, characterized in that, n＝2。 14. A signal transmission method, characterized in that, include: Receive a second signal, which includes (m*x) / 8 physical channel signals, where m is an integer greater than 1 and x is an integer greater than or equal to 1; Based on a 10*n bit symbol granularity, the second signal is deinterleaved to obtain the first signal. The first signal is generated from m x*25Gbit / s optical transport network OTN signals. The first signal has undergone the first FEC processing, where n is an integer greater than or equal to 1.

15. The method according to claim 14, characterized in that, The method further includes: Receive third signal; The third signal is subjected to a third FEC process to obtain the second signal.

16. The method according to claim 15, characterized in that, The second signal is padded with information after being processed by the second FEC.

17. The method according to claim 16, characterized in that, The size of the padding information is 8×128b.

18. The method according to claim 15 or 16, characterized in that, The insertion interval between two adjacent padding messages is 8704×128b or 8×4096×128b.

19. The method according to any one of claims 14 to 18, characterized in that, The second signal contains a bit rate of 223.618 Gbit / s, or 213.865 Gbit / s, or 214.304 Gbit / s, or 213.836 Gbit / s for each physical channel signal.

20. The method according to any one of claims 15 to 19, characterized in that, The third signal contains a bit rate of 238.746 Gbit / s, or 238.585 Gbit / s, or 228.332 Gbit / s, or 228.800 Gbit / s, or 228.301 Gbit / s for each physical channel signal.

21. The method according to any one of claims 16 to 20, characterized in that, When the insertion interval between two adjacent padding messages is 8704×128b, the bit rate of each physical channel signal contained in the third signal is 238.746Gbit / s.

22. The method according to any one of claims 16 to 20, characterized in that, When the insertion interval between two adjacent padding messages is 8×4096×128b, the bit rate of each physical channel signal contained in the third signal is 238.585Gbit / s.

23. The method according to any one of claims 14 to 22, characterized in that, The method further includes: RS decoding is performed on the first signal to obtain at least one y*100Gbit / s FlexO signal, where y is an integer greater than or equal to 1.

24. The method according to claim 23, characterized in that, The method further includes: At least one y*100Gbit / s flexible optical transport network FlexO signal is deinterleaved to obtain at least y FlexO instance signals, each FlexO instance signal having a bit rate of 100Gbit / s. The optical transmission unit OTUCy signal is obtained by demapping from the at least y-channel FlexO instance signal.

25. The method according to any one of claims 14 to 24, characterized in that, The first signal is a FlexO frame from a flexible optical transport network.

26. The method according to any one of claims 14 to 25, characterized in that, n＝2。 27. An optical module, characterized in that, Includes signal processors and optical emission components; The signal processor is used to acquire a second signal, wherein the transmission rate of each physical channel signal contained in the second signal is 223.618 Gbit / s; The signal processor is further configured to perform a second FEC process on the second signal to obtain a third signal, wherein the bit rate of each physical channel signal contained in the third signal is 238.746 Gbit / s or 238.585 Gbit / s; The optical emitting component is used to transmit the third signal.

28. An optical module, characterized in that, Includes signal processors and optical receiving components; The optical receiving component is used to receive a third signal, wherein each physical channel signal contained in the third signal has a bit rate of 238.746 Gbit / s or 238.585 Gbit / s. The signal processor is used to perform a third FEC process on the third signal to obtain a second signal, wherein the transmission rate of each physical channel signal contained in the second signal is 223.618 Gbit / s.

29. An optical communication device, characterized in that, It includes at least one processor, said at least one processor being used to perform the method as described in any one of claims 1 to 13.

30. An optical communication device, characterized in that, It includes at least one processor, said at least one processor being used to perform the method as described in any one of claims 14 to 26.

31. An optical module, characterized in that, The optical module includes a signal processor and an optical emitting component, wherein... The signal processor is configured to perform the method as described in any one of claims 1 to 13; The optical emitting component is used to transmit the second signal.

32. An optical module, characterized in that, The optical module includes a signal processor and an optical receiver component, wherein... The optical receiving component is used to receive the second signal; The signal processor is configured to perform the method as described in any one of claims 14 to 26.

33. An optical chip, characterized in that, It includes at least one processor and a communication interface for performing the method as described in any one of claims 1 to 13.

34. An optical chip, characterized in that, It includes at least one processor and a communication interface for performing the method as described in any one of claims 14 to 26.

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