Silicon substrate and manufacturing method therefor, and heterojunction solar cell and manufacturing method therefor

Abstract

The present invention relates to a silicon substrate and a manufacturing method therefor, and a heterojunction solar cell and a manufacturing method therefor. The manufacturing method for the silicon substrate comprises: an initial silicon substrate comprising a first surface and a second surface, forming a first mask layer on the first surface, and forming a second mask layer on the second surface; performing first dot matrix laser etching processing on the first mask layer to form a first intermediate mask layer having holes; performing second dot matrix laser etching processing on the second mask layer corresponding to a target region on the second surface to form a second intermediate mask layer having holes, wherein the target region is used for arranging gate lines; performing alkaline etching processing on the first surface by means of the holes of the first intermediate mask layer, and performing alkaline etching processing on the target region by means of the holes of the second intermediate mask layer; and removing the first intermediate mask layer to obtain a first textured surface, and removing the second intermediate mask layer, so as to obtain the silicon substrate having a second textured surface located in the target region. In the silicon substrate manufactured by the manufacturing method for the silicon substrate, the adhesiveness between the second surface of the silicon substrate and the gate lines is excellent, and the first surface has ultra-low reflectivity.

Description

Silicon substrates and their fabrication methods and heterojunction solar cells and their fabrication methods

[0001] Cross-references to related applications

[0002] This application claims priority to Chinese Patent Application No. 202411544441.8, filed on October 31, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This invention relates to the field of solar cell fabrication technology, specifically to silicon substrates and their fabrication methods, and heterojunction solar cells and their fabrication methods. Background Technology

[0004] Against the backdrop of energy structure transformation, the new energy industry is booming, and photovoltaics, as a new energy source, has also ushered in unprecedented prosperity. Silicon substrate heterojunction solar cells are currently one of the key areas of focus in photovoltaic solar cells. To improve the light utilization of silicon substrate heterojunction solar cells, the main method currently used is to texturize the silicon substrate to form a pyramidal textured surface with low reflectivity, thereby improving the light-trapping effect of the silicon substrate, facilitating better light absorption, and increasing the light utilization efficiency of silicon substrate heterojunction solar cells.

[0005] Currently, silicon substrates for heterojunction solar cells are typically textured on both sides. However, the textured back side can cause uneven mask layer deposition, negatively impacting passivation. Furthermore, the textured back side hinders secondary reflection absorption of incident light, negatively affecting the conversion efficiency of heterojunction solar cells. Existing methods involve polishing the back side of the silicon substrate to create a polished surface, thereby reducing reflectivity, increasing secondary reflection absorption of incident light, and enhancing the substrate's light absorption. Simultaneously, the polished back side facilitates uniform deposition of the passivation layer. However, current methods primarily involve coating the back side of the silicon substrate with low-temperature silver paste to form the grid lines. In the case of a smooth back surface, the adhesion between the paste and the substrate is poor, easily leading to poor contact between the paste and the silicon wafer, and causing partial grid detachment during the welding process of heterojunction solar cell modules. Summary of the Invention

[0006] This invention provides a method for fabricating a silicon substrate, which can produce a silicon substrate with excellent adhesion between the second surface and the gate lines, and ultra-low reflectivity on the first surface. This method is simple, has a short process, and is suitable for widespread application.

[0007] The present invention also provides a method for fabricating a heterojunction solar cell, comprising fabricating a silicon substrate using the above-described method for fabricating a silicon substrate, and fabricating a heterojunction solar cell using the fabricated silicon substrate. The heterojunction solar cell fabricated by this method has high light utilization efficiency.

[0008] The first aspect of this invention provides a method for preparing a silicon substrate, comprising:

[0009] S1: Set a mask layer on the initial silicon substrate;

[0010] The initial silicon substrate includes a first surface and a second surface disposed opposite to each other, and the mask layer is formed by: forming a first mask layer on the first surface and forming a second mask layer on the second surface;

[0011] S2: Perform a first dot matrix laser etching process on the first mask layer to form a first intermediate mask layer with holes;

[0012] The second mask layer corresponding to the target area of ​​the second surface is subjected to a second dot matrix laser etching process to form a second intermediate mask layer with holes, wherein the target area is used to set gate lines;

[0013] S3: Alkaline etching is performed on the first surface through the holes in the first intermediate mask layer, and alkaline etching is performed on the target area through the holes in the second intermediate mask layer;

[0014] S4: Remove the first intermediate mask layer to obtain the first textured surface, and remove the second intermediate mask layer to obtain the second textured surface located in the target area.

[0015] In the silicon substrate fabrication method described above, in S2, during the first dot matrix laser etching process, the size of a single laser spot is 0.5-50 micrometers, and the minimum distance between any two adjacent laser spots is 0.1-3 micrometers; and / or,

[0016] In the second dot matrix laser etching process, the size of a single spot is 0.5-50 micrometers, and the minimum distance between any two adjacent spots is 0.1-3 micrometers.

[0017] In the silicon substrate fabrication method described above, in S2, the time for the first dot matrix laser etching process is 1-30 s, and the power of the first dot matrix laser etching process is 1-100 W; and / or,

[0018] The second dot matrix laser etching process takes 1-30 seconds and has a power of 1-100W.

[0019] In the silicon substrate fabrication method described above, the first mask layer and / or the second mask layer are each independently an oxide layer or a silicon nitride layer.

[0020] In the silicon substrate preparation method described above, the thickness of the oxide layer is 5 nm-300 nm.

[0021] In the silicon substrate preparation method described above, the thickness of the silicon nitride layer is 30nm-300nm.

[0022] The silicon substrate preparation method described above further includes, before S1: performing a pre-cleaning treatment, an RCA cleaning treatment, and a drying treatment on the initial silicon substrate in sequence;

[0023] The pre-cleaning process includes: performing a first cleaning process on the initial silicon substrate using a first solution, and then performing a second cleaning process on the initial silicon substrate using a second solution;

[0024] The first solution comprises: 1-15 wt% alkaline solution, 1-15 wt% hydrogen peroxide, the temperature of the first solution is 45-65°C, and the time of the first cleaning treatment is 1-4 min.

[0025] The second solution comprises 0.1-10 wt% alkaline solution, the temperature of the second solution is 45-80℃, and the time of the second cleaning treatment is 0.5-4 min.

[0026] The silicon substrate preparation method described above, wherein the alkaline etching process includes: performing the alkaline etching process using an alkaline solution with a mass percentage of 1-5%.

[0027] In the silicon substrate preparation method described above, the alkaline etching temperature is 40-80°C and the alkaline etching time is 60-300s.

[0028] In the silicon substrate fabrication method described above, S4 includes: removing the first intermediate mask layer and the second intermediate mask layer respectively using hydrofluoric acid with a mass percentage of 0.001-38%.

[0029] A second aspect of the present invention provides a method for fabricating a heterojunction solar cell, comprising fabricating a silicon substrate using the silicon substrate fabrication method described above;

[0030] A first passivation layer is formed on the first textured surface of the silicon substrate, and a second passivation layer is formed on the surface where the second textured surface of the silicon substrate is located;

[0031] A first doped layer is disposed on the surface of the first passivation layer away from the silicon substrate, and a second doped layer is disposed on the surface of the second passivation layer away from the silicon substrate, wherein the first doped layer and the second doped layer have opposite conductivity types;

[0032] A first transparent conductive film is formed on the surface of the first doped layer away from the silicon substrate, and a second transparent conductive film is formed on the surface of the second doped layer away from the silicon substrate;

[0033] An electrode is disposed on the surface of the first transparent conductive film away from the silicon substrate, and an electrode is disposed on the surface of the second transparent conductive film corresponding to the second textured surface away from the silicon substrate, thereby obtaining the heterojunction solar cell.

[0034] A third aspect of the present invention provides a silicon substrate for a solar cell, comprising a first surface and a second surface disposed opposite to each other; the first surface has holes, the surface of which has a first textured surface; a target region of the second surface has holes, the surface of which has a second textured surface; the position of the target region corresponds to the position of the grid line of the solar cell.

[0035] A fourth aspect of the present invention provides a heterojunction solar cell comprising the silicon substrate described in the third aspect of the present invention.

[0036] The heterojunction solar cell described above comprises, from top to bottom, the following layers stacked sequentially: an electrode, a first transparent conductive film, a first doped layer, a first passivation layer, the silicon substrate, a second passivation layer, a second doped layer, a second transparent conductive film, and an electrode.

[0037] The method for fabricating a silicon substrate according to the present invention involves forming a first mask layer on a first surface of an initial silicon substrate, performing a first dot matrix laser etching process on the first mask layer to form a first intermediate mask layer with holes, performing an alkaline etching process on the first surface through the holes of the first intermediate mask layer, allowing the alkaline solution to contact the initial silicon substrate through the holes of the first intermediate mask layer to achieve texturing of the first surface, and removing the first intermediate mask layer to obtain a first textured surface; and forming a second mask layer on a second surface of the initial silicon substrate, the second surface having a target area for setting gate lines, performing a second dot matrix laser etching process on the second mask layer corresponding to the target area to form a second intermediate mask layer with holes, performing an alkaline etching process on the target area through the holes of the second intermediate mask layer, allowing the alkaline solution to contact the initial silicon substrate through the holes of the second intermediate mask layer, and removing the second intermediate mask layer to obtain a second textured surface located in the target area, the second textured surface being used for setting gate lines. This invention improves the adhesion between the gate lines and the target area by texturing the target area where the gate lines are set, thereby increasing the pull between them. Furthermore, this invention only texturizes the target area on the back side used for setting the gate lines (other areas are smooth), ensuring uniform deposition of the passivation layer on the back side of the silicon substrate without affecting its reflectivity. Simultaneously, since this method omits the polishing step after texturing the initial silicon substrate, it shortens the process flow and avoids thinning of the initial silicon substrate due to polishing, preventing waste of initial substrate thickness and reducing the probability of wafer breakage in subsequent processes. Notably, because the first dot-matrix laser etching process in this invention can form a first intermediate mask layer with highly regular morphology holes, when alkaline solution performs alkaline etching on the first surface through these holes, a more uniform first textured surface can be formed, thereby reducing the front reflectivity of the silicon substrate.

[0038] The method for fabricating a heterojunction solar cell of the present invention includes preparing a silicon substrate using the above-described method for preparing a silicon substrate, and then using the prepared silicon substrate to fabricate a heterojunction solar cell. The heterojunction solar cell fabricated by this method has high light utilization efficiency. Furthermore, this method is simple, efficient, and has excellent practical value.

[0039] The silicon substrate obtained by this invention has highly regular holes on its first surface. The surface of these holes has a textured structure, which helps to reduce the front reflectivity, improve the light-trapping effect of the silicon substrate, and allow the front side of the silicon substrate to better absorb light, thereby improving the photoelectric conversion efficiency. Simultaneously, the target area of ​​the second surface of the silicon substrate has holes with a textured surface, which helps to improve the adhesion between the gate lines and the target area. Furthermore, the other areas of the second surface outside the target area are smooth, which facilitates the uniform deposition of the passivation layer without affecting the back reflectivity of the silicon substrate.

[0040] The heterojunction solar cell of the present invention includes the aforementioned silicon substrate, which is beneficial to improving the light utilization rate of the heterojunction solar cell and thus improving the cell conversion efficiency. Attached Figure Description

[0041] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0042] Figure 1 is a schematic diagram of the initial silicon substrate structure of Embodiment 1 of the present invention;

[0043] Figure 2 is a schematic diagram of the structure of the first intermediate silicon substrate in Embodiment 1 of the present invention;

[0044] Figure 3 is a schematic diagram of the structure of the second intermediate silicon substrate in Embodiment 1 of the present invention;

[0045] Figure 4 is a schematic diagram of the silicon substrate structure of Embodiment 1 of the present invention;

[0046] Figure 5 is a schematic diagram of the heterojunction solar cell of Embodiment 1 of the present invention;

[0047] Figure 6 is a schematic diagram of the silicon substrate of Comparative Example 2 of the present invention.

[0048] Explanation of reference numerals in the attached figures: 1-Silicon substrate; 2-First intrinsic amorphous silicon layer; 3-N-type amorphous silicon layer; 4-First transparent conductive film; 5-Second intrinsic amorphous silicon layer; 6-P-type amorphous silicon layer; 7-Second transparent conductive film; 8-Metal electrode; 11-Initial silicon substrate; 12-First mask layer; 13-Second mask layer; 14-First intermediate mask layer; 15-Second intermediate mask layer. Detailed Implementation

[0049] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below in conjunction with the accompanying drawings and embodiments. Obviously, the described embodiments are only some embodiments of this invention, not all embodiments. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention.

[0050] Furthermore, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0051] The first aspect of this invention provides a method for preparing a silicon substrate, comprising:

[0052] S1: Set a mask layer on the initial silicon substrate;

[0053] The initial silicon substrate includes a first surface and a second surface disposed opposite to each other, and the mask layer is formed by: forming a first mask layer on the first surface and forming a second mask layer on the second surface;

[0054] S2: Perform first dot matrix laser etching on the first mask layer to form a first intermediate mask layer with holes;

[0055] The second mask layer corresponding to the target area of ​​the second surface is subjected to a second dot matrix laser etching process to form a second intermediate mask layer with holes, wherein the target area is used to set the gate lines;

[0056] S3: Alkali etching is performed on the first surface through the holes in the first intermediate mask layer, and alkali etching is performed on the target area through the holes in the second intermediate mask layer;

[0057] S4: Remove the first intermediate mask layer to obtain the first textured surface, which is the location of the first surface after alkaline etching; remove the second intermediate mask layer to obtain the second textured surface located in the target area, which is the location of the second surface after alkaline etching.

[0058] The initial silicon substrate of the present invention has two opposing first surfaces and a second surface. In the present invention, the first surface can be used as the front side of the initial silicon substrate, and the second surface can be used as the back side of the initial silicon substrate.

[0059] A first mask layer is formed on the first surface, and similarly, a second mask layer is formed on the second surface. The function of the first and second mask layers is to protect specific areas of the silicon substrate from being etched in subsequent processing steps.

[0060] The present invention does not limit the shape, size, or thickness of the initial silicon substrate; it can be selected according to actual needs.

[0061] The first dot-matrix laser etching process involves forming holes penetrating the first mask layer on its surface using a laser beam. During this process, the laser beam etches the surface of the first mask layer, creating holes that penetrate the first mask layer and expose the first surface of the silicon substrate, thus obtaining a first intermediate mask layer. This first intermediate mask layer is resistant to alkalis but not acids, and its alkali resistance is superior to that of the silicon substrate. Therefore, the first intermediate mask layer can continuously cover the first surface during subsequent alkaline etching processes, acting as a "mask," while the holes provide etching sites for creating the first textured surface on the first surface.

[0062] The second surface of the present invention has a target area for setting gate lines. The second dot-matrix laser etching process involves forming holes penetrating the second mask layer on the surface of the second mask layer corresponding to the target area using a laser beam. During the second dot-matrix laser etching process, the laser beam can etch holes into the surface of the second mask layer corresponding to the target area. These holes penetrate the second mask layer and expose the target area of ​​the silicon substrate, thereby obtaining a second intermediate mask layer. The second intermediate mask layer is resistant to alkalis but not to acids, and its alkali resistance is superior to that of the silicon substrate. Therefore, the second intermediate mask layer can continuously cover the second surface during subsequent alkaline etching processes, acting as a "mask," while the holes provide etchable locations for preparing the second textured surface in the target area.

[0063] In some embodiments, the holes may include various shapes, such as square or circular, and there is no limitation, as long as the holes can penetrate the first mask layer and the second mask layer and expose the first surface and the second surface of the silicon substrate.

[0064] Alkali etching is performed on the first surface. Since the first intermediate mask layer is resistant to alkali but not acid, it will not be dissolved by the alkali etching. The alkali can then texturize the first surface of the silicon substrate through the vias penetrating the first mask layer. Similarly, alkali etching is performed on the target area of ​​the second surface. Since the second intermediate mask layer is resistant to alkali but not acid, it will not be dissolved by the alkali etching. The alkali can then texturize the target area of ​​the second surface of the silicon substrate through the vias penetrating the second mask layer.

[0065] After performing alkaline etching on the first surface, the first intermediate mask layer is removed to expose the alkaline-etched area, thus obtaining the first textured surface. The area of ​​the first surface that has not undergone alkaline etching is the smooth surface. Similarly, after performing alkaline etching on the target area of ​​the second surface, the second intermediate mask layer is removed to expose the alkaline-etched area, thus obtaining the second textured surface. The second textured surface is located in the target area, and the area of ​​the second surface that has not undergone alkaline etching is the smooth surface. That is, the other areas outside the target area are smooth surfaces, and finally, a silicon substrate is obtained.

[0066] The fabrication method of this invention can produce a silicon substrate with a textured surface on the front side and a textured surface on the target area on the back side (other areas outside the target area on the back side are smooth). When grid lines are formed on the surface of this silicon substrate, the textured surface on the target area on the back side exhibits excellent adhesion to the grid lines, preventing poor grid line contact from affecting the efficiency of heterojunction solar cells. Furthermore, the highly regular textured surface on the front side, combined with the textured target area and smooth surfaces on the back side, reduces the reflectivity of the silicon substrate and enhances its absorption of light, especially long-wavelength light. Notably, the fabrication method of this invention does not involve alkaline polishing, thus avoiding the thinning of the silicon substrate and excessive fragmentation during subsequent welding caused by alkaline polishing. The fabrication method of this invention also has the advantages of simple process and short flow, making it suitable for widespread application.

[0067] The present invention does not impose any particular limitation on the first dot matrix laser etching process, as long as it enables the first mask layer to form a first intermediate mask layer with holes; the present invention does not impose any particular limitation on the second dot matrix laser etching process, as long as it enables the second mask layer to form a second intermediate mask layer with holes.

[0068] This invention does not limit the shape and size of the laser spot used in the laser etching process. For example, the shape of the laser spot can be circular, square, or irregular. "Spot size" refers to the maximum size of the laser spot. For example, for a circular laser spot, the spot size refers to the diameter of the circular laser spot; for a square laser spot, the spot size refers to the side length of the square laser spot; for an irregular laser spot, the spot size refers to the maximum value of the irregular laser spot in all directions.

[0069] In some implementations, when the size of a single laser spot in the first dot matrix laser etching process is 0.5-50 micrometers (specifically, it can be 0.5 micrometers, 1 micrometer, 5 micrometers, 10 micrometers, 15 micrometers, 20 micrometers, 25 micrometers, 30 micrometers, 35 micrometers, 40 micrometers, 45 micrometers, 50 micrometers, or any combination thereof), and the minimum distance between any two adjacent laser spots is 0.1-3 micrometers (specifically, it can be 0.1 micrometers, 0.5 micrometers, 1 micrometer, 1.5 micrometers, 2 micrometers, 2.5 micrometers, 3 micrometers, or any combination thereof), the surface roughness of the front side of the silicon substrate can be made suitable, thereby reducing the reflectivity of the silicon substrate.

[0070] When the size of a single laser spot in the second-order laser etching process is 0.5-50 micrometers (specifically, it can be 0.5 micrometers, 1 micrometer, 5 micrometers, 10 micrometers, 15 micrometers, 20 micrometers, 25 micrometers, 30 micrometers, 35 micrometers, 40 micrometers, 45 micrometers, 50 micrometers, or any combination thereof), and the minimum distance between any two adjacent laser spots is 0.1-3 micrometers (specifically, it can be 0.1 micrometers, 0.5 micrometers, 1 micrometer, 1.5 micrometers, 2 micrometers, 2.5 micrometers, 3 micrometers, or any combination thereof), the roughness of the back surface texture of the silicon substrate can be appropriate, ensuring the adhesion between the gate lines and the silicon substrate.

[0071] In some embodiments of the present invention, when the time of the first dot matrix laser etching process is 1-30s (specifically, it can be 1s, 5s, 10s, 15s, 20s, 25s, 30s, or any combination thereof), and the power of the first dot matrix laser etching process is 1-100W (specifically, it can be 1W, 10W, 20W, 30W, 40W, 50W, 60W, 70W, 80W, 90W, 100W, or any combination thereof), a portion of the first mask layer can be removed more thoroughly without damaging the initial silicon substrate, forming a first intermediate mask layer with holes.

[0072] When the second dot matrix laser etching process takes 1-30 seconds (specifically, it can be 1 second, 5 seconds, 10 seconds, 15 seconds, 20 seconds, 25 seconds, 30 seconds, or any combination thereof), and the power of the second dot matrix laser etching process is 1-100W (specifically, it can be 1W, 10W, 20W, 30W, 40W, 50W, 60W, 70W, 80W, 90W, 100W, or any combination thereof), a portion of the second mask layer can be removed more thoroughly without damaging the initial silicon substrate, forming a second intermediate mask layer with holes.

[0073] In this invention, the specific process parameters for the first dot matrix laser etching process and the second dot matrix laser etching process can be the same or different.

[0074] In one specific embodiment, the first mask layer and / or the second mask layer are each independently an oxide layer or a silicon nitride layer. For example, in this invention, the first mask layer can be an oxide layer or a silicon nitride layer; the second mask layer can be an oxide layer or a silicon nitride layer. The oxide layer includes a silicon dioxide layer, and the silicon nitride layer includes SiN. x Layer, where x is a positive integer.

[0075] In some implementations, the oxide layer can be formed by thermal oxidation; the silicon nitride layer can be formed by CVD deposition.

[0076] In this invention, when the first mask layer includes an oxide layer or a silicon nitride layer, during alkaline etching, the first intermediate mask layer formed by the first mask layer can better protect the first surface, forming a first textured surface; when the second mask layer includes an oxide layer or a silicon nitride layer, during alkaline etching, the second intermediate mask layer formed by the second mask layer can better protect the second surface, forming a second textured surface in the target area, and after alkaline etching, the first intermediate mask layer including the oxide layer or the silicon nitride layer and the second intermediate mask layer can be more easily removed, thereby obtaining a silicon substrate with a textured surface on the front side and a textured surface on the back target area.

[0077] In one specific embodiment, when the first mask layer and / or the second mask layer is an oxide layer, the thickness of the oxide layer is 5nm-300nm. For example, the thickness of the oxide layer includes, but is not limited to, a range of 5nm, 50nm, 100nm, 150nm, 200nm, 250nm, 300nm, or any combination thereof.

[0078] By controlling the thickness of the oxide layer, this invention can fully protect the first and second surfaces during alkaline etching, and more efficiently obtain silicon substrates with a textured first surface and a textured target area on the second surface.

[0079] In one specific embodiment, when the first mask layer and / or the second mask layer are silicon nitride layers, the thickness of the silicon nitride layer is 30nm-300nm. For example, the thickness of the silicon nitride layer includes, but is not limited to, a range of 30nm, 100nm, 150nm, 200nm, 250nm, 300nm, or any combination thereof.

[0080] By controlling the thickness of the silicon nitride layer, this invention can fully protect the first and second surfaces during alkaline etching, and more efficiently obtain silicon substrates with a textured first surface and a textured target area on the second surface.

[0081] In one specific embodiment, the alkaline etching process includes: performing alkaline etching using an alkaline solution with a mass percentage of 1-5%.

[0082] The alkali in the alkaline solution includes at least one of sodium hydroxide, potassium hydroxide, calcium hydroxide, ammonia, sodium carbonate, and potassium carbonate. For example, the mass percentage of the alkaline solution includes, but is not limited to, a range of 1%, 2%, 3%, 4%, 5%, or any combination thereof.

[0083] By using an alkaline solution with a mass percentage within the above-mentioned range, the present invention can more fully etch the first surface and the target area of ​​the second surface without damaging the first intermediate mask layer and the second intermediate mask layer, thereby forming a silicon substrate with a textured first surface and a textured target area of ​​the second surface.

[0084] In one specific embodiment, the alkaline etching temperature is 40-80°C, and the alkaline etching time is 60-300 seconds. For example, the temperature in the alkaline etching process includes, but is not limited to, a range of 40°C, 50°C, 60°C, 70°C, 80°C, or any combination thereof; the time in the alkaline etching process includes, but is not limited to, a range of 60 seconds, 100 seconds, 150 seconds, 200 seconds, 250 seconds, 300 seconds, or any combination thereof.

[0085] By controlling the temperature and time of the alkaline etching process within the aforementioned range, this invention enables more uniform etching of the target areas corresponding to the first and second surfaces while saving energy, thereby obtaining a silicon substrate including the first textured surface and the second textured surface more efficiently.

[0086] In one specific embodiment, removing the first intermediate mask layer and the second intermediate mask layer respectively includes: removing the first intermediate mask layer and the second intermediate mask layer respectively using hydrofluoric acid with a mass percentage of 0.001-38%. For example, the mass percentage of hydrofluoric acid used to remove the first intermediate mask layer and the second intermediate mask layer includes, but is not limited to, 0.001%, 1%, 5%, 10%, 15%, 20%, 25%, 30%, 35%, 38%, or any combination thereof.

[0087] The present invention removes the first intermediate mask layer and the second intermediate mask layer respectively by using hydrofluoric acid with a mass percentage within the above range, thereby removing the first intermediate mask layer and the second intermediate mask layer more efficiently with almost no impact on the first and second velvet surfaces.

[0088] In some embodiments of the present invention, before S1, the process further includes: performing a pre-cleaning process, an RCA cleaning process, and a drying process on the initial silicon substrate in sequence;

[0089] The pre-cleaning process includes: performing a first cleaning process on the initial silicon substrate using a first solution, and then performing a second cleaning process on the initial silicon substrate using a second solution;

[0090] The first solution comprises: 1-15 wt% alkali solution and 1-15 wt% hydrogen peroxide. The temperature of the first solution is 45-65°C, and the time for the first cleaning treatment is 1-4 min. Specifically, the concentration of the alkali solution in the first solution can be 1 wt%, 3 wt%, 5 wt%, 7 wt%, 10 wt%, 13 wt%, 15 wt%, or any combination thereof, and the concentration of the hydrogen peroxide can be 1 wt%, 3 wt%, 5 wt%, 7 wt%, 10 wt%, 13 wt%, 15 wt%, or any combination thereof. The temperature of the first solution can be 45°C, 50°C, 55°C, 60°C, 65°C, or any combination thereof, and the time for the first cleaning treatment can be 1 min, 2 min, 3 min, 4 min, or any combination thereof.

[0091] The second solution comprises: 0.1-10 wt% alkali solution, the temperature of the second solution is 45-80℃, and the time of the second cleaning treatment is 0.5-4 min. Specifically, the concentration of the alkali solution in the second solution can be 0.1 wt%, 1 wt%, 3 wt%, 7 wt%, 10 wt%, 13 wt%, 15 wt%, or any combination thereof; the temperature of the second solution can be 45℃, 50℃, 60℃, 70℃, 80℃, or any combination thereof; and the time of the second cleaning treatment can be 0.5 min, 1 min, 2 min, 3 min, 4 min, or any combination thereof.

[0092] Specifically, before S1, the process may include: performing a first cleaning treatment on the initial silicon substrate using a first solution to remove grease and other contaminants from the surface of the initial silicon substrate; then performing a second cleaning treatment on the initial silicon substrate using a second solution to remove the surface damage layer of the initial silicon substrate; followed by an RCA cleaning treatment to further remove the oxide layer of the initial silicon substrate; and finally performing a drying treatment to obtain a clean and dry initial silicon substrate.

[0093] Before S1, the present invention further includes performing the above-mentioned pre-cleaning treatment, RCA cleaning treatment and drying treatment on the initial silicon substrate in sequence, so as to obtain a clean and dry initial silicon substrate, thereby promoting the subsequent formation of the first mask layer and the second mask layer, and thus obtaining a silicon substrate with better overall performance.

[0094] In this invention, the RCA cleaning treatment can be a standard RCA cleaning treatment. In some embodiments, the RCA cleaning treatment may include a first RCA cleaning treatment, a second RCA cleaning treatment, and a hydrofluoric acid treatment. In the first RCA cleaning treatment, the solution comprises 1-15 wt% alkaline solution and 1-15 wt% hydrogen peroxide, at a temperature of 45-65°C for 1-4 minutes. In the second RCA cleaning treatment, the solution comprises 1-15 wt% hydrochloric acid and 1-15 wt% hydrogen peroxide, at a temperature of 25-65°C for 1-4 minutes. In the hydrofluoric acid treatment, the solution comprises 1-10 wt% HF, at a temperature of 25°C for 2-4 minutes.

[0095] The alkali used in this invention can be any alkali commonly used in the art. For example, the alkali can be at least one of KOH and NaOH.

[0096] A second aspect of the present invention provides a method for fabricating a heterojunction solar cell, comprising fabricating a silicon substrate using the above-described method for fabricating a silicon substrate;

[0097] A first passivation layer is formed on the first textured surface of the silicon substrate, and a second passivation layer is formed on the surface where the second textured surface of the silicon substrate is located;

[0098] A first doped layer is formed on the surface of the first passivation layer away from the silicon substrate, and a second doped layer is formed on the surface of the second passivation layer away from the silicon substrate. The first doped layer and the second doped layer have opposite conductivity types.

[0099] A first transparent conductive film is disposed on the surface of the first doped layer away from the silicon substrate, and a second transparent conductive film is disposed on the surface of the second doped layer away from the silicon substrate.

[0100] An electrode is disposed on the surface of the first transparent conductive film away from the silicon substrate, and an electrode is disposed on the surface of the second transparent conductive film corresponding to the second textured surface away from the silicon substrate, to obtain a heterojunction solar cell.

[0101] The method for fabricating a heterojunction solar cell of the present invention includes fabricating a silicon substrate using the above-described method for fabricating a silicon substrate. The heterojunction solar cell fabricated by this method exhibits high light utilization efficiency. This method is simple, efficient, and has excellent practical value.

[0102] A third aspect of the present invention provides a silicon substrate for a solar cell, comprising a first surface and a second surface disposed opposite to each other; the first surface has holes, the surface of which has a first textured surface; a target region of the second surface has holes, the surface of which has a second textured surface; the position of the target region corresponds to the position of the grid line of the solar cell.

[0103] The silicon substrate obtained by this invention has highly regular holes on its first surface. The surface of these holes has a textured structure, which helps to reduce the front reflectivity, improve the light-trapping effect of the silicon substrate, and allow the front side of the silicon substrate to better absorb light, thereby improving the photoelectric conversion efficiency. Simultaneously, the target area of ​​the second surface of the silicon substrate has holes with a textured surface, which helps to improve the adhesion between the gate lines and the target area. Furthermore, the other areas of the second surface outside the target area are smooth, which facilitates the uniform deposition of the passivation layer without affecting the back reflectivity of the silicon substrate.

[0104] A fourth aspect of the present invention provides a heterojunction solar cell, comprising the silicon substrate described in the third aspect of the present invention. This silicon substrate is advantageous for improving the light utilization efficiency of the heterojunction solar cell, thereby increasing the cell conversion efficiency.

[0105] Specifically, the heterojunction solar cell of the present invention comprises, from top to bottom, the following layers stacked sequentially: an electrode, a first transparent conductive film, a first doped layer, a first passivation layer, a silicon substrate, a second passivation layer, a second doped layer, a second transparent conductive film, and an electrode.

[0106] The present invention does not impose any particular limitation on the first passivation layer and the second passivation layer. The first passivation layer and the second passivation layer can be passivation layers commonly used in the art. For example, the first passivation layer can be a first intrinsic amorphous silicon doped layer, and the second passivation layer can be a second intrinsic amorphous silicon doped layer.

[0107] This invention does not impose any particular limitations on the first and second doped layers, as long as the conductivity types of the first and second doped layers are opposite. For example, the first doped layer can be an N-type doped layer (either an N-type amorphous silicon layer or an N-type microcrystalline silicon layer), and the second doped layer can be a P-type doped layer (either a P-type amorphous silicon layer or a P-type crystalline silicon layer). In this invention, an N-type doped layer is disposed on the front side, and a P-type doped layer is disposed on the back side.

[0108] The present invention does not limit the arrangement of the first passivation layer, the second passivation layer, the first doped layer, and the second doped layer. Commonly used methods in the art can be employed to form the first passivation layer, the second passivation layer, the first doped layer, and the second doped layer, respectively. For example, chemical vapor deposition can be used to form at least one of the first passivation layer, the second passivation layer, the first doped layer, and the second doped layer.

[0109] This invention does not limit the specific formation methods of the first transparent conductive film and the second transparent conductive film. The first transparent conductive film and the second transparent conductive film can be formed using methods commonly used in the art. For example, the first transparent conductive film and / or the second transparent conductive film can be formed using physical vapor deposition.

[0110] The present invention will be further described in detail below through specific embodiments.

[0111] Example 1

[0112] Figure 1 is a schematic diagram of the initial silicon substrate of Embodiment 1 of the present invention; Figure 2 is a schematic diagram of the first intermediate silicon substrate of Embodiment 1 of the present invention; Figure 3 is a schematic diagram of the second intermediate silicon substrate of Embodiment 1 of the present invention; Figure 4 is a schematic diagram of the silicon substrate of Embodiment 1 of the present invention; Figure 5 is a schematic diagram of the heterojunction solar cell of Embodiment 1 of the present invention. As shown in Figures 1-5, the fabrication method of the heterojunction solar cell of this embodiment includes the following steps:

[0113] 1. Preparation of silicon substrates

[0114] 1) First, place the initial silicon substrate 11 in a mixed solution of 2wt% potassium hydroxide and 2wt% hydrogen peroxide and clean it at 65°C for 4 min. Then, place it in a 5wt% KOH solution and clean it at 50°C for 2 min. Next, perform RCA cleaning to obtain a clean initial silicon substrate. Then, dry the clean initial silicon substrate 11 to obtain a clean and dry initial silicon substrate 11, as shown in Figure 1.

[0115] 2) A first mask layer 12 and a second mask layer 13 are respectively disposed on the two surfaces of the initial silicon substrate 11 to obtain a first intermediate silicon substrate, as shown in Figure 2;

[0116] The first mask layer 12 is SiN formed by CVD deposition. x The first layer has a thickness of 150 nm; the second mask layer 13 is SiN formed by CVD deposition. x The layer has a thickness of 150nm;

[0117] 3) Select a circular light spot to perform a first dot matrix laser etching process on the first mask layer 12 to form a first intermediate mask layer 14 with holes; select a circular light spot to perform a second dot matrix laser etching process on the second mask layer 13 corresponding to the target area (the target area is used to set the gate line) to form a second intermediate mask layer 15 with second holes.

[0118] In the first dot matrix laser etching process, the time is 10s, the power is 5W, the minimum distance between any two adjacent light spots is 1 micrometer, and the diameter of a single light spot is 2 micrometers.

[0119] In the second dot matrix laser etching process, the time is 10s, the power is 5W, the minimum distance between any two adjacent light spots is 1 micrometer, and the diameter of a single light spot is 2 micrometers.

[0120] 4) At 50°C, perform alkaline etching with 1wt% KOH solution for 3 min to obtain the second intermediate silicon substrate, as shown in Figure 3; remove the first intermediate mask layer with 8wt% hydrofluoric acid to obtain the first textured surface; remove the second intermediate mask layer with 8% hydrofluoric acid to obtain the second textured surface located in the target area, and obtain silicon substrate 1, as shown in Figure 4.

[0121] Finally, the silicon substrate is subjected to RCA cleaning and drying.

[0122] 2. Fabrication of heterojunction solar cells

[0123] 1) A first intrinsic amorphous silicon layer 2 and an N-type amorphous silicon layer 3 are sequentially deposited on the first surface of a silicon substrate 1 using chemical vapor deposition (CVD); wherein the first surface has holes, and the surface of the holes has a first textured surface;

[0124] A second intrinsic amorphous silicon layer 5 and a P-type amorphous silicon layer 6 are sequentially deposited on the second surface of a silicon substrate 1 using CVD; wherein the target area of ​​the second surface has holes, and the surface of the holes in the target area has a second textured surface.

[0125] 2) A first transparent conductive film 4 is deposited on the surface of the N-type amorphous silicon layer 3 away from the silicon substrate 1 using physical vapor deposition (PVD), and a second transparent conductive film 7 is deposited on the surface of the P-type amorphous silicon layer 6 away from the silicon substrate 1 using PVD.

[0126] A metal electrode 8 is disposed on the surface of the first transparent conductive film 4 away from the silicon substrate 1, and a metal electrode 8 is disposed on the surface of the second transparent conductive film 7 away from the silicon substrate 1, wherein the metal electrode 8 is disposed at a position corresponding to the second textured surface, forming a heterojunction solar cell, as shown in Figure 5.

[0127] Example 2

[0128] The method for fabricating the heterojunction solar cell provided in this embodiment is basically the same as that in Embodiment 1, except that:

[0129] A square laser spot is selected to perform a first dot matrix laser etching process on the first mask layer 12 to form a first intermediate mask layer 14; a square laser spot is selected to perform a second dot matrix laser etching process on the second mask layer 13 corresponding to the target area (the target area is used to set the gate line) to form a second intermediate mask layer 15.

[0130] In the first dot matrix laser etching process, the time is 10s, the power is 5W, the minimum distance between any two adjacent light spots is 1 micrometer, and the side length of a single light spot is 2 micrometers.

[0131] In the second dot matrix laser etching process, the time is 10s, the power is 5W, the minimum distance between any two adjacent light spots is 1 micrometer, and the side length of a single light spot is 2 micrometers.

[0132] Comparative Example 1

[0133] This comparative example provides a method for fabricating a heterojunction solar cell, which includes the following steps:

[0134] 1. Preparation of silicon substrates

[0135] 1) First, place the initial silicon substrate in a mixed solution of 2wt% potassium hydroxide and 2wt% hydrogen peroxide and clean it at 65°C for 4 min. Then, place it in a 5wt% KOH solution and clean it at 50°C for 2 min. Next, perform RCA cleaning to obtain a clean initial silicon substrate. Then, dry the clean initial silicon substrate to obtain a clean and dry initial silicon substrate.

[0136] 2) At 80°C, a mixed solution of 1 wt% KOH and 1% texturing additive (JY-106S) was used to perform positive pyramid texturing-alkaline etching on both surfaces of the initial silicon substrate for 480 s to obtain a double-sided texturized sheet.

[0137] 3) The double-sided textured wafer is subjected to tubular furnace thermal oxidation treatment at a temperature of 900℃, an oxygen flow rate of 300L / min, and a time of 20min to form oxide layers on both sides of the double-sided textured wafer; then, the oxide layer on one side is removed by a chain pickling device with an HF concentration of 5%; followed by alkaline polishing treatment with 1wt% KOH at 80℃ for 2min to obtain a silicon substrate with a textured front side and a polished back side.

[0138] Finally, the silicon substrate was subjected to RCA cleaning and drying.

[0139] 2. Fabrication of heterojunction solar cells

[0140] The fabrication of the heterojunction solar cell provided in this comparative example is basically the same as that in Example 1, except that the silicon substrate prepared in this comparative example is used.

[0141] Comparative Example 2

[0142] 1. The preparation method of the silicon substrate provided in this comparative example is basically the same as that in Example 1, except that:

[0143] A circular laser spot is selected to perform a first dot matrix laser etching process on the first mask layer 12 to form a first intermediate mask layer 14; a circular laser spot is selected to perform a second dot matrix laser etching process on the entire surface of the second mask layer 13 to form a second intermediate mask layer with holes evenly distributed on the surface. The final silicon substrate has holes with high regularity morphology on both the front and back sides, and the surface of the holes is textured, as shown in Figure 6.

[0144] 2. Fabrication of heterojunction solar cells

[0145] The fabrication of the heterojunction solar cell provided in this comparative example is basically the same as that in Example 1, except that the silicon substrate prepared in this comparative example is used.

[0146] Performance testing

[0147] The silicon substrates and heterojunction solar cells of the examples and comparative examples were subjected to the following performance tests, and the results are shown in Table 1.

[0148] 1) Velvet surface reflectance test

[0149] The reflectance of the front textured surface of the silicon substrate was obtained using a D8 reflectance testing device.

[0150] 2) Pull force between the gate line and the silicon substrate

[0151] The pull force between the front grid lines and the silicon substrate (i.e., front pull force) and the pull force between the back grid lines and the silicon substrate (i.e., back pull force) in heterojunction solar cells were tested using a grid line pull force testing device.

[0152] Table 1 Test Results

[0153] As shown in Table 1, 1) compared with Comparative Example 1, the silicon substrates obtained in Examples 1-2 of the present invention have lower front surface textured reflectivity. The reason is that, compared with the texturing method of Comparative Example 1, the first dot matrix laser etching process used in Examples 1-2 of the present invention can form a first intermediate mask layer with highly regular morphology holes. When the alkaline solution performs alkaline etching on the first surface through these highly regular morphology holes, it can form a more uniform first textured surface, thereby reducing the front surface reflectivity of the silicon substrate.

[0154] 2) Compared with Comparative Example 1, the silicon substrates obtained in Examples 1 and 2 of the present invention can improve the pull between the front grid lines and the silicon substrate, as well as the pull between the back grid lines and the silicon substrate, especially the pull between the back grid lines and the silicon substrate when used to fabricate heterojunction solar cells. This is because the fabrication method of the present invention can form a more uniform first textured surface, which helps to improve the pull between the front grid lines and the silicon substrate. Furthermore, since the area on the back of the silicon substrate used for setting the grid lines is textured, the pull between the back grid lines and the silicon substrate can be further improved. In contrast, the back of the silicon substrate in Comparative Example 1 is entirely polished, resulting in lower pull between the back grid lines and the silicon substrate, which makes it easier for some main grids to detach during the welding process of the solar cell module.

[0155] 3) Meanwhile, since only the area on the back side of the silicon substrate used for setting the grid lines in Embodiments 1 and 2 of the present invention is texturized, while the other areas on the back side are smooth, the back reflectivity of the heterojunction solar cells prepared in Embodiments 1 and 2 of the present invention is basically consistent with that of the heterojunction solar cells prepared in Comparative Example 1. However, since the back side of the silicon substrate in Comparative Example 2 is a uniformly textured surface, the passivation layer cannot be uniformly deposited on the back side. Moreover, the textured surface structure on the back side results in a low back reflectivity, which is not conducive to the absorption of secondary reflection of incident light and the improvement of the photoelectric conversion efficiency of the cell.

[0156] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for preparing a silicon substrate, characterized in that, include: S1: Set a mask layer on the initial silicon substrate; The initial silicon substrate includes a first surface and a second surface disposed opposite to each other, and the mask layer is formed by: forming a first mask layer on the first surface and forming a second mask layer on the second surface; S2: Perform a first dot matrix laser etching process on the first mask layer to form a first intermediate mask layer with holes; The second mask layer corresponding to the target area of ​​the second surface is subjected to a second dot matrix laser etching process to form a second intermediate mask layer with holes, wherein the target area is used to set the gate lines; S3: Alkaline etching is performed on the first surface through the holes in the first intermediate mask layer, and alkaline etching is performed on the target area through the holes in the second intermediate mask layer; S4: Remove the first intermediate mask layer to obtain the first textured surface, and remove the second intermediate mask layer to obtain the second textured surface located in the target area.

2. The method for preparing a silicon substrate according to claim 1, characterized in that, In S2, during the first dot matrix laser etching process, the size of a single laser spot is 0.5-50 micrometers, and the minimum distance between any two adjacent laser spots is 0.1-3 micrometers; and / or, In the second dot matrix laser etching process, the size of a single spot is 0.5-50 micrometers, and the minimum distance between any two adjacent spots is 0.1-3 micrometers.

3. The method for preparing a silicon substrate according to claim 2, characterized in that, In S2, the time for the first dot matrix laser etching process is 1-30 seconds, and the power of the first dot matrix laser etching process is 1-100W; and / or, The second dot matrix laser etching process takes 1-30 seconds and has a power of 1-100W.

4. The method for preparing a silicon substrate according to claim 1, characterized in that, The first mask layer and / or the second mask layer are each independently an oxide layer or a silicon nitride layer.

5. The method for preparing a silicon substrate according to claim 4, characterized in that, The thickness of the oxide layer is 5nm-300nm; and / or the thickness of the silicon nitride layer is 30nm-300nm.

6. The method for preparing a silicon substrate according to any one of claims 1-5, characterized in that, S1 includes the following steps: sequentially performing a pre-cleaning process, an RCA cleaning process, and a drying process on the initial silicon substrate; The pre-cleaning process includes: performing a first cleaning process on the initial silicon substrate using a first solution, and then performing a second cleaning process on the initial silicon substrate using a second solution; The first solution comprises: 1-15 wt% alkaline solution, 1-15 wt% hydrogen peroxide, the temperature of the first solution is 45-65°C, and the time of the first cleaning treatment is 1-4 min. The second solution comprises 0.1-10 wt% alkaline solution, the temperature of the second solution is 45-80℃, and the time of the second cleaning treatment is 0.5-4 min.

7. The method for preparing a silicon substrate according to any one of claims 1-5, characterized in that, The alkaline etching process includes: using an alkaline solution with a mass percentage of 1-5% to perform the alkaline etching process.

8. The method for preparing a silicon substrate according to claim 7, characterized in that, The alkaline etching process is performed at a temperature of 40-80℃ for 60-300 seconds.

9. The method for preparing a silicon substrate according to any one of claims 1-5, characterized in that, S4 includes: The first intermediate mask layer and the second intermediate mask layer were removed using hydrofluoric acid with a mass percentage of 0.001-38%.

10. A method for fabricating a heterojunction solar cell, characterized in that, include: The silicon substrate is prepared using the method for preparing the silicon substrate according to any one of claims 1-9; A first passivation layer is formed on the first textured surface of the silicon substrate, and a second passivation layer is formed on the surface where the second textured surface of the silicon substrate is located; A first doped layer is disposed on the surface of the first passivation layer away from the silicon substrate, and a second doped layer is disposed on the surface of the second passivation layer away from the silicon substrate, wherein the first doped layer and the second doped layer have opposite conductivity types; A first transparent conductive film is formed on the surface of the first doped layer away from the silicon substrate, and a second transparent conductive film is formed on the surface of the second doped layer away from the silicon substrate; An electrode is disposed on the surface of the first transparent conductive film away from the silicon substrate, and an electrode is disposed on the surface of the second transparent conductive film corresponding to the second textured surface away from the silicon substrate, thereby obtaining the heterojunction solar cell.

11. A silicon substrate for a solar cell, characterized in that, It includes a first surface and a second surface arranged opposite to each other; the first surface has holes, and the surface of the holes has a first textured surface; a target area of ​​the second surface has holes, and the surface of the holes in the target area has a second textured surface; the position of the target area corresponds to the position of the grid line of the solar cell.

12. A heterojunction solar cell, characterized in that, Includes the silicon substrate as described in claim 11.

13. The heterojunction solar cell according to claim 12, characterized in that, The layers stacked from top to bottom include: an electrode, a first transparent conductive film, a first doped layer, a first passivation layer, the silicon substrate, a second passivation layer, a second doped layer, a second transparent conductive film, and an electrode.

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