Control method and apparatus, and communication device

Abstract

A control method and apparatus, and a communication device, for use in lowering design constraints of a PPS signal receiving device on an external device, or improving the compatibility of the PPS signal receiving device and the flexibility of a corresponding EE architecture. During implementation, a first device is connected to a second device; on the basis of first information, the first device can enable a target line among at least one line of the first device; and a first PPS signal from the second device is processed by means of the target line to obtain a second PPS signal, the second PPS signal being used for time synchronization between the first device and the second device.

Description

A control method, apparatus and communication equipment

[0001] Cross-reference to related applications

[0002] This application claims priority to Chinese Patent Application No. 202411527655.4, filed on October 29, 2024, entitled "A Control Method, Apparatus and Communication Equipment", the entire contents of which are incorporated herein by reference. Technical Field

[0003] This application relates to the field of communication technology, and in particular to a control method, apparatus and communication equipment. Background Technology

[0004] Currently, vehicles with autonomous driving or intelligent assisted driving capabilities use various sensors such as LiDAR, cameras, and radar to collect surrounding data. The domain controller of the autonomous driving system or intelligent assisted driving system can acquire various perception information and perform fusion perception to realize the vehicle's autonomous driving or intelligent assisted driving functions based on the fusion perception results.

[0005] To improve fusion accuracy, time synchronization between the domain controller and other electronic control units (ECUs) in the vehicle is required. For example, as shown in Figure 1, the domain controller of an autonomous driving system or intelligent driver assistance system can synchronize time with Global Navigation Satellite System (GNSS) devices, lidar, etc. GNSS devices can send Coordinated Universal Time (UTC) information to the domain controller via the Generalized Precision Time Protocol (gPTP), and simultaneously send the corresponding pulse-per-second (PPS) signal to the domain controller. The domain controller corrects the UTC information based on the PPS signal to achieve time synchronization. A similar method can be used to achieve time synchronization between the domain controller and sensors such as lidar. In this process, the device used to output the PPS signal can be called the input device, and the device used to receive the PPS signal can be called the receiving device.

[0006] Currently, there is no unified protocol for PPS signals. In different application scenarios, when different types of input modules are connected to the same receiving module, compatibility issues may arise, affecting the implementation of the aforementioned time synchronization mechanism. Summary of the Invention

[0007] This application provides a control method, apparatus, and communication device for reducing the design constraints of PPS signal receiving devices on external devices, or for improving the compatibility of PPS signal receiving devices and the flexibility of the corresponding electrical and electronic architecture (EE).

[0008] In a first aspect, this application provides a control method, which can be implemented by a first device connected to a second device. The method may include: enabling a target line in at least one line of the first device according to first information; and processing a first pulse-per-second (PPS) signal from the second device through the target line to obtain a second PPS signal, wherein the second PPS signal is used for time synchronization between the first device and the second device.

[0009] Using the above method, the first device, as a PPS signal receiving device, can enable the target line for the second device, allowing the first device to flexibly adapt to different second devices. This reduces the design constraints of the PPS signal receiving device on external devices, or in other words, improves the compatibility of the PPS signal receiving device and the flexibility of the corresponding EE architecture.

[0010] In conjunction with the first aspect, in one possible implementation, the first information can be associated with the output type of the PPS signal of the second device. Thus, the first device can know the output type of the PPS signal of the second device based on the first information, and thereby know how to process the first PPS signal from the second device based on the target line, in order to achieve time synchronization between the first and second devices.

[0011] In conjunction with the first aspect, in one possible implementation, the at least one line may include a first line and a second line, with the output port of the second line connected to the input port of the first line. If the output type of the PPS signal of the second device is a first type, the target line includes the first line and the second line, the second line is enabled, and its output port is connected to the input port of the first line. If the output type of the PPS signal of the second device is a second type, the target line includes the first line, the second line is disabled, and its output port is disconnected from the input port of the first line.

[0012] By connecting the output port of the second line to the input port of the first line and enabling the second line according to the output type of the PPS signal of the second device, the first PPS signal from the second device can be processed using a target line including both the first and second lines when the second line is enabled, and vice versa when the second line is disabled. This allows the first device to flexibly adapt to different second devices, reducing the design constraints of the PPS signal receiving device on external devices, or improving the compatibility of the PPS signal receiving device and the flexibility of the corresponding EE architecture. In conjunction with the first aspect, in one possible implementation, the first device further includes a control module, wherein the enable pin of the control module is connected to the input port of the second line to provide an enable or disable signal to the second line; the output port of the first line is connected to the control module, which is used to achieve time synchronization between the first device and the second device based on the second PPS signal.

[0013] In conjunction with the first aspect, in one possible implementation, if the output type of the PPS signal of the second device is a first type, enabling the target line in at least one line of the first device according to the first information includes: inputting the enable signal to the input port of the second line through the enable pin according to the first information, so that the output port of the second line is connected to the input port of the first line; if the output type of the PPS signal of the second device is a second type, enabling the target line in at least one line of the first device according to the first information includes: inputting the disable signal to the input port of the second line through the enable pin according to the first information, so that the output port of the second line is disconnected from the input port of the first line.

[0014] In conjunction with the first aspect, in one possible implementation, the second line includes a first power supply, which, when the second line is enabled, provides a high-level signal to the input port of the first line.

[0015] In conjunction with the first aspect, in one possible implementation, the second line further includes an NPN transistor and a PNP transistor. The input port of the second line is connected to the base of the NPN transistor, the emitter of the NPN transistor is grounded, the collector of the NPN transistor is connected to the base of the PNP transistor, the emitter of the PNP transistor is connected to the first power supply, and the collector of the PNP transistor is connected to the input port of the first line.

[0016] In conjunction with the first aspect, in one possible implementation, the first device includes a connector connected to the second device, wherein the connector includes at least one pin, each pin being connected to one of the at least one lines, and the first information is associated with a mapping relationship between the second device, the at least one pin, and the at least one line. Thus, the first device can determine, based on the first information, which pin of the second device is connected to the connector and which line that pin is connected to, thereby determining which line to use as the target line to process the first PPS signal from the second device to obtain a second PPS signal.

[0017] In conjunction with the first aspect, in one possible implementation, enabling a target line in at least one line of the first device according to the first information includes: if the first information indicates that the second device is connected to a first pin in the at least one pin, then a third line in the at least one line to which the first pin is connected is designated as the target line; or, if the first information indicates that the second device is connected to a second pin in the at least one pin, then a fourth line in the at least one line to which the second pin is connected is designated as the target line.

[0018] In conjunction with the first aspect, in one possible implementation, when the PPS signal output type of the second device is a first type, the second device is connected to the first pin; or, when the PPS signal output type of the second device is a second type, the second device is connected to the second pin.

[0019] In conjunction with the first aspect, in one possible implementation, the first type includes: a PPS control line in the second device with a low input logic level and a high output impedance state; or a PPS control line in the second device with a high input logic level and a low output logic level; or, the second type includes: a PPS control line in the second device with a low input logic level and a low output logic level; or a PPS control line in the second device with a high input logic level and a high output logic level.

[0020] In conjunction with the first aspect, in one possible implementation, the method further includes: receiving second information from the second device, the second information including Coordinated Universal Time (UTC) information; performing edge sampling in the second PPS signal; and achieving time synchronization between the first device and the second device based on the sampling edges of the second PPS signal and the UTC information.

[0021] In conjunction with the first aspect, in one possible implementation, if the PPS signal output type of the second device is a first type, the step of achieving time synchronization between the first device and the second device based on the sampling edge of the second PPS signal and the UTC information includes: keeping the sampling edge of the second PPS signal unchanged, and achieving time synchronization between the first device and the second device based on the sampling edge of the second PPS signal and the UTC information; if the PPS signal output type of the second device is a second type, the step of achieving time synchronization between the first device and the second device based on the sampling edge of the second PPS signal and the UTC information includes: flipping the sampling edge of the second PPS signal, and achieving time synchronization between the first device and the second device based on the flipped sampling edge and the UTC information.

[0022] In conjunction with the first aspect, in one possible implementation, the method further includes: retrieving the first information from a storage medium when the first device is powered on.

[0023] Secondly, this application provides a control device, comprising: a control module for enabling a target line in at least one line of a first device according to first information, wherein the first device is connected to a second device; and a processing module for processing a first PPS signal from the second device through the target line to obtain a second PPS signal, wherein the second PPS signal is used for time synchronization between the first device and the second device.

[0024] Thirdly, this application provides a communication device, including a control module and at least one line, the communication device being connected to a second device, the control module being configured to enable a target line among the at least one line according to first information; the target line being configured to process a first PPS signal from the second device to obtain a second PPS signal, the second PPS signal being used for time synchronization between the communication device and the second device.

[0025] In conjunction with the third aspect, in one possible implementation, the first information is associated with the output type of the PPS signal of the second device.

[0026] In conjunction with the third aspect, in one possible implementation, the at least one line includes a first line and a second line, with the output port of the second line connected to the input port of the first line. If the output type of the PPS signal of the second device is a first type, the target line includes the first line and the second line, the second line is enabled, and its output port is connected to the input port of the first line. If the output type of the PPS signal of the second device is a second type, the target line includes the first line, the second line is disabled, and its output port is disconnected from the input port of the first line.

[0027] In conjunction with the third aspect, in one possible implementation, the first device further includes a control module, wherein the enable pin of the control module is connected to the input port of the second line for providing an enable signal or a disable signal to the second line; the output port of the first line is connected to the control module, and the control module is used to achieve time synchronization between the first device and the second device based on the second PPS signal.

[0028] In conjunction with the third aspect, in one possible implementation, if the output type of the PPS signal of the second device is a first type, the control module is specifically configured to: input the enable signal to the input port of the second line through the enable pin according to the first information, so that the output port of the second line is connected to the input port of the first line; if the output type of the PPS signal of the second device is a second type, the control module is specifically configured to: input the disable signal to the input port of the second line through the enable pin according to the first information, so that the output port of the second line is disconnected from the input port of the first line.

[0029] In conjunction with the third aspect, in one possible implementation, the second line includes a first power supply, which, when the second line is enabled, provides a high-level signal to the input port of the first line.

[0030] In conjunction with the third aspect, in one possible implementation, the second line further includes an NPN transistor and a PNP transistor. The input port of the second line is connected to the base of the NPN transistor, the emitter of the NPN transistor is grounded, the collector of the NPN transistor is connected to the base of the PNP transistor, the emitter of the PNP transistor is connected to the first power supply, and the collector of the PNP transistor is connected to the input port of the first line.

[0031] In conjunction with the third aspect, in one possible implementation, the first device further includes a connector connected to the second device, wherein the connector includes at least one pin, the at least one pin being connected to the at least one line, and the first information is associated with a mapping relationship between the second device, the at least one pin, and the at least one line.

[0032] In conjunction with the third aspect, in one possible implementation, the control module is specifically configured to: if the first information indicates that the second device is connected to the first pin among the at least one pins, use the third line among the at least one lines to which the first pin is connected as the target line; or, if the first information indicates that the second device is connected to the second pin among the at least one pins, use the fourth line among the at least one lines to which the second pin is connected as the target line.

[0033] In conjunction with the third aspect, in one possible implementation, when the PPS signal output type of the second device is of the first type, the second device is connected to the first pin; or, when the PPS signal output type of the second device is of the second type, the second device is connected to the second pin.

[0034] In conjunction with the third aspect, in one possible implementation, the first type includes: a PPS control line in the second device with a low input logic level and a high output impedance state; or a PPS control line in the second device with a high input logic level and a low output logic level; or, the second type includes: a PPS control line in the second device with a low input logic level and a low output logic level; or a PPS control line in the second device with a high input logic level and a high output logic level.

[0035] In conjunction with the third aspect, in one possible implementation, the communication device further includes a communication module for receiving second information from the second device, the second information including Coordinated Universal Time (UTC) information; the control module is further configured to perform edge sampling in the second PPS signal, and based on the sampling edge of the second PPS signal and the UTC information, realize time synchronization between the first device and the second device.

[0036] In conjunction with the third aspect, in one possible implementation, if the PPS signal output type of the second device is of the first type, the control module is specifically used to: keep the sampling edge of the second PPS signal unchanged, and realize time synchronization between the first device and the second device based on the sampling edge of the second PPS signal and the UTC information; if the PPS signal output type of the second device is of the second type, the control module is specifically used to: flip the sampling edge of the second PPS signal, and realize time synchronization between the first device and the second device based on the flipped sampling edge and the UTC information.

[0037] In conjunction with the third aspect, in one possible implementation, the control module is further configured to retrieve the first information from the storage medium when the first device is powered on.

[0038] Fourthly, this application provides a communication device including at least one processor and an interface circuit, wherein the interface circuit is used to provide data or code instructions to the at least one processor, and the at least one processor is used to implement the method described in the first aspect and any possible implementation thereof through logic circuits or execution code instructions.

[0039] Fifthly, this application provides a computer-readable storage medium storing program code that, when run on a computer, causes the computer to perform the method described in the first aspect and any possible implementation thereof.

[0040] In a sixth aspect, this application provides a computer program product that, when run on a computer, causes the computer to perform the method described in the first aspect and any possible implementation thereof.

[0041] In a seventh aspect, this application provides a vehicle including a first device and a second device, wherein the first device is configured to implement the method described in the first aspect and any possible implementation thereof, for time synchronization with the second device.

[0042] Based on the implementations provided in the above aspects, the embodiments of this application can be further combined to provide more implementations.

[0043] The technical effects that can be achieved by any possible implementation of any aspect from the second to the seventh aspect above can be described with reference to the technical effects that can be achieved by any possible implementation of any aspect from the first aspect above, and the repetitions will not be discussed. Attached Figure Description

[0044] Figure 1 is a schematic diagram of the architecture of an autonomous driving system or intelligent driver assistance system;

[0045] Figure 2 is a schematic diagram of the principle of precise time synchronization;

[0046] Figure 3a is a schematic diagram of the internal circuit structure of a GNSS device;

[0047] Figure 3b is a waveform diagram of the input or output PPS signal of a GNSS device;

[0048] Figure 3c is a schematic diagram of the internal wiring structure of a domain controller in an autonomous driving system or intelligent driver assistance system.

[0049] Figure 4a is a schematic diagram of the internal wiring structure of another GNSS device;

[0050] Figure 4b is a waveform diagram of the input or output PPS signal of another GNSS device;

[0051] Figure 4c is a schematic diagram of the internal wiring structure of a domain controller in another type of autonomous driving system or intelligent driver assistance system.

[0052] Figure 5 is a schematic diagram of the architecture of the communication system applicable to the embodiments of this application;

[0053] Figures 6a-6c are schematic diagrams of system architectures for different examples of different implementations of the GNSS module according to embodiments of this application;

[0054] Figure 7a is a schematic diagram of the structure of the first device according to an embodiment of this application;

[0055] Figure 7b is a schematic diagram of the logic control principle of the target circuit in an embodiment of this application;

[0056] Figure 8 is a flowchart illustrating the control method according to an embodiment of this application;

[0057] Figure 9a is a schematic diagram of one implementation of at least one line of the first device according to an embodiment of this application;

[0058] Figure 9b is a schematic diagram of another implementation of at least one line of the first device according to an embodiment of this application;

[0059] Figure 10a is a schematic diagram of one implementation of at least one line of the first device according to an embodiment of this application;

[0060] Figure 10b is a waveform diagram of line 1 and line 2 in the enabled state according to an embodiment of this application.

[0061] Figure 10c is a waveform diagram of line 2 in the disabled state according to an embodiment of this application;

[0062] Figure 11a is a schematic diagram of another implementation of at least one line of the first device according to an embodiment of this application;

[0063] Figure 11b is a waveform diagram of line 3 in the enabled state according to an embodiment of this application.

[0064] Figure 11c is a waveform diagram of line 4 in the enabled state according to an embodiment of this application.

[0065] Figure 12 is a schematic diagram of the structure of a control device according to an embodiment of this application;

[0066] Figure 13 is a schematic diagram of the structure of a communication device according to an embodiment of this application. Detailed Implementation

[0067] To facilitate understanding, some terms used in the embodiments of this application will be explained below:

[0068] (1) Coordinated Universal Time (UTC): Also known as Coordinated Universal Time or International Standard Time, it is an international time standard based on atomic clocks. It has high precision and stability and is an important standard for modern time measurement.

[0069] UTC time has a wide range of applications, including but not limited to Global Navigation Satellite Systems (GNSS) and other systems that require high-precision time synchronization. GNSS systems, also known as Global Navigation Satellite Systems, can specifically include: Global Positioning System (GPS), BeiDou Navigation Satellite System (BDS), GLONASS, Galileo, etc.

[0070] (2) Generalized Precision Time Protocol (gPTP): Also known as a generalized clock synchronization protocol, it is an extension of the Institute of Electrical and Electronics Engineers (IEEE) 1588 protocol. It provides globally accurate time services for time-sensitive networking (TSN) to implement the stream synchronization function in the TSN standard set. In the network, the network port that publishes time synchronization messages is called the master port, and the port that receives time synchronization messages is called the slave port.

[0071] The main logic of gPTP is as follows: using the best master clock algorithm (BMCA), an optimal node is selected in the network system as the master clock (or a pre-determined one) to send the initial reference clock. Other nodes act as slave clocks, forming a tree structure with the master clock as the root to receive clock signals and align with the master clock. That is, the error between the master and slave clock ports is calculated to achieve synchronization, thereby achieving the goal of time synchronization.

[0072] The master clock serves as the time reference for the entire system. Generally, a higher time accuracy is required, and it needs to be synchronized with even higher-precision clocks, such as atomic clocks and satellites. Master clock allocation can be divided into dynamic and static allocation. For vehicles, whose network composition is generally stable, static pre-allocation can be used to determine the master clock. For systems where the network composition changes dynamically, the BMCA algorithm is typically used for allocation.

[0073] (3) Pulse per second (PPS): In the communications industry, PPS stands for pulses per second, and it is generally used in fields requiring precise time synchronization, such as GNSS systems. The purpose of the pulse per second signal is to indicate the exact second. The rising edge of the PPS signal (or PPS pulse) indicates the exact second in UTC, with an accuracy down to the nanosecond level and no accumulated error. This signal is very important in applications requiring high-precision time synchronization, such as clock synchronization and precise time dissemination.

[0074] Taking autonomous driving systems as an example, autonomous driving mainly encompasses three key technical aspects: perception, planning, and control. Currently, it primarily utilizes various sensors (such as radar, lidar, and cameras) to collect external information, and the domain controller employs multi-sensor fusion to achieve planning and control. During sensor fusion, to improve fusion accuracy, motion compensation, time synchronization, and sensor calibration are required beforehand.

[0075] When achieving time synchronization across multiple sensors, a unified clock source must first be selected to provide a time reference for the entire system. This is accomplished by using a combination of PPS pulses and time synchronization messages to synchronize the master device's time. In autonomous driving systems containing multiple different types of sensors, time synchronization protocols based on Ethernet or CAN are typically employed to achieve high-precision time synchronization between the master device and each sensor.

[0076] In autonomous driving systems, time synchronization typically involves a high-precision GNSS onboard receiver. This receiver decodes navigation satellite signals to achieve positioning and timing. Specifically, the GNSS receiver calculates the clock difference between the high-precision atomic clock in the navigation satellite and the local system time, thereby calibrating the system time and completing the GNSS timing function. Subsequently, the GNSS receiver sends a PPS pulse and a time synchronization message to the receiving device (e.g., a domain controller or industrial control computer). As shown in Figure 2, the PPS pulse is a synchronization pulse signal with a time period (t1) of 1 second, generated based on UTC. The pulse width is typically between 5 and 100 milliseconds, denoted as t0. The time synchronization message may include information such as latitude and longitude, date (year, month, day), and UTC time (accurate to the second).

[0077] Upon receiving a PPS pulse, the receiving device resets its internal system time (based on a crystal oscillator) to zero (in milliseconds and below) and begins calculating millisecond time from this point. After receiving a time synchronization message, the receiving device extracts the UTC time (hour, minute, second, year, month, day) from the message. The time taken from receiving the PPS pulse to parsing the UTC time from the time synchronization message is denoted as tx. This tx time is added to the UTC integer second and synchronized to the device system, thus completing one time synchronization cycle. The system time is precisely calibrated every second to ensure accuracy.

[0078] With the evolution of electrical and electronic architecture (EE) in automobiles, the internal wiring structure and PPS signal output type of GNSS equipment are inconsistent, resulting in several possible scenarios, as shown below:

[0079] Option (1):

[0080] The internal circuitry of GNSS equipment incorporates circuitry based on open collector (OC) devices (e.g., transistors) or open drain (OD) devices (e.g., MOSFETs). OC or OD devices are denoted as device ①. As shown in Figure 3a, taking device ① as an example implemented with an NPN transistor, the input terminal of this circuit is connected to the base of the NPN transistor via a resistor, the emitter of the NPN transistor is grounded, and the collector of the NPN transistor is connected to the output terminal via a resistor.

[0081] After other components (not shown in the figure) inside the GNSS device generate a PPS signal, this PPS signal is input through the input terminal of this line, passes through device ①, and is output at the output terminal of this line, and provided to the input terminal of the domain controller connected to the GNSS device. The line shown in Figure 3a is characterized by only being able to output a logic low level, not a logic high level. Specifically, for example, if the PPS signal input to the input terminal of the line shown in Figure 3a is a square wave signal as shown in Figure 3b, denoted as PPS signal 1, then if the input PPS signal is a logic low level (denoted as L), the output terminal of this line outputs a high-impedance state; if the input PPS signal is a logic high level (denoted as H), the output terminal outputs a logic low level. The output signal corresponding to the input square wave signal is shown as PPS signal 2 in Figure 3b, presenting either a low-level signal or a high-impedance state. It should be understood that the example of a "high-impedance" PPS signal in the figure is only an example; in reality, there is "no signal." Correspondingly, the PPS signal obtained at the domain controller input terminal also presents as a low-level signal or a high-impedance state. Since the input PPS signal has no edges, the domain controller cannot achieve time synchronization based on the input PPS signal.

[0082] Specifically, if the output of the GNSS device is connected to the PPS signal input (denoted as PPS_IN) of the domain controller, and the domain controller provides power to the output of the GNSS device (i.e., the input of the domain controller), then the circuit shown in Figure 3a can provide a square wave signal to the domain controller with the help of the power provided by the domain controller, denoted as PPS signal 1. For example, when the PPS signal input to the circuit shown in Figure 3a is at a logic low level, the GNSS output provides a logic high level signal to the domain controller; when the PPS signal input to the circuit shown in Figure 3a is at a logic high level, the GNSS output provides a logic low level signal to the domain controller. The waveform of the PPS signal obtained by the input port of the domain controller is PPS signal 2 as shown in Figure 3b. In this case, the internal circuit of the domain controller can, for example, connect the input to power supply 1 through a resistor and a diode, as shown in Figure 3c. Power supply 1 can be used to provide a high level to the PPS signal input of the domain controller when the GNSS device outputs a high impedance state, so that the domain controller obtains PPS signal 3 as shown in Figure 3b.

[0083] Furthermore, as shown in Figure 3c, the internal circuitry of the domain controller may also include a device ① (e.g., an NPN transistor) and a power supply 2. For example, the PPS signal input terminal of the domain controller is connected to the base of the NPN transistor via a resistor, the emitter of the NPN transistor is grounded, and the collector of the NPN transistor is connected to the power supply 2 and the output terminal via a resistor. The PPS signal 3 obtained at the domain controller input terminal, as shown in Figure 3b, can be used to provide the PPS signal 1 shown in Figure 3b to the system-on-chip (SoC) of the domain controller at the output terminal under the control of the internal circuitry based on the NPN transistor and the power supply 2. Therefore, the SoC can achieve time synchronization between the domain controller and the GNSS device based on the PPS signal 1.

[0084] Therefore, based on the circuit structure of the GNSS device shown in Figure 3a, the input terminal of the domain controller is required to provide power to the GNSS device.

[0085] Option (2):

[0086] As shown in Figure 4a, the internal circuit structure of the GNSS equipment includes components such as a power supply, an NPN transistor, and a MOSFET. The input terminal of the circuit is connected to the base of the NPN transistor through a resistor, the emitter of the NPN transistor is grounded, the collector of the NPN transistor is connected to the gate (G) of the MOSFET through a resistor, the power supply is connected to the source (S) of the MOSFET through a resistor, and the drain (D) of the MOSFET is connected to the output terminal of the circuit through a diode.

[0087] After other components (not shown in the figure) inside the GNSS device generate a PPS signal, this PPS signal is input through the input terminal of this line, passes through components such as NPN transistors and MOSFETs, and is output at the output terminal, providing it to the domain controller connected to the GNSS device. As shown in Figure 4a, this line can output both logic high and logic low levels. Specifically, for example, if the PPS signal input to the input terminal of the line shown in Figure 4a is a square wave signal as shown in Figures 3b and 4b, represented as PPS signal 1, after internal processing, the PPS signal output at the output terminal is PPS signal 4 as shown in Figure 4b. That is, when the PPS signal input to the input terminal of the line shown in Figure 4a is at a logic high level, the PPS signal output at the output terminal of the line shown in Figure 4a is at a logic high level; when the PPS signal input to the input terminal of the line shown in Figure 4a is at a logic low level, the PPS signal output at the output terminal of the line shown in Figure 4a is at a logic low level. Correspondingly, PPS signal 4 as shown in Figure 4b is obtained at the PPS signal input terminal of the domain controller.

[0088] In this scenario, the internal circuitry of the domain controller can be as shown in Figure 4c. No power supply is required at the PPS signal input. The PPS signal input of the domain controller is connected to the base of an NPN transistor via a resistor. The emitter of the NPN transistor is grounded, and the collector of the NPN transistor is connected to both the power supply and the output via a resistor. The PPS signal 4 obtained at the domain controller input, as shown in Figure 4b, can be used to provide the PPS signal 5 (as shown in Figure 4b) to the SoC at the output, under the control of the internal circuitry based on the NPN transistor and power supply. Therefore, the SoC can achieve time synchronization between the domain controller and the GNSS device based on the PPS signal 6.

[0089] Therefore, based on the circuit structure of the GNSS device shown in Figure 4a, there is no need for the internal circuitry of the domain controller to provide power to the GNSS device.

[0090] However, when a GNSS device using the wiring shown in Figure 3a is connected to a domain controller using the wiring shown in Figure 4c, if the GNSS device's input still receives the PPS signal 1 shown in Figure 3b, the domain controller's input will only receive the PPS signal 2 shown in Figure 3b from the GNSS device because there is no power supply to provide a high level. Under the control of the domain controller's wiring shown in Figure 4c, the SoC will continuously receive a high-level signal, and without a PPS signal sampling edge, the SoC cannot achieve time synchronization between the domain controller and the GNSS device.

[0091] Alternatively, when a GNSS device using the wiring shown in Figure 4a is connected to a domain controller using the wiring shown in Figure 3c, if the GNSS device still inputs PPS signal 1, the domain controller's input will provide a high level. Therefore, the PPS signal input from the GNSS device's output to the domain controller will be PPS signal 4 as shown in Figure 4b. The high level provided by the domain controller's input will pull the low level in PPS signal 4 high, causing the PPS signal actually input to the NPN transistor of the domain controller to always be at a logic high level. Under the control of the domain controller's wiring shown in Figure 3c, the SoC will always receive a low-level signal, and there will be no PPS signal sampling edge. Thus, the SoC cannot achieve time synchronization between the domain controller and the GNSS device.

[0092] Therefore, the GNSS equipment using the route shown in Figure 3a is incompatible with the domain controller using the route shown in Figure 4c, and the GNSS equipment using the route shown in Figure 4a is also incompatible with the domain controller using the route shown in Figure 3c. This compatibility issue affects the time synchronization of the domain controller and the time synchronization of the various sensors connected to the domain controller, thus affecting the fusion perception accuracy of the autonomous driving system.

[0093] As can be seen, in the current solution, when the PPS signal receiving device (e.g., a domain controller or industrial computer) interfaces with GNSS devices using different wiring structures, the receiving device needs to modify its wiring because the PPS signal output types of different GNSS devices are inconsistent. In other words, different circuit adaptations are required for different signal types. The module providing the PPS signal is called the input module, and the module receiving the PPS signal can be called the receiving module. Since there is no unified protocol for PPS signals, when different types of input modules are connected to the same receiving module, compatibility issues as mentioned above will arise. This necessitates separate adaptation for the receiving module, making platform-based design impossible and resulting in extremely high costs. Furthermore, the fixed wiring of the receiving module also significantly constrains the selection of GNSS devices, thus limiting the flexibility of the architecture design for autonomous driving systems (or intelligent assisted driving systems).

[0094] To address the aforementioned problems, this application provides a control method and communication device to reduce the design constraints of PPS signal receiving devices on external devices, or to improve the compatibility of PPS signal receiving devices and the flexibility of the corresponding EE architecture. The method and apparatus are based on the same technical concept. Since the principles by which the method and apparatus solve problems are similar, their implementations can be mutually referenced, and repeated details will not be elaborated upon. Furthermore, in the various embodiments of this application, unless otherwise specified or logically conflicting, the terminology and / or descriptions between the embodiments are consistent and can be mutually referenced. Technical features in different embodiments can be combined to form new embodiments based on their inherent logical relationships.

[0095] It should be noted that in the embodiments of this application, "at least one" refers to one or more, and "more than one" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can represent: a, b, c, a and b, a and c, b and c, or a and b and c, where a, b, and c can be single or multiple.

[0096] Furthermore, unless otherwise specified, the ordinal numbers such as "first" and "second" mentioned in the embodiments of this application are used to distinguish multiple objects and are not used to limit the priority or importance of multiple objects. For example, "first device" and "second device" are only used to distinguish different electronic devices, and do not indicate that the two devices have different priorities or importance. For example, in some embodiments, the method steps performed by the first device and the second device can be interchanged.

[0097] To make the objectives, technical solutions, and advantages of this application clearer, the application will now be described in further detail with reference to the accompanying drawings.

[0098] Figure 5 shows a schematic diagram of the architecture of a communication system applicable to an embodiment of this application.

[0099] As shown in Figure 5, the communication system may include a first device and a second device. The first device can be connected to the second device. The second device can act as a provider (or input) of the PPS signal, and the first device can act as a receiver (or receiving end) of the PPS signal. The second device can be used to provide the PPS signal to the first device. The first device can also be called a PPS signal receiving device, and the second device can also be called a PPS signal output device. Accordingly, the first device can receive the PPS signal from the second device and can synchronize its time with the second device based on the PPS signal from the second device. Optionally, the communication system may also include at least one third device. The first device and / or the second device can be connected to the at least one third device. The third device can use a similar method to achieve time synchronization with the first device and / or the second device. It should be understood that the dashed boxes in Figure 5 represent optional devices. The connections between different devices only indicate that they can communicate with each other and do not limit the communication technology used by either device.

[0100] For example, the first device in Figure 5 can be the domain controller in Figure 1, specifically the domain controller of the vehicle's autonomous driving system or intelligent driver assistance system. The second device in Figure 5 can be the GNSS device in Figure 1. The third device in Figure 5 can be a camera, lidar, or other sensor in Figure 1. It should be understood that each device in Figure 5 can be an independent device or a functional module integrated into a certain ECU of the vehicle; this application embodiment does not specifically limit this.

[0101] Taking GNSS as an example, as shown in Figure 6a, the GNSS module can be integrated into device A in the vehicle. Device A can be, for example, the vehicle's automated driving integration platform (ADIP). Device A may also include a microcontroller unit (MCU) and an inertial measurement unit (IMU). After the GNSS module receives navigation satellite signals through its antenna, the MCU can calculate the clock difference between the high-precision atomic clock in the navigation satellite and the local system time. It then sends a time synchronization message to the domain controller via the CAN bus and sends a PPS signal to the domain controller to achieve time synchronization between the domain controller and the GNSS module. Furthermore, the domain controller can synchronize its time with the in-vehicle communication terminal (e.g., the vehicle's Tbox) via Ethernet, enabling the in-vehicle communication terminal to implement its own high-precision positioning algorithm.

[0102] In another example, as shown in Figure 6b, the GNSS module can be integrated into device B, which can be, for example, a vehicle-mounted communication terminal. The IMU can be integrated into the domain controller. After receiving navigation satellite signals through the antenna, the GNSS module can calculate the clock difference between the high-precision atomic clock in the navigation satellite and the local system time, and send a time synchronization message to the domain controller via Ethernet, as well as a PPS signal to the domain controller, to achieve time synchronization between the domain controller and the GNSS module.

[0103] In another example, as shown in Figure 6c, the GNSS module can be integrated into either device A or device B. Device A can be implemented as shown in Figure 6a, and device B can be implemented as shown in Figure 6b. Both devices A and B have PPS outputs from their GNSS modules. In the vehicle cabling topology design, the PPS signals output by the GNSS modules of both devices A and B can be connected to the domain controller. When either device A or device B malfunctions, for example, when the domain controller's SoC cannot access the PPS signal from device A, it can switch to accessing the PPS signal from device B, forming a redundant but more reliable EE architecture, without affecting the time synchronization function. Alternatively, if there is a supply problem with device A, without changing the domain controller, a software upgrade can be performed to enable the domain controller to support the control method of this embodiment, achieving a smooth switch and ensuring compatibility between new and old vehicle models.

[0104] It should be understood that Figures 6a-6c are merely illustrative examples of how GNSS devices and domain controllers can be implemented on a vehicle and are not intended to limit the scope of the implementation. In other embodiments, the GNSS device may be implemented as a functional module integrated into other ECUs, and the domain controller may include modules other than the IMU. Further details will not be provided here.

[0105] In this embodiment, the first device serves as a PPS signal receiving device. In order to enable the first device to be flexibly adapted to different types of GNSS devices, one implementation is to set at least one line in the first device. The control module of the first device enables the target line in the at least one line as needed, so that after processing the first PPS signal from the second device through the target line, the second PPS signal output based on the target line is synchronized with the second device in time.

[0106] Taking the domain controller described above as an example, the control module of the first device can be implemented as a System-on-a-Chip (SoC) within the first device. As shown in Figure 7a, the SoC may include modules for implementing computing functions, such as an MCU or a CPU. When implementing the control method of this embodiment, the MCU or CPU can obtain first information indicating the output type of the PPS signal from the second device. The MCU or CPU can enable a target line in at least one line of the first device (schematically represented by a double-arrow solid line in Figure 7a) according to the first information, so as to process the first PPS signal from the second device through the target line. The MCU or CPU can synchronize time with the second device based on the second PPS signal output from the target line.

[0107] For example, taking the circuit structure shown in Figure 3a as an example, the output type of the PPS signal of this circuit structure can be represented as the first type, that is, the PPS control line in the second device has a low input logic level and a high output impedance state; or a high input logic level and a low output logic level. Or, for example, taking the circuit structure shown in Figure 4a as an example, the output type of the PPS signal of this circuit structure can be represented as the second type, that is, the PPS control line in the second device has a low input logic level and a low output logic level; or a high input logic level and a high output logic level. Regardless of which control circuit structure the second device adopts, in this embodiment, the first device can enable at least one target line in its own circuit and process the first PPS signal from the second device through the target line to obtain a second PPS signal. The second PPS signal can be used for time synchronization between the first device and the second device. Thus, by enabling the target line, the first device can be adapted to the second device, which can reduce the design constraints of the PPS signal receiving device on external devices, or improve the compatibility of the PPS signal receiving device and the flexibility of the corresponding EE architecture.

[0108] In specific implementation, at least one line of the first device itself can be an independent line or a line with an associated relationship. The target line can be an independent line or one or more lines with an associated relationship, so that the first device can be adapted to the second device through the target line, facilitating time synchronization between the first and second devices. This application does not specifically limit this aspect. When the first device enables the target line among the at least one line, it can, for example, enable the target line among the at least one line based on first information. For example, at least one line of the first device itself can be a line with an associated relationship, and the first information can be associated with the output type of the PPS signal of the second device. The first device can enable the target line among the at least one line according to the output type of the PPS signal of the second device. Or, for example, at least one line of the first device itself can be an independent line, and at least one pin of the connector of the first device is respectively connected to the at least one line. The first information can be associated with the mapping relationship between the second device, the at least one pin, and the at least one line. The first device can enable the line connected to the pin of the second device as the target line according to the pin connected to the second device. This will be described in conjunction with examples below, and will not be elaborated further here.

[0109] In one optional embodiment, the first device may further include a storage medium, which may include pre-stored first information. For example, as shown in FIG7a, the storage medium may be an external storage medium associated with the SoC of the first device. In other embodiments, the SoC in FIG7a may have an internal storage medium, and the MCU or CPU on the SoC may act as the control module of the first device, obtaining the first information from the storage medium. The first information may be obtained when the first device is powered on. Specifically, for example, when the first device is powered on, the control module of the first device may obtain the first information from the storage medium and enable a target line in at least one of the lines based on the first information to achieve line enabling and a time synchronization mechanism based on the target line. In other embodiments, the first information may be obtained, for example, when the first device and the second device are first connected and powered on. The control module of the first device may obtain the first information from the storage medium and enable a target line in at least one of the lines based on the first information to achieve line enabling and a time synchronization mechanism based on the target line. In another optional embodiment, when the first device is powered on, the control module of the first device may also obtain the first information from the external storage medium of the first device or a cloud server to enable the target line based on the first information. This application does not specifically limit the timing or method of acquiring the first information.

[0110] For example, taking the deployment of different types of GNSS devices (such as those shown in Figure 6a or Figure 6b) in a vehicle as an example, the first device can be implemented as the domain controller of the vehicle's autonomous driving system or intelligent driver assistance system, and the first information can be in the form of a software configuration word (identifier). When the domain controller is powered on, the domain controller's control module can obtain the first information by loading the operating system (OS), and analyze the output type of the PPS signal of the second device based on the first information, or analyze the connector pins to which the second device is connected based on the first information.

[0111] The first information may include, for example, the device identifier of the second device and a software configuration word. The device identifier, for example, is represented as IDn, where n represents the equipment serial number (ESN) of the second device, used to uniquely identify the second device. The software configuration word can be represented in binary, for example, 01 represents the first type, and 10 represents the second type. When the output type of the PPS signal of the second device is the first type, the PPS control circuit within the second device can be as shown in Figure 3a, used for input logic low level and output high impedance; or input logic high level and output logic low level. When the output type of the PPS signal of the second device is the second type, the PPS control circuit within the second device can be as shown in Figure 4a, used for input logic low level and output logic low level; or input logic high level and output logic high level.

[0112] In a specific implementation, as shown in Figure 7b, the first device may include a first interface (e.g., a synchronization signal interface, which can be represented as TSYNC_N), a second interface (e.g., a development environment interface, which can be represented as DEVM_N), and a system driver (e.g., which can be represented as SOC_SYSDRV). After the first device is powered on, configuration information (e.g., first information) can be read and initialized through the first interface to enable the target line in at least one of the lines.

[0113] For example, if at least one line of the first device is an associated line, and the first information is associated with the output type of the PPS signal of the second device, then for the first type indicated in the configuration information, i.e., the output type of the PPS signal of the second device connected to the first device is the first type, the first interface can send signal 1 to the second interface to enable the logic control line (e.g., the second line) of the PPS signal through the second interface. Furthermore, the first interface can send signal 2 to the system driver (e.g., MCU or CPU) to indicate cancellation of polarity reversal (i.e., cancellation of the sampling edge toggling of the PPS signal). Subsequently, during time synchronization between the first and second devices, after receiving the first PPS signal from the second device, the first device processes the first PPS signal through the target line (including the first line and the second line) to obtain the second PPS signal. The MCU or CPU of the first device can act as a control module, performing edge sampling in the second PPS signal, and based on the sampling edge of the second PPS signal and the UTC information, achieving time synchronization between the first and second devices. For example, if the output type of the PPS signal of the second device is the first type, the MCU or CPU of the first device keeps the sampling edge of the second PPS signal unchanged, and realizes time synchronization between the first device and the second device based on the sampling edge of the second PPS signal and the UTC information.

[0114] Similarly, for the second type indicated in the configuration information, i.e., the output type of the PPS signal of the second device connected to the first device is the second type, then there is no need for the first interface to send signal 1 to the second interface, i.e., there is no need to enable the second line. In this case, there is also no need for the first interface to send signal 2 to the system driver (e.g., MCU or CPU), i.e., there is no need to cancel the polarity reversal. Furthermore, when synchronizing time between the first device and the second device, after receiving the first PPS signal from the second device, the first device processes the first PPS signal through the target line (including the first line) to obtain the second PPS signal. The MCU or CPU of the first device can act as a control module, performing edge sampling in the second PPS signal, and realizing time synchronization between the first device and the second device based on the sampling edge of the second PPS signal and the UTC information. For example, in the case where the output type of the PPS signal of the second device is the second type, the MCU or CPU of the first device flips the sampling edge of the second PPS signal, and realizes time synchronization between the first device and the second device based on the flipped sampling edge and the UTC information.

[0115] It should be understood that Figure 7b is merely an example illustrating the implementation of the first information and the output type of the PPS signal of the second device, and does not constitute any limitation. In other embodiments, the PPS control circuit within the second device may adopt a circuit structure other than that shown in Figure 3a or Figure 3b, and the output type of the PPS signal of the second device may also include, for example, a third type, a fourth type, etc. The third type may be, for example, a PPS control circuit within the second device with a low input logic level and a high output logic level; or a PPS control circuit with a high input logic level and a high output logic level. The fourth type may be, for example, a PPS control circuit within the second device with a low input logic level and a high output logic level; or a PPS control circuit with a high input logic level and a low output logic level. Accordingly, the first device can obtain the first information to know the output type of the PPS signal of the second device, or to know the connector pins to which the second device is connected, so as to enable at least one target line in the circuit of the second device, allowing the first device to flexibly adapt to different types of second devices.

[0116] To facilitate understanding, the following explanation will be provided in conjunction with a flowchart and various examples.

[0117] Figure 8 shows a flowchart of the control method according to an embodiment of this application.

[0118] As shown in Figure 8, the method may include the following steps:

[0119] S810: The first device enables the target line in at least one of its lines based on the first information.

[0120] In this embodiment of the application, the first device may include a control module and at least one line. When implementing S810, the control module may enable the target line in at least one line of the first device according to the first information.

[0121] In one example, the at least one line can be a line with an association, and the first information can be associated with the output type of the PPS signal of the second device.

[0122] As shown in Figure 9a, at least one line of the first device may include line 1 and line 2. Line 1 can be represented as the first line, and line 2 can be represented as the second line. These distinctions will not be elaborated further below. The relationship between these at least one line can be, for example, that the output port of line 1 is connected to the control module of the first device, the enable pin of the control module is connected to the input port of line 2, and the output port of line 2 is connected to the input port of line 1. When implementing S810, the control module can, based on the first information, provide an enable signal or a disable signal to line 2 using a pin to control the state of line 2, thereby controlling whether the target line includes line 2.

[0123] For example, if the output type of the PPS signal of the second device is the first type described above, when implementing S810, the control module can send an enable signal (e.g., a high-level signal) to line 2 through the enable pin according to the first information, so that the output port of line 2 is connected to the input port of line 1. In this case, line 2 is in the enabled state, and the target lines include line 1 and line 2.

[0124] Alternatively, for example, if the output type of the PPS signal of the second device is the second type described above, when implementing S810, the control module can send a de-enabled signal (e.g., a low-level signal or no signal) to line 2 through the enable pin according to the first information, so that the output port of line 2 is disconnected from the input port of line 1. In this case, line 2 is in a de-enabled state, and the target line includes line 1.

[0125] It should be understood that the dashed line in Figure 9a represents line 2 as an optional line and does not constitute any limitation on at least one line for the first device. In other embodiments, the target line may also be enabled in other ways, which will not be elaborated here.

[0126] In another example, at least one line of the first device can be an independent line. The first device may include, for example, a connector that may include at least one pin connected to at least one line of the first device, the output port of which is connected to the control module of the first device. First information may be associated with a mapping relationship between the second device, the at least one pin, and the at least one line.

[0127] As shown in Figure 9b, the first device may include at least one line, which can be line 3 and line 4. The first device may also include a connector connected to the second device. The connector includes at least one pin, for example, represented as pin 1 and pin 2. This at least one pin is connected to the input port of at least one line of the first device, and the output port of the at least one line is connected to the control module. For example, pin 1 is connected to the input port of line 3, and pin 2 is connected to the input port of line 4. When implementing S820, the control module can determine the connector pin to which the second device is connected based on the first information, and connect that pin to the line as the target line, thus identifying the target line among the at least one line.

[0128] For example, if the first information indicates that the second device is connected to pin 1 in Figure 9b, designated as the first pin, then when implementing S810, the control module can use the third line (e.g., line 3) of the at least one line to which the first pin is connected as the target line. Or, for example, if the first information indicates that the second device is connected to pin 2 in Figure 9b, designated as the second pin, then when implementing S810, the control module can use the fourth line (e.g., line 4) of the at least one line to which the second pin is connected as the target line.

[0129] It should be understood that the dashed lines in Figure 9b represent optional connector pins and optional lines, and do not constitute any limitation. In other embodiments, the number of connector pins and the number of lines can be greater than 2, which will not be elaborated here.

[0130] S820: The first device processes the first PPS signal from the second device through the target line to obtain the second PPS signal.

[0131] In this embodiment, the second PPS signal is used for time synchronization between the first device and the second device. For example, after S820, the following steps may also be included:

[0132] S830 (Optional Step): The first device achieves time synchronization between the first device and the second device based on the second PPS signal.

[0133] For example, prior to implementing S830, the first device could receive second information from the second device, which included Coordinated Universal Time (UTC) information. As an example, the second information could be carried in a time synchronization message from the second device. When implementing S830, the first device could perform edge sampling on the second PPS signal and, based on the sampled edges of the second PPS signal and the UTC information, achieve time synchronization between the first device and the second device.

[0134] For example, based on the sampling edge of the second PPS signal, the control module resets its internal system time (to milliseconds or less) to zero and begins calculating millisecond time. The control module extracts the UTC time (hour, minute, second, year, month, day) from the second information. The time used by the control module to parse the UTC time from the sampling edge of the second PPS signal is represented as tx. The tx time is added to the UTC whole-second time and synchronized to the control module, thus completing one time synchronization. The system time is precisely calibrated every second to ensure accuracy.

[0135] Therefore, by using the above method, at least one line is set up inside the first device, and the control module enables the target line in the at least one line to process the first PPS signal from the second device according to the output type of the PPS signal from the second device. This allows the first device to flexibly adapt to different types of GNSS devices, be compatible with devices with multiple PPS output types, reduce the constraints of the first device on peripheral devices, and standardize the design of the first device, greatly saving costs. When deployed in a vehicle, this method allows the first device to accommodate both new and old vehicle models, improving the compatibility of the first device and the flexibility of the corresponding EE architecture.

[0136] In this embodiment, the target line may include different line branches under different circumstances to process the first PPS signals from different second devices to obtain a second PPS signal that can be used for time synchronization. For ease of understanding, examples are given below with reference to the line structures shown in Figure 9a or Figure 9b.

[0137] Example 1:

[0138] Taking at least one line of the first device as an example, which adopts the structure shown in Figure 9a, the internal circuit structure of the first device can be specifically shown in Figure 10a. For example, line 2 may include an NPN transistor and a PNP transistor. The input port of line 2 is connected to the base of the NPN transistor through a resistor, the emitter of the NPN transistor is grounded, the collector of the NPN transistor is connected to the base of the PNP transistor through a resistor, the emitter of the PNP transistor is connected to power supply 1 (e.g., represented as the first power supply), and the collector of the PNP transistor is connected to the output terminal of line 2 and the input port of line 1 through a diode and a resistor. Line 2 may also include capacitors, resistors, and other components connected to the NPN transistor or the PNP transistor respectively, as shown in Figure 10a. Line 1 may include an NPN transistor. The input port of Line 1 is connected to the base of the NPN transistor via a resistor. The emitter of the NPN transistor is grounded. The collector of the NPN transistor is connected to a second power supply (e.g., power supply 2) and the output port of Line 1 via a resistor, as well as the SoC of the first device.

[0139] The SoC can implement S810 as the aforementioned control module. For example, if the output type of the PPS signal of the second device is the first type mentioned above, that is, the PPS control line in the second device has a low input logic level and a high output impedance state; or a high input logic level and a low output logic level. When implementing S810, based on the internal circuit structure shown in FIG10a, the control module (SoC) can send an enable signal to the input port (POWER_EN) of line 2 through the enable pin to enable line 2. This enable signal is, for example, a high-level signal. When line 2 is in the enabled state, the output port of line 2 is connected to the input port of line 1, and the target lines include line 1 and line 2.

[0140] When implementing S820, if the input port of line 1 receives the first PPS signal from the second device, since line 2 is enabled, power supply 1 in line 2 can provide a high level (e.g., 12V) to provide a high-level signal to the input port of line 1 when the second device outputs a high-impedance state. Therefore, under the control of line 2, the PPS signal actually obtained by line 1 is a square wave signal. As shown in Figure 10b, in the second device, if a high level is input at the input terminal, a low level is output at the output terminal; if a low level is input at the input terminal, a high-impedance state is output at the output terminal. It should be understood that the example of the "high-impedance state" PPS signal in the figure is only an example, and in reality, there is "no signal". Since the output port of the second device is connected to the input port of line 1 of the first device, and line 2 is enabled, it can provide a high level based on power supply 1 under the control of line 2, so that when the output terminal of the second device outputs a high-impedance state, a high-level signal can be obtained at the input port of line 1. Therefore, the PPS signal actually obtained by the input port of line 1 is a square wave signal, i.e., the first PPS signal. In the first device, under the control of line 2 and based on the line structure of line 1, line 1 can be configured to: input logic low level, output logic high level; or input logic high level, output logic low level, i.e., the second PPS signal. The second PPS signal is transmitted to the SoC through the output port of line 1.

[0141] The SoC can implement S830 as the aforementioned control module to achieve time synchronization between the first device and the second device. For example, the control module can perform edge sampling on the second PPS signal received from the output port of the first line, and keep the sampling edge of the second PPS signal unchanged. Based on the sampling edge of the second PPS signal, the UTC information is corrected to achieve time synchronization between the first device and the second device.

[0142] Example 2:

[0143] Taking the example of at least one line of the first device adopting the structure shown in Figure 9a, the internal circuit structure of the first device can be specifically shown in Figure 10a.

[0144] The SoC can implement S810 as the aforementioned control module. For example, if the output type of the PPS signal of the second device is the second type mentioned above, that is, the PPS control line in the second device has a low input logic level and a low output logic level, or a high input logic level and a high output logic level. When implementing S810, based on the internal circuit structure shown in Figure 10a, the control module (SoC) can send a de-enabled signal to the input port (POWER_EN) of line 2 through the enable pin. At this time, when line 2 is in the de-enabled state, the output port of line 2 is disconnected from the input port of line 1, and the target line includes line 1.

[0145] When implementing S820, if the input port of line 1 receives the first PPS signal from the second device, since line 2 is in a disabled state, power supply 1 in line 2 will not provide a high level (e.g., 12V). Therefore, the actual PPS signal obtained by line 1 is consistent with the waveform of the PPS signal output by the second device. As shown in Figure 10c, in the second device, if the input terminal is high, the output terminal is high; if the input terminal is low, the output terminal is low. Since the output port of the second device is connected to the input port of line 1 of the first device, and the first device does not provide power to the second device, the output PPS signal in the second device is also the input port PPS signal of line 1, i.e., the first PPS signal. In the first device, based on the line structure of line 1, line 1 can have: input logic low level, output logic high level; input logic high level, output logic low level, i.e., the second PPS signal. The second PPS signal is transmitted to the SoC through the output port of line 1.

[0146] The SoC can implement S830 as the aforementioned control module to achieve time synchronization between the first device and the second device. For example, the control module can perform edge sampling on the second PPS signal received from the output port of the first line, and after flipping the sampled edge of the second PPS signal, achieve time synchronization between the first device and the second device based on the flipped sampled edge and the UTC information.

[0147] Example 3:

[0148] Taking the structure shown in Figure 9b as an example, the internal circuit structure of the first device can be specifically shown in Figure 11a. For example, pin 1 of the connector is connected to the input port of line 3, and pin 2 of the connector is connected to the input port of line 4.

[0149] Line 3 includes power supply 1, power supply 2, and an NPN transistor. Power supply 1 is connected to the input port of line 3 via a diode and a resistor. The input port of line 3 is connected to the base of the NPN transistor via a resistor. The emitter of the NPN transistor is grounded. The collector of the NPN transistor is connected to the output port of line 3 via a resistor and to power supply 2 via a resistor and a diode. The output port of line 3 is connected to the SoC. Alternatively, line 4 includes power supply 3 and an NPN transistor. The input port of line 4 is connected to the base of the NPN transistor via a resistor. The emitter of the NPN transistor is grounded. The collector of the NPN transistor is connected to the output port of line 4 via a resistor and to power supply 3 via a resistor and a diode. The output port of line 4 is connected to the SoC.

[0150] The SoC can implement S810 as the aforementioned control module. For example, if the output type of the PPS signal of the second device is the aforementioned first type, that is, the PPS control line in the second device has a low input logic level and a high output impedance state; or a high input logic level and a low output logic level, and the mapping relationship contained in the first information indicates that the second device is connected to the connector of the first device at pin 1, and pin 1 is connected to line 3, then when implementing S810, based on the internal circuit structure shown in FIG11a, the control module (SoC) can enable pin 1 according to the first information and take the line 3 connected to pin 1 as the target line.

[0151] When implementing S820, if the input port of line 3 receives the first PPS signal from the second device, since power supply 1 in line 3 can provide a high level (e.g., 12V), a high-level signal can be provided to the input port of line 3 when the second device outputs a high-impedance state. Therefore, the first PPS signal actually obtained at the input port of line 3 is a square wave signal. As shown in Figure 11b, in the second device, if a high level is input at the input terminal, a low level is output at the output terminal; if a low level is input at the input terminal, a high-impedance state is output at the output terminal. It should be understood that the example of the "high-impedance state" PPS signal in the figure is only an example, and in reality, there is "no signal". Since the output port of the second device is connected to the input port of line 3 of the first device through pin 1, and line 3 of the first device can provide a high level based on power supply 1, a high-level signal can be obtained at the input port of line 3 when the output terminal of the second device outputs a high-impedance state. Therefore, the PPS signal actually obtained at the input port of line 3 is a square wave signal, i.e., the first PPS signal. In the first device, based on the circuit structure of line 3, line 3 can have: input logic low level, output logic high level; or input logic high level, output logic low level, i.e., the second PPS signal. The second PPS signal is transmitted to the SoC through the output port of line 3.

[0152] The SoC can implement S830 as the aforementioned control module to achieve time synchronization between the first device and the second device. For example, the control module can perform edge sampling on the second PPS signal received from the output port of line 3, and keep the sampling edge of the second PPS signal unchanged. Based on the sampling edge of the second PPS signal and the UTC information, time synchronization between the first device and the second device can be achieved.

[0153] Example 4:

[0154] Taking the example of at least one line of the first device adopting the structure shown in Figure 9b, the internal circuit structure of the first device can be specifically shown in Figure 11a.

[0155] The SoC can implement S810 as the aforementioned control module. For example, if the output type of the PPS signal of the second device is the aforementioned second type, that is, the PPS control line in the second device has a low input logic level and a low output logic level, or a high input logic level and a high output logic level, and the mapping relationship contained in the first information indicates that the second device is connected to the connector of the first device at pin 2, and pin 2 is connected to line 4, then when implementing S810, based on the internal circuit structure shown in FIG11a, the control module (SoC) can enable pin 2 according to the first information and take the line 4 to which pin 2 is connected as the target line.

[0156] When implementing S820, if the input port of line 4 receives the first PPS signal from the second device, since the input port of line 4 will not provide a high level, the waveform of the PPS signal output by the second device will be consistent with the waveform of the PPS signal obtained at the input port of line 4. As shown in Figure 11c, in the second device, if the input terminal is high, the output terminal is high; if the input terminal is low, the output terminal is low. Since the output port of the second device is connected to the input port of line 4 of the first device through pin 2, and the input port of line 4 of the first device does not provide power to the second device, the PPS signal at the output terminal of the second device is also the PPS signal at the input port of line 1, i.e., the first PPS signal. In the first device, based on the line structure of line 4, line 4 can have: input logic low level, output logic high level; input logic high level, output logic low level, i.e., the second PPS signal. The second PPS signal is transmitted to the SoC through the output port of line 4.

[0157] The SoC can implement S830 as the aforementioned control module to achieve time synchronization between the first device and the second device. For example, the control module can perform edge sampling on the second PPS signal received from the output port of line 4, flip the sampled edge of the second PPS signal, and achieve time synchronization between the first device and the second device based on the flipped sampled edge and the UTC information.

[0158] Therefore, through the control methods of the different examples described above, the first device, as a PPS signal receiving device, can enable the target line for the second device, so that the first device can flexibly adapt to different second devices, thereby reducing the design constraints of the PPS signal receiving device on external devices, or improving the compatibility of the PPS signal receiving device and the flexibility of the corresponding EE architecture.

[0159] This application also provides a control device for executing the method executed by the first device or the control module of the first device or the target line of the first device in the above method embodiments. The relevant features can be found in the above method embodiments, and will not be repeated here.

[0160] As shown in Figure 12, the control device 1200 may include: a control module 1201, configured to enable a target line in at least one line of the first device according to first information, wherein the first device is connected to the second device; and a processing module 1202, configured to process a first PPS signal from the second device through the target line to obtain a second PPS signal, wherein the second PPS signal is used for time synchronization between the first device and the second device.

[0161] For specific implementation details, please refer to the method steps implemented by the first device, the control module of the first device, or the target line of the first device in the above method embodiments, which will not be repeated here.

[0162] It should be understood that the division of units in the above device is only a logical functional division. In actual implementation, they can be fully or partially integrated into a single physical entity, or they can be physically separated. Furthermore, the units in the device can be implemented by a processor calling software; for example, the device includes a processor connected to a memory containing instructions. The processor calls the instructions stored in the memory to implement any of the above methods or to implement the functions of each unit in the device. The processor can be, for example, a general-purpose processor, such as a Central Processing Unit (CPU) or a microprocessor, and the memory can be internal or external to the device. Alternatively, the units in the device can be implemented as hardware circuits. The functionality of some or all units can be achieved through the design of these hardware circuits, which can be understood as one or more processors. For example, in one implementation, the hardware circuit is an application-specific integrated circuit (ASIC). The functionality of some or all of the above units is achieved through the design of the logical relationships between the components within the circuit. In another implementation, the hardware circuit can be implemented using a programmable logic device (PLD). Taking a field-programmable gate array (FPGA) as an example, it can include a large number of logic gates. The connection relationships between the logic gates are configured through a configuration file, thereby achieving the functionality of some or all of the above units. All units of the above device can be implemented entirely through processor-invoked software, entirely through hardware circuits, or partially through processor-invoked software with the remaining parts implemented through hardware circuits.

[0163] In this application embodiment, the processor is a circuit with signal processing capabilities. In one implementation, the processor can be a circuit with instruction reading and execution capabilities, such as a CPU, microprocessor, graphics processing unit (GPU) (which can be understood as a type of microprocessor), or digital signal processor (DSP). In another implementation, the processor can implement certain functions through the logical relationships of hardware circuits. These logical relationships of hardware circuits are fixed or reconfigurable. For example, the processor is a hardware circuit implemented as an ASIC or PLD, such as an FPGA. In a reconfigurable hardware circuit, the process of the processor loading a configuration document and configuring the hardware circuit can be understood as the process of the processor loading instructions to implement the functions of some or all of the above units. Furthermore, it can also be a hardware circuit designed for artificial intelligence, which can be understood as an ASIC, such as a Neural Network Processing Unit (NPU), Tensor Processing Unit (TPU), or Deep Learning Processing Unit (DPU).

[0164] As can be seen, each unit in the above device can be one or more processors (or processing circuits) configured to implement the above methods, such as: CPU, GPU, NPU, TPU, DPU, microprocessor, DSP, ASIC, FPGA, or a combination of at least two of these processor forms.

[0165] Furthermore, the units in the above devices can be integrated in whole or in part, or they can be implemented independently. In one implementation, these units are integrated together as a system-on-a-chip (SOC). The SOC may include at least one processor for implementing any of the above methods or implementing the functions of the units in the device. The at least one processor may be of different types, such as CPU and FPGA, CPU and artificial intelligence processor, CPU and GPU, etc.

[0166] In a simplified embodiment, those skilled in the art will realize that the communication devices in the above embodiments can all take the form shown in FIG13.

[0167] The device 1300 shown in Figure 13 includes at least one processor 1310 and a communication interface 1330. In an alternative design, a memory 1320 may also be included.

[0168] The specific connection medium between the processor 1310 and the memory 1320 described above is not limited in the embodiments of this application.

[0169] In the device shown in Figure 13, when the processor 1310 communicates with other devices, it can transmit data through the communication interface 1330.

[0170] When the communication device adopts the form shown in FIG13, the processor 1310 in FIG13 can call the computer execution instructions stored in the memory 1320, so that the device 1300 can execute any of the above method embodiments.

[0171] This application also relates to a chip system including a processor for calling a computer program or computer instructions stored in a memory to cause the processor to execute the methods of any of the above embodiments.

[0172] In one possible implementation, the processor can be coupled to the memory via an interface.

[0173] In one possible implementation, the chip system may also directly include a memory in which computer programs or computer instructions are stored.

[0174] For example, the memory can be volatile memory or non-volatile memory, or may include both. The non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. The volatile memory can be random access memory (RAM), which serves as an external cache. By way of example, but not limitation, many forms of RAM are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous linked dynamic random access memory (SLDRAM), and direct rambus RAM (DR RAM).

[0175] This application also relates to a processor for calling a computer program or computer instructions stored in a memory to cause the processor to execute the methods described in any of the above embodiments.

[0176] For example, in the embodiments of this application, the processor is an integrated circuit chip with signal processing capabilities. For instance, the processor can be an FPGA, a general-purpose processor, a DSP, an ASIC, or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, a system-on-chip (SoC), a CPU, a network processor (NP), a microcontroller unit (MCU), a PLD, or other integrated chips, capable of implementing or executing the methods, steps, and logic block diagrams disclosed in the embodiments of this application. A general-purpose processor can be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of this application can be directly embodied in the execution of a hardware decoding processor, or executed by a combination of hardware and software modules in the decoding processor. The software modules can reside in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. This storage medium is located in memory; the processor reads information from the memory and, in conjunction with its hardware, completes the steps of the above methods.

[0177] It should be understood that embodiments of this application may be provided as methods, systems, or computer program products.

[0178] In one possible implementation, embodiments of this application provide a computer-readable storage medium storing program code that, when executed on a computer, causes the computer to perform the method embodiments described above.

[0179] In one possible implementation, this application provides a computer program product that, when run on a computer, causes the computer to execute the above-described method embodiments.

[0180] Therefore, this application may take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0181] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means that implement the functions specified in one or more flowcharts and / or one or more block diagrams.

[0182] These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process, such that the instructions, which execute on the computer or other programmable apparatus, provide steps for implementing the functions specified in one or more flowcharts and / or one or more block diagrams.

[0183] Obviously, those skilled in the art can make various modifications and variations to the embodiments of this application without departing from the scope of the embodiments of this application. Therefore, if these modifications and variations to the embodiments of this application fall within the scope of the claims of this application and their equivalents, this application also intends to include these modifications and variations. In the various embodiments of this application, unless otherwise specified or logically conflicting, the terminology and / or descriptions between the various embodiments are consistent and can be mutually referenced. Technical features in different embodiments can be combined to form new embodiments based on their inherent logical relationships.

Claims

1. A control method, characterized in that, Applied to a first device, the first device being connected to a second device, the method includes: Based on the first information, enable the target line in at least one of the lines of the first device; The first second pulse (PPS) signal from the second device is processed through the target line to obtain a second PPS signal, which is used for time synchronization between the first device and the second device.

2. The method according to claim 1, characterized in that, The first information is associated with the output type of the PPS signal of the second device.

3. The method according to claim 2, characterized in that, The at least one line includes a first line and a second line, wherein the output port of the second line is connected to the input port of the first line, wherein... If the output type of the PPS signal of the second device is the first type, the target line includes the first line and the second line, the second line is in an enabled state, and the output port of the second line is connected to the input port of the first line; If the output type of the PPS signal of the second device is the second type, the target line includes the first line, the second line is in a disabled state, and the output port of the second line is disconnected from the input port of the first line.

4. The method according to claim 3, characterized in that, The first device further includes a control module, wherein the enable pin of the control module is connected to the input port of the second line and is used to provide an enable signal or a disable signal to the second line; the output port of the first line is connected to the control module, and the control module is used to realize time synchronization between the first device and the second device based on the second PPS signal.

5. The method according to claim 3, characterized in that, If the output type of the PPS signal of the second device is the first type, enabling the target line in at least one line of the first device according to the first information includes: Based on the first information, the enable signal is input to the input port of the second line through the enable pin, so that the output port of the second line is connected to the input port of the first line; If the output type of the PPS signal of the second device is the second type, enabling the target line in at least one line of the first device according to the first information includes: Based on the first information, the de-enable signal is input to the input port of the second line through the enable pin, so that the output port of the second line is disconnected from the input port of the first line.

6. The method according to any one of claims 3-5, characterized in that, The second line includes a first power supply, which provides a high-level signal to the input port of the first line when the second line is enabled.

7. The method according to claim 6, characterized in that, The second circuit also includes an NPN transistor and a PNP transistor. The input port of the second circuit is connected to the base of the NPN transistor, the emitter of the NPN transistor is grounded, the collector of the NPN transistor is connected to the base of the PNP transistor, the emitter of the PNP transistor is connected to the first power supply, and the collector of the PNP transistor is connected to the input port of the first circuit.

8. The method according to claim 1, characterized in that, The first device further includes a connector connected to the second device, wherein the connector includes at least one pin, the at least one pin being connected to the at least one line, and the first information is associated with a mapping relationship between the second device, the at least one pin, and the at least one line.

9. The method according to claim 8, characterized in that, The step of enabling a target line in at least one line of the first device according to the first information includes: If the first information indicates that the second device is connected to the first pin of the at least one pin, then the third line of the at least one line to which the first pin is connected is taken as the target line; or... If the first information indicates that the second device is connected to the second pin of the at least one pin, the fourth line of the at least one line to which the second pin is connected shall be the target line.

10. The method according to claim 9, characterized in that, When the PPS signal output type of the second device is the first type, the second device is connected to the first pin; or, when the PPS signal output type of the second device is the second type, the second device is connected to the second pin.

11. The method according to any one of claims 3-7 and 10, characterized in that, The first type includes: a PPS control line in the second device with a low input logic level and a high output impedance state; a high input logic level and a low output logic level; or... The second type includes: input logic low level and output logic low level in the PPS control line within the second device; input logic high level and output logic high level.

12. The method according to claim 11, characterized in that, The method further includes: Receive second information from the second device, the second information including Coordinated Universal Time (UTC) information; Edge sampling is performed on the second PPS signal, and time synchronization between the first device and the second device is achieved based on the sampling edge of the second PPS signal and the UTC information.

13. The method according to claim 12, characterized in that, If the PPS signal output type of the second device is the first type, the step of achieving time synchronization between the first device and the second device based on the sampling edge of the second PPS signal and the UTC information includes: Keeping the sampling edge of the second PPS signal unchanged, time synchronization between the first device and the second device is achieved based on the sampling edge of the second PPS signal and the UTC information; If the PPS signal output type of the second device is the second type, the step of achieving time synchronization between the first device and the second device based on the sampling edge of the second PPS signal and the UTC information includes: After flipping the sampling edge of the second PPS signal, time synchronization between the first device and the second device is achieved based on the flipped sampling edge and the UTC information.

14. The method according to any one of claims 1-13, characterized in that, The method further includes: When the first device is powered on, the first information is retrieved from the storage medium.

15. A control device, characterized in that, include: A control module is configured to enable a target line in at least one line of a first device based on first information, wherein the first device is connected to a second device. The processing module is used to process the first PPS signal from the second device through the target line to obtain a second PPS signal, which is used for time synchronization between the first device and the second device.

16. A communication device, characterized in that, The communication device includes a control module and at least one line, and is connected to a second device. The control module is used to enable a target line in the at least one line according to first information. The target line is used to process the first PPS signal from the second device to obtain a second PPS signal, which is used for time synchronization between the communication device and the second device.

17. A communication device, characterized in that, It includes at least one processor and an interface circuit, the interface circuit being used to provide data or code instructions to the at least one processor, the at least one processor being used to implement the method as described in any one of claims 1-14 through logic circuits or executing code instructions.

18. A computer-readable storage medium, characterized in that, The computer-readable medium stores program code that, when run on a computer, causes the computer to perform the method as described in any one of claims 1-14.

19. A computer program product, characterized in that, When the computer program product is run on a computer, it causes the computer to perform the method as described in any one of claims 1-14.

20. A vehicle, characterized in that, It includes a first device and a second device, wherein the first device is used to implement the method as described in any one of claims 1-14 to synchronize time with the second device.

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