Ceramic electronic component and method of manufacturing ceramic electronic component

Abstract

This ceramic electronic component is provided with a multilayer chip that has a substantially rectangular cuboid shape and that comprises a plurality of dielectric layers and a plurality of internal electrode layers alternately laminated in a first direction, the plurality of internal electrode layers being alternately led out to two end faces of the substantially rectangular cuboid shape that face in a second direction orthogonal to the first direction. The multilayer chip is provided with an end margin at which internal electrode layers exposed on the same end face of the two end faces face one another without any interposed internal electrode layer exposed on a different end face. In a cross-section of the end margin that includes the first direction and the second direction, there are discontinuities occurring in a portion of layers of the plurality of internal electrode layers. In the discontinuities, one side of the portion of layers in the second direction is deformed so as to be oriented to one side in the first direction, and the other side of the portion of layers in the second direction is deformed so as to be oriented to the other side in the first direction.　

Description

Ceramic electronic components and methods for manufacturing ceramic electronic components

[0001] This invention relates to ceramic electronic components and methods for manufacturing ceramic electronic components.

[0002] In recent years, there has been a growing demand for highly reliable ceramic electronic components, such as multilayer ceramic capacitors, in fields such as automobiles (see, for example, Patent Document 1).

[0003] Japanese Patent Publication No. 2021-86972

[0004] In ceramic electronic components, external impacts are known to cause delamination at the boundary between the internal electrode layer and the dielectric layer at the end margin, leading to insulation degradation. Therefore, a structure that makes the component more resistant to external impacts can be considered, for example, by forming undulations in all internal electrode layers within the end margin. However, if the undulations extend to the capacitance portion, the internal electrode layer in the capacitance portion may deform, potentially causing two adjacent internal electrode layers to come into contact and leading to insulation degradation.

[0005] This invention has been made in view of the above problems, and aims to provide a ceramic electronic component and a method for manufacturing a ceramic electronic component that can suppress peeling while suppressing insulation degradation.

[0006] The ceramic electronic component according to the present invention comprises a laminated chip having a substantially rectangular parallelepiped shape, in which a plurality of dielectric layers and a plurality of internal electrode layers are alternately stacked in a first direction, and the plurality of internal electrode layers are alternately drawn out from two opposing end faces of the substantially rectangular parallelepiped shape in a second direction perpendicular to the first direction, the laminated chip having an end margin in which internal electrode layers exposed on the same end face of the two end faces face each other without intervening internal electrode layers exposed on different end faces, and in a cross section of the end margin including the first and second directions, a break occurs in some of the plurality of internal electrode layers, and at the break, one side of the plurality of layers in the second direction is deformed toward one side in the first direction, and the other side of the plurality of layers in the second direction is deformed toward the other side in the first direction.

[0007] In the aforementioned break in the ceramic electronic component, the gap in the first direction may be 0.1 μm or more and 1.0 μm or less.

[0008] In the ceramic electronic component described above, the "partial layer" may be one of each of the outermost layers in the first direction among the plurality of internal electrode layers.

[0009] In the ceramic electronic component described above, the "partial layer" may consist of two outermost layers in the first direction from among the plurality of internal electrode layers.

[0010] In the above-described ceramic electronic component, the portion of the layer may be included in the middle region when the plurality of internal electrode layers are divided into three equal parts in the first direction.

[0011] In the ceramic electronic component described above, the interrupted portion may be wavy in a cross-section that includes a third direction perpendicular to the first and second directions and the second direction.

[0012] In the above-mentioned ceramic electronic component, in a cross-section including the second and third directions, the maximum width of the undulation in the second direction may be 10 μm or more and 20 μm or less, and the maximum width of the undulation in the third direction may be 100 μm or more and 150 μm or less.

[0013] In the ceramic electronic component described above, one of the undulations may be formed in each of the aforementioned layers.

[0014] In the ceramic electronic component described above, two of the undulations may be formed in each of the aforementioned layers.

[0015] The present invention provides a method for manufacturing a ceramic electronic component, comprising the steps of: preparing a laminate in which a plurality of dielectric green sheets containing ceramic particles and a plurality of internal electrode patterns containing metal particles are stacked; and firing the laminate to obtain a laminated chip having a substantially rectangular parallelepiped shape, in which a plurality of dielectric layers obtained from the plurality of dielectric green sheets and a plurality of internal electrode layers obtained from the plurality of internal electrode patterns are alternately stacked in a first direction, and the plurality of internal electrode layers are alternately drawn out from two end faces of the substantially rectangular parallelepiped shape facing each other in a second direction perpendicular to the first direction, wherein the plurality of internal electrode patterns By making the viscosity of some internal electrode patterns higher than that of other internal electrode patterns, in a cross section including the first and second directions of the end margins where internal electrode layers exposed on the same end face of the two end faces of the laminated chip face each other without an internal electrode layer exposed on a different end face, a discontinuity is created in some internal electrode layers obtained from some internal electrode patterns, and at the discontinuity, one side of the some internal electrode layer in the second direction is deformed toward one side in the first direction, and the other side of the some internal electrode layer in the second direction is deformed toward the other side in the first direction.

[0016] According to the present invention, it is possible to provide a ceramic electronic component that can suppress insulation degradation while suppressing peeling.

[0017] This is a partial cross-sectional perspective view of a multilayer ceramic capacitor. This is a cross-sectional view taken along line A-A in Figure 1. This is a cross-sectional view taken along line B-B in Figure 1. (a) and (b) are enlarged cross-sectional views near the external electrodes. This figure illustrates peeling at the end margin. (a) and (b) illustrate the shape of the undulation. (a) and (b) illustrate the location of the undulation. This figure illustrates the location of the undulation. (a) to (d) are figures illustrating the undulation. This figure illustrates a modified example 1. This figure illustrates a modified example 2. This figure illustrates a modified example 3. This figure illustrates a modified example 4. This figure illustrates a modified example 5. This figure illustrates a flow diagram of the manufacturing method of a multilayer ceramic capacitor. (a) and (b) illustrate the internal electrode formation process. This figure illustrates the crimping process. This figure illustrates the crimping process.

[0018] The embodiments will be described below with reference to the drawings.

[0019] (Embodiment) Figure 1 is a partial cross-sectional perspective view of a multilayer ceramic capacitor 100 according to an embodiment. Figure 2 is a cross-sectional view taken along line A-A in Figure 1. Figure 3 is a cross-sectional view taken along line B-B in Figure 1. As illustrated in Figures 1 to 3, the multilayer ceramic capacitor 100 comprises a stacked chip 10 having a substantially rectangular parallelepiped shape and external electrodes 20a and 20b provided on two opposing end faces of either of the stacked chips 10. Of the four faces of the stacked chip 10 other than the two end faces, the two faces other than the top and bottom faces in the stacking direction are referred to as side faces. The external electrodes 20a and 20b extend to the top, bottom, and two side faces of the stacked chip 10 in the stacking direction. However, the external electrodes 20a and 20b are spaced apart from each other.

[0020] In Figures 1 to 3, the T direction (first direction) is the stacking direction, and is the direction in which each internal electrode layer faces another. The L direction (second direction) is the length direction of the stacked chip 10, and is the direction in which the two end faces of the stacked chip 10 face each other, and is the direction in which the external electrode 20a and external electrode 20b face each other. The W direction (third direction) is the width direction of the internal electrode layer, and is the direction in which the two sides of the stacked chip 10 (excluding the two end faces) face each other. The T direction, the L direction, and the W direction are mutually orthogonal.

[0021] The multilayer chip 10 has a configuration in which dielectric layers 11 containing a ceramic material that functions as a dielectric and internal electrode layers are alternately stacked. The internal electrode layers comprise a plurality of first internal electrode layers 12a and a plurality of second internal electrode layers 12b. The first internal electrode layers 12a and the second internal electrode layers 12b are stacked alternately. The edges of the first internal electrode layers 12a are drawn out to the first end face of the multilayer chip 10 on which the external electrode 20a is provided. The edges of the second internal electrode layers 12b are drawn out to the second end face of the multilayer chip 10 on which the external electrode 20b is provided. As a result, the first internal electrode layers 12a and the second internal electrode layers 12b are alternately conductive to the external electrode 20a and the external electrode 20b. Consequently, the multilayer ceramic capacitor 100 has a configuration in which capacitor units are stacked. Furthermore, in the laminate of the dielectric layer 11 and the internal electrode layer, the internal electrode layer is arranged as the outermost layer in the lamination direction, and the upper and lower surfaces of the laminate are covered by a cover layer 13. The cover layer 13 mainly consists of a ceramic material. For example, the composition of the cover layer 13 may be the same as or different from that of the dielectric layer 11.

[0022] The dimensions of the multilayer ceramic capacitor 100 are, for example, 0.25 mm in length, 0.125 mm in width, and 0.125 mm in height, or 0.4 mm in length, 0.2 mm in width, and 0.2 mm in height, or 0.6 mm in length, 0.3 mm in width, and 0.3 mm in height, or 1.0 mm in length, 0.5 mm in width, and 0.5 mm in height, or 3.2 mm in length, 1.6 mm in width, and 1.6 mm in height, or 4.5 mm in length, 3.2 mm in width, and 2.5 mm in height, but are not limited to these dimensions.

[0023] The first internal electrode layer 12a and the second internal electrode layer 12b are mainly composed of base metals such as nickel (Ni), copper (Cu), tin (Sn), or alloys thereof. As the main components of the first internal electrode layer 12a and the second internal electrode layer 12b, noble metals such as platinum (Pt), palladium (Pd), silver (Ag), gold (Au), or alloys containing these may also be used. The average thickness per layer of the first internal electrode layer 12a and the second internal electrode layer 12b in the T direction is 0.3 μm or more and 1.0 μm or less, or 0.5 μm or more and 0.8 μm or less, or 0.4 μm or more and 0.6 μm or less. The average thickness per layer of the first internal electrode layer 12a can be measured by observing the cross-section of the multilayer ceramic capacitor 100 with a SEM (scanning electron microscope), measuring the thicknesses of 10 points each for 10 different layers of the first internal electrode layer 12a, and deriving the average value of all the measurement points. The average thickness per layer of the second internal electrode layer 12b can be measured by observing the cross-section of the multilayer ceramic capacitor 100 with a SEM (scanning electron microscope), measuring the thicknesses of 10 points each for 10 different layers of the second internal electrode layer 12b, and deriving the average value of all the measurement points.

[0024] The dielectric layer 11 is, for example, mainly composed of a ceramic material having a perovskite structure represented by the general formula ABO ３ . The perovskite structure contains ABO ３－α deviating from the stoichiometric composition. For example, as the ceramic material, barium titanate (BaTiO ３ ), calcium zirconate (CaZrO ３ ), calcium titanate (CaTiO ３ ), strontium titanate (SrTiO ３ ), magnesium titanate (MgTiO ３ ), Ba １-ｘ－ｙ Ca ｘ Sr ｙ Ti １－ｚ Zr ｚ O ３ (0 ≤ x ≤ 1, 0 ≤ y ≤ 1, 0 ≤ z ≤ 1), etc. can be selected and used from at least one of them. Ba １-ｘ－ｙ Ca ｘ Srｙ Ti １－ｚ Zr ｚ O ３ These include barium strontium titanate, barium calcium titanate, barium zirconate, barium zirconate titanate, calcium zirconate titanate, and barium calcium zirconate titanate. For example, in the dielectric layer 11, the main component ceramic is contained in an amount of 90 at% or more. The average thickness per layer of the dielectric layer 11 in the T direction is 0.3 μm or more and 1.0 μm or less, or 0.5 μm or more and 0.8 μm or less, or 0.4 μm or more and 0.6 μm or less. The average thickness per layer of the dielectric layer 11 in the T direction can be measured by observing the cross-section of the multilayer ceramic capacitor 100 with an SEM (scanning electron microscope), measuring the thickness at 10 points for each of 10 different dielectric layers 11, and deriving the average value of all measurement points.

[0025] The dielectric layer 11 may contain additives. Examples of additives to the dielectric layer 11 include oxides of zirconium (Zr), hafnium (Hf), magnesium (Mg), manganese (Mn), molybdenum (Mo), vanadium (V), chromium (Cr), rare earth elements (yttrium (Y), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), and ytterbium (Yb)), or oxides containing cobalt (Co), nickel (Ni), lithium (Li), boron (B), sodium (Na), potassium (K), or silicon (Si), or glass containing cobalt, nickel, lithium, boron, sodium, potassium, or silicon.

[0026] As illustrated in Figure 2, the region where the first internal electrode layer 12a connected to the external electrode 20a and the second internal electrode layer 12b connected to the external electrode 20b face each other is a region in the multilayer ceramic capacitor 100 that generates capacitance. Therefore, this region that generates capacitance is referred to as the capacitance section 14. In other words, the capacitance section 14 is a region where adjacent internal electrode layers connected to different external electrodes face each other.

[0027] The region in which the first internal electrode layers 12a connected to the external electrode 20a face each other in the stacking direction without passing through the second internal electrode layer 12b connected to the external electrode 20b is referred to as the first end margin 15a. Similarly, the region in which the second internal electrode layers 12b connected to the external electrode 20b face each other in the stacking direction without passing through the first internal electrode layer 12a connected to the external electrode 20a is referred to as the second end margin 15b. Each end margin is a region in which internal electrode layers connected to the same external electrode face each other in the stacking direction without passing through internal electrode layers connected to different external electrodes. The first end margin 15a and the second end margin 15b are regions in which no capacitance is generated.

[0028] As illustrated in Figure 3, in the stacked chip 10, the side margin 16 is a region provided to cover the two side edges (the edges in the W direction) of the stacked structure of the dielectric layer 11, the first internal electrode layer 12a, and the second internal electrode layer 12b. That is, in Figure 3, the side margin 16 is a region provided outside the capacitance portion 14 in the W direction. In other words, the side margin 16 is an outer region adjacent to the capacitance portion 14 when viewed from the stacking direction, and is an outer region adjacent to the capacitance portion 14 on the side where the internal electrode layer is not drawn out. The side margin 16 is also a region that does not generate capacitance.

[0029] Figure 4(a) is an enlarged cross-sectional view of the vicinity of the external electrode 20a. Hatching is omitted in Figure 4(a). As illustrated in Figure 4(a), the external electrode 20a has a structure in which a plating layer 22a is provided on a base layer 21a. The base layer 21a functions as a contact layer that is in contact with the first end face of the laminated chip 10. The base layer 21a mainly consists of Ni, Cu, etc. The base layer 21a may also contain ceramic components as co-materials, or it may contain glass components.

[0030] The plating layer 22a is mainly composed of a metal such as Ni, Cu, Al, Zn, Sn or an alloy of two or more of these. The plating layer 22a may be a plating layer of a single metal component or a plurality of plating layers of different metal components. For example, in Fig. 4(a), the plating layer 22a has a structure in which a first plating layer 23a, a second plating layer 24a, and a third plating layer 25a are formed in order from the side of the base layer 21a. The first plating layer 23a is, for example, a Cu plating layer. The second plating layer 24a is, for example, a Ni plating layer. The third plating layer 25a is, for example, a Sn plating layer.

[0031] Fig. 4(b) is an enlarged cross-sectional view near the external electrode 20b. In Fig. 4(b), the hatching is omitted. As illustrated in Fig. 4(b), the external electrode 20b has a structure in which a plating layer 22b is provided on the base layer 21b. The base layer 21b functions as a contact layer that contacts the second end face of the stacked chip 10. The base layer 21b is mainly composed of Ni, Cu, etc. The base layer 21b may contain a ceramic component as a co-material or may contain a glass component.

[0032] The plating layer 22b is mainly composed of a metal such as Ni, Cu, Al, Zn, Sn or an alloy of two or more of these. The plating layer 22b may be a plating layer of a single metal component or a plurality of plating layers of different metal components. For example, the plating layer 22b has a structure in which a first plating layer 23b, a second plating layer 24b, and a third plating layer 25b are formed in order from the side of the base layer 21b. The first plating layer 23b is, for example, a Cu plating layer. The second plating layer 24b is, for example, a Ni plating layer. The third plating layer 25b is, for example, a Sn plating layer.

[0033] The underlayers 21a and 21b may have the same composition or different compositions. The plating layers 22a and 22b may have the same laminated structure or different laminated structures. For example, the number of plating layers may be different. The first plating layer 23a and 23b may have the same composition or different compositions. The second plating layer 24a and 24b may have the same composition or different compositions. The third plating layer 25a and 25b may have the same composition or different compositions.

[0034] In such multilayer ceramic capacitors, as illustrated in Figure 5, external impact can cause delamination at the boundary between the internal electrode layer and the dielectric layer at the end margin (the area circled in Figure 5), as indicated by the arrow, leading to insulation degradation. Therefore, a structure that makes the capacitor more resistant to external impacts can be considered, for example, by forming a wavy shape in the center of the WL plane in all internal electrode layers within the end margin. Here, a wavy shape refers to a shape that appears bent or distorted, such as an N shape as shown in Figure 6(a) or a K shape as shown in Figure 6(b), when viewed in plan with respect to the WL plane of the internal electrode layer (WL cross-section of the multilayer chip), because the internal electrode layer is not in a uniform state. The wavy shape 50 can be observed using a metallurgical microscope after polishing until the WL plane of the internal electrode layer is exposed.

[0035] As illustrated in Figure 7(a), such undulations 50 are provided in the central part of the WL plane of the internal electrode layer region in the end margin. Then, as illustrated in Figure 7(b), undulations 50 are provided in all internal electrode layers. In Figure 7(b), undulations 50 are provided in the thickly drawn portion of the internal electrode layer. In this way, even if an external impact is applied, the stress caused by the impact is suppressed, and delamination between the internal electrode layer and the dielectric layer can be suppressed.

[0036] However, when the undulation 50 of the internal electrode layer extends to the capacitance portion, the internal electrode layer in the capacitance portion may be deformed, and there is a risk that the two adjacent internal electrode layers may come into contact with each other, causing insulation degradation. By providing undulations 50 in all the internal electrode layers, the probability of contact between two adjacent internal electrode layers increases.

[0037] Therefore, the multilayer ceramic capacitor 100 according to the present embodiment has a configuration capable of suppressing peeling between the internal electrode layer and the dielectric layer while suppressing insulation degradation. Details will be described below.

[0038] In the present embodiment, as illustrated in FIG. 8, in the end margin, undulations 50 are provided at the central portion of the WL plane of the internal electrode layer of the outermost layer (the uppermost layer and the lowermost layer) in the T direction. In the example of FIG. 8, in the first end margin 15a, undulations 50 are provided at the central portion of the WL plane of the first internal electrode layer 12a of the uppermost layer. Also, in the second end margin 15b, undulations 50 are provided at the central portion of the WL plane of the second internal electrode layer 12b of the lowermost layer. By providing undulations 50 in the internal electrode layer in this way, even when an external impact is applied, the stress caused by the impact is suppressed. Further, as a reason for preferably providing undulations 50 only in the internal electrode layer of the outermost layer in the T direction, even if the undulations 50 extend to the capacitance portion 14, since there is only an internal electrode layer on one side, contact between two adjacent internal electrode layers can be reduced more than in the vicinity of the center. Further, if undulations are provided in all layers, not only does the overall shape become likely to collapse, but the number of portions where the distance between adjacent internal electrode layers approaches increases, and short-circuiting becomes likely. From the above, it is possible to suppress peeling between the internal electrode layer and the dielectric layer while suppressing insulation degradation.

[0039] Figure 9(a) illustrates the shape of the TL cross-section in the undulating portion 50. As illustrated in Figure 9(a), in the TL cross-section in the undulating portion 50, a break occurs in the internal electrode layer. At this break, one side of the internal electrode layer in the L direction deforms toward one side in the T direction, and the other side of the internal electrode layer in the L direction deforms toward the other side in the T direction. In the example of Figure 9(a), at this break, the left portion of the internal electrode layer deforms toward the right and diagonally downward, and the right portion of the internal electrode layer deforms toward the left and diagonally upward. Conversely, at this break, the left portion of the internal electrode layer may deform toward the right and diagonally upward, and the right portion of the internal electrode layer may deform toward the left and diagonally downward.

[0040] As a result, as illustrated in Figure 9(b), a gap G is created in the interruption, separating in the T direction. The gap G is the distance in the T direction between each end of the interruption. The gap G is, for example, 0.1 μm to 1.0 μm below, or 0.3 μm to 0.8 μm, or 0.4 μm to 0.6 μm. The ends of the interruption may or may not overlap when viewed from the T direction.

[0041] Figure 9(c) illustrates a break that occurs without being caused by the swell 50. In a break that occurs without being caused by the swell 50, there is no deformation in the T direction, resulting in a shape that creates a gap in the L direction. Therefore, breaks caused by the swell 50 can be distinguished from breaks that are not caused by the swell 50.

[0042] As illustrated in Figure 9(d), in the WL plane, the maximum width of the undulation 50 in the L direction is, for example, 10 μm or more and 20 μm or less. In the WL plane, the maximum width of the undulation 50 in the W direction is, for example, 100 μm or more and 150 μm or less.

[0043] (Modification 1) The location where the undulation 50 is provided in the internal electrode layer is not limited to the center of the WL plane within the end margin. For example, as illustrated in Figure 10, the undulation 50 may be provided at two locations in the W direction of the WL plane of the internal electrode layer within the end margin. By providing multiple undulations 50 in a single internal electrode layer in this way, stress caused by external impacts can be further suppressed.

[0044] (Modification 2) In addition, the undulation 50 may be provided in internal electrode layers other than the uppermost and lowermost internal electrode layers. For example, as shown in Figure 11, the undulation 50 may be provided in the center of the WL plane of the uppermost layer and its adjacent layer (a total of two layers) and the lowermost layer and its adjacent layer (a total of two layers) of internal electrode layers in the T direction within the end margin.

[0045] (Modification 3) Alternatively, as illustrated in Figure 12, undulations 50 may be provided at two locations in the W direction of the WL plane of the two internal electrode layers in the WL plane within the end margin: the uppermost layer and the adjacent layer in the T direction, and the lowermost layer and the adjacent layer in the T direction.

[0046] (Modification 4) Furthermore, the internal electrode layer on which the undulation 50 is provided is not limited to the uppermost or lowermost layer. For example, within the end margin, the undulation 50 may be provided in the central part of the WL plane of the internal electrode layer near the center in the T direction. The area near the center in the T direction refers to the middle region when the laminate of internal electrode layers is divided into three equal parts in the T direction. In the example shown in Figure 13, as an example, the undulation 50 is provided in the uppermost and lowermost layers in the T direction and in the central part of the WL plane of the internal electrode layer near the center in the T direction within the end margin.

[0047] (Modification 5) Alternatively, within the end margin, undulations 50 may be provided at two locations in the W direction on the WL plane of the internal electrode layer near the center in the T direction. In the example shown in Figure 14, as an example, undulations 50 are provided within the end margin at the uppermost and lowermost layers in the T direction, and at both ends in the W direction on the WL plane of the internal electrode layer near the center in the T direction.

[0048] As described above, by providing the undulation 50 in only a portion of all the stacked internal electrode layers, it is possible to suppress the deterioration of insulation while suppressing the peeling of the internal electrode layer and the dielectric layer.

[0049] Next, the manufacturing method of the multilayer ceramic capacitor 100 will be described. Figure 15 is a diagram illustrating the flow of the manufacturing method of the multilayer ceramic capacitor 100.

[0050] (Raw material powder preparation process) First, a dielectric material for forming the dielectric layer 11 is prepared. The A-site element and B-site element contained in the dielectric layer 11 are usually ABO ３ The particles are contained in the dielectric layer 11 in the form of a sintered body. For example, barium titanate is a tetragonal compound having a perovskite structure and exhibits a high dielectric constant. This barium titanate can generally be obtained by synthesizing barium titanate by reacting a titanium raw material such as titanium dioxide with a barium raw material such as barium carbonate.

[0051] A predetermined additive compound is added to the obtained ceramic powder according to the purpose. Examples of additive compounds include oxides of zirconium, hafnium, magnesium, manganese, molybdenum, vanadium, chromium, rare earth elements (yttrium, samarium, europium, gadolinium, terbium, dysprosium, holmium, erbium, thulium, and ytterbium), or oxides containing cobalt, nickel, lithium, boron, sodium, potassium, or silicon, or glass containing cobalt, nickel, lithium, boron, sodium, potassium, or silicon.

[0052] For example, a ceramic material can be prepared by wet-mixing a ceramic raw material powder with a compound containing an additive, followed by drying and pulverization. For example, the ceramic material obtained as described above may be subjected to pulverization as needed to adjust the particle size, or the particle size may be adjusted by combining this with a classification process. A dielectric material can be obtained through the above steps.

[0053] (Coating Process) Next, a binder such as polyvinyl butyral (PVB) resin, an organic solvent such as ethanol or toluene, and a plasticizer are added to the obtained raw material powder and wet-mixed. Using the obtained slurry, a dielectric green sheet 51 is coated onto the substrate by, for example, a die coater or a doctor blade and then dried. The substrate is, for example, polyethylene terephthalate (PET) film. A diagram illustrating the coating process has been omitted.

[0054] (Internal Electrode Formation Process) Next, as illustrated in Figure 16(a), an internal electrode pattern 52 for the internal electrode layer is arranged on the surface of the dielectric green sheet 51 by screen printing, gravure printing, or the like, by printing a metal conductive paste for forming internal electrodes containing an organic binder. In addition to nickel, ceramic particles are added to the metal conductive paste as a co-material. The main component of the ceramic particles is not particularly limited, but it is preferable that it is the same as the main component ceramic of the dielectric layer 11. The viscosity of the internal electrode pattern 52 corresponding to the internal electrode layer in which the undulations 50 are provided is set higher than the viscosity of the other internal electrode patterns 52. For example, the viscosity of the internal electrode pattern 52 corresponding to the internal electrode layer in which the undulations 50 are provided is adjusted to be 1.5 times or more and 2.0 times or less than the viscosity of the other internal electrode patterns 52.

[0055] Next, a binder such as ethyl cellulose and an organic solvent such as terpineol are added to the dielectric pattern material obtained in the raw material powder preparation process, and the mixture is kneaded in a roll mill to obtain a dielectric pattern paste for the reverse pattern layer. As illustrated in Figure 16(a), the dielectric pattern 53 is placed on the dielectric green sheet 51 by printing the dielectric pattern paste in the peripheral area where the internal electrode pattern 52 is not printed, thereby filling the step between it and the internal electrode pattern 52. The dielectric green sheet 51 with the internal electrode pattern 52 and dielectric pattern 53 printed on it is called a laminated unit.

[0056] Subsequently, as illustrated in Figure 16(b), stacking units are carried out so that the internal electrode layer and the dielectric layer 11 are staggered, and the edges of the first internal electrode layer 12a and the second internal electrode layer 12b are alternately exposed on both ends of the dielectric layer 11 in the longitudinal direction, alternately leading to a pair of external electrodes 20a and 20b with different polarities. In this embodiment, the number of stacking units is 300 or more.

[0057] (Pressing process) As illustrated in Figure 17, a predetermined number of cover sheets 54 (for example, 2 to 10 layers) are laminated on the top and bottom of the laminate, which is made up of stacked laminate units, and then heat-pressed. The cover sheets 54 are also green sheets containing ceramic powder.

[0058] The side margin portion may be attached to the side surface of the laminated portion, or a ceramic slurry may be applied to it. Specifically, as illustrated in Figure 18, a laminated portion is obtained by alternately laminating a dielectric green sheet 51 and an internal electrode pattern 52 with the same width as the dielectric green sheet 51. Next, a sheet formed from dielectric pattern paste may be attached to the side surface of the laminated portion as a side margin portion 55.

[0059] (Firing process) The ceramic laminate obtained in this way is fired in N ２ After debinding treatment in an atmosphere, metal pastes that will become external electrodes 20a and 20b are applied by the dip method, and the oxygen partial pressure is 10 －１２ MPa ~ 10 －９ The product is fired in a reducing atmosphere at MPa and a temperature of 1160°C to 1280°C (for example, above 1180°C and below 1230°C) for 5 minutes to 10 hours.

[0060] (Re-oxidation process) In order to return oxygen to the barium titanate, which is the partially reduced main phase of the dielectric layer 11 fired in a reducing atmosphere, the first internal electrode layer 12a and the second internal electrode layer 12b are subjected to a process at approximately 1000°C to the extent that they are not oxidized. ２ Heat treatment may be performed in a gas mixture of water vapor or in air at 500°C to 700°C. This process is called the re-oxidation process.

[0061] (Plating process) Subsequently, metal coatings such as copper, nickel, and tin are applied to the external electrodes 20a and 20b by plating. The multilayer ceramic capacitor 100 is completed through the above process.

[0062] According to the manufacturing method of this embodiment, the viscosity of the internal electrode pattern 52 corresponding to the internal electrode layer on which the undulations 50 are formed is made higher than the viscosity of the other internal electrode patterns 52. In this case, when the screen printing stencil is released, an upward tensile force acts due to the paste adhering to the mesh. In particular, on the screen surface, the areas above and below the end margin are non-product areas, so the repulsive force when the stencil is released becomes stronger. As a result, undulations 50 are formed in the end margin region of the internal electrode layer during the firing process. Furthermore, by increasing the viscosity even further, two or more undulations 50 can be formed in the end margin region of the internal electrode layer. Alternatively, two or more undulations 50 can be formed by selecting and using a sheet on which two or more undulations are formed.

[0063] In the embodiments described above, multilayer ceramic capacitors were explained as an example of multilayer ceramic electronic components, but the invention is not limited to them. For example, other multilayer ceramic electronic components such as varistors and thermistors may be used.

[0064] (Example 1) In Example 1, a multilayer ceramic capacitor was manufactured according to the above embodiment. The size of the multilayer ceramic capacitor was 105 shape (length 1.0 mm, width 0.5 mm, height 0.5 mm). The number of layers of internal electrode layers was 160. By making the viscosity of the internal electrode patterns of the uppermost and lowermost layers 1.5 to 2.0 times that of the other internal electrode patterns, undulations were formed in the center of the WL plane of the end margins of the internal electrode layers of the uppermost and lowermost layers. The maximum size of the undulations in the L direction was 12 μm, and the maximum size in the W direction was 121 μm. In the TL cross-section of the undulating portion, the gap G between the breaks was 0.8 μm.

[0065] (Example 2) In Example 2, a multilayer ceramic capacitor was fabricated according to Modification 1. The size of the multilayer ceramic capacitor was set to a 105 shape (length 1.0 mm, width 0.5 mm, height 0.5 mm). The number of layers of internal electrode layers was set to 160. By setting the viscosity of the internal electrode patterns of the topmost and bottommost layers to 1.5 to 2.0 times that of the other internal electrode patterns, one undulation was formed at each end of the end margin in the W direction of the internal electrode layers of the topmost and bottommost layers. The maximum size of the undulation in the L direction was 14 μm, and the maximum size in the W direction was 123 μm. In the TL cross-section of the undulating portion, the gap G between the interruptions was 0.8 μm.

[0066] (Example 3) In Example 3, a multilayer ceramic capacitor was fabricated according to Modification 2. The size of the multilayer ceramic capacitor was 105 shape (length 1.0 mm, width 0.5 mm, height 0.5 mm). The number of layers of internal electrode layers was 160. By making the viscosity of the top layer and its adjacent internal electrode pattern, and the bottom layer and its adjacent internal electrode pattern 1.5 to 2.0 times that of the other internal electrode patterns, a undulation was formed in the center of the end margin of the top layer and its adjacent internal electrode layer, and the bottom layer and its adjacent internal electrode layer. The maximum size of the undulation in the L direction was 16 μm, and the maximum size in the W direction was 125 μm. In the TL cross section of the undulating portion, the gap G between the breaks was 0.8 μm.

[0067] (Example 4) In Example 4, a multilayer ceramic capacitor was fabricated according to Modification 3. The size of the multilayer ceramic capacitor was 105 shape (length 1.0 mm, width 0.5 mm, height 0.5 mm). The number of layers of internal electrode layers was 160. By making the viscosity of the top layer and its adjacent internal electrode pattern, and the bottom layer and its adjacent internal electrode pattern 1.5 to 2.0 times that of the other internal electrode patterns, one undulation was formed at both ends in the W direction of the end margin of the top layer and its adjacent internal electrode layer, and the bottom layer and its adjacent internal electrode layer. The maximum size of the undulation in the L direction was 18 μm, and the maximum size in the W direction was 127 μm. In the TL cross section of the undulating portion, the gap G between the breaks was 0.8 μm.

[0068] (Example 5) In Example 5, a multilayer ceramic capacitor was fabricated according to Modification 4. The size of the multilayer ceramic capacitor was 105 shape (length 1.0 mm, width 0.5 mm, height 0.5 mm). The number of layers of internal electrode layers was 160. By making the viscosity of the top layer and its adjacent internal electrode pattern, the bottom layer and its adjacent internal electrode pattern, and one layer of internal electrode pattern in the central region 1.5 to 2.0 times that of the other internal electrode patterns, a undulation was formed in the center of the end margin of the top layer and its adjacent internal electrode layer, the bottom layer and its adjacent internal electrode layer, and one layer of internal electrode layer in the central region. The maximum size of the undulation in the L direction was 22 μm, and the maximum size in the W direction was 132 μm. In the TL cross section of the undulating portion, the gap G between the breaks was 0.8 μm.

[0069] (Example 6) In Example 6, a multilayer ceramic capacitor was fabricated according to Modification 5. The size of the multilayer ceramic capacitor was 105 shape (length 1.0 mm, width 0.5 mm, height 0.5 mm). The number of layers of internal electrode layers was 160. By making the viscosity of the top layer and its adjacent internal electrode pattern, the bottom layer and its adjacent internal electrode pattern, and the internal electrode pattern of one layer in the central region 1.5 to 2.0 times that of the other internal electrode patterns, one undulation was formed at both ends in the W direction of the end margin of the top layer and its adjacent internal electrode layer, the bottom layer and its adjacent internal electrode layer, and the internal electrode layer of one layer in the central region. The maximum size of the undulation in the L direction was 23 μm, and the maximum size in the W direction was 131 μm. In the TL cross section of the undulating portion, the gap G of the interruption was 0.8 μm.

[0070] (Comparative Example 1) In Comparative Example 1, the size of the multilayer ceramic capacitor was set to 105 shape (length 1.0 mm, width 0.5 mm, height 0.5 mm). The number of layers of internal electrode layers was set to 160. By increasing the viscosity of the internal electrode pattern of all layers, undulations were formed in the center of the end margin of all internal electrode layers. The maximum size of the undulations in the L direction was 30 μm, and the maximum size in the W direction was 135 μm. In the TL cross section of the undulating portion, the gap G between the interruptions was 0.8 μm.

[0071] For each of Examples 1-6 and Comparative Example 1, the percentage of samples showing delamination between the internal electrode layer and the dielectric layer (delamination rate) was examined out of 1000 samples. The results are shown in Table 1. In all of Examples 1-6 and Comparative Example 1, the delamination rate was 0%. This is thought to be because undulation was formed in the internal electrode layer.

[0072] For each of Examples 1-6 and Comparative Example 1, the percentage of samples with short circuits (short circuit rate) out of 1000 samples was examined. The results are shown in Table 1. In Examples 1-4, the short circuit rate was 0%. In Example 5, the short circuit rate was 0.5%. In Example 6, the short circuit rate was 1%. In Comparative Example 1, the short circuit rate was 10%. The high short circuit rate in Comparative Example 1 is thought to be due to the formation of undulations in all layers of the internal electrode layer. In contrast, the short circuit rates were low in Examples 1-6. This is thought to be because undulations were formed in only some of the internal electrode layers. The lower short circuit rates in Examples 1-4 compared to Examples 5 and 6 are thought to be because fewer internal electrode layers had undulations formed in Examples 1-4.

[0073] (Example 7) In Example 7, a multilayer ceramic capacitor was manufactured according to the manufacturing method of the above embodiment. The size of the multilayer ceramic capacitor was 105 shape (length 1.0 mm, width 0.5 mm, height 0.5 mm). The number of layers of internal electrode layers was 554. By making the viscosity of the internal electrode patterns of the uppermost and lowermost layers 1.5 to 2.0 times that of the other internal electrode patterns, undulations were formed in the center of the end margins of the internal electrode layers of the uppermost and lowermost layers. The maximum size of the undulations in the L direction was 13 μm, and the maximum size in the W direction was 122 μm. In the TL cross-section of the undulating portion, the gap G between the breaks was 0.8 μm.

[0074] (Example 8) In Example 8, a multilayer ceramic capacitor was fabricated according to Modification 1. The size of the multilayer ceramic capacitor was 105 shape (length 1.0 mm, width 0.5 mm, height 0.5 mm). The number of layers of internal electrode layers was 554. By making the viscosity of the internal electrode patterns of the uppermost and lowermost layers 1.5 to 2.0 times that of the other internal electrode patterns, one undulation was formed at both ends in the W direction of the end margin of the internal electrode layers of the uppermost and lowermost layers. The maximum size of the undulation in the L direction was 14 μm, and the maximum size in the W direction was 125 μm. In the TL cross-section of the undulating portion, the gap G between the interruptions was 0.8 μm.

[0075] (Example 9) In Example 9, a multilayer ceramic capacitor was fabricated according to Modification 2. The size of the multilayer ceramic capacitor was 105 shape (length 1.0 mm, width 0.5 mm, height 0.5 mm). The number of layers of internal electrode layers was 554. By making the viscosity of the top layer and its adjacent internal electrode pattern, and the bottom layer and its adjacent internal electrode pattern 1.5 to 2.0 times that of the other internal electrode patterns, a undulation was formed in the center of the end margin of the top layer and its adjacent internal electrode layer, and the bottom layer and its adjacent internal electrode layer. The maximum size of the undulation in the L direction was 18 μm, and the maximum size in the W direction was 124 μm. In the TL cross-section of the undulating portion, the gap G between the breaks was 0.8 μm.

[0076] (Example 10) In Example 10, a multilayer ceramic capacitor was fabricated according to Modification 3. The size of the multilayer ceramic capacitor was 105 shape (length 1.0 mm, width 0.5 mm, height 0.5 mm). The number of layers of internal electrode layers was 554. By making the viscosity of the top layer and its adjacent internal electrode pattern, and the bottom layer and its adjacent internal electrode pattern 1.5 to 2.0 times that of the other internal electrode patterns, one undulation was formed at both ends in the W direction of the end margin of the top layer and its adjacent internal electrode layer, and the bottom layer and its adjacent internal electrode layer. The maximum size of the undulation in the L direction was 17 μm, and the maximum size in the W direction was 128 μm. In the TL cross section of the undulating portion, the gap G between the breaks was 0.8 μm.

[0077] (Example 11) In Example 11, a multilayer ceramic capacitor was fabricated according to Modification 4. The size of the multilayer ceramic capacitor was 105 shape (length 1.0 mm, width 0.5 mm, height 0.5 mm). The number of layers of internal electrode layers was 554. By making the viscosity of the top layer and its adjacent internal electrode pattern, the bottom layer and its adjacent internal electrode pattern, and one layer of internal electrode pattern in the central region 1.5 to 2.0 times that of the other internal electrode patterns, a undulation was formed in the center of the end margin of the top layer and its adjacent internal electrode layer, the bottom layer and its adjacent internal electrode layer, and one layer of internal electrode layer in the central region. The maximum size of the undulation in the L direction was 24 μm, and the maximum size in the W direction was 134 μm. In the TL cross-section of the undulating portion, the gap G between the breaks was 0.8 μm.

[0078] (Example 12) In Example 12, a multilayer ceramic capacitor was fabricated according to Modification 5. The size of the multilayer ceramic capacitor was 105 shape (length 1.0 mm, width 0.5 mm, height 0.5 mm). The number of layers of internal electrode layers was 554. By making the viscosity of the top layer and its adjacent internal electrode pattern, the bottom layer and its adjacent internal electrode pattern, and the internal electrode pattern of one layer in the central region 1.5 to 2.0 times that of the other internal electrode patterns, one undulation was formed at both ends in the W direction of the end margin of the top layer and its adjacent internal electrode layer, the bottom layer and its adjacent internal electrode layer, and the internal electrode layer of one layer in the central region. The maximum size of the undulation in the L direction was 25 μm, and the maximum size in the W direction was 136 μm. In the TL cross section of the undulating portion, the gap G of the interruption was 0.8 μm.

[0079] (Comparative Example 2) In Comparative Example 2, the size of the multilayer ceramic capacitor was set to 105 shape (length 1.0 mm, width 0.5 mm, height 0.5 mm). The number of layers of internal electrode layers was set to 554. By increasing the viscosity of the internal electrode pattern of all layers, undulations were formed in the center of the end margin of all internal electrode layers. The maximum size of the undulations in the L direction was 33 μm, and the maximum size in the W direction was 139 μm. In the TL cross section of the undulating portion, the gap G between the interruptions was 0.8 μm.

[0080] For each of Examples 7-12 and Comparative Example 2, the percentage of samples showing delamination between the internal electrode layer and the dielectric layer (delamination rate) was examined out of 1000 samples. The results are shown in Table 2. In all of Examples 7-12 and Comparative Example 2, the delamination rate was 0%. This is thought to be because undulation was formed in the internal electrode layer.

[0081] For each of Examples 7-12 and Comparative Example 2, the percentage of samples with short circuits (short circuit rate) out of 1000 samples was examined. The results are shown in Table 2. In Examples 7-10, the short circuit rate was 0%. In Example 11, the short circuit rate was 2%. In Example 12, the short circuit rate was 3%. In Comparative Example 2, the short circuit rate was 15%. The high short circuit rate in Comparative Example 2 is thought to be due to the formation of undulations in all layers of the internal electrode layer. In contrast, the short circuit rates were lower in Examples 7-12. This is thought to be because undulations were formed in only some of the internal electrode layers. The lower short circuit rates in Examples 7-10 compared to Examples 11 and 12 are thought to be because fewer internal electrode layers had undulations formed in Examples 7-10.

[0082] (Example 13) In Example 13, a multilayer ceramic capacitor was manufactured according to the manufacturing method of the above embodiment. The size of the multilayer ceramic capacitor was 063 shape (length 0.6 mm, width 0.3 mm, height 0.3 mm). The number of layers of internal electrode layers was 237. By making the viscosity of the internal electrode patterns of the uppermost and lowermost layers 1.5 to 2.0 times that of the other internal electrode patterns, undulations were formed in the center of the end margins of the internal electrode layers of the uppermost and lowermost layers. The maximum size of the undulations in the L direction was 11 μm, and the maximum size in the W direction was 120 μm. In the TL cross-section of the undulating portion, the spacing of the gap G of the interruption was 0.8 μm.

[0083] (Example 14) In Example 14, a multilayer ceramic capacitor was fabricated according to Modification 1. The size of the multilayer ceramic capacitor was 063 shape (length 0.6 mm, width 0.3 mm, height 0.3 mm). The number of layers of internal electrode layers was 237. By making the viscosity of the internal electrode patterns of the topmost and bottommost layers 1.5 to 2.0 times that of the other internal electrode patterns, one undulation was formed at each end of the end margin in the W direction of the internal electrode layers of the topmost and bottommost layers. The maximum size of the undulation in the L direction was 12 μm, and the maximum size in the W direction was 122 μm. In the TL cross section of the undulating portion, the gap G between the interruptions was 0.8 μm.

[0084] (Example 15) In Example 15, a multilayer ceramic capacitor was fabricated according to Modification 2. The size of the multilayer ceramic capacitor was 063 shape (length 0.6 mm, width 0.3 mm, height 0.3 mm). The number of layers of internal electrode layers was 237. By making the viscosity of the top layer and its adjacent internal electrode pattern, and the bottom layer and its adjacent internal electrode pattern 1.5 to 2.0 times that of the other internal electrode patterns, a undulation was formed in the center of the end margin of the top layer and its adjacent internal electrode layer, and the bottom layer and its adjacent internal electrode layer. The maximum size of the undulation in the L direction was 15 μm, and the maximum size in the W direction was 124 μm. In the TL cross section of the undulating portion, the gap G between the breaks was 0.8 μm.

[0085] (Example 16) In Example 16, a multilayer ceramic capacitor was fabricated according to Modification 3. The size of the multilayer ceramic capacitor was 063 shape (length 0.6 mm, width 0.3 mm, height 0.3 mm). The number of layers of internal electrode layers was 237. By making the viscosity of the top layer and its adjacent internal electrode pattern, and the bottom layer and its adjacent internal electrode pattern 1.5 to 2.0 times that of the other internal electrode patterns, one undulation was formed at both ends in the W direction of the end margin of the top layer and its adjacent internal electrode layer, and the bottom layer and its adjacent internal electrode layer. The maximum size of the undulation in the L direction was 17 μm, and the maximum size in the W direction was 126 μm. In the TL cross section of the undulating portion, the gap G between the breaks was 0.8 μm.

[0086] (Example 17) In Example 17, a multilayer ceramic capacitor was fabricated according to Modification 4. The size of the multilayer ceramic capacitor was 063 shape (length 0.6 mm, width 0.3 mm, height 0.3 mm). The number of layers of internal electrode layers was 237. By making the viscosity of the top layer and its adjacent internal electrode pattern, the bottom layer and its adjacent internal electrode pattern, and one layer of internal electrode pattern in the central region 1.5 to 2.0 times that of the other internal electrode patterns, a undulation was formed in the center of the end margin of the top layer and its adjacent internal electrode layer, the bottom layer and its adjacent internal electrode layer, and one layer of internal electrode layer in the central region. The maximum size of the undulation in the L direction was 21 μm, and the maximum size in the W direction was 131 μm. In the TL cross-section of the undulating portion, the gap G between the breaks was 0.8 μm.

[0087] (Example 18) In Example 18, a multilayer ceramic capacitor was fabricated according to Modification 5. The size of the multilayer ceramic capacitor was 063 shape (length 0.6 mm, width 0.3 mm, height 0.3 mm). The number of layers of internal electrode layers was 237. By making the viscosity of the top layer and its adjacent internal electrode pattern, the bottom layer and its adjacent internal electrode pattern, and the internal electrode pattern of one layer in the central region 1.5 to 2.0 times that of the other internal electrode patterns, one undulation was formed at both ends in the W direction of the end margin of the top layer and its adjacent internal electrode layer, the bottom layer and its adjacent internal electrode layer, and the internal electrode layer of one layer in the central region. The maximum size of the undulation in the L direction was 24 μm, and the maximum size in the W direction was 132 μm. In the TL cross section of the undulating portion, the gap G of the interruption was 0.8 μm.

[0088] (Comparative Example 3) In Comparative Example 3, the size of the multilayer ceramic capacitor was 063 shape (length 0.6 mm, width 0.3 mm, height 0.3 mm). The number of layers of internal electrode layers was 237. By increasing the viscosity of the internal electrode pattern of all layers, undulations were formed in the center of the end margin of all internal electrode layers. The maximum size of the undulations in the L direction was 31 μm, and the maximum size in the W direction was 134 μm. In the TL cross-section of the undulating portion, the gap G between the interruptions was 0.8 μm.

[0089] For each of Examples 13-18 and Comparative Example 3, the percentage of samples showing delamination between the internal electrode layer and the dielectric layer (delamination rate) was examined out of 1000 samples. The results are shown in Table 3. In all of Examples 13-18 and Comparative Example 3, the delamination rate was 0%. This is thought to be because undulation was formed in the internal electrode layer.

[0090] For each of Examples 13-18 and Comparative Example 3, the percentage of samples with short circuits (short circuit rate) out of 1000 samples was examined. The results are shown in Table 3. In Examples 13-18, the short circuit rate was 0%. In Comparative Example 3, the short circuit rate was 5%. The high short circuit rate in Comparative Example 3 is thought to be due to the formation of undulations in the internal electrode layers of all layers. In contrast, the short circuit rates were low in Examples 13-18. This is thought to be because undulations were formed only in some of the internal electrode layers.

[0091] Although embodiments of the present invention have been described in detail above, the present invention is not limited to these specific embodiments, and various modifications and changes are possible within the scope of the gist of the present invention as described in the claims.

[0092] 10 Multilayer chip 11 Dielectric layer 12a First internal electrode layer 12b Second internal electrode layer 13 Cover layer 14 Capacitance section 15a First end margin 15b Second end margin 16 Side margins 20a, 20b External electrodes 50 Wavy 51 Dielectric green sheet 52 Internal electrode pattern 53 Dielectric pattern 54 Cover sheet 55 Side margin section 100 Multilayer ceramic capacitor

Claims

1. A ceramic electronic component comprising a laminated chip having a substantially rectangular parallelepiped shape, wherein a plurality of dielectric layers and a plurality of internal electrode layers are alternately stacked in a first direction, and the plurality of internal electrode layers are alternately drawn out from two opposing end faces of the substantially rectangular parallelepiped shape in a second direction perpendicular to the first direction, wherein the laminated chip has an end margin where internal electrode layers exposed on the same end face face each other without intervening internal electrode layers exposed on different end faces, and in a cross-section of the end margin including the first and second directions, a break occurs in some of the plurality of internal electrode layers, and at the break, one side of the plurality of layers in the second direction is deformed toward one side in the first direction, and the other side of the plurality of layers in the second direction is deformed toward the other side in the first direction.

2. The ceramic electronic component according to claim 1, wherein the gap in the first direction at the interruption is 0.1 μm or more and 1.0 μm or less.

3. The ceramic electronic component according to claim 1, wherein the "partial layer" refers to one outermost layer in the first direction among the plurality of internal electrode layers.

4. The ceramic electronic component according to claim 1, wherein the "partial layer" refers to two layers each of the outermost layers in the first direction among the plurality of internal electrode layers.

5. The ceramic electronic component according to claim 1, wherein the portion of the layers is included in the middle region when the plurality of internal electrode layers are divided into three equal parts in the first direction.

6. The ceramic electronic component according to claim 1, wherein in a cross-section including a third direction perpendicular to the first and second directions and the second direction, the interrupted portion is wavy.

7. In a cross-section including the second and third directions, the maximum width of the undulation in the second direction is 10 μm or more and 20 μm or less, and the maximum width of the undulation in the third direction is 100 μm or more and 150 μm or less, according to claim 6.

8. The ceramic electronic component according to claim 6, wherein one of the undulations is formed in each of the aforementioned layers.

9. The ceramic electronic component according to claim 6, wherein two of the undulations are formed in each of the aforementioned layers.

10. The process includes: preparing a laminate in which a plurality of dielectric green sheets containing ceramic particles and a plurality of internal electrode patterns containing metal particles are stacked; and firing the laminate to obtain a laminated chip having a substantially rectangular parallelepiped shape, in which a plurality of dielectric layers obtained from the plurality of dielectric green sheets and a plurality of internal electrode layers obtained from the plurality of internal electrode patterns are alternately stacked in a first direction, and the plurality of internal electrode layers are alternately drawn out from two opposing end faces of the substantially rectangular parallelepiped shape in a second direction perpendicular to the first direction. A method for manufacturing a ceramic electronic component, wherein the viscosity of some of the internal electrode patterns among the plurality of internal electrode patterns is made higher than the viscosity of the other internal electrode patterns, thereby causing a discontinuity in some of the internal electrode layers obtained from some of the internal electrode patterns in a cross section including the first and second directions of the end margins where internal electrode layers exposed on the same end face of the two end faces of the stacked chip face each other without intervening with internal electrode layers exposed on different end faces, and in the discontinuity, one side of the some internal electrode layer in the second direction is deformed toward one side in the first direction, and the other side of the some internal electrode layer in the second direction is deformed toward the other side in the first direction.

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