Digital phase-shift circuit

Abstract

A digital phase-shift circuit comprising: a signal line; a pair of inner lines; a pair of outer lines; a first ground conductor; a second ground conductor; and a pair of electronic switches. The pair of inner lines are provided on both sides of the signal line. The pair of outer lines are provided outside the pair of inner lines. The first ground conductor is connected to a first end of each of the pair of inner lines and the pair of outer lines. The second ground conductor is connected to a second end of each of the pair of outer lines. One of the pair of electronic switches is provided between the second end of one of the pair of inner lines and the second ground conductor. The other of the pair of electronic switches is provided between the second end of the other of the pair of inner lines and the second ground conductor. At least one of the pair of outer lines is a bent line having a bent shape in a plan view.

Description

Digital phase shift circuit

[0001] This invention relates to a digital phase shift circuit. This application claims priority based on Japanese Patent Application No. 2024-188846, filed in Japan on October 28, 2024, the contents of which are incorporated herein by reference.

[0002] Non-Patent Document 1 discloses a digitally controlled phase shift circuit (digital phase shift circuit) for microwave, quasi-millimeter wave, or millimeter wave applications. As shown in Figure 2 of Non-Patent Document 1, this digital phase shift circuit comprises a signal line, a pair of inner lines, a pair of outer lines, a first grounding bar, a second grounding bar, and a pair of NMOS (N-type metal-oxide-semiconductor) switches. The pair of inner lines are provided on both sides of the signal line. The pair of outer lines are provided outside the pair of inner lines. The first grounding bar is connected to the first ends of each of the pair of inner lines and the pair of outer lines. The second grounding bar is connected to the second ends of each of the pair of outer lines. The pair of NMOS switches correspond one-to-one with the pair of inner lines. Each NMOS switch is provided between the second end of the corresponding inner line and the second grounding bar.

[0003] In such a digital phase shift circuit, the return current flowing through a pair of inner or outer lines due to the transmission of signal waves in the signal line switches according to the opening / closing of a pair of NMOS switches. This causes the operating mode of the digital phase shift circuit to switch between a low-latency mode and a high-latency mode. In other words, the operating mode of the digital phase shift circuit is low-latency mode when the return current flows through the pair of inner lines, and high-latency mode when the return current flows through the pair of outer lines.

[0004] A Ka-band Digitally-Controlled Phase Shifter with sub-degree Phase Precision (2016,IEEE,RFIC)

[0005] In the digital phase shift circuit described above, it is desirable to achieve a large phase shift amount.

[0006] This invention has been made in consideration of these circumstances and aims to provide a digital phase shift circuit that can achieve an increase in the amount of phase shift.

[0007] To solve the above problems, the digital phase shift circuit according to embodiment 1 of the present invention includes a signal line, a first inner line provided on the first side of the signal line, a second inner line provided on the second side of the signal line, a first outer line provided on the outside of the first inner line on the first side of the signal line, a second outer line provided on the outside of the second inner line on the second side of the signal line, a first end of the first inner line, a first end of the second inner line, and a first end of the first outer line. The circuit comprises a first grounding conductor connected to the end of the first outer line and the first end of the second outer line, a second grounding conductor connected to the second end of the first outer line and the second end of the second outer line, a first electronic switch provided between the second end of the first inner line and the second grounding conductor, and a second electronic switch provided between the second end of the second inner line and the second grounding conductor, wherein at least one of the first outer line and the second outer line is a curved line having a curved shape in plan view.

[0008] According to aspect 1 of the present invention, a digital phase shift circuit capable of increasing the amount of phase shift can be provided.

[0009] Furthermore, in embodiment 2 of the present invention, in the digital phase shift circuit of embodiment 1, the bent line includes an outward-convex line having a convex shape that moves away from the signal line.

[0010] Furthermore, in a third aspect of the present invention, in a digital phase shift circuit of aspect 1 or aspect 2, the bent line includes an inwardly convex line having a convex shape that approaches the signal line.

[0011] Furthermore, in embodiment 4 of the present invention, in the digital phase shift circuit of embodiment 3, the inward convex line and the signal line are non-parallel at the portion of the inward convex line that is closest to the signal line.

[0012] Further, in the digital phase-shifting circuit of Embodiment 5 of the present invention, the inner convex line includes a stepped line, the stepped line includes a plurality of parallel lines extending parallel to the signal line, and a plurality of intersecting lines extending in a direction intersecting the signal line, and in the stepped line, the plurality of parallel lines and the plurality of intersecting lines are alternately connected, and the stepped line extends so that the inner convex line tapers as it approaches the signal line.

[0013] Further, in the digital phase-shifting circuit according to any one of Embodiments 1 to 5 of the present invention, at least one of the cross-sectional area of the first outer line and the cross-sectional area of the second outer line is smaller than at least one of the cross-sectional area of the signal line, the cross-sectional area of the first inner line, and the cross-sectional area of the second inner line.

[0014] According to the above aspect of the present invention, it is possible to provide a digital phase-shifting circuit that can easily achieve both an increase in the phase shift amount and size reduction.

[0015] It is a plan view showing a digital phase-shifting circuit according to a first embodiment. It is a perspective view showing the configuration of a digital phase-shifting circuit according to a first embodiment. It is a diagram for explaining a low-delay mode of a digital phase-shifting circuit according to a first embodiment. It is a diagram for explaining a high-delay mode of a digital phase-shifting circuit according to a first embodiment. It is a plan view showing a conventional digital phase-shifting circuit. It is a plan view showing a digital phase-shifting circuit according to a second embodiment. It is a plan view showing a digital phase-shifting circuit according to a third embodiment. It is a plan view showing a digital phase-shifting circuit according to a fourth embodiment. It is a plan view showing a digital phase-shifting circuit according to a modified example of a third embodiment.

[0016] Hereinafter, a digital phase-shifting circuit according to an embodiment of the present invention will be described with reference to the drawings.

[0017] (First Embodiment) The digital phase-shifting circuit 10 according to the first embodiment of the present invention is a high-frequency circuit that inputs a high-frequency signal such as a microwave, a quasi-millimeter wave, or a millimeter wave, and outputs an externally a high-frequency signal whose phase has been shifted by a predetermined phase shift amount.

[0018] <Configuration of the Digital Phase Shift Circuit> Figure 1 is a plan view showing the digital phase shift circuit 10 according to this embodiment. Figure 2 is a perspective view showing the configuration of the digital phase shift circuit 10 according to this embodiment. As shown in Figures 1 and 2, the digital phase shift circuit 10 includes a signal line 1, a pair of inner lines 2 (first inner line 2a and second inner line 2b), a pair of outer lines 3 (first outer line 3a and second outer line 3b), a pair of ground conductors 4 (first ground conductor 4a and second ground conductor 4b), a capacitor 5, a plurality of connecting conductors 6, four electronic switches 7 (first electronic switch 7a, second electronic switch 7b, third electronic switch 7c and fourth electronic switch 7d), and a switch control unit 8.

[0019] As shown in Figures 1 and 2, the signal line 1 is a straight, strip-shaped conductor extending in one direction. That is, the signal line 1 is a long, plate-shaped conductor having a certain width, a certain thickness, and a predetermined length. In the example shown in Figure 2, the signal S flows through the signal line 1 from the front end (input end) to the back end (output end). In Figure 1, the input end corresponds to the left end of the signal line 1, and the output end corresponds to the right end of the signal line 1. This signal S is a high-frequency signal such as microwave, quasi-millimeter wave, or millimeter wave as described above.

[0020] In this specification, the longitudinal direction of signal line 1 (the direction in which signal line 1 extends) is simply referred to as the longitudinal direction X. The direction from the input end to the output end of signal line 1 along the longitudinal direction X is referred to as the rightward direction and is represented by the +X direction in the figures. The direction opposite to the rightward direction is referred to as the leftward direction and is represented by the -X direction in the figures. The direction that intersects (for example, perpendicular to) the longitudinal direction X is referred to as the intersecting direction Y. One direction along the intersecting direction Y is referred to as the far side and is represented by the +Y direction in the figures. The direction opposite to the far side is referred to as the near side and is represented by the -Y direction in the figures. In addition, the direction along the intersecting direction Y that approaches the center line O of signal line 1 may be referred to as the "inside in the intersecting direction Y" or simply the "inside". The direction along the intersecting direction Y that moves away from the center line O of signal line 1 may be referred to as the "outside in the intersecting direction Y" or simply the "outside". The direction that intersects both the longitudinal direction X and the intersecting direction Y (for example, perpendicular to them) is called the vertical direction Z. One direction along the vertical direction Z is called "up" and is represented by the +Z direction in the diagram. The direction opposite to "up" is called "down" and is represented by the -Z direction in the diagram. Viewing from the vertical direction Z is called a plan view. Note that the vertical direction Z does not have to coincide with the direction parallel to gravity (the direction of gravity). Also, "up" and "down" do not have to coincide with the up and down directions in the direction of gravity. Furthermore, instead of defining the +X direction and the -X direction as left and right, respectively, the +X direction and the -X direction may be defined as right and left, respectively.

[0021] The signal line 1 has an inductance L1 as an electrically lumped-element circuit element. This inductance L1 is a parasitic inductance whose size depends on the shape of the signal line 1, such as its length. The signal line 1 also has a capacitance C1 as an electrically lumped-element circuit element. This capacitance C1 is a parasitic capacitance between the signal line 1 and the inner line 2, between the signal line 1 and the outer line 3, or between the signal line 1 and the silicon substrate (not shown). Of the ends of the signal line 1, the end located on the +X side is called the first end (one end), and the end located on the -X side is called the second end (the other end).

[0022] The pair of inner lines 2a and 2b are straight, strip-shaped conductors provided on both sides of the signal line 1.

[0023] In the following description, one side of the signal line 1 in the Y direction (-Y side) will be referred to as the first side of the signal line 1, and the other side of the signal line 1 in the Y direction (+Y side) will be referred to as the second side of the signal line 1. The first inner line 2a is provided on the first side (-Y side) of the signal line 1. The first inner line 2a is a long, plate-shaped conductor having a certain width, a certain thickness, and a predetermined length. The first inner line 2a extends parallel to the signal line 1 (in the longitudinal direction X). The first inner line 2a and the signal line 1 are spaced apart in the intersecting direction Y. Of the ends of the first inner line 2a, the end located on the +X side will be referred to as the first end (one end), and the end located on the -X side will be referred to as the second end (the other end).

[0024] The second inner track 2b is located on the second side (+Y side) of the signal line 1. The second inner track 2b is a long, plate-shaped conductor having a certain width, a certain thickness, and a predetermined length. The second inner track 2b extends parallel to the signal line 1 (in the longitudinal direction X). The second inner track 2b and the signal line 1 are spaced apart in the intersecting direction Y. Of the ends of the second inner track 2b, the end located on the +X side is called the first end (one end), and the end located on the -X side is called the second end (the other end).

[0025] The pair of outer tracks 3a and 3b are strip-shaped conductors provided on the outside of the inner track 2, respectively.

[0026] The first outer track 3a is located on the first side (-Y side) of the signal track 1, outside the first inner track 2a. The first outer track 3a and the first inner track 2a are spaced apart in the crossing direction Y. The first outer track 3a and the signal track 1 are also spaced apart in the crossing direction Y. The first inner track 2a described above is located between the signal track 1 and the first outer track 3a in the crossing direction Y. Of the ends of the first outer track 3a, the end located on the +X side is called the first end (one end), and the end located on the -X side is called the second end (the other end).

[0027] The second outer track 3b is located on the second side (+Y side) of the signal track 1, outside the second inner track 2b. The second outer track 3b and the second inner track 2b are spaced apart in the crossing direction Y. The second outer track 3b and the signal track 1 are also spaced apart in the crossing direction Y. The second inner track 2b described above is located between the signal track 1 and the second outer track 3b in the crossing direction Y. Of the ends of the second outer track 3b, the end located on the +X side is called the first end (one end), and the end located on the -X side is called the second end (the other end).

[0028] The widths of the outer tracks 3a and 3b may be smaller than at least one of the widths of the inner tracks 2a and 2b and the width of the signal track 1 (first condition). Specifically, the first condition means that at least one of the widths of the first outer track 3a and the second outer track 3b is smaller than at least one of the widths of the first inner track 2a, the second inner track 2b, and the width of the signal track 1. Also, the thicknesses of the outer tracks 3a and 3b may be smaller than at least one of the thicknesses of the inner tracks 2a and 2b and the thickness of the signal track 1 (second condition). Specifically, the second condition means that at least one of the thicknesses of the first outer track 3a and the second outer track 3b is smaller than at least one of the thicknesses of the first inner track 2a, the second inner track 2b, and the thickness of the signal track 1. Alternatively, both the first and second conditions may be adopted. In other words, the cross-sectional areas of the outer lines 3a and 3b may be smaller than at least one of the cross-sectional areas of the inner lines 2a and 2b and the cross-sectional area of ​​the signal line 1. Specifically, at least one of the cross-sectional areas of the first outer line 3a and the second outer line 3b may be smaller than at least one of the cross-sectional areas of the first inner line 2a, the second inner line 2b, and the signal line 1. This will result in the inductance Lg described later. high By increasing this value, the amount of phase shift can be increased.

[0029] In this embodiment, each of the pair of outer lines 3a and 3b extends non-linearly in a plan view. In other words, each of the pair of outer lines 3a and 3b is a curved line 20 having a bent shape in a plan view. The curved line 20 will be described in detail below. In this embodiment, the shape of the first outer line 3a and the shape of the second outer line 3b are symmetrical with respect to the center line O of the signal line 1. Therefore, unless otherwise specified, the first outer line 3a and the second outer line 3b will not be distinguished in the following description.

[0030] The curved track 20 according to this embodiment includes two shifted tracks 21 and 22, and an outward-convex track 23.

[0031] The shift line 21 is a long, plate-shaped conductor having a certain width, a certain thickness, and a predetermined length. The length of the shift line 21 is shorter than the length of the signal line 1. The shift line 21 extends parallel to the signal line 1 (in the longitudinal direction X). The shift line 21 is located at the second end (left end) of the outer line 3, which is the curved line 20. The shift line 21 has an inner end, which is the end located on the inside in the longitudinal direction X.

[0032] The shift line 22 is a long, plate-shaped conductor having a certain width, a certain thickness, and a predetermined length. The length of the shift line 22 is shorter than the length of the signal line 1. The length of the shift line 22 may be equal to the length of the shift line 21. The shift line 22 extends parallel to the signal line 1 (in the longitudinal direction X). The shift line 22 is located at the first end (right end) of the outer line 3, which is the curved line 20. The shift line 22 has an inner end, which is the end located on the inside in the longitudinal direction X.

[0033] The outward-protruding track 23 connects the inner end of the shift track 21 and the inner end of the shift track 22. The outward-protruding track 23 according to this embodiment includes a first crossing track 23c1, a second crossing track 23c2, and a parallel track 23p.

[0034] The first crossing line 23c1 is a straight, strip-shaped conductor connected to the inner end of the shift line 21. The first crossing line 23c1 is a long, plate-shaped conductor having a certain width, a certain thickness, and a predetermined length. The first crossing line 23c1 extends outward in the crossing direction Y from the inner end of the shift line 21. In other words, the first crossing line 23c1 extends away from the signal line 1 in the crossing direction Y from the inner end of the shift line 21. The first crossing line 23c1 has an outer end, which is the end located on the outside in the crossing direction Y.

[0035] The second crossing line 23c2 is a straight, strip-shaped conductor connected to the inner end of the shift line 22. The second crossing line 23c2 is a long, plate-shaped conductor having a certain width, a certain thickness, and a predetermined length. The second crossing line 23c2 extends outward in the crossing direction Y from the inner end of the shift line 22. In other words, the second crossing line 23c2 extends away from the signal line 1 in the crossing direction Y from the inner end of the shift line 22. The second crossing line 23c2 has an outer end, which is the end located on the outside in the crossing direction Y.

[0036] The parallel line 23p is a straight, strip-shaped conductor. The parallel line 23p connects the outer end of the first crossing line 23c1 to the outer end of the second crossing line 23c2. The parallel line 23p is a long, plate-shaped conductor having a constant width, a constant thickness, and a predetermined length. The length of the parallel line 23p is shorter than the length of the signal line 1. The parallel line 23p extends parallel to the signal line 1 (in the longitudinal direction X).

[0037] As shown in Figure 1, the outward-convex track 23 configured as described above has a convex shape that moves away from the signal track 1 in the crossing direction Y. That is, the outward-convex track 23 has a convex shape that is directed outward in the crossing direction Y.

[0038] Furthermore, the curved track 20 according to this embodiment has a shape that is symmetrical in the longitudinal direction X. Therefore, in each curved track 20, the positions of the shifted tracks 21 and 22 in the intersection direction Y are equal to each other. Also, in each curved track 20, the lengths of the intersecting tracks 23c1 and 23c2 are equal to each other.

[0039] The first grounding conductor 4a is a straight, strip-shaped conductor provided on the side where the first end (right end) of the first inner line 2a, the first end (right end) of the second inner line 2b, the first end (right end) of the first outer line 3a, and the first end (right end) of the second outer line 3b are located. That is, the first grounding conductor 4a is a long, plate-shaped conductor having a certain width, a certain thickness, and a certain length. The first grounding conductor 4a is electrically grounded. In this embodiment, the first grounding conductor 4a extends in the intersecting direction Y. Of the ends of the first grounding conductor 4a, the end located on the -Y side is referred to as the first end (one end), and the end located on the +Y side is referred to as the second end (the other end).

[0040] Furthermore, the first grounding conductor 4a is located below the first inner line 2a, the second inner line 2b, the first outer line 3a, and the second outer line 3b at a predetermined distance (see also Figure 2). In other words, in the vertical direction Z, a certain distance is provided between the first end (right end) of the first inner line 2a, the first end (right end) of the second inner line 2b, the first end (right end) of the first outer line 3a, and the first end (right end) of the second outer line 3b, and the first grounding conductor 4a.

[0041] Here, both ends of the first grounding conductor 4a in the crossing direction Y and the outer edge of the shift line 22 in the crossing direction Y are in approximately the same position in the crossing direction Y (see also Figure 2). That is, the first end (-Y end) of the first grounding conductor 4a in the crossing direction Y is in approximately the same position in the crossing direction Y as the outer edge (-Y side edge) of the shift line 22 of the first outer line 3a in the crossing direction Y. Similarly, the second end (+Y end) of the first grounding conductor 4a in the crossing direction Y is in approximately the same position in the crossing direction Y as the outer edge (+Y side edge) of the shift line 22 of the second outer line 3b in the crossing direction Y.

[0042] The second grounding conductor 4b is a straight, strip-shaped conductor provided on the side where the second end (left end) of the first inner line 2a, the second end (left end) of the second inner line 2b, the second end (left end) of the first outer line 3a, and the second end (left end) of the second outer line 3b are located. That is, the second grounding conductor 4b is a long, plate-shaped conductor having a certain width, a certain thickness, and a certain length. The second grounding conductor 4b is electrically grounded. In this embodiment, the second grounding conductor 4b extends in the intersecting direction Y. Of the ends of the second grounding conductor 4b, the end located on the -Y side is referred to as the first end (one end), and the end located on the +Y side is referred to as the second end (the other end).

[0043] Furthermore, the second grounding conductor 4b is located below the first inner line 2a, the second inner line 2b, the first outer line 3a, and the second outer line 3b at a predetermined distance (see also Figure 2). In other words, in the vertical direction Z, a certain distance is provided between the second end (left end) of the first inner line 2a, the second end (left end) of the second inner line 2b, the second end (left end) of the first outer line 3a, and the second end (left end) of the second outer line 3b and the second grounding conductor 4b.

[0044] Here, both ends of the second grounding conductor 4b in the crossing direction Y and the outer edge of the shift line 21 in the crossing direction Y are in approximately the same position in the crossing direction Y (see also Figure 2). That is, the first end (-Y end) of the second grounding conductor 4b in the crossing direction Y is in approximately the same position in the crossing direction Y as the outer edge (-Y side edge) of the shift line 21 of the first outer line 3a in the crossing direction Y. Similarly, the second end (+Y end) of the second grounding conductor 4b in the crossing direction Y is in approximately the same position in the crossing direction Y as the outer edge (+Y side edge) of the shift line 21 of the second outer line 3b in the crossing direction Y.

[0045] As shown in Figure 2, capacitor 5 is provided between the input terminal of signal line 1 and the second ground conductor 4b. Capacitor 5 is a parallel plate having an upper electrode and a lower electrode. The upper electrode is connected to signal line 1, and the lower electrode is connected to the second ground conductor 4b via a fourth electronic switch 7d. Capacitor 5 has a capacitance Ca corresponding to the opposing area of ​​the parallel plate. That is, this capacitance Ca is a circuit constant provided between signal line 1 and the second ground conductor 4b. However, capacitor 5 may be a comb-type capacitor or the like.

[0046] The plurality of connecting conductors 6 include at least a first connecting conductor 6a, a second connecting conductor 6b, a third connecting conductor 6c, a fourth connecting conductor 6d, a fifth connecting conductor 6e, and a sixth connecting conductor 6f. The plurality of connecting conductors 6 according to this embodiment further includes a seventh connecting conductor 6g.

[0047] The first connecting conductor 6a is a conductor that electrically and mechanically connects the first end of the first inner line 2a to the first grounding conductor 4a. For example, the first connecting conductor 6a is a conductor that extends in the vertical direction Z and has a first end (upper end) and a second end (lower end). The first end (upper end) is connected to the lower surface of the first inner line 2a, and the second end (lower end) is connected to the upper surface of the first grounding conductor 4a.

[0048] The second connecting conductor 6b is a conductor that electrically and mechanically connects the first end of the second inner line 2b to the first grounding conductor 4a. For example, the second connecting conductor 6b is a conductor that extends in the vertical direction Z, similar to the first connecting conductor 6a, and has a first end (upper end) and a second end (lower end). The first end (upper end) is connected to the lower surface of the second inner line 2b, and the second end (lower end) is connected to the upper surface of the first grounding conductor 4a.

[0049] The third connecting conductor 6c is a conductor that electrically and mechanically connects the first end of the first outer line 3a (in this embodiment, the end where the shift line 22 is located) to the first grounding conductor 4a. For example, the third connecting conductor 6c is a conductor that extends in the vertical direction Z and has a first end (upper end) and a second end (lower end). The first end (upper end) is connected to the lower surface of the first outer line 3a, and the second end (lower end) is connected to the upper surface of the first grounding conductor 4a.

[0050] The fourth connecting conductor 6d is a conductor that electrically and mechanically connects the second end of the first outer line 3a (in this embodiment, the end where the shift line 21 is located) and the second grounding conductor 4b. For example, the fourth connecting conductor 6d is a conductor that extends in the vertical direction Z and has a first end (upper end) and a second end (lower end). The first end (upper end) is connected to the lower surface of the first outer line 3a, and the second end (lower end) is connected to the upper surface of the second grounding conductor 4b.

[0051] The fifth connecting conductor 6e is a conductor that electrically and mechanically connects the first end of the second outer line 3b (in this embodiment, the end where the shift line 22 is located) to the first grounding conductor 4a. For example, the fifth connecting conductor 6e is a conductor that extends in the vertical direction Z and has a first end (upper end) and a second end (lower end). The first end (upper end) is connected to the lower surface of the second outer line 3b, and the second end (lower end) is connected to the upper surface of the first grounding conductor 4a.

[0052] The sixth connecting conductor 6f is a conductor that electrically and mechanically connects the second end of the second outer line 3b (in this embodiment, the end where the shift line 21 is located) and the second grounding conductor 4b. For example, the sixth connecting conductor 6f is a conductor that extends in the vertical direction Z and has a first end (upper end) and a second end (lower end). The first end (upper end) is connected to the lower surface of the second outer line 3b, and the second end (lower end) is connected to the upper surface of the second grounding conductor 4b.

[0053] The seventh connecting conductor 6g is a conductor that electrically and mechanically connects the second end of the signal line 1 to the upper electrode of the capacitor 5. For example, the seventh connecting conductor 6g is a conductor that extends in the vertical direction Z and has a first end (upper end) and a second end (lower end). The first end (upper end) is connected to the lower surface of the second end of the signal line 1, and the second end (lower end) is connected to the upper electrode of the capacitor 5.

[0054] The first electronic switch 7a is connected between the second end of the first inner line 2a and the second ground conductor 4b. The first electronic switch 7a is, for example, a MOS-type FET (field-effect transistor) having a drain terminal, a source terminal, and a gate terminal. The drain terminal is electrically connected to the second end of the first inner line 2a, the source terminal is electrically connected to the second ground conductor 4b, and the gate terminal is electrically connected to the switch control unit 8.

[0055] The first electronic switch 7a is controlled to be either closed or open based on a gate signal input to the gate terminal from the switch control unit 8. The closed state is a state in which the drain terminal and source terminal are conducting. The open state is a state in which the drain terminal and source terminal are not conducting, and the electrical connection between these terminals is interrupted. The first electronic switch 7a, under the control of the switch control unit 8, sets the second end of the first inner line 2a and the second ground conductor 4b to a conducting state in which they are electrically connected, or to an interrupted state in which their electrical connection is interrupted.

[0056] The second electronic switch 7b is connected between the second end of the second inner line 2b and the second ground conductor 4b. The second electronic switch 7b is, for example, a MOS-type FET having a drain terminal, a source terminal, and a gate terminal. The drain terminal is electrically connected to the second end of the second inner line 2b, the source terminal is electrically connected to the second ground conductor 4b, and the gate terminal is electrically connected to the switch control unit 8.

[0057] The second electronic switch 7b is controlled to be either closed or open based on a gate signal input to the gate terminal from the switch control unit 8. The second electronic switch 7b, under the control of the switch control unit 8, causes the second end of the second inner line 2b and the second ground conductor 4b to be in a conductive state where they are electrically connected, or in a disconnected state where their electrical connection is broken.

[0058] The third electronic switch 7c is connected between the second end of the signal line 1 and the second ground conductor 4b. The third electronic switch 7c is, for example, a MOS-type FET having a drain terminal, a source terminal, and a gate terminal. The drain terminal is electrically connected to the second end of the signal line 1, the source terminal is electrically connected to the second ground conductor 4b, and the gate terminal is electrically connected to the switch control unit 8. In the example shown in Figure 2, the third electronic switch 7c is provided on the second end side of the signal line 1, but the position of the third electronic switch 7c is not limited to this. The third electronic switch 7c may also be provided on the first end side of the signal line 1. The third electronic switch 7c may not be used if it is not necessary.

[0059] The third electronic switch 7c is controlled to be either closed or open based on a gate signal input to the gate terminal from the switch control unit 8. The third electronic switch 7c, under the control of the switch control unit 8, causes the second end of the signal line 1 and the second ground conductor 4b to be in a conductive state where they are electrically connected, or in a disconnected state where their electrical connection is broken.

[0060] The fourth electronic switch 7d is connected in series with the capacitor 5 between the second end of the signal line 1 and the second ground conductor 4b. The fourth electronic switch 7d is, for example, a MOS-type FET having a drain terminal, a source terminal, and a gate terminal. In the example shown in Figure 2, the drain terminal of the fourth electronic switch 7d is electrically connected to the lower electrode of the capacitor 5, the source terminal of the fourth electronic switch 7d is electrically connected to the second ground conductor 4b, and the gate terminal of the fourth electronic switch 7d is electrically connected to the switch control unit 8.

[0061] The fourth electronic switch 7d is controlled to be either closed or open based on a gate signal input to the gate terminal from the switch control unit 8. The fourth electronic switch 7d, under the control of the switch control unit 8, causes the lower electrode of the capacitor 5 and the second ground conductor 4b to be in a conductive state where they are electrically connected, or in a disconnected state where their electrical connection is broken.

[0062] The switch control unit 8 is a control circuit that controls a plurality of electronic switches 7, namely the first electronic switch 7a, the second electronic switch 7b, the third electronic switch 7c, and the fourth electronic switch 7d. For example, the switch control unit 8 has four output ports that correspond one-to-one with the four electronic switches 7. The switch control unit 8 outputs individual gate signals from each output port and supplies these gate signals to the gate terminals of the corresponding electronic switches 7. In this way, the switch control unit 8 controls each of the plurality of electronic switches 7 individually to an open or closed state.

[0063] Figure 2 shows a schematic diagram of the digital phase shift circuit 10 from an oblique angle to make its mechanical structure easier to understand. However, the actual digital phase shift circuit 10 is formed as a multilayer structure using semiconductor manufacturing technology.

[0064] As an example, the digital phase shift circuit 10 has a signal line 1, a first inner line 2a, a second inner line 2b, a first outer line 3a, and a second outer line 3b formed in the first conductive layer. The first ground conductor 4a and the second ground conductor 4b are formed in the second conductive layer, which is opposite the first conductive layer with an insulating layer in between. The components formed in the first conductive layer and the components formed in the second conductive layer are interconnected by via holes. Multiple connecting conductors 6 correspond to via holes embedded in the insulating layer.

[0065] <Operation of the Digital Phase Shift Circuit> Next, the operation of the digital phase shift circuit 10 configured as described above will be explained.

[0066] The digital phase shift circuit 10 according to this embodiment switches its operating mode according to the conduction state of the first electronic switch 7a, the second electronic switch 7b, and the fourth electronic switch 7d. Specifically, the operating modes of the digital phase shift circuit 10 include a low-latency mode in which the switch control unit 8 sets the first electronic switch 7a and the second electronic switch 7b to a closed state and the fourth electronic switch 7d to an open state, and a high-latency mode in which the switch control unit 8 sets the first electronic switch 7a and the second electronic switch 7b to an open state and the fourth electronic switch 7d to a closed state.

[0067] <<Low-Latency Mode>> Figure 3 illustrates the low-latency mode of the digital phase shift circuit 10 according to this embodiment. In low-latency mode, the switch control unit 8 sets the first electronic switch 7a and the second electronic switch 7b to the closed state and the fourth electronic switch 7d to the open state. That is, in low-latency mode, the first propagation delay time T is the time it takes for the high-frequency signal to propagate from the input end to the output end of the signal line 1. Ｌ As a result, the phase at the output terminal is the second phase θ in the high-delay mode. Ｈ A first phase θ smaller than Ｌ This is the result. The low-latency mode will be explained in more detail below.

[0068] When the first electronic switch 7a is set to the closed position, the second end of the first inner line 2a is connected to the second grounding conductor 4b. On the other hand, the first end of the first inner line 2a is always connected to the first grounding conductor 4a via the first connecting conductor 6a. Therefore, the second end of the first inner line 2a is connected to the second grounding conductor 4b via the first electronic switch 7a, thereby forming a first current-carrying path through which current can flow between the first and second ends.

[0069] Furthermore, when the second electronic switch 7b is set to the closed position, the second end of the second inner line 2b is connected to the second grounding conductor 4b. On the other hand, the first end of the second inner line 2b is always connected to the first grounding conductor 4a via the second connecting conductor 6b. Therefore, the second inner line 2b forms a second current-carrying path between its first and second ends, through which current can flow, by having its second end connected to the second grounding conductor 4b via the second electronic switch 7b.

[0070] When both ends of the first inner line 2a and the second inner line 2b are connected to the ground conductors 4a and 4b, and a signal current (signal S) flows through the signal line 1 from the input end to the output end, a return current is generated in the first inner line 2a and the second inner line 2b due to this propagation. This return current flows through the first inner line 2a and the second inner line 2b from the first end to the second end.

[0071] That is, a first return current flows in the first inner line 2a forming the first current conduction path, in a direction opposite to the direction of the signal current in the signal line 1 due to the conduction of the signal current in the signal line 1. Further, a second return current flows in the second inner line 2b forming the second current conduction path, in a direction opposite to the direction of the signal current in the signal line 1, that is, in the same direction as the first return current, due to the conduction of the signal current in the signal line 1.

[0072] Here, both the first return current flowing in the first inner line 2a and the second return current flowing in the second inner line 2b are in directions opposite to the direction of the signal current conduction. Therefore, the first return current and the second return current act to reduce the inductance of the entire digital phase shift circuit 10 due to the electrical coupling (mutual induction) between the signal line 1 and the first inner line 2a and the electromagnetic coupling (mutual induction) between the signal line 1 and the second inner line 2b. Let the inductance of the signal line 1 be Ls low , the inductance of the return path (the first inner line 2a and the second inner line 2b) be Lg low , and the mutual inductance between the signal line 1 and the return path be M low . The overall inductance L low of the digital phase shift circuit 10 in the low delay mode low is Ls low + Lg low - M low

[0073] becomes. Also, as described above, the signal line 1 has a capacitance C1 as a parasitic capacitance. In the low delay mode, since the fourth electronic switch 7d is set to the open state, the capacitor 5 can be regarded as not being connected between the signal line 1 and the second ground conductor 4b. That is, the capacitance Ca of the capacitor 5 does not affect the high-frequency signal propagating through the signal line 1. Therefore, a first propagation delay time T １／２ proportional to (Lm × C1) Ｌ acts on the high-frequency signal propagating through the signal line 1.

[0074] And the phase of the high-frequency signal at the output end (the first end) of the signal line 1 is such a first propagation delay time T ＬAs a result, the phase θ of the high-frequency signal at the input terminal (second terminal) of the signal line 1 is greater than the phase of the first phase θ. Ｌ It is delayed by only L. In other words, in low-latency mode, the total inductance of the digital phase shift circuit 10 is due to the first return current and the second return current, resulting in an inductance L. low This reduces the propagation delay time.

[0075] In the low-latency mode, the loss of the signal line 1 may be intentionally increased by setting the third electronic switch 7c to the closed state. This loss is added to bring the output amplitude of the high-frequency signal in the low-latency mode closer to the output amplitude in the high-latency mode.

[0076] In other words, the loss of high-frequency signals in low-latency mode is significantly smaller than the loss of high-frequency signals in high-latency mode. This difference in loss leads to an amplitude difference in the high-frequency signals output from the digital phase shift circuit 10 when the operating mode is switched between low-latency mode and high-latency mode. To address this issue, the digital phase shift circuit 10 may eliminate the amplitude difference by setting the third electronic switch 7c to a closed state in low-latency mode.

[0077] ≪High-Latency Mode≫ Figure 4 is a diagram illustrating the high-latency mode of the digital phase shift circuit 10 according to this embodiment. In high-latency mode, the switch control unit 8 sets the first electronic switch 7a and the second electronic switch 7b to the open state and the fourth electronic switch 7d to the closed state. That is, in high-latency mode, the second propagation delay time T is the time it takes for the high-frequency signal to propagate from the input end to the output end of the signal line 1. Ｈ As a result, the phase at the output terminal is the first phase θ in the low-latency mode. Ｌ A second phase θ that is larger than Ｈ This is the result. The high-latency mode will be explained in more detail below.

[0078] As described above, in high-latency mode, the first electronic switch 7a and the second electronic switch 7b are set to the open state. Therefore, the first current path described above is not formed in the first inner line 2a, and the second current path described above is not formed in the second inner line 2b. Consequently, the first return current flowing through the first inner line 2a becomes extremely small, and the second return current flowing through the second inner line 2b becomes extremely small.

[0079] In contrast, the first end of the first outer line 3a is connected to the first ground conductor 4a via the third connecting conductor 6c, and the second end of the first outer line 3a is connected to the second ground conductor 4b via the fourth connecting conductor 6d. That is, the first outer line 3a has a third current-carrying path pre-formed between the first and second ends through which current can flow. Therefore, in high-latency mode, a third return current flows from the first end to the second end of the first outer line 3a due to the signal current in the signal line 1. This third return current is in the opposite direction to the direction of current flow of the signal current in the signal line 1. Therefore, the third return current acts to reduce the overall inductance of the digital phase shift circuit 10 due to electromagnetic coupling (mutual induction) between the signal line 1 and the first outer line 3a.

[0080] Furthermore, the first end of the second outer line 3b is connected to the first ground conductor 4a via the fifth connecting conductor 6e, and the second end of the second outer line 3b is connected to the second ground conductor 4b via the sixth connecting conductor 6f. In other words, the second outer line 3b has a pre-formed fourth current-carrying path through which current can flow between the first and second ends. Therefore, in high-latency mode, a fourth return current flows from the first end to the second end of the second outer line 3b due to the signal current in the signal line 1. This fourth return current is in the opposite direction to the direction of current flow of the signal current in the signal line 1. Therefore, the fourth return current acts to reduce the overall inductance of the digital phase shift circuit 10 due to electromagnetic coupling (mutual induction) between the signal line 1 and the second outer line 3b.

[0081] The inductance of signal line 1 is Ls highThe inductance of the return path (first outer line 3a and second outer line 3b) is Lg high The mutual inductance between signal line 1 and the return path is M. high Let's assume that Ls high = Ls low The total inductance L of the digital phase shift circuit 10 in high-latency mode. high Ls high +Lg high -M high This is the result.

[0082] Here, the distance between signal line 1 and outer lines 3a and 3b is greater than the distance between signal line 1 and inner lines 2a and 2b. Therefore, M low > M high The following holds true. Also, the outer tracks 3a and 3b are longer than the inner tracks 2a and 2b. This is because, while the inner tracks 2a and 2b are tracks that extend in a straight line in a plan view, the outer tracks 3a and 3b are curved tracks 20 that have a bent shape in a plan view. Since the outer tracks 3a and 3b are longer than the inner tracks 2a and 2b, Lg low <Lg high The following holds true. Therefore, L high > L low This holds true.

[0083] On the other hand, the signal line 1 has a capacitance C1 as a parasitic capacitance. Also, in the high-delay mode, the fourth electronic switch 7d is set to the closed state, so a capacitor 5 is connected between the signal line 1 and the second ground conductor 4b. That is, the signal line 1 has a capacitance Cb which is the sum of the capacitance Ca of the capacitor 5 and the capacitance C1 (parasitic capacitance). Therefore, the high-frequency signal propagating through the signal line 1 has the above-mentioned inductance L high The second propagation delay time T related to the sum of capacitance Cb and the total capacitance Cb. Ｈ It takes effect.

[0084] Furthermore, the phase of the high-frequency signal at the output terminal of the signal line 1 is such that the second propagation delay time T Ｈ As a result, the second phase θ is greater than the phase of the high-frequency signal at the input terminal of the signal line 1. ＨThe delay is only by a certain amount. In other words, in the high-latency mode, the propagation delay time increases compared to the low-latency mode due to the third and fourth return currents, and because the fourth electronic switch 7d is set to the closed state.

[0085] In high-latency mode, the third electronic switch 7c may be set to the open state. In other words, in high-latency mode, it is not necessary to intentionally increase the loss of the signal line 1. As a result, the output amplitude of the high-frequency signal in high-latency mode approaches that of the output amplitude in low-latency mode.

[0086] <Operation> Next, the operation of the digital phase shift circuit 10 configured as described above will be explained.

[0087] Conventionally, a digital phase shift circuit 10' as shown in Figure 5 is known. The digital phase shift circuit 10' includes a pair of inner lines 2 (first inner line 2a and second inner line 2b), a pair of outer lines 3 (first outer line 3a and second outer line 3b), and a pair of ground conductors 4 (first ground conductor 4a and second ground conductor 4b), etc. As shown in Figure 5, in the conventional digital phase shift circuit 10', each of the outer lines 3a and 3b has a linear shape in a plan view.

[0088] One way to increase the phase shift amount of this digital phase shift circuit 10' is to increase its size (i.e., its dimensions in the longitudinal direction X and the intersecting direction Y). However, such an increase in the size of the digital phase shift circuit 10' is not always desirable. Therefore, a novel digital phase shift circuit with a structure that easily achieves both an increase in phase shift amount and a reduction in size is desired.

[0089] To solve the above problems, in the digital phase shift circuit 10 according to this embodiment, each outer line 3a, 3b is a bent line 20 having a bent shape in a plan view (see Figure 1). As a result, the length of the outer lines 3a, 3b according to this embodiment is longer than the length of the conventional outer lines 3a, 3b which are straight in a plan view (see Figure 5). Therefore, in this embodiment, the inductance Lg described above highThe value of becomes larger compared to the conventional value. As a result, the overall inductance L of the digital phase shift circuit 10 in high-latency mode becomes larger. high Because the value of becomes larger, the amount of phase shift can be increased compared to the conventional digital phase shift circuit 10'.

[0090] Furthermore, the curved line 20 according to this embodiment includes an outward-convex line 23 having a convex shape that moves away from the signal line 1. In the outward-convex line 23, the distance between the outer lines 3a, 3b and the signal line 1 is larger than in the conventional design. Therefore, the mutual inductance M described above is high The value is expected to be smaller compared to the conventional value. The total inductance L of the digital phase shift circuit 10 in high-latency mode. high The value of is mutual inductance M high It increases in proportion to the decrease in [the current]. For this reason, it is expected that the amount of phase shift will increase further if the outward-facing convex track 23 has a convex shape so that it moves away from the signal track 1.

[0091] Furthermore, the digital phase shift circuit 10 according to this embodiment does not require an increase in the distance between the first ground conductor 4a and the second ground conductor 4b (i.e., the size of the digital phase shift circuit 10 in the longitudinal direction X) in order to obtain the increased phase shift amount described above. Therefore, the digital phase shift circuit 10 according to this embodiment makes it possible to obtain a larger phase shift amount compared to the conventional digital phase shift circuit 10' while also suppressing an increase in size in the longitudinal direction X.

[0092] <Summary> As described above, the digital phase shift circuit 10 according to this embodiment includes a signal line 1, a first inner line 2a provided on the first side of the signal line 1, a second inner line 2b provided on the second side of the signal line 1, a first outer line 3a provided on the outside of the first inner line 2a on the first side of the signal line 1, a second outer line 3b provided on the outside of the second inner line 2b on the second side of the signal line 1, the first end of the first inner line 2a, the first end of the second inner line 2b, and the first end of the first outer line 3a. The digital phase shift circuit 10 comprises a first grounding conductor 4a connected to the first end of the second outer line 3b, a second grounding conductor 4b connected to the second end of the first outer line 3a and the second end of the second outer line 3b, a first electronic switch 7a provided between the second end of the first inner line 2a and the second grounding conductor 4b, and a second electronic switch 7b provided between the second end of the second inner line 2b and the second grounding conductor 4b, wherein each of the first outer line 3a and the second outer line 3b is a bent line 20 having a bent shape in plan view. This configuration makes it possible to provide a digital phase shift circuit 10 that can achieve an increase in the amount of phase shift.

[0093] Furthermore, the curved track 20 includes an outward-convex track 23 that has a convex shape so as to move away from the signal track 1. This configuration allows for a further increase in the amount of phase shift.

[0094] Furthermore, at least one of the cross-sectional areas of the first outer line 3a and the second outer line 3b may be smaller than at least one of the cross-sectional areas of the signal line 1, the first inner line 2a, and the second inner line 2b. According to this configuration, the inductance Lg described above high By increasing this value, the phase shift amount can be further increased.

[0095] The specific values ​​of the phase shift amount achieved by the digital phase shift circuit 10 according to this embodiment will be shown in the examples described later, along with the values ​​in other embodiments.

[0096] (Second Embodiment) Next, a second embodiment will be described, but the basic configuration is the same as that of the first embodiment. For this reason, the same reference numerals are used for similar components, and their descriptions are omitted; only the differences will be described.

[0097] <Configuration of the Digital Phase Shift Circuit> Figure 6 is a plan view showing the digital phase shift circuit 10A according to the second embodiment. As shown in Figures 1 and 6, the digital phase shift circuit 10A according to the second embodiment differs from the digital phase shift circuit 10 according to the first embodiment in the shape of the curved line 20 (outer lines 3a, 3b). Specifically, the curved line 20 according to the second embodiment includes an inwardly convex line 24 instead of the outwardly convex line 23 according to the first embodiment.

[0098] Here, as shown in Figure 6, we define baseline B (the first baseline Ba and the second baseline Bb) and baseline region A. The first baseline Ba is a straight line passing through the outer edge (-Y side edge) in the intersection direction Y of the first end (shifted track 22) of the first outer track 3a and the outer edge (-Y side edge) in the intersection direction Y of the second end (shifted track 21) of the first outer track 3a. The second baseline Bb is a straight line passing through the outer edge (+Y side edge) in the intersection direction Y of the first end (shifted track 22) of the second outer track 3b and the outer edge (+Y side edge) in the intersection direction Y of the second end (shifted track 21) of the second outer track 3b. Each baseline Ba and Bb extends in the longitudinal direction X. Baseline region A is the region located between the two baselines Ba and Bb in a plan view.

[0099] The inwardly convex track 24 connects the inner end of the shift track 21 and the inner end of the shift track 22. The inwardly convex track 24 according to this embodiment includes a first crossing track 24c1, a second crossing track 24c2, and a parallel track 24p.

[0100] The first crossing line 24c1 is a straight, strip-shaped conductor connected to the inner end of the shift line 21. The first crossing line 24c1 is a long, plate-shaped conductor having a certain width, a certain thickness, and a predetermined length. The first crossing line 24c1 extends inward in the crossing direction Y from the inner end of the shift line 21. In other words, the first crossing line 24c1 extends from the inner end of the shift line 21 so as to approach the signal line 1 in the crossing direction Y. The first crossing line 24c1 has an inner end, which is the end located on the inside in the crossing direction Y.

[0101] The second crossing line 24c2 is a straight, strip-shaped conductor connected to the inner end of the shift line 22. The second crossing line 24c2 is a long, plate-shaped conductor having a certain width, a certain thickness, and a predetermined length. The second crossing line 24c2 extends inward in the crossing direction Y from the inner end of the shift line 22. In other words, the second crossing line 24c2 extends from the inner end of the shift line 22 so as to approach the signal line 1 in the crossing direction Y. The second crossing line 24c2 has an inner end, which is the end located on the inside in the crossing direction Y.

[0102] The parallel line 24p is a straight, strip-shaped conductor. The parallel line 24p connects the inner end of the first intersecting line 24c1 to the inner end of the second intersecting line 24c2. The parallel line 24p is a long, plate-shaped conductor having a constant width, a constant thickness, and a predetermined length. The parallel line 24p extends parallel to the signal line 1 (in the longitudinal direction X). The length of the parallel line 24p is shorter than the length of the signal line 1.

[0103] As shown in Figure 6, the inwardly convex track 24, configured as described above, has a convex shape that approaches the signal track 1 in the crossing direction Y. That is, the inwardly convex track 24 has a shape that is convex inward in the crossing direction Y.

[0104] Furthermore, the curved track 20 according to this embodiment has a shape that is symmetrical in the longitudinal direction X, similar to the first embodiment. Therefore, in each curved track 20, the lengths of the intersecting tracks 24c1 and 24c2 are equal to each other.

[0105] <Operation> In the digital phase shift circuit 10A according to this embodiment, as in the digital phase shift circuit 10 according to the first embodiment, each outer line 3a, 3b is a bent line 20. Therefore, in this embodiment as well, the inductance Lg described above high The value becomes larger compared to the conventional value, and the amount of phase shift can be increased compared to the conventional digital phase shift circuit 10'.

[0106] Furthermore, the curved line 20 according to this embodiment includes an inwardly convex line 24 having a convex shape that approaches the signal line 1. The method of providing the inwardly convex line 24 in the curved line 20 is less likely to increase the size of the digital phase shift circuit 10A in the crossing direction Y compared to the method of providing the outwardly convex line 23 in the curved line 20. In other words, by adopting the inwardly convex line 24, it is possible to increase the amount of phase shift while suppressing the increase in the size of the digital phase shift circuit 10A in the crossing direction Y. In particular, in the example shown in Figure 6, the entire outer lines 3a and 3b (the entire digital phase shift circuit 10A) are located within the baseline region A. This configuration is preferable in that it does not require an increase in the size in the crossing direction Y compared to the conventional digital phase shift circuit 10' (see Figure 5), and it is possible to more reliably suppress the increase in size in the crossing direction Y.

[0107] Furthermore, in the inwardly convex line 24, the distance between the outer lines 3a and 3b and the signal line 1 becomes smaller than in the conventional case. This is due to the mutual inductance M mentioned above. high This means that the value of mutual inductance M will be larger compared to the conventional value. high The increase in the total inductance L of the digital phase shift circuit 10 in high-latency mode high It acts to reduce the value of . For this reason, it seems that the presence of the inwardly convex track 24 in the curved track 20 may actually lead to a decrease in the amount of phase shift.

[0108] However, after diligent study by the inventors of the present invention, it was found that even if an inwardly convex line 24 is provided in the bent line 20, the amount of phase shift increases compared to the conventional method. As described in the first embodiment, because the outer line 3 is bent (i.e., the outer line 3 is the bent line 20), the inductance Lg of the outer line 3 high The value of increases. The reason why the phase shift amount increased even when an inwardly convex line 24 was provided in the bent line 20 is the inductance Lg high The increase in the value of the inductance L high The effect (positive effect) on the value is the mutual inductance M high The increase in inductance L high This is thought to be because the impact (negative effect) on the value was greater than the potential impact.

[0109] <Summary> As described above, in the digital phase shift circuit 10A according to this embodiment, the bent line 20 includes an inwardly convex line 24 having a convex shape that approaches the signal line 1. This configuration makes it possible to increase the amount of phase shift while suppressing an increase in the size of the digital phase shift circuit 10A. The specific values ​​of the amount of phase shift achieved by the digital phase shift circuit 10A according to this embodiment will be shown in the examples described later, along with the values ​​in other embodiments.

[0110] (Third Embodiment) Next, a third embodiment will be described, but the basic configuration is the same as that of the second embodiment. For this reason, the same reference numerals are used for similar components, and their descriptions are omitted; only the differences will be described.

[0111] <Configuration of the Digital Phase Shift Circuit> Figure 7 is a plan view showing the digital phase shift circuit 10B according to the third embodiment. As shown in Figures 6 and 7, the digital phase shift circuit 10B according to the third embodiment differs from the digital phase shift circuit 10A according to the second embodiment in the shape of the curved line 20 (outer lines 3a, 3b). Specifically, the curved line 20 according to the third embodiment differs from the digital phase shift circuit 10A according to the second embodiment in the shape of the inwardly convex line 24. More specifically, the inwardly convex line 24 according to the third embodiment includes a first inclined line 24d1 and a second inclined line 24d2 instead of the parallel line 24p according to the second embodiment.

[0112] The first inclined line 24d1 is a straight, strip-shaped conductor. The first inclined line 24d1 is a long, plate-shaped conductor having a certain width, a certain thickness, and a predetermined length. The first inclined line 24d1 is connected to the inner end of the first intersecting line 24c1. The first inclined line 24d1 extends in a direction inclined with respect to both the longitudinal direction X and the intersecting direction Y. Specifically, the first inclined line 24d1 extends from the inner end of the first intersecting line 24c1 so as to approach the signal line 1 in the intersecting direction Y and approach the first grounding conductor 4a in the longitudinal direction X.

[0113] The second inclined line 24d2 is a straight, strip-shaped conductor. The second inclined line 24d2 is a long, plate-shaped conductor having a certain width, a certain thickness, and a predetermined length. The second inclined line 24d2 is connected to the inner end of the second intersecting line 24c2. The second inclined line 24d2 extends in a direction inclined with respect to both the longitudinal direction X and the intersecting direction Y. Specifically, the second inclined line 24d2 extends from the inner end of the second intersecting line 24c2 so as to approach the signal line 1 in the intersecting direction Y and approach the second grounding conductor 4b in the longitudinal direction X.

[0114] The tip of the first inclined track 24d1 (the end closest to the signal track 1 in the crossing direction Y) is connected to the tip of the second inclined track 24d2 (the end closest to the signal track 1 in the crossing direction Y). As a result, the first inclined track 24d1 and the second inclined track 24d2 connect the inner end of the first intersecting track 24c1 and the inner end of the second intersecting track 24c2. The tips of the inclined tracks 24d1 and 24d2 (the tips of the inwardly protruding tracks 24) correspond to the parts of the inwardly protruding track 24 that are closest to the signal track 1.

[0115] Furthermore, the curved track 20 according to this embodiment has a shape that is symmetrical in the longitudinal direction X, similar to the second embodiment. Therefore, in each curved track 20, the lengths of the diagonal tracks 24d1 and 24d2 are equal to each other.

[0116] Furthermore, in the example shown in Figure 7, the first inclined track 24d1 extends in a direction inclined at 45° with respect to both the longitudinal direction X and the intersecting direction Y. Similarly, the second inclined track 24d2 extends in a direction inclined at 45° with respect to both the longitudinal direction X and the intersecting direction Y. As a result, in the example shown in Figure 7, the first inclined track 24d1 and the second inclined track 24d2 are perpendicular to each other. Note that the inclination angles of the inclined tracks 24d1 and 24d2 with respect to the longitudinal direction X and the intersecting direction Y can be changed as appropriate.

[0117] <Operation> In the digital phase shift circuit 10B according to this embodiment, as with the digital phase shift circuit 10 according to the first embodiment and the digital phase shift circuit 10A according to the second embodiment, each of the outer lines 3a and 3b is a bent line 20. Therefore, in this embodiment as well, the inductance Lg described above highThe value of becomes larger compared to the conventional value, and the amount of phase shift can be increased compared to the conventional digital phase shift circuit 10'. Furthermore, in the digital phase shift circuit 10B according to this embodiment, similar to the digital phase shift circuit 10A according to the second embodiment, the bent line 20 includes the inwardly convex line 24, and the entirety of the outer lines 3a and 3b are located within the baseline region A. Therefore, in this embodiment as well, the increase in size of the digital phase shift circuit 10B can be suppressed more reliably.

[0118] Furthermore, in this embodiment, at the tips of the inclined tracks 24d1 and 24d2, which are the parts of the inclined track 24 that are closest to the signal line 1 (hereinafter referred to as the nearest point), the inclined track 24 and the signal line 1 are not parallel. This is because each of the inclined tracks 24d1 and 24d2 is inclined with respect to the direction of extension of the signal line 1 (i.e., the longitudinal direction X).

[0119] When the nearest point of the inward-facing convex line 24 is not parallel to the signal line 1, the mutual inductance M described above is different compared to when the nearest point of the inward-facing convex line 24 is parallel to the signal line 1. high It is expected that the value of will decrease. In other words, according to this embodiment, the mutual inductance M caused by the fact that the bent line 20 includes the inwardly convex line 24 will decrease. high This suppresses the increase in and ensures a larger phase shift.

[0120] <Summary> As explained above, in the digital phase shift circuit 10B according to this embodiment, the inward-protruding line 24 and the signal line 1 are non-parallel at the portion of the inward-protruding line 24 that is closest to the signal line 1. This configuration makes it easier to secure a large phase shift amount while suppressing an increase in the size of the digital phase shift circuit 10B. The specific values ​​of the phase shift amount realized by the digital phase shift circuit 10B according to this embodiment will be shown in the examples described later, along with the values ​​in other embodiments.

[0121] (Fourth Embodiment) Next, the fourth embodiment will be described, but the basic configuration is the same as that of the first embodiment. For this reason, the same reference numerals are used for similar components, and their descriptions are omitted; only the differences will be described.

[0122] <Configuration of the Digital Phase Shift Circuit> Figure 8 is a plan view showing the digital phase shift circuit 10C according to the fourth embodiment. As shown in Figures 1 and 8, the digital phase shift circuit 10C according to the fourth embodiment differs from the digital phase shift circuit 10 according to the first embodiment in the shape of the curved line 20 (outer lines 3a, 3b). Specifically, the curved line 20 according to the fourth embodiment includes a meandering line 25 instead of the outward-convex line 23 according to the first embodiment.

[0123] The meandering track 25 connects the inner end of the shift track 21 and the inner end of the shift track 22. The meandering track 25 according to this embodiment includes a first crossing track 25c1, a second crossing track 25c2, a third crossing track 25c3, a first parallel track 25p1, and a second parallel track 25p2.

[0124] The first crossing line 25c1 is a straight, strip-shaped conductor connected to the inner end of the shift line 21. The first crossing line 25c1 is a long, plate-shaped conductor having a certain width, a certain thickness, and a predetermined length. The first crossing line 25c1 extends inward in the crossing direction Y from the inner end of the shift line 21. In other words, the first crossing line 25c1 extends from the inner end of the shift line 21 so as to approach the signal line 1 in the crossing direction Y.

[0125] The second crossing line 25c2 is a straight, strip-shaped conductor connected to the inner end of the shift line 22. The second crossing line 25c2 is a long, plate-shaped conductor having a constant width, a constant thickness, and a predetermined length. The second crossing line 25c2 extends outward in the crossing direction Y from the inner end of the shift line 22. In other words, the second crossing line 25c2 extends away from the signal line 1 in the crossing direction Y from the inner end of the shift line 22. The length of the second crossing line 25c2 is equal to the length of the first crossing line 25c1.

[0126] The first parallel line 25p1 is a straight, strip-shaped conductor. The first parallel line 25p1 is a long, plate-shaped conductor having a certain width, a certain thickness, and a predetermined length. The first parallel line 25p1 is connected to the end of the first crossing line 25c1 that is located on the inside in the crossing direction Y (hereinafter referred to as the inner end). The first parallel line 25p1 extends parallel to the signal line 1 (in the longitudinal direction X). Specifically, the first parallel line 25p1 extends from the inner end of the first crossing line 25c1 so as to approach the first grounding conductor 4a in the longitudinal direction X. The length of the first parallel line 25p1 is shorter than the length of the signal line 1. The first parallel line 25p1 has an inner end which is located on the inside in the longitudinal direction X.

[0127] The second parallel line 25p2 is a straight, strip-shaped conductor. The second parallel line 25p2 is a long, plate-shaped conductor having a certain width, a certain thickness, and a predetermined length. The second parallel line 25p2 is connected to the outer end (hereinafter referred to as the outer end) of the second crossing line 25c2, which is located in the crossing direction Y. The second parallel line 25p2 extends parallel to the signal line 1 (in the longitudinal direction X). Specifically, the second parallel line 25p2 extends from the outer end of the second crossing line 25c2 in the longitudinal direction X so as to approach the second grounding conductor 4b. The length of the second parallel line 25p2 is shorter than the length of the signal line 1. The length of the second parallel line 25p2 is equal to the length of the first parallel line 25p1. The second parallel line 25p2 has an inner end, which is located on the inside in the longitudinal direction X.

[0128] The third crossing line 25c3 is a straight, strip-shaped conductor. The third crossing line 25c3 connects the inner end of the first parallel line 25p1 to the inner end of the second parallel line 25p2. The third crossing line 25c3 is a long, plate-shaped conductor having a certain width, a certain thickness, and a predetermined length. The third crossing line 25c3 extends in the crossing direction Y. The length of the third crossing line 25c3 is longer than the length of both the first crossing line 25c1 and the second crossing line 25c2.

[0129] As shown in Figure 8, the meandering track 25 configured as described above has a meandering shape that extends in the longitudinal direction X while meandering in the intersecting direction Y. Here, it is also possible to interpret the meandering track 25 as including both the outward-convex track 23 in the first embodiment and the inward-convex track 24 in the second embodiment. That is, in the example in Figure 8, the first intersecting track 25c1, the first parallel track 25p1, and a part of the third intersecting track 25c3 (more specifically, the inner half in the intersecting direction Y) can be interpreted as constituting the inward-convex track 24. Similarly, a part of the third intersecting track 25c3 (more specifically, the outer half in the intersecting direction Y), the second parallel track 25p2, and the second intersecting track 25c2 can be interpreted as constituting the outward-convex track 23.

[0130] <Operation> In the digital phase shift circuit 10C according to this embodiment, as in the digital phase shift circuit 10 according to the first embodiment, each outer line 3a, 3b is a bent line 20. Therefore, in this embodiment as well, the inductance Lg described above high The value becomes larger compared to the conventional value, and the amount of phase shift can be increased compared to the conventional digital phase shift circuit 10'.

[0131] Furthermore, the curved line 20 according to this embodiment includes a meandering line 25 having a meandering shape that extends in the longitudinal direction X while meandering in the intersecting direction Y. In other words, the curved line 20 has both an outward-convex line 23 and an inward-convex line 24. This allows the length of the curved line 20 to be increased, thereby increasing the inductance Lg high The value of can be made even larger. In other words, the amount of phase shift of the digital phase shift circuit 10C can be further increased.

[0132] The curved track 20 may include a plurality of outward-convex tracks 23 and a plurality of inward-convex tracks 24 arranged alternately in the longitudinal direction X. Also, the number of outward-convex tracks 23 and the number of inward-convex tracks 24 included in the curved track 20 may be different. For example, the curved track 20 may include two inward-convex tracks 24 arranged at intervals in the longitudinal direction X, and one outward-convex track 23 connecting them.

[0133] <Summary> As described above, in the digital phase shift circuit 10C according to this embodiment, the bent line 20 includes both the outward-convex line 23 and the inward-convex line 24. This configuration allows for a further increase in the phase shift amount of the digital phase shift circuit 10C. The specific values ​​of the phase shift amount achieved by the digital phase shift circuit 10C according to this embodiment will be shown in the examples described later, along with the values ​​in other embodiments.

[0134] The above embodiments will be described below using specific examples. However, the present invention is not limited to the following embodiments.

[0135] Five digital phase shift circuits were prepared, corresponding to Examples 1 to 4 and the Comparative Example. Specifically, the digital phase shift circuit according to Example 1 is the digital phase shift circuit 10 (first embodiment) shown in Figure 1. The digital phase shift circuit according to Example 2 is the digital phase shift circuit 10A (second embodiment) shown in Figure 6. The digital phase shift circuit according to Example 3 is the digital phase shift circuit 10B (third embodiment) shown in Figure 7. The digital phase shift circuit according to Example 4 is the digital phase shift circuit 10C (fourth embodiment) shown in Figure 8. The digital phase shift circuit according to the Comparative Example is the digital phase shift circuit 10' (conventional example) shown in Figure 5.

[0136] Here, the only difference between the five digital phase shift circuits 10, 10A, 10B, 10C, and 10' was the shape of the outer lines 3a and 3b. For example, the size in the longitudinal direction X (the distance between the outer edge of the first grounding conductor 4a and the outer edge of the second grounding conductor 4b in the longitudinal direction X) was the same at 40 μm for the five digital phase shift circuits 10, 10A, 10B, 10C, and 10'. Similarly, the distance between the baselines Ba and Bb in the crossing direction Y was the same at 87.5 μm for the five digital phase shift circuits 10, 10A, 10B, 10C, and 10'. Furthermore, for the four digital phase shift circuits 10, 10A, 10B, and 10C, the lengths of the first crossing lines 23c1, 24c1, and 25c1 were all the same at 16 μm, and the lengths of the second crossing lines 23c2, 24c2, and 25c2 were all the same at 16 μm.

[0137] For each of the five digital phase shift circuits 10, 10A, 10B, 10C, and 10' relating to Examples 1 to 4 and the Comparative Example, the amount of phase shift at 29.5 GHz was calculated by simulation. The reference impedance was set to 30 Ω. Table 1 is a diagram summarizing the simulation results. In Table 1, "Amount of phase shift at 29.5 GHz" shows the amount of phase shift obtained by simulation. "Difference from reference" shows the difference in the amount of phase shift relative to the reference, when the phase shift amount of the Comparative Example is used as the reference.

[0138]

[0139] As shown in Table 1, it was confirmed that the phase shift amount in Examples 1 to 4 was greater than the phase shift amount in the comparative example. In other words, it was confirmed that by making the outer lines 3a and 3b into bent lines 20, the phase shift amount can be increased compared to the conventional digital phase shift circuit 10' in which the outer lines 3a and 3b extend in a straight line. Furthermore, as mentioned above, the size in the longitudinal direction X of the five digital phase shift circuits 10, 10A, 10B, 10C, and 10' is the same. This indicates that the phase shift amount can be increased by making the outer lines 3a and 3b into bent lines 20 without changing the size in the longitudinal direction X from the conventional method.

[0140] In particular, Embodiment 2 (digital phase shift circuit 10A according to the second embodiment) suggests that even when the bent line 20 includes an inward-convex line 24, the amount of phase shift can be increased compared to the conventional example. As described in the second embodiment, in the inward-convex line 24, the distance between the outer lines 3a, 3b and the signal line 1 is smaller than in the conventional example, and the mutual inductance M high The value of became larger, and it was thought that this could cause a decrease in the phase shift amount. However, the phase shift amount in Example 2 is greater than that of the Comparative Example. This is due to the inductance Lg of the outer line 3 being bent (i.e., the outer line 3 is a bent line 20). high The positive effect of the increase in mutual inductance M high This is thought to be because the negative impact of the increase outweighed the negative effects.

[0141] Furthermore, Example 3 (digital phase shift circuit 10B according to the third embodiment) has an even larger phase shift amount compared to Example 2. This is because the portion of the inwardly protruding line 24 that is closest to the signal line 1 is non-parallel to the signal line 1, and the mutual inductance M described above high This is thought to be because the value of is kept small. Also, the sum of the lengths of the inclined lines 24d1 and 24d2 (see Figure 7) is √2 times the length of the parallel line 24p (see Figure 6). This is because the inductance Lg of Example 3 high Since this value is larger compared to Example 2, it is considered that these differences in line length also contributed to the increase in phase shift.

[0142] (Variations) The technical scope of the present invention is not limited to the embodiments described above, and various modifications can be made without departing from the spirit of the present invention.

[0143] <Modification of the Third Embodiment> Figure 9 is a plan view showing a modified digital phase shift circuit 10D according to the third embodiment. As shown in Figures 7 and 9, the digital phase shift circuit 10D according to this modification differs from the digital phase shift circuit 10B according to the third embodiment in the shape of the bent line 20 (outer lines 3a, 3b). Specifically, the bent line 20 according to this modification differs from the digital phase shift circuit 10B according to the third embodiment in the shape of the inwardly convex line 24. More specifically, the inwardly convex line 24 according to this modification includes a first stepped line 24s1 and a second stepped line 24s2 instead of the first inclined line 24d1 and the second inclined line 24d2 according to the third embodiment.

[0144] The first stepped line 24s1 is a strip-shaped conductor having a stepped shape in plan view. That is, the first stepped line 24s1 has a plurality of parallel lines extending in the longitudinal direction X and a plurality of intersecting lines extending in the intersecting direction Y. Each parallel line is a long plate-shaped conductor having a certain width, a certain thickness, and a predetermined length. Each intersecting line is a long plate-shaped conductor having a certain width, a certain thickness, and a predetermined length. In the first stepped line 24s1, the plurality of intersecting lines and the plurality of parallel lines are connected alternately. The length of each parallel line in the first stepped line 24s1 is shorter than the length of the signal line 1. The length of each parallel line in the first stepped line 24s1 is shorter than the length of the parallel line 24p in the second embodiment (see Figure 6).

[0145] The first stepped track 24s1 is connected to the inner end of the first intersecting track 24c1. The first stepped track 24s1 extends from the inner end of the first intersecting track 24c1, alternating between parallel and intersecting tracks in a stepped manner, approaching the signal track 1 in the intersecting direction Y and approaching the first grounding conductor 4a in the longitudinal direction X.

[0146] The second stepped line 24s2 is a strip-shaped conductor having a stepped shape in plan view. That is, the second stepped line 24s2 has a plurality of parallel lines extending in the longitudinal direction X and a plurality of intersecting lines extending in the intersecting direction Y. Each parallel line is a long plate-shaped conductor having a certain width, a certain thickness, and a predetermined length. Each intersecting line is a long plate-shaped conductor having a certain width, a certain thickness, and a predetermined length. In the second stepped line 24s2, the plurality of intersecting lines and the plurality of parallel lines are connected alternately. The length of each parallel line in the second stepped line 24s2 is shorter than the length of signal line 1. The length of each parallel line in the second stepped line 24s2 is shorter than the length of parallel line 24p in the second embodiment (see Figure 6).

[0147] The second stepped track 24s2 is connected to the inner end of the second intersecting track 24c2. The second stepped track 24s2 extends from the inner end of the second intersecting track 24c2, alternating between parallel and intersecting tracks in a stepped manner, approaching the signal track 1 in the intersecting direction Y and approaching the second grounding conductor 4b in the longitudinal direction X.

[0148] Each of the first-tiered track 24s1 and the second-tiered track 24s2 extends such that the inwardly convex track 24 tapers as it approaches the signal line 1 in the crossing direction Y (i.e., the size of the inwardly convex track 24 in the longitudinal direction X decreases). The tip of the first-tiered track 24s1 (the end that is close to the signal line 1 in the crossing direction Y) is connected to the tip of the second-tiered track 24s2 (the end that is close to the signal line 1 in the crossing direction Y). In the illustrated example, a parallel track is located at the tip of the first-tiered track 24s1, and a parallel track is located at the tip of the second-tiered track 24s2. These two parallel tracks are connected to each other.

[0149] Furthermore, the curved track 20 according to this modified example has a shape that is symmetrical in the longitudinal direction X, similar to the third embodiment.

[0150] In this modified example, unlike the digital phase shift circuit 10B according to the third embodiment, the inward-protruding convex line 24 and the signal line 1 are parallel at the tips (parallel lines) of the stepped lines 24s1 and 24s2, which are the parts of the inward-protruding convex line 24 that are closest to the signal line 1 (nearest point). However, by adopting stepped lines 24s1 and 24s2, the length of the nearest point (parallel line) of the inward-protruding convex line 24 can be made sufficiently short. As a result, in this modified example as well, the mutual inductance M is the same as in the third embodiment. high It is thought that the increase can be suppressed. Also, the length of the stepped lines 24s1 and 24s2 in this modified example is longer than the length of the inclined lines 24d1 and 24d2 in the third embodiment. Therefore, compared to the third embodiment, the inductance Lg high It is thought that the value of can be increased. Therefore, it is expected that the amount of phase shift can be greatly increased by the digital phase shift circuit 10D according to this modified example.

[0151] As described above, in the digital phase shift circuit 10D according to this modified example, the inwardly convex line 24 includes stepped lines 24s1 and 24s2, each stepped line 24s1 and 24s2 includes a plurality of parallel lines extending parallel to the signal line 1 (longitudinal direction X) and a plurality of intersecting lines extending in a direction intersecting the signal line 1 (intersecting direction Y), and in each stepped line 24s1 and 24s2, the plurality of parallel lines and the plurality of intersecting lines are connected alternately, and each stepped line 24s1 and 24s2 extends such that the inwardly convex line 24 tapers as it approaches the signal line 1. With this configuration, the amount of phase shift of the digital phase shift circuit 10D can be further increased.

[0152] <Other Modifications> For example, in each of the digital phase shift circuits 10, 10A, 10B, 10C, and 10D described above, the bent line 20 does not have to include the shift line 21 (see Figures 1, 6, 7, 8, and 9). That is, in the longitudinal direction X, the first crossing lines 23c1, 24c1, 25c1 and the second grounding conductor 4b may be in the same position. Similarly, in each of the digital phase shift circuits 10, 10A, 10B, 10C, and 10D, the bent line 20 does not have to include the shift line 22. That is, in the longitudinal direction X, the second crossing lines 23c2, 24c2, 25c2 and the first grounding conductor 4a may be in the same position.

[0153] Furthermore, in each of the digital phase shift circuits 10B and 10D described above, the bent line 20 does not have to include the crossing lines 24c1 and 24c2. That is, the inclined lines 24d1 and 24d2 or the stepped lines 24s1 and 24s2 may be directly connected to the inner ends of the shift lines 21 and 22. Alternatively, in each of the digital phase shift circuits 10B and 10D, the bent line 20 does not have to include any of the shift lines 21 and 22 and the crossing lines 24c1 and 24c2. That is, the first inclined line 24d1 or the first stepped line 24s1 may be directly connected to the fourth connecting conductor 6d or the sixth connecting conductor 6f (see Figure 2), and the second inclined line 24d2 or the second stepped line 24s2 may be directly connected to the third connecting conductor 6c or the fifth connecting conductor 6e (see Figure 2). In other words, the first end of the outer track 3 may be located at the second inclined track 24d2 or the second stepped track 24s2, and the second end of the outer track 3 may be located at the first inclined track 24d1 or the first stepped track 24s1.

[0154] Furthermore, the shape of the curved line 20 (outer lines 3a, 3b) can be changed as appropriate, as long as it has a curved shape in plan view. For example, in each of the digital phase shift circuits 10, 10A, 10B, and 10D described above, the curved line 20 does not have to have a shape that is symmetrical in the longitudinal direction X.

[0155] Furthermore, the shapes of the first outer line 3a and the second outer line 3b do not have to be symmetrical with respect to the center line O of the signal line 1. For example, the shapes of the curved lines 20 may be different for the first outer line 3a and the second outer line 3b. Alternatively, only one of the first outer line 3a and the second outer line 3b may be a curved line 20. That is, one of the first outer line 3a and the second outer line 3b may be a parallel line extending parallel to the signal line 1 (in the longitudinal direction X). In other words, it is sufficient that at least one of the first outer line 3a and the second outer line 3b is a curved line 20. Even if only one of the first outer line 3a and the second outer line 3b is a curved line 20, it is expected that the same effects and advantages as those described in each of the above embodiments will be obtained.

[0156] Furthermore, a digital phase shifter (not shown) may be constructed by connecting multiple digital phase shift circuits 10, 10A, 10B, 10C, and 10D described above in cascading directions along the longitudinal direction X. In such a digital phase shifter, multiple phase shift amounts can be achieved for the digital phase shifter as a whole by independently switching the mode of each digital phase shift circuit 10, 10A, 10B, 10C, and 10D between a high-latency mode and a low-latency mode.

[0157] Furthermore, without departing from the spirit of the present invention, the components in the above-described embodiments may be replaced with well-known components as appropriate, and the above-described embodiments and modifications may be combined as appropriate.

[0158] 10, 10A, 10B, 10C, 10D... Digital phase shift circuit 1... Signal line 2a... First inner line 2b... Second inner line 3a... First outer line 3b... Second outer line 4a... First ground conductor 4b... Second ground conductor 7a... First electronic switch 7b... Second electronic switch 20... Bent line path 23... External convex line 24... Inner convex track 24s1... First stepped track (stepped track) 24s2... Second stepped track (stepped track)

Claims

1. A signal line comprising: a signal line; a first inner line provided on the first side of the signal line; a second inner line provided on the second side of the signal line; a first outer line provided on the outside of the first inner line on the first side of the signal line; a second outer line provided on the outside of the second inner line on the second side of the signal line; a first grounding conductor connected to the first end of the first inner line, the first end of the second inner line, the first end of the first outer line, and the first end of the second outer line; a second grounding conductor connected to the second end of the first outer line and the second end of the second outer line; a first electronic switch provided between the second end of the first inner line and the second grounding conductor; and a second electronic switch provided between the second end of the second inner line and the second grounding conductor. A digital phase shift circuit in which at least one of the first outer line and the second outer line is a curved line having a bent shape in a plan view.

2. The digital phase shift circuit according to claim 1, wherein the curved line includes an outward-convex line having a convex shape that moves away from the signal line.

3. The digital phase shift circuit according to claim 1 or 2, wherein the curved line includes an inwardly convex line having a convex shape that approaches the signal line.

4. The digital phase shift circuit according to claim 3, wherein the inward-facing convex line and the signal line are non-parallel at the portion of the inward-facing convex line closest to the signal line.

5. The digital phase shift circuit according to claim 3, wherein the convex inward line includes a stepped line, the stepped line includes a plurality of parallel lines extending parallel to the signal line and a plurality of intersecting lines extending in a direction intersecting the signal line, the plurality of parallel lines and the plurality of intersecting lines are alternately connected in the stepped line, and the stepped line extends such that the convex inward line tapers as it approaches the signal line.

6. The digital phase shift circuit according to any one of claims 1 to 5, wherein at least one of the cross-sectional area of ​​the first outer line and the cross-sectional area of ​​the second outer line is smaller than at least one of the cross-sectional area of ​​the signal line, the cross-sectional area of ​​the first inner line, and the cross-sectional area of ​​the second inner line.

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