Imaging device and camera system

Abstract

This imaging device comprises: a first substrate having a pixel region in which a plurality of pixels are arranged and a peripheral region adjacent to the pixel region, the first substrate including a semiconductor substrate and an insulating layer positioned above the semiconductor substrate; a pixel electrode positioned on the upper surface of the insulating layer in the pixel region; a photoelectric conversion layer positioned above the pixel electrode; a counter electrode positioned above the photoelectric conversion layer; a through electrode electrically connected to the pixels and penetrating the semiconductor substrate in the peripheral region; and a connection electrode positioned on the upper surface of the insulating layer in the peripheral region and electrically connected to the counter electrode. The through electrode is electrically insulated from the connection electrode. In plan view, at least a part of the through electrode overlaps the connection electrode.

Description

Imaging Device and Camera System

[0001] The present disclosure relates to an imaging device and a camera system.

[0002] In digital cameras and the like, imaging devices such as CCD (Charge Coupled Device) image sensors and CMOS (Complementary Metal Oxide Semiconductor) image sensors are widely used. As such an imaging device, an imaging device having a structure in which a substrate on which a pixel array formed of a plurality of pixels is formed and a substrate on which a circuit connected to the pixel array is formed are laminated has been proposed.

[0003] For example, Patent Document 1 discloses a technique for miniaturizing an image sensor by laminating a substrate on which a pixel region is formed and a substrate on which a drive circuit or the like is formed.

[0004] Japanese Unexamined Patent Application Publication No. 2022 - 18088

[0005] In the imaging device, further miniaturization is required.

[0006] The present disclosure provides an imaging device and the like that can be miniaturized.

[0007] An imaging device according to an aspect of the present disclosure is a first substrate having a pixel region in which a plurality of pixels are arranged and a peripheral region adjacent to the pixel region in a plan view, the first semiconductor substrate located in the pixel region and the peripheral region, and an insulating layer located above the first semiconductor substrate in the pixel region and the peripheral region. A first electrode located on the upper surface of the insulating layer in the pixel region, a photoelectric conversion layer located above the first electrode and converting light into charge, a second electrode located above the photoelectric conversion layer, a through electrode electrically connected to a first pixel among the plurality of pixels and penetrating the first semiconductor substrate in the peripheral region, and a third electrode located on the upper surface of the insulating layer in the peripheral region and electrically connected to the second electrode. The through electrode is electrically insulated from the third electrode, and in a plan view, at least a part of the through electrode overlaps either the third electrode or a gap formed in the third electrode.

[0008] A camera system according to one aspect of this disclosure includes the above-mentioned imaging device.

[0009] According to this disclosure, it is possible to provide an imaging device and the like that can be miniaturized.

[0010] Figure 1 is a block diagram showing an example of the configuration of an imaging device according to Embodiment 1. Figure 2 is a diagram showing an example of the circuit configuration of a pixel according to Embodiment 1. Figure 3 is a schematic cross-sectional view showing an example of the device structure of an imaging device according to Embodiment 1. Figure 4 is a schematic plan view showing an example of the planar layout of the first substrate of the imaging device according to Embodiment 1. Figure 5 is an enlarged view of the vicinity of line III-III in Figure 4. Figure 6 is a schematic plan view showing an example of the planar layout of the second substrate of the imaging device according to Embodiment 1. Figure 7 is a plan view illustrating another example of the planar shape of the connecting electrode according to Embodiment 1. Figure 8 is a plan view illustrating another planar layout of the connecting electrode with a gap formed therein according to Embodiment 1. Figure 9 is a schematic cross-sectional view showing an example of the device structure of an imaging device equipped with a connecting electrode with a gap formed therein according to Embodiment 1. Figure 10 is a schematic cross-sectional view showing an example of the device structure of an imaging device according to Modification 1 of Embodiment 1. Figure 11 is a schematic cross-sectional view showing an example of the device structure of an imaging device according to Modification 2 of Embodiment 1. Figure 12 is a schematic cross-sectional view showing an example of the device structure of an imaging device according to Modification 3 of Embodiment 1. Figure 13 is a schematic cross-sectional view showing an example of the device structure of an imaging device according to a modification 4 of Embodiment 1. Figure 14 is a schematic cross-sectional view showing an example of the device structure of an imaging device according to a modification 5 of Embodiment 1. Figure 15 is a block diagram showing an example of the configuration of a camera system according to Embodiment 2.

[0011] (Background to obtaining one aspect of this disclosure) In recent years, due to market demands for higher resolution imaging devices, the pixel size has been decreasing. There is also a demand for miniaturization of imaging devices, and development is underway on substrate-stacked imaging devices that stack two or more semiconductor substrates.

[0012] In a substrate-type imaging device, a pixel array that performs photoelectric conversion is arranged on a substrate including a semiconductor substrate placed on the light incidence side, and the pixel array is connected to another substrate by through-electrodes that penetrate the semiconductor substrate. The through-electrodes are used for transmitting control signals for driving the pixels and output signals from the pixels, as well as supplying voltage for driving the pixels. As pixel sizes become smaller and imaging devices become higher resolution, the number of through-electrodes becomes enormous, and the proportion of the substrate area occupied by groups of through-electrodes also increases.

[0013] In view of the above-mentioned problems, the inventors of the present invention focused on the fact that the imaging device can be miniaturized by the layout of the through-electrode, and have obtained one aspect of the present disclosure.

[0014] (Summary of this disclosure) An example of an imaging device and camera system related to this disclosure is shown below as an overview of this disclosure.

[0015] For example, an imaging apparatus according to a first aspect of the present disclosure is a first substrate having, in a plan view, a pixel region in which a plurality of pixels are arranged and a peripheral region adjacent to the pixel region, the first substrate including a first semiconductor substrate located in the pixel region and the peripheral region, and an insulating layer located above the first semiconductor substrate in the pixel region and the peripheral region, a first electrode located on the upper surface of the insulating layer in the pixel region, a photoelectric conversion layer located above the first electrode that converts light into electric charge, a second electrode located above the photoelectric conversion layer, a through electrode electrically connected to a first pixel among the plurality of pixels and penetrating the first semiconductor substrate in the peripheral region, and a third electrode located on the upper surface of the insulating layer in the peripheral region and electrically connected to the second electrode, wherein the through electrode is electrically insulated from the third electrode, and in a plan view, at least a part of the through electrode overlaps with either the third electrode or a gap formed in the third electrode.

[0016] As a result, the through-electrode, which is electrically connected to the first pixel but electrically insulated from the third electrode, overlaps with the region where the third electrode is formed in a plan view. Therefore, the additional area required for the placement of the through-electrode electrically connected to the first pixel can be reduced, allowing for a smaller imaging device.

[0017] Furthermore, for example, an imaging apparatus according to a second aspect of the present disclosure is an imaging apparatus according to a first aspect, further comprising a second substrate laminated on the first substrate, and at least one of a signal processing circuit and a control circuit that supplies a control signal to the first pixel, which are arranged on the second substrate, wherein the signal processing circuit or the control circuit arranged on the second substrate are electrically connected to the first pixel via the through-electrode.

[0018] This allows the through-electrode to transmit signals output from the first pixel, or control signals to the first pixel.

[0019] Furthermore, for example, an imaging device according to a third aspect of the present disclosure is an imaging device according to the first or second aspect, wherein the first pixel is configured to be supplied with a first voltage via the through electrode.

[0020] This allows the through-electrode to supply the first voltage used to drive the first pixel.

[0021] Furthermore, for example, an imaging device according to a fourth aspect of the present disclosure is an imaging device according to any one of the first to third aspects, further comprising a first wiring in contact with the upper surface of the through electrode, wherein the first wiring is located in the same layer as a second wiring located in the insulating layer within the pixel region.

[0022] This allows the first wiring connected to the upper surface of the through-electrode and the second wiring located in the pixel area to be formed using the same process, thereby simplifying the manufacturing process of the imaging device.

[0023] Furthermore, for example, an imaging device according to a fifth aspect of the present disclosure is an imaging device according to any one of the first to fourth aspects, further comprising a first via located in the insulating layer in the peripheral region, and a first wiring in contact with the upper surface of the through electrode and the upper surface of the first via, wherein, in a plan view, at least a portion of the first via overlaps with either the third electrode or the gap formed in the third electrode.

[0024] As a result, not only the through-electrode but also the first via connected to the through-electrode via the first wiring overlap the region where the third electrode is formed in a plan view. Therefore, the imaging device can be further miniaturized.

[0025] Furthermore, for example, an imaging apparatus according to the sixth aspect of the present disclosure is an imaging apparatus according to any one of the first to fifth aspects, wherein the distance between the upper surface of the through electrode and the third electrode is greater than the distance between the upper surface of the through electrode and the first semiconductor substrate.

[0026] This allows for a greater distance between the wiring in contact with the upper surface of the through electrode and the third electrode. As a result, it becomes less likely for noise caused by the potential of the third electrode to occur in the signals transmitted from or to the first pixel via the wiring, or in the voltage supplied to the first pixel through the wiring.

[0027] Furthermore, for example, an imaging device according to a seventh aspect of the present disclosure is an imaging device according to any one of the first to sixth aspects, further comprising a first wiring in contact with the upper surface of the through electrode and a third wiring located between the third electrode and the first wiring.

[0028] This suppresses coupling between the first wiring and the third electrode through the third wiring, making it less likely for noise caused by the potential of the third electrode to occur in signals from or to pixels transmitted by the first wiring, or in the voltage supplied to pixels via the first wiring.

[0029] Furthermore, for example, the imaging device according to the eighth aspect of this disclosure is the imaging device according to the seventh aspect, wherein the potential of the third wiring is fixed.

[0030] This further reduces noise in signals transmitted to or from the first pixel via the first wiring, or in voltages supplied to the first pixel via the first wiring.

[0031] Furthermore, for example, an imaging device according to the ninth aspect of the present disclosure is an imaging device according to any one of the first to eighth aspects, further comprising: a fourth wiring located within the insulating layer and overlapping the third electrode in a plan view; and a second via electrically connecting the third electrode and the fourth wiring.

[0032] This allows for a lower resistance in the voltage supply path to the second electrode. As a result, shading phenomena caused by voltage drops within the second electrode can be suppressed. Furthermore, by lowering the resistance of the voltage supply path to the second electrode, voltage control, such as when switching the voltage applied to the second electrode, can be accelerated.

[0033] Furthermore, for example, the imaging device according to the tenth aspect of the present disclosure is an imaging device according to any one of the first to ninth aspects, wherein the second electrode is in contact with the third electrode.

[0034] This allows for the formation of an electrical connection between the second and third electrodes by forming the second electrode, thereby simplifying the manufacturing process of the imaging device.

[0035] Furthermore, for example, the imaging device according to the 11th aspect of this disclosure is an imaging device according to any one of the first to tenth aspects, wherein, in a plan view, the entire through electrode overlaps the third electrode.

[0036] This allows for further miniaturization of the imaging device.

[0037] Furthermore, for example, an imaging device according to a twelfth aspect of the present disclosure is an imaging device according to any one of the first to eleventh aspects, further comprising a first wiring that contacts the upper surface of the through electrode, wherein in a plan view, the entirety of the first wiring overlaps the third electrode.

[0038] This allows for further miniaturization of the imaging device.

[0039] Further, for example, the imaging device according to the 13th aspect of the present disclosure is an imaging device according to any one of the 1st to 12th aspects, and the third electrode has a stripe-shaped portion in a plan view.

[0040] Thereby, it is possible to form a third electrode in which a dishing phenomenon in which the central portion is recessed is suppressed, and it is possible to reduce the electrical resistance in the connection between the third electrode and the second electrode.

[0041] Further, for example, the imaging device according to the 14th aspect of the present disclosure is an imaging device according to any one of the 1st to 13th aspects, and the third electrode is located in the same layer as the first electrode.

[0042] Thereby, since the first electrode located on the insulating layer in the pixel region and the third electrode located on the insulating layer in the peripheral region can be formed using the same process, the manufacturing process of the imaging device can be simplified.

[0043] Further, for example, the imaging device according to the 15th aspect of the present disclosure is an imaging device according to any one of the 1st to 14th aspects, and the third electrode contains the same material as the material contained in the first electrode.

[0044] Thereby, the materials used for the first electrode and the third electrode can be made common, and the types of materials used in the manufacture of the imaging device can be reduced.

[0045] Further, for example, the camera system according to the 16th aspect of the present disclosure includes an imaging device according to any one of the 1st to 15th aspects.

[0046] Thereby, since the camera system according to the present aspect includes the above-described imaging device, it can be miniaturized.

[0047] Hereinafter, embodiments of the present disclosure will be described in detail while referring to the drawings. Note that all of the embodiments described below show comprehensive or specific examples. The numerical values, shapes, materials, components, arrangements and connection forms of the components, steps, order of steps, etc. shown in the following embodiments are merely examples and are not intended to limit the present disclosure. Various aspects described in this specification can be combined with each other as long as there is no contradiction. In addition, among the components in the following embodiments, the components not described in the independent claims are described as optional components. In each figure, components having substantially the same function are denoted by a common reference numeral, and redundant descriptions may be omitted or simplified.

[0048] In addition, the various elements shown in the drawings are merely schematically shown for the purpose of understanding the present disclosure, and the dimensional ratios, appearances, etc. may be different from the actual ones. That is, each figure is a schematic diagram and is not necessarily drawn precisely. Therefore, for example, the scales in each figure do not necessarily match.

[0049] In addition, in this specification, terms indicating the relationship between elements such as vertical or parallel, terms indicating the shape of elements such as circular or rectangular, and numerical ranges are not expressions representing only strict meanings, but are expressions meaning substantially equivalent ranges, for example, including differences on the order of several percent.

[0050] Furthermore, in this specification, the terms "upper" and "lower" do not refer to the upward (vertically upward) and downward (vertically downward) directions in absolute spatial perception, but rather to terms defined by the relative positional relationship based on the stacking order in the stacked configuration. Specifically, the light-receiving side of the imaging device is defined as "upper," and the side opposite the light-receiving side is defined as "lower." Similarly, for the "upper surface" and "lower surface" of each component, the light-receiving side of the imaging device is defined as the "upper surface," and the side opposite the light-receiving side is defined as the "lower surface." It should be noted that terms such as "upper," "lower," "upper surface," and "lower surface" are used solely to specify the relative arrangement of components and are not intended to limit the orientation of the imaging device when in use. Moreover, the terms "upper" and "lower" apply not only when two components are spaced apart and another component exists between them, but also when two components are placed in close proximity and touching each other. Furthermore, in this specification, "plan view" refers to a view taken from a direction perpendicular to the semiconductor substrate (in other words, in the thickness direction of the semiconductor substrate).

[0051] Furthermore, in this specification and the drawings, the X, Y, and Z axes represent the three axes of a three-dimensional Cartesian coordinate system. In the following embodiments, the Z-axis direction is the thickness direction of the semiconductor substrate and the stacking direction of the semiconductor substrate. Also, the negative side of the Z-axis is defined as "downward," and the positive side of the Z-axis is defined as "upward."

[0052] Furthermore, in this specification, "connection" means an electrical connection unless otherwise specified.

[0053] Furthermore, in this specification, for convenience, not only visible light but also invisible light such as ultraviolet light and near-infrared light will be referred to as "light."

[0054] Furthermore, in this specification, ordinal numbers such as "first," "second," etc., unless otherwise specified, do not refer to the number or order of constituent elements, etc., but are used for the purpose of avoiding confusion and distinguishing similar constituent elements, etc.

[0055] (Embodiment 1) The imaging device according to Embodiment 1 will be described.

[0056] [Configuration] First, an overview of the configuration of the imaging device according to this embodiment will be described. Figure 1 is a block diagram showing an example of the configuration of the imaging device 100 according to this embodiment.

[0057] As shown in Figure 1, the imaging device 100 comprises a first substrate 10, a pixel array 30 composed of a plurality of pixels 31 arranged on the first substrate 10, a second substrate 20, peripheral circuits 51 arranged on the second substrate 20, and a group of through electrodes 40 composed of a plurality of through electrodes 41 for connecting the plurality of pixels 31 and the peripheral circuits 51. The peripheral circuits 51 include circuits for driving the plurality of pixels 31 and circuits for processing signals output by the plurality of pixels 31. In the example shown in Figure 1, these include a vertical scanning circuit 52, a column signal processing circuit 53, an analog circuit 54, a memory 55, a logic circuit 56, and an output circuit 59. Some of the peripheral circuits 51 may be arranged on the first substrate 10.

[0058] As will be described in detail later, the first substrate 10 and the second substrate 20 are stacked on top of each other. The electrical connection between the first substrate 10 and the second substrate 20 is made via multiple through electrodes 41 of the through electrode group 40. Depending on the arrangement of the peripheral circuit 51, some of the connections made via the through electrodes 41 described below may be made without using the through electrodes 41.

[0059] The pixel array 30 includes a plurality of pixels 31 arranged in two dimensions. Each of the plurality of pixels 31 includes a photoelectric conversion unit that converts light into electric charge and outputs a signal corresponding to the incidence of light on the photoelectric conversion unit. In the example shown in Figure 1, the plurality of pixels 31 are depicted as being spatially separated from each other, but this is merely for the sake of explanation, and the plurality of pixels 31 may also be arranged continuously without any spacing between them.

[0060] Multiple pixels 31 are connected to voltage lines Lv. Although Figure 1 shows one voltage line Lv, multiple pixels 31 may be connected to multiple voltage lines Lv. The voltage lines Lv are connected via through electrodes 41 to an external power supply that provides voltages such as the power supply voltage VDD and reset voltage VR, which will be described later. At least a portion of the power supply may be provided in the imaging device 100.

[0061] The vertical scanning circuit 52 is connected to the multiple pixels 31 via control signal lines Lcon provided for each row of pixels 31, and performs signal reading and resetting of the pixels 31 for each row of pixels 31. The vertical scanning circuit 52 is an example of a control circuit that supplies control signals such as row selection signals and reset signals to the pixels 31. Figure 1 shows a diagram in which one control signal line Lcon is provided for each row of multiple pixels 31, but multiple control signal lines Lcon may be provided for each row of pixels 31. The control signal lines Lcon are connected to the vertical scanning circuit 52 via through electrodes 41.

[0062] The column signal processing circuit 53 is connected to the multiple pixels 31 via vertical signal lines 77 provided for each column of the multiple pixels 31, and converts the analog signals output for each column of the multiple pixels 31 into digital signals. The column signal processing circuit 53 is an example of a signal processing circuit that processes signals from the pixels 31. The column signal processing circuit 53 may perform noise suppression signal processing, such as correlated double sampling, before AD conversion. The vertical signal lines 77 are connected to the column signal processing circuit 53 via through electrodes 41.

[0063] The analog circuit 54 includes various analog circuits in the imaging device 100, such as a constant voltage source, a constant current source, a voltage supply circuit, and a phase-locking circuit. Although not shown in Figure 1, at least one of the circuits included in the analog circuit 54 may be connected to a plurality of pixels 31 via a through electrode 41.

[0064] Memory 55 temporarily stores, for example, the digital signals converted by the column signal processing circuit 53. Memory 55 may also temporarily store the digital signals processed by the digital signal processing circuit 58.

[0065] In the example shown in Figure 1, the logic circuit 56 includes a digital control circuit 57 and a digital signal processing circuit 58. The logic circuit 56 can be implemented, for example, by a microcontroller or one or more processors. The functions of the logic circuit 56 may be implemented by a combination of general-purpose processing circuits and software, or by hardware specialized for such processing. Although the digital control circuit 57 and the digital signal processing circuit 58 are shown as separate blocks, the digital control circuit 57 and the digital signal processing circuit 58 may be implemented by a single processor or the like.

[0066] The digital control circuit 57 controls the drive of the imaging device 100. The digital control circuit 57 controls the drive of at least one of the following: the column signal processing circuit 53, the analog circuit 54, and the output circuit 59.

[0067] The digital signal processing circuit 58 processes the digital signal converted by the column signal processing circuit 53. For example, the digital signal processing circuit 58 processes the data stored in the memory 55 as needed and outputs it to the outside via the output circuit 59 at the appropriate timing.

[0068] The output circuit 59 outputs data from the digital signal processing circuit 58 to the outside.

[0069] Next, the circuit configuration of the pixel 31 according to this embodiment will be described. Figure 2 is a diagram showing an example of the circuit configuration of the pixel 31 according to this embodiment. Each of the multiple pixels 31 has, for example, the circuit configuration shown in Figure 2.

[0070] As shown in Figure 2, the pixel 31 includes a photoelectric conversion unit 70 and a detection circuit 32 which includes an amplification transistor 33, a selection transistor 34, and a reset transistor 35.

[0071] The photoelectric conversion unit 70 generates positive and negative charges upon the incidence of light. In other words, the photoelectric conversion unit 70 converts light into electric charge. Positive and negative charges are typically hole-electron pairs. As will be described in detail later, the photoelectric conversion unit 70 includes a pixel electrode 71, a counter electrode 72 facing the pixel electrode 71, and a photoelectric conversion layer 73 located between the pixel electrode 71 and the counter electrode 72.

[0072] The counter electrode 72 of the photoelectric conversion unit 70 is connected to the connecting electrode 75, and a predetermined voltage Vp is applied to the counter electrode 72 when the imaging device 100 is in operation. By applying the predetermined voltage Vp to the counter electrode 72, one of the positive and negative charges generated in the photoelectric conversion layer 73 by photoelectric conversion can be selectively stored in the charge storage region as a signal charge. In the following description, unless otherwise specified, the example will be that of the positive charges, i.e., holes, generated by photoelectric conversion are used as the signal charge.

[0073] The detection circuit 32 is connected to the pixel electrode 71 of the photoelectric conversion unit 70 and detects a signal based on the charge generated by the photoelectric conversion unit 70.

[0074] The amplification transistor 33, the selection transistor 34, and the reset transistor 35 are, for example, field-effect transistors (FETs) formed on a semiconductor substrate supporting the photoelectric conversion unit 70. In the example shown in Figure 2, each of the amplification transistor 33, the selection transistor 34, and the reset transistor 35 is an N-channel MOSFET (Metal Oxide Semiconductor FET). Which of the two diffusion regions of the FET corresponds to the source and which corresponds to the drain is determined by the polarity of the FET and the potential level at that time. Therefore, which is the source and which is the drain may vary depending on the operating state of the FET.

[0075] The gate of the amplification transistor 33 is connected to the charge storage node FD connected to the pixel electrode 71 of the photoelectric conversion unit 70. The charge storage node FD is at least a part of the charge storage region where the signal charge generated by the photoelectric conversion unit 70 is stored, and the potential of the charge storage node FD is substantially the same as the potential of the charge storage region. The potential of the charge storage node FD of the pixel 31 after the exposure period corresponds to the amount of signal charge stored in the charge storage region of the pixel 31 during the exposure period.

[0076] The power supply voltage VDD is applied to the drain of the amplification transistor 33 via a through electrode 41. The power supply voltage VDD is an example of a first voltage. The power supply voltage VDD is, for example, about 3.3V. The wiring connecting the drain of the amplification transistor 33 and the through electrode 41 corresponds to one of the voltage lines Lv described above. The through electrode 41 connected to the drain of the amplification transistor 33 is shared by, for example, multiple pixels 31. The source of the amplification transistor 33 is connected to the corresponding vertical signal line 77 via a selection transistor 34. The drain of the amplification transistor 33 outputs an analog signal corresponding to the potential of the charge storage node FD to the corresponding vertical signal line 77 via the selection transistor 34. When the selection transistor 34 is ON, the amplification transistor 33 forms a source follower circuit together with a current source (not shown) connected to the vertical signal line 77. The current source is, for example, one of the circuits included in the analog circuit 54.

[0077] A row selection signal SEL is supplied to the gate of the selection transistor 34 from the vertical scanning circuit 52 via a through electrode 41. The row selection signal SEL controls the on and off states of the selection transistor 34. The wiring connecting the gate of the selection transistor 34 and the through electrode 41 corresponds to one of the control signal lines Lcon described above. The through electrode 41 connected to the gate of the selection transistor 34 is provided, for example, for each row of multiple pixels 31. By controlling the on and off states of the selection transistor 34, the vertical scanning circuit 52 can read the output of the amplification transistor 33 of the selected pixel 31 to the corresponding vertical signal line 77. The analog signal from the amplification transistor 33 output to the vertical signal line 77 is input to the column signal processing circuit 53 via the through electrode 41. The through electrode 41 connected to the vertical signal line 77 is provided, for example, for each column of multiple pixels 31 corresponding to the vertical signal line 77.

[0078] One of the drains and sources of the reset transistor 35 is connected to the charge storage node FD. A reset voltage VR is applied to the other drain and source of the reset transistor 35 via a through electrode 41. The reset voltage VR is another example of the first voltage. For example, a voltage of 0V or near 0V is used as the reset voltage VR. The wiring connecting the other drain and source of the reset transistor 35 to the through electrode 41 corresponds to another of the voltage lines Lv described above. The through electrode 41 connected to the other drain and source of the reset transistor 35 is shared by, for example, multiple pixels 31.

[0079] A reset signal RST is supplied to the gate of the reset transistor 35 from the vertical scanning circuit 52 via a through electrode 41. The reset signal RST controls the on and off states of the reset transistor 35. The wiring connecting the gate of the reset transistor 35 and the through electrode 41 corresponds to one of the other control signal lines Lcon described above. When the reset transistor 35 is turned on, the potential of the charge storage node FD is reset to the reset voltage VR. The through electrode 41 connected to the gate of the reset transistor 35 is provided, for example, for each row of multiple pixels 31.

[0080] Next, the detailed device configuration of the imaging device 100 according to this embodiment will be described with reference to Figures 3 to 6.

[0081] Figure 3 is a schematic cross-sectional view showing an example of the device structure of the imaging device 100 according to this embodiment. Figure 4 is a schematic plan view showing an example of the planar layout of the first substrate 10 of the imaging device 100 according to this embodiment. Figure 5 is an enlarged view of the vicinity of line III-III in Figure 4. Figure 6 is a schematic plan view showing an example of the planar layout of the second substrate 20 of the imaging device 100 according to this embodiment. Figure 3 shows a cross-section of the imaging device 100 at a position corresponding to line III-III in Figures 4 and 5. In Figure 3, for ease of viewing, the shading indicating the cross-section of the insulating layers 12, 22, 80 and 81, the protective layer 83 and the planarization layer 85 has been omitted. This is also the case in subsequent cross-sectional views. In addition, in Figures 4 and 6, a pattern has been added to the area where the through-electrode group 40 is arranged for clarity.

[0082] As shown in Figure 3, the imaging device 100 comprises a first substrate 10, a second substrate 20, a photoelectric conversion unit 70, a connecting electrode 75, an insulating layer 80, an insulating layer 81, a light-shielding layer 82, a protective layer 83, a color filter 84, a planarization layer 85, and a microlens 86. The photoelectric conversion unit 70, the insulating layer 81, the protective layer 83, the color filter 84, the planarization layer 85, and the microlens 86 are included in each pixel 31.

[0083] As shown in Figure 3, the first substrate 10 and the second substrate 20 are stacked on top of each other. The first substrate 10 and the second substrate 20 have the same shape and size in a plan view, for example, and their outer edges coincide. The first substrate 10 and the second substrate 20 are joined at the interface between the first substrate 10 and the second substrate 20. The first substrate 10 and the second substrate 20 can be manufactured, for example, using a semiconductor manufacturing process.

[0084] As shown in Figures 3 and 4, the first substrate 10 has, in a plan view, a pixel region R1 in which a plurality of pixels 31 are arranged, which is the area where the pixel array 30 is placed, and a peripheral region R2 adjacent to the pixel region R1. The pixel region R1 is, for example, a rectangular region. The peripheral region R2 is, for example, arranged to surround the pixel region R1 in a plan view.

[0085] As shown in Figure 3, the first substrate 10 includes a semiconductor substrate 11 located in the pixel region R1 and the peripheral region R2, and an insulating layer 12 located above the semiconductor substrate 11 in the pixel region R1 and the peripheral region R2. In the example shown in Figure 3, the insulating layer 12 is located on the upper surface of the semiconductor substrate 11.

[0086] The second substrate 20 includes a semiconductor substrate 21 and an insulating layer 22 located above the semiconductor substrate 21. In the example shown in Figure 3, the insulating layer 22 is located on the upper surface of the semiconductor substrate 21. The orientation of the second substrate 20 may be reversed compared to the example shown in Figure 3.

[0087] The semiconductor substrates 11 and 21 are, for example, p-type or n-type semiconductor substrates in which various impurity regions are formed. Semiconductor substrate 11 is an example of a first semiconductor substrate. Wells may be formed in each of the semiconductor substrates 11 and 21.

[0088] A detection circuit 32 for each pixel 31 is formed on the upper surface of the semiconductor substrate 11. Figure 3 shows some of the transistors in the detection circuit 32. The first substrate 10 may further include another semiconductor substrate besides the semiconductor substrate 11. In this case, each transistor in the detection circuit 32 is formed on either the semiconductor substrate 11 or the other semiconductor substrate.

[0089] The insulating layer 12 includes a plurality of constituent layers 12A, 12B, 12C, 12D, and 12E. Each of the constituent layers 12A, 12B, 12C, 12D, and 12E is formed of an insulating material such as silicon dioxide, and is stacked in this order from the semiconductor substrate 11 side. In other words, in the insulating layer 12, constituent layer 12A is the constituent layer closest to the semiconductor substrate 11, and constituent layer 12E is the constituent layer furthest from the semiconductor substrate 11. The number of constituent layers included in the insulating layer 12 is not particularly limited.

[0090] Each of the constituent layers 12A, 12B, 12C, and 12D has a wiring layer. The wiring layer is located, for example, at the top of each of the constituent layers 12A, 12B, 12C, and 12D. In the example shown in Figure 3, the imaging device 100 includes wiring 15A, 15B, 15C, and 15D located within the insulating layer 12 in the pixel region R1, respectively, and arranged in the constituent layers 12A, 12B, 12C, and 12D. Each wiring within the insulating layer 12, such as wiring 15A, 15B, 15C, and 15D, is connected by vias to wiring located in other constituent layers. Vias are columnar conductors extending in the thickness direction of the semiconductor substrate 11. Also in the example shown in Figure 3, the imaging device 100 includes a contact plug 19 located in the constituent layer 12E within the insulating layer 12 in the pixel region R1, and connected to wiring 15D and the pixel electrode 71. The pixel electrode 71 is connected to the detection circuit 32 via the contact plug 19 and wiring 15A, 15B, 15C, and 15D. The imaging device 100 also includes a plurality of contact plugs arranged in the constituent layer 12A within the insulating layer 12 and connected to the source, drain, and gate of a transistor formed on the semiconductor substrate 11.

[0091] Peripheral circuits 51 are formed on the upper surface of the semiconductor substrate 21. The second substrate 20 may further include another semiconductor substrate separate from the semiconductor substrate 21. In this case, each circuit of the peripheral circuits 51 is formed separately on the semiconductor substrate 21 and the other semiconductor substrate.

[0092] The insulating layer 22, like the insulating layer 12, includes multiple constituent layers formed of an insulating material such as silicon dioxide. Within the insulating layer 22, connection structures 25 are arranged for connecting the through-electrode 41 to the peripheral circuit 51, and for connecting circuits within the peripheral circuit 51. These connection structures include, for example, wiring, vias, and contact plugs.

[0093] The wiring, vias, and contact plugs placed within the insulating layer 12 and the insulating layer 22 include, for example, at least one selected from the group consisting of copper, aluminum, tungsten, and tantalum. The wiring, vias, and contact plugs placed within the insulating layer 12 and the insulating layer 22 may contain copper as the main component. Here, the main component means the component that is present in the largest amount by mass. In one example, the main component is a component that makes up more than 50% by mass. The main component may also be a component that makes up more than 80% by mass.

[0094] As described above, the photoelectric conversion unit 70 includes a pixel electrode 71, a counter electrode 72, and a photoelectric conversion layer 73. The pixel electrode 71 is an example of a first electrode, and the counter electrode 72 is an example of a second electrode. The photoelectric conversion unit 70 may further include other layers such as a charge blocking layer, a buffer layer, or a charge transport layer in at least one of the spaces between the pixel electrode 71 and the photoelectric conversion layer 73, and between the photoelectric conversion layer 73 and the counter electrode 72.

[0095] The pixel electrode 71 is located on the upper surface of the insulating layer 12 in the pixel region R1. The pixel electrode 71 is a film-like electrode. The pixel electrode 71 may include at least one selected from metals, metal compounds, and polysilicon doped with impurities to impart conductivity. Examples of metals include copper, titanium, tantalum, and aluminum. Examples of metal compounds include metal nitrides. Examples of metal nitrides include titanium nitride and tantalum nitride. The pixel electrode 71 may contain metal nitride as its main component. The pixel electrode 71 collects one of the positive and negative charges generated in the photoelectric conversion layer 73. The pixel electrode 71 is electrically isolated from the pixel electrodes 71 of other adjacent pixels 31 by being spatially separated from them.

[0096] The photoelectric conversion layer 73 is located above the pixel electrode 71 and covers the pixel electrode 71. The photoelectric conversion layer 73 contains an organic semiconductor material or an inorganic semiconductor material such as amorphous silicon, and receives light incident through the counter electrode 72 to generate positive and negative charges through photoelectric conversion. In other words, the photoelectric conversion layer 73 converts light into charge. The positive and negative charges are, for example, hole-electron pairs. The photoelectric conversion layer 73 is formed continuously, for example, across a plurality of pixels 31. The photoelectric conversion layer 73 is shared by a plurality of pixels 31. The photoelectric conversion layer 73 may be provided separately for each pixel 31 or for each block of two or more pixels 31.

[0097] The counter electrode 72 is located above the photoelectric conversion layer 73 and covers the photoelectric conversion layer 73. The counter electrode 72 is a film-like electrode. In the example shown in Figure 3, the counter electrode 72 and the photoelectric conversion layer 73 are aligned in terms of their side surfaces when viewed from above. The counter electrode 72 is formed from a transparent conductive material such as ITO (Indium Tin Oxide) and is positioned on the light-receiving surface side of the photoelectric conversion layer 73. The counter electrode 72 is formed continuously across multiple pixels 31, similar to the photoelectric conversion layer 73. That is, the counter electrodes 72 of multiple pixels 31 are electrically connected to each other. The counter electrodes 72 may be provided separately for each pixel 31 or for each block of two or more pixels 31.

[0098] The potential of the counter electrode 72 is controlled via the connecting electrode 75. When the imaging device 100 is in operation, the potential of the counter electrode 72 is controlled to make it different from the potential of the pixel electrode 71, so that the signal charge generated by photoelectric conversion can be collected by the pixel electrode 71. For example, the potential of the counter electrode 72 is controlled so that its potential is higher than the potential of the pixel electrode 71. Specifically, when the imaging device 100 is in operation, a predetermined voltage Vp different from the reset voltage VR is applied to the counter electrode 72 via the connecting electrode 75. For example, the connecting electrode 75 is connected to a voltage supply circuit (not shown) that supplies the voltage Vp. The voltage supply circuit that supplies the voltage Vp is, for example, one of the circuits included in the analog circuit 54. The absolute value of the voltage Vp is, for example, greater than the absolute value of the power supply voltage VDD. A specific example of the voltage Vp is a positive voltage of about 10V. As a result, the holes from the hole-electron pairs generated in the photoelectric conversion layer 73 can be collected as signal charges by the pixel electrode 71. The signal charges collected by the pixel electrode 71 are stored in a charge storage region connected to the pixel electrode 71 and detected by the detection circuit 32. When electrons are used as signal charges, a voltage Vp is applied to the counter electrode 72 such that the potential of the counter electrode 72 is lower than the potential of the pixel electrode 71.

[0099] The imaging device 100 may perform a global shutter operation during operation. In this case, for example, a voltage Vp is applied to the counter electrode 72 during the exposure period of all pixels 31 at once, and a voltage Vn is applied during the non-exposure period such that substantially no movement of signal charge generated in the photoelectric conversion layer 73 occurs. As a result, during the non-exposure period, signal charge is not collected on the pixel electrode 71, and the signal charge collected on the pixel electrode 71 during the exposure period can be detected. The voltage Vn is, for example, a voltage such that the potential difference between the counter electrode 72 and the pixel electrode 71 is 0V or near 0V. Thus, in the imaging device 100, the potential of the counter electrode 72 and the connecting electrode 75 connected to the counter electrode 72 can fluctuate with an amplitude of about 10V.

[0100] The color filter 84 is located above the counter electrode 72 and faces the counter electrode 72 via an insulating layer 81 and a protective layer 83. The color filter 84 is formed, for example, as an on-chip color filter by patterning, and a photosensitive resin in which dyes or pigments are dispersed is used. The microlens 86 is located above the color filter 84 and faces the color filter 84 via a planarization layer 85. The microlens 86 is formed, for example, as an on-chip microlens, and an ultraviolet photosensitive material is used. The insulating layer 81, protective layer 83 and planarization layer 85 are formed, for example, from an insulating material such as silicon dioxide.

[0101] As shown in Figure 4, the first substrate 10 has a pixel array 30, a connecting electrode 75, a through-electrode group 40 composed of multiple through-electrodes 41, and a bonding pad region group 92 composed of multiple bonding pad regions 91. The connecting electrode 75 is an example of a third electrode. The connecting electrode 75, the through-electrode group 40, and the bonding pad region group 92 are arranged in the peripheral region R2. Also, as shown in Figure 6, the second substrate 20 has a peripheral circuit 51, a through-electrode group 40 composed of multiple through-electrodes 41, and a bonding pad region group 94 composed of multiple bonding pad regions 93. The through-electrode group 40 is formed spanning the first substrate 10 and the second substrate 20.

[0102] In a plan view, the connecting electrode 75 is elongated and extends along the outer circumference of the pixel array 30. In the examples shown in Figures 4 and 5, the connecting electrode 75 is elongated and rectangular in a plan view. In the example shown in Figure 4, in a plan view, four connecting electrodes 75 are arranged along each of the four sides of the rectangle of the pixel array 30 so as to surround the pixel array 30. Note that the number of connecting electrodes 75 is not limited to the example shown in Figure 4, and may be one, two, or three, for example.

[0103] As shown in Figure 3, the connecting electrode 75 is located on the upper surface of the insulating layer 12 in the peripheral region R2. The connecting electrode 75 is a film-like electrode. In the example shown in Figure 3, the connecting electrode 75 is located in the same layer as the pixel electrode 71. This allows the connecting electrode 75 to be formed using the same process as the pixel electrode 71, thereby simplifying the manufacturing process of the imaging device 100. In this specification, "located in the same layer" means that the distance from the semiconductor substrate 11 is the same.

[0104] The material used for the connecting electrode 75 can be the same material used for the pixel electrode 71. The connecting electrode 75 may contain the same material as the pixel electrode 71, or the material of the connecting electrode 75 may be the same as the material of the pixel electrode 71. This allows for the common use of materials for the pixel electrode 71 and the connecting electrode 75, thereby reducing the number of materials used in the manufacture of the imaging device 100.

[0105] In the example shown in Figure 3, the connecting electrode 75 is electrically connected to the counter electrode 72 via a conductive light-shielding layer 82. Specifically, the connecting electrode 75 is electrically connected to the light-shielding layer 82 on its upper surface, and the counter electrode 72 is electrically connected to the light-shielding layer 82 on the side facing the connecting electrode 75. The light-shielding layer 82 is in contact with the upper surface of the connecting electrode 75 and the side of the counter electrode 72. Note that the connecting electrode 75 may also be connected to the counter electrode 72 via a conductor other than the light-shielding layer 82, as long as it is electrically connected to the counter electrode 72.

[0106] The light-shielding layer 82 covers the connecting electrode 75 and the counter electrode 72 from above. In the pixel region R1, the light-shielding layer 82 is located between the insulating layer 81 and the protective layer 83 and faces the counter electrode 72. The light-shielding layer 82 shields the light incident on the photoelectric conversion unit 70 of some of the pixels 31, specifically the pixels 31 located at the edges of the pixel array 30. Therefore, the pixels 31 whose photoelectric conversion unit 70 is covered by the light-shielding layer 82 become OB (Optical Black) pixels. In the peripheral region R2, the light-shielding layer 82 is located above the connecting electrode 75.

[0107] The light-shielding layer 82 includes at least one selected from the group consisting of metals and metal compounds. For example, the light-shielding layer 82 includes at least one selected from the group consisting of titanium, titanium nitride, aluminum, silicon, copper-added aluminum, copper, and tungsten. The light-shielding layer 82 may also include an alloy containing at least two of the above-mentioned materials.

[0108] As shown in Figure 4, the through-electrode group 40 is elongated in plan view, extending along the outer circumference of the pixel array 30. In the example shown in Figure 4, in plan view, two through-electrode groups 40 are arranged together with the connecting electrodes 75 along two adjacent sides of the rectangle of the pixel array 30. The number of through-electrode groups 40 is not limited to the example shown in Figure 4, and may be, for example, one, three, or four. Also, as shown in Figure 6, in plan view, the through-electrode groups 40 are positioned on the outer circumference side of the second substrate 20, relative to the peripheral circuitry 51. A portion of the peripheral circuitry 51 may be positioned on the outer circumference side of the second substrate 20, relative to the through-electrode groups 40, in plan view.

[0109] As shown in Figures 3 to 5, the multiple through electrodes 41 constituting the through electrode group 40 overlap the connecting electrode 75 in a plan view. In the illustrated example, all of the multiple through electrodes 41 overlap the connecting electrode 75 in a plan view, but the multiple through electrodes 41 may include through electrodes 41 that do not overlap the connecting electrode 75. For example, more than half of the multiple through electrodes 41 overlap the connecting electrode 75. Also, in the illustrated example, the entirety of the through electrodes 41 overlaps the connecting electrode 75 in a plan view. Note that it is sufficient for at least a portion of the through electrodes 41 to overlap the connecting electrode 75 in a plan view.

[0110] Multiple through electrodes 41 are arranged, for example, at a predetermined pitch in a plan view. In the example shown in Figure 5, the pitch at which the through electrodes 41 are arranged is different from the pitch at which the pixels 31 are arranged, but they may be the same.

[0111] As shown in Figure 3, the through-electrode 41 is a via that penetrates the semiconductor substrate 11 in the peripheral region R2. The through-electrode 41 is electrically insulated from the connecting electrode 75. An insulating layer 80 is placed between the through-electrode 41 and the semiconductor substrate 11, and the through-electrode 41 and the semiconductor substrate 11 are separated by the insulating layer 80. In Figure 3, one of the multiple through-electrodes 41 is shown as a representative example. The through-electrode 41 shown in Figure 3 is connected to the detection circuit 32 and peripheral circuit 51 of the pixels 31 at the edge of the pixel array 30. More specifically, the through-electrode 41 shown in Figure 3 corresponds to the through-electrode 41 connected to the vertical signal line 77 described above, and the signal output by the pixel 31 is transmitted to it. Note that the multiple through-electrodes 41 may include many through-electrodes 41 (not shown in Figure 3) that are electrically connected to various locations on each of the multiple pixels 31, as explained using Figures 1 and 2.

[0112] The through electrode 41 may contain a metal. For example, the through electrode 41 may contain at least one selected from the group consisting of copper, aluminum, tungsten, and tantalum. The through electrode 41 may contain copper as its main component.

[0113] In the example shown in Figure 3, the imaging device 100 includes vias 43 located within the insulating layer 12 in the peripheral region R2, and wiring 42 located within the insulating layer 12 in the peripheral region R2 and in contact with the upper surface of the through electrode 41 and the upper surface of the via 43. The wiring 42 is an example of a first wiring. The via 43 is an example of a first via. In each of the multiple through electrodes 41 constituting the through electrode group 40, for example, the positions of the upper surfaces of the through electrodes 41 in the Z-axis direction are the same. The multiple through electrodes 41 constituting the through electrode group 40 may include through electrodes 41 whose upper surfaces are in different positions in the Z-axis direction.

[0114] In the example shown in Figure 3, the wiring 42 and via 43 are embedded in the constituent layer 12E within the insulating layer 12. Via 43 connects wiring 42 to wiring 44 located in the constituent layer 12D in the surrounding region R2.

[0115] As shown in Figures 3 and 5, the wiring 42 and vias 43 overlap the connecting electrode 75 in a plan view. Multiple wirings 42 and vias 43 are provided in a one-to-one correspondence with multiple through electrodes 41. In the example shown in Figure 5, all of the multiple wirings 42 and multiple vias 43 overlap the connecting electrode 75, but there may be wirings 42 and vias 43 that do not overlap the connecting electrode 75. Also, in the illustrated example, in a plan view, the entirety of the wiring 42 and the entirety of the vias 43 overlap the connecting electrode 75. Note that in a plan view, it is sufficient that at least a portion of the wiring 42 and vias 43 overlap the connecting electrode 75.

[0116] Furthermore, the imaging device 100 is provided with wiring 45 that is arranged within the insulating layer 12 spanning the pixel region R1 and the peripheral region R2, and electrically connects the through electrode 41 and the pixel 31. In the example shown in Figure 3, the wiring 45 is connected to the detection circuit 32 of the pixel 31. The wiring 45 is located in a different constituent layer 12B in the insulating layer 12 than the constituent layer 12E where the wiring 42 is located. In the example shown in Figure 3, the wiring 45 is closer to the semiconductor substrate 11 than the wiring 42.

[0117] In the imaging device 100, bonding pads for transmitting and receiving power and signals are formed in either of the plurality of bonding pad regions 91 arranged on the first substrate 10 or the plurality of bonding pad regions 93 arranged on the second substrate 20. For example, when bonding pads are formed in the plurality of bonding pad regions 91, vias connected to the bonding pads are arranged in the plurality of bonding pad regions 93. Also, for example, when bonding pads are formed in the plurality of bonding pad regions 93, holes are formed in the plurality of bonding pad regions 91. The holes may be filled with insulating material or the like.

[0118] As described above, in the imaging device 100 according to this embodiment, the through-electrode 41, which is electrically connected to the pixel 31 but electrically insulated from the connecting electrode 75, overlaps with the connecting electrode 75 in a plan view. Therefore, no additional area is required for the arrangement of the through-electrode 41 electrically connected to the pixel 31, and the imaging device 100 can be miniaturized. Furthermore, in the imaging device 100, in a plan view, the via 43 and the wiring 42 that is in contact with the upper surface of the through-electrode 41 and the upper surface of the via 43 overlap with the connecting electrode 75. Thus, the imaging device 100 can be further miniaturized.

[0119] Furthermore, in a plan view, if the wiring 42 contains copper, the exposure of the copper in the wiring 42 can be suppressed by dry etching to define the shape of the light-shielding layer 82, as the wiring 42 overlaps the connecting electrode 75.

[0120] [Another example of the plan view shape of the connecting electrode] Next, another example of the plan view shape of the connecting electrode 75 will be described. Figure 7 is a plan view illustrating another example of the plan view shape of the connecting electrode according to this embodiment. Figure 7 is an enlarged view of the first substrate 10 at the position corresponding to Figure 5. Figure 7 shows the case in which a connecting electrode 75A is placed on the first substrate 10 instead of the connecting electrode 75.

[0121] As shown in Figure 7, the connecting electrode 75A differs from the connecting electrode 75 in that a gap 76 is formed therein. In the example shown in Figure 7, the gap 76 is a slit formed in the connecting electrode 75A. Due to the formation of the gap 76, the connecting electrode 75A has a striped shape in plan view. This suppresses the dishing phenomenon, in which the central part becomes concave due to CMP (Chemical Mechanical Polishing) or the like during the formation of the connecting electrode 75A, and reduces the electrical resistance in the connection between the connecting electrode 75A and the opposing electrode 72. In the example shown in Figure 7, the entire connecting electrode 75A is not striped; rather, the striped portions are connected to each other at the longitudinal ends of the connecting electrode 75A. However, the entire connecting electrode 75A may also be striped.

[0122] In the example shown in Figure 7, in a plan view, the through electrode 41, wiring 42, and via 43 do not overlap with the gap 76 formed in the connecting electrode 75A, but rather overlap with the connecting electrode 75A itself.

[0123] As shown in Figure 8, the through electrode 41, wiring 42, and via 43 may overlap the gap 76 formed in the connecting electrode 75A. Figure 8 is a plan view illustrating another planar layout of the connecting electrode 75A with the gap 76 formed therein according to this embodiment. Figure 9 is a schematic cross-sectional view showing an example of the device structure of the imaging device 100A equipped with the connecting electrode 75A with the gap 76 formed therein. Figure 9 shows a cross-section of the imaging device 100A at a position corresponding to the IX-IX line in Figure 8.

[0124] In the examples shown in Figures 8 and 9, in a plan view, each of the through electrode 41, wiring 42, and via 43 overlaps entirely with the gap 76 formed in the connecting electrode 75A. In a plan view, at least one of the through electrode 41, wiring 42, and via 43 may partially overlap with the gap 76. Also, in a plan view, at least one of the through electrode 41, wiring 42, and via 43 may not overlap with the gap 76.

[0125] In addition, in the imaging devices according to each of the modifications of Embodiment 1 described below, a connecting electrode 75A may be provided instead of the connecting electrode 75.

[0126] [Modification 1] Next, Modification 1 of Embodiment 1 will be described. In the following, the differences from Embodiment 1 will be the main focus of the explanation, and the explanation of the common points will be omitted or simplified.

[0127] Figure 10 is a schematic cross-sectional view showing an example of the device structure of the imaging device 101 according to this modified example. Figure 10 shows a cross-section of the imaging device 101 at a position corresponding to Figure 3.

[0128] As shown in Figure 10, the imaging device 101 according to this modified example differs from the imaging device 100 according to Embodiment 1 mainly in that the constituent layer on which the wiring 42 is arranged is different, and that it does not have vias 43 and wiring 44.

[0129] In the imaging device 101, the wiring 42 is located in the constituent layer 12D directly below the constituent layer 12E where the contact plug 19 is located. Constituent layer 12D is the layer in which the uppermost wiring layer is located among the multiple wiring layers arranged within the insulating layer 12. In this modified example, wiring 15D is an example of a second wiring. In the imaging device 101, wiring 42 is located in the same layer as wiring 15D located within the insulating layer 12 in the pixel region R1. As a result, wiring 42 can be formed using the same process as wiring 15D, thus simplifying the manufacturing process of the imaging device 101.

[0130] Wiring 42 may contain the same material as wiring 15D, and the material of wiring 42 and the material of wiring 15D may be identical.

[0131] Furthermore, in the imaging device 101, since the wiring 42 is located in the constituent layer 12D, the distance between the wiring 42 and the connecting electrode 75 can be increased compared to the case where the wiring 42 is located in the constituent layer 12E. As a result, the wiring 42 is less susceptible to fluctuations in the potential of the connecting electrode 75, for example, when supplying voltage to the counter electrode 72. Therefore, it is possible to reduce noise caused by the potential of the connecting electrode 75 in the signal transmitted by the wiring 42.

[0132] [Modification 2] Next, Modification 2 of Embodiment 1 will be described. In the following, the differences between Embodiment 1 and Modification 1 of Embodiment 1 will be explained, and the explanation of the common points will be omitted or simplified.

[0133] Figure 11 is a schematic cross-sectional view showing an example of the device structure of the imaging device 102 according to this modified example. Figure 11 shows a cross-section of the imaging device 102 at a position corresponding to Figure 3.

[0134] As shown in Figure 11, the imaging device 102 according to this modified example differs from the imaging device 101 according to Modification 1 of Embodiment 1 mainly in that the constituent layer on which the wiring 42 is arranged is different, and that it further includes shield wiring 46. The shield wiring 46 is an example of a third wiring.

[0135] In the imaging device 102, the wiring 42 is located on the constituent layer 12C. The constituent layer 12C is the layer on which the second wiring layer from the top is located among a plurality of wiring layers arranged within the insulating layer 12. In the imaging device 102, the wiring 42 is located on the same layer as the wiring 15C located within the insulating layer 12 in the pixel region R1. In this modified example, the wiring 15C is an example of a second wiring.

[0136] The shielded wiring 46 is located between the connecting electrode 75 and the wiring 42. In the example shown in Figure 11, the shielded wiring 46 is located in the same layer as the wiring 15D, in the constituent layer 12D. The shielded wiring 46 is electrically insulated from the connecting electrode 75 and the wiring 42. The shielded wiring 46 is, for example, wiring connected to a power source or ground, and the potential of the shielded wiring 46 is fixed.

[0137] The imaging device 102 is equipped with shielded wiring 46, which suppresses coupling between the wiring 42 and the connecting electrode 75. As a result, the wiring 42 is less susceptible to the influence of the potential of the connecting electrode 75 in supplying voltage to the counter electrode 72. Therefore, it is possible to reduce noise caused by the potential of the connecting electrode 75 in the signal transmitted by the wiring 42.

[0138] [Modification 3] Next, Modification 3 of Embodiment 1 will be described. In the following, the differences between Embodiment 1 and Modifications 1 and 2 of Embodiment 1 will be described, and the explanation of the common points will be omitted or simplified.

[0139] Figure 12 is a schematic cross-sectional view showing an example of the device structure of the imaging device 103 according to this modified example. Figure 12 shows a cross-section of the imaging device 103 at a position corresponding to Figure 3.

[0140] As shown in Figure 12, the imaging device 103 according to this modified example differs from the imaging device 102 according to Modification 2 of Embodiment 1 mainly in that it does not have shield wiring 46, and further includes backing wiring 47 and vias 48. Backing wiring 47 is an example of a fourth wiring, and vias 48 is an example of a second via.

[0141] The backing wiring 47 is located within the insulating layer 12 and overlaps with the connecting electrode 75 in a plan view. In the example shown in Figure 12, the backing wiring 47 is located in the constituent layer 12D and is on the same layer as the wiring 15D. The backing wiring 47 is electrically insulated from the through electrode 41. The via 48 electrically connects the connecting electrode 75 and the backing wiring 47. The via 48 is located within the constituent layer 12E.

[0142] The imaging device 103 includes a backing wire 47 and vias 48 that electrically connect the backing wire 47 to the connecting electrode 75, thereby reducing the resistance of the voltage supply path to the counter electrode 72. This suppresses the shading phenomenon caused by voltage drop within the counter electrode 72. Shading is a phenomenon in which a part of the image becomes dark. Furthermore, by reducing the resistance of the voltage supply path to the counter electrode 72, voltage control, such as when switching the voltage applied to the counter electrode 72, can be accelerated.

[0143] [Modification 4] Next, Modification 4 of Embodiment 1 will be described. In the following, the differences between Embodiment 1 and Modifications 1 to 3 of Embodiment 1 will be described, and the explanation of the common points will be omitted or simplified.

[0144] Figure 13 is a schematic cross-sectional view showing an example of the device structure of the imaging device 104 according to this modified example. Figure 13 shows a cross-section of the imaging device 104 at a position corresponding to Figure 3.

[0145] As shown in Figure 13, the imaging device 104 according to this modified example differs from the imaging device 102 according to Modification 2 of Embodiment 1 mainly in that it further includes backing wiring 47 and vias 48, and that the constituent layers on which the wiring 42, wiring 45 and shield wiring 46 are arranged are different.

[0146] In the imaging device 104, the wiring 42 is located on the constituent layer 12B. The constituent layer 12B is the layer on which the second-to-last wiring layer is located among a plurality of wiring layers arranged within the insulating layer 12. In the imaging device 104, the wiring 42 is located on the same layer as the wiring 15B located within the insulating layer 12 in the pixel region R1. In this modified example, the wiring 15B is an example of a second wiring. Also, in the imaging device 104, the wiring 45 is located on the constituent layer 12A.

[0147] In the imaging device 104, the shield wiring 46 is located between the connecting electrode 75 and the wiring 42, and between the backing wiring 47 and the wiring 42. The shield wiring 46 is electrically insulated from the connecting electrode 75 and the backing wiring 47.

[0148] Since the imaging device 104 is equipped with shielded wiring 46 similar to that of the imaging device 102, it is possible to reduce noise caused by the potential of the connecting electrode 75 in the signal transmitted by the wiring 42. Furthermore, since the imaging device 104 is equipped with backing wiring 47 and vias 48 similar to those of the imaging device 103, shading phenomena can be suppressed, and voltage control, such as when switching the voltage applied to the counter electrode 72, can be accelerated.

[0149] Furthermore, in the imaging device 104, the distance between the upper surface of the through electrode 41 and the connecting electrode 75 is greater than the distance between the upper surface of the through electrode 41 and the semiconductor substrate 11. This allows for a larger distance between the wiring 42 in contact with the upper surface of the through electrode 41 and the connecting electrode 75, making it less likely for noise caused by the potential of the connecting electrode 75 to occur in the signal transmitted by the wiring 42. Note that the imaging device 104 does not necessarily have to include shield wiring 46 and at least one of backing wiring 47 and via 48.

[0150] [Modification 5] Next, Modification 5 of Embodiment 1 will be described. In the following, the differences between Embodiment 1 and Modifications 1 to 4 of Embodiment 1 will be described, and the explanation of common points will be omitted or simplified.

[0151] Figure 14 is a schematic cross-sectional view showing an example of the device structure of the imaging device 105 according to this modified example. Figure 14 shows a cross-section of the imaging device 105 at a position corresponding to Figure 3.

[0152] As shown in Figure 14, the imaging device 105 according to this modified example differs from the imaging device 100 according to Embodiment 1 mainly in that the counter electrode 72 is connected to the connecting electrode 75 without going through the light-shielding layer 82.

[0153] In the imaging device 105, the counter electrode 72 is positioned across the pixel region R1 and the peripheral region R2, and covers the insulating layer 12 in a portion of the peripheral region R2. Furthermore, in the imaging device 105, the counter electrode 72 is in contact with the upper surface of the connecting electrode 75 and is directly connected to the connecting electrode 75. As a result, the electrical connection between the counter electrode 72 and the connecting electrode 75 can be formed by the formation of the counter electrode 72, thereby simplifying the manufacturing process of the imaging device 105. Moreover, the counter electrode 72 is not electrically connected to the connecting electrode 75 by being electrically connected to other conductors on its side, but rather is electrically connected to the connecting electrode 75 on the surface facing the connecting electrode 75. Therefore, the connection area between the connecting electrode 75 and the counter electrode 72 is increased, and the electrical resistance between the connecting electrode 75 and the counter electrode 72 can be reduced.

[0154] In the example shown in Figure 14, the light-shielding layer 82 does not cover the connecting electrode 75. In the example shown in Figure 14, in a plan view, the side of the light-shielding layer 82 on the connecting electrode 75 side and the side of the insulating layer 81 on the connecting electrode 75 side are aligned. Also, in the example shown in Figure 14, the light-shielding layer 82 is electrically insulated from the opposing electrode 72 and the connecting electrode 75. The arrangement and shape of the light-shielding layer 82, as well as the electrical connection between the light-shielding layer 82 and the opposing electrode 72 and the connecting electrode 75, are not particularly limited. Furthermore, the imaging device 105 does not need to be equipped with a light-shielding layer 82.

[0155] In addition, in the imaging device according to any of the modifications 1 to 4 of the above embodiment 1, the opposing electrode 72 may be in contact with the connecting electrode 75.

[0156] (Embodiment 2) Next, Embodiment 2 will be described. Embodiment 2 will describe a camera system equipped with an imaging device according to the present disclosure.

[0157] Figure 15 is a block diagram showing an example of the configuration of the camera system 400 according to this embodiment.

[0158] As shown in Figure 15, the camera system 400 according to this embodiment comprises a lens optical system 601, an imaging device 602, a system controller 603, and a camera signal processing circuit 604. The camera system 400 may be, for example, a smartphone, a digital camera, a video camera, or an in-vehicle camera.

[0159] The lens optical system 601 focuses light onto the imaging surface of the imaging device 602. The lens optical system 601 may include, for example, a lens group including an autofocus lens and a zoom lens, and an aperture. As the imaging device 602, for example, an imaging device according to any of the above-described embodiments 1 and 1 to 5 of embodiment 1 can be used.

[0160] The system controller 603 controls the entire camera system 400. The system controller 603 is, for example, a semiconductor integrated circuit, and a specific example is a CPU (Central Processing Unit).

[0161] The camera signal processing circuit 604 has the function of processing the output signal from the imaging device 602. The camera signal processing circuit 604 receives output data from the imaging device 602 and performs processing such as gamma correction, color interpolation, spatial interpolation, and auto white balance. The camera signal processing circuit 604 is, for example, a DSP (Digital Signal Processor). The imaging device 602 and the camera signal processing circuit 604 may be implemented as a single semiconductor device. The semiconductor device may be, for example, a so-called SoC (System on a Chip). With such a configuration, the electronic device including the imaging device 602 as part can be made smaller.

[0162] (Other Embodiments) The imaging apparatus and camera system relating to the present disclosure have been described above based on embodiments, but the present disclosure is not limited to these embodiments. Various modifications to the embodiments that a person skilled in the art can conceive of, as long as they do not depart from the spirit of the present disclosure, as well as other forms constructed by combining some of the components of the embodiments, are also included in the scope of the present disclosure.

[0163] For example, in the above embodiment, the imaging device comprises a first substrate 10 and a second substrate 20, but is not limited thereto. The imaging device according to this disclosure may comprise only the first substrate 10 as a substrate, and the pixels 31 may be connected to a device or element other than the imaging device according to this disclosure via a through electrode 41.

[0164] Furthermore, each of the above embodiments can be modified, replaced, added, or omitted in various ways within the scope of the claims or their equivalents.

[0165] The imaging device and camera system described herein are useful for, for example, image sensors, digital cameras, etc. The imaging device and camera system described herein can be used for medical cameras, robot cameras, security cameras, cameras mounted on vehicles, etc.

[0166] 10 First substrate 11, 21 Semiconductor substrate 12, 22, 80, 81 Insulating layer 12A, 12B, 12C, 12D, 12E Constituent layer 15A, 15B, 15C, 15D, 42, 44, 45 Wiring 19 Contact plug 20 Second substrate 25 Connection structure 30 Pixel array 31 Pixel 32 Detection circuit 33 Amplifying transistor 34 Selecting transistor 35 Reset transistor 40 Through-hole electrode group 41 Through-hole electrode 43, 48 Via 46 Shielding wiring 47 Backing wiring 51 Peripheral circuit 52 Vertical scanning circuit 53 Column signal processing circuit 54 Analog circuit 55 Memory 56 Logic circuit 57 Digital control circuit 58 Digital signal processing circuit 59 Output circuit 70 Photoelectric conversion unit 71 Pixel electrode 72 Opposing electrode 73 Photoelectric conversion layer 75, 75A Connecting electrodes 76 Gap 77 Vertical signal line 82 Light-shielding layer 83 Protective layer 84 Color filter 85 Planarization layer 86 Microlens 91, 93 Bonding pad area 92, 94 Bonding pad area group 100, 100A, 101, 102, 103, 104, 105, 602 Imaging device 400 Camera system 601 Lens optical system 603 System controller 604 Camera signal processing circuit FD Charge storage node Lcon Control signal line Lv Voltage line R1 Pixel area R2 Peripheral area

Claims

1. An imaging device comprising: a first substrate having a pixel region in which a plurality of pixels are arranged in a plan view, and a peripheral region adjacent to the pixel region, the first substrate including: a first semiconductor substrate located in the pixel region and the peripheral region; an insulating layer located above the first semiconductor substrate in the pixel region and the peripheral region; a first electrode located on the upper surface of the insulating layer in the pixel region; a photoelectric conversion layer located above the first electrode that converts light into electric charge; a second electrode located above the photoelectric conversion layer; a through electrode electrically connected to a first pixel among the plurality of pixels and penetrating the first semiconductor substrate in the peripheral region; and a third electrode located on the upper surface of the insulating layer in the peripheral region and electrically connected to the second electrode, wherein the through electrode is electrically insulated from the third electrode, and in a plan view, at least a part of the through electrode overlaps either the third electrode or a gap formed in the third electrode.

2. The imaging apparatus according to claim 1, further comprising: a second substrate laminated on the first substrate; and at least one of a signal processing circuit and a control circuit that supplies a control signal to the first pixel, which is disposed on the second substrate, wherein the signal processing circuit or the control circuit disposed on the second substrate is electrically connected to the first pixel via the through electrode.

3. The imaging apparatus according to claim 1, wherein the first pixel is configured to be supplied with a first voltage via the through electrode.

4. The imaging apparatus according to claim 1, further comprising a first wiring in contact with the upper surface of the through electrode, wherein the first wiring is located in the same layer as a second wiring located in the insulating layer within the pixel region.

5. The imaging apparatus according to claim 1, further comprising: a first via located within the insulating layer in the peripheral region; and a first wiring in contact with the upper surface of the through electrode and the upper surface of the first via, wherein, in a plan view, at least a portion of the first via overlaps with either the third electrode or a gap formed in the third electrode.

6. The imaging apparatus according to claim 1, wherein the distance between the upper surface of the through electrode and the third electrode is greater than the distance between the upper surface of the through electrode and the first semiconductor substrate.

7. The imaging apparatus according to claim 1, further comprising: a first wiring in contact with the upper surface of the through electrode; and a third wiring located between the third electrode and the first wiring.

8. The imaging apparatus according to claim 7, wherein the potential of the third wiring is fixed.

9. The imaging apparatus according to claim 1, further comprising: a fourth wiring located within the insulating layer and overlapping the third electrode in a plan view; and a second via electrically connecting the third electrode and the fourth wiring.

10. The imaging apparatus according to claim 1, wherein the second electrode is in contact with the third electrode.

11. The imaging apparatus according to claim 1, wherein, in a plan view, the entire through electrode overlaps the third electrode.

12. The imaging apparatus according to claim 1, further comprising a first wiring in contact with the upper surface of the through electrode, wherein in a plan view, the entirety of the first wiring overlaps the third electrode.

13. The imaging apparatus according to claim 1, wherein the third electrode has a striped portion in a plan view.

14. The imaging apparatus according to claim 1, wherein the third electrode is located in the same layer as the first electrode.

15. The imaging apparatus according to claim 1, wherein the third electrode contains the same material as the material contained in the first electrode.

16. A camera system comprising an imaging device according to any one of claims 1 to 15.

Images