Encoding device and decoding device

Abstract

The present disclosure pertains to an encoding device and a decoding device that enable suppression of image quality deterioration while maintaining throughput. In the present disclosure, a distributor divides a frame of an input image into pixel group units that serve as the smallest processing units for predictive encoding. A plurality of encoders predictively encode the pixels in the groups by sequentially switching for each of the divided groups. The present disclosure can be applied to, for example, an interface portion of an image sensor.

Description

Symbolization Device and Decoding Device

[0001] The present disclosure relates to a symbolization device and a decoding device, and particularly to a symbolization device and a decoding device that can suppress image quality degradation while maintaining throughput.

[0002] In recent years, with the increase in image resolution, frame rate, and dynamic range, the amount of data has also increased. In particular, in the interface part, the bandwidth requirements in each system have become more stringent, and there are also problems related to power consumption.

[0003] In response, a method of reducing the bandwidth by data compression technology is used. For example, there is a standard called DSC as an image data compression technology for displays formulated by VESA. DSC is a Lossy compression transmission technology, and it is a technology that can reduce the transmission bandwidth by applying irreversible compression to image data. This compression transmission technology is required to be at a level where degradation cannot be perceived visually by humans.

[0004] In DSC, in order to achieve a predetermined throughput in hardware implementation, "slice division" that divides the screen in the vertical and horizontal directions is performed. However, especially when vertical slice division is performed, a gap occurs in the compression mode at the boundary between slices, and degradation may be perceived near the boundary. In contrast, Patent Document 1 discloses a technique for reducing visual artifacts between slices by adjusting the quantization parameter of a block adjacent to the slice boundary.

[0005] Special Table 2018 - 534875 Gazette

[0006] It is required to suppress image quality degradation at the slice boundary while maintaining throughput.

[0007] The present disclosure has been made in view of such a situation, and is intended to suppress image quality degradation while maintaining throughput.

[0008] The encoding device according to the first aspect of this disclosure is an encoding device comprising a distributor that divides a frame of an input image into groups of pixels that constitute the smallest processing unit for predictive coding, and a plurality of encoders that sequentially switch between each of the divided groups to predictively encode the pixels within the group.

[0009] The decoding device according to the first aspect of this disclosure is a decoding device comprising a distributor that divides an encoded stream into groups of pixels that constitute the smallest processing unit for predictive coding, and a plurality of decoders that sequentially switch between each of the divided groups to predictively decode the pixels within the group.

[0010] The encoding device according to the second aspect of this disclosure is an encoding device comprising a distributor that divides a frame of an input image into M regions that serve as processing units for predictive encoding, and N encoders that predictively encode M / N (N << M) pixels within the regions that are not spatially adjacent.

[0011] The decoding device of the second aspect of this disclosure is a decoding device comprising a distributor that divides an encoded stream into M regions that serve as processing units for predictive coding, and N decoders that predictively decode M / N (N << M) pixels within the regions that are not spatially adjacent.

[0012] In the first aspect of this disclosure, the input image frame is divided into groups of pixels that constitute the smallest processing unit for predictive coding, and each divided group is sequentially switched over to predictively encode the pixels within the group. Alternatively, the encoded stream is divided into groups of pixels that constitute the smallest processing unit for predictive coding, and each divided group is sequentially switched over to predictively decode the pixels within the group.

[0013] In a second aspect of this disclosure, the input image frame is divided into M regions that serve as processing units for predictive coding, and M / N (N << M) pixels within these spatially non-adjacent regions are predictively coded. Alternatively, the coded stream is divided into M regions that serve as processing units for predictive coding, and pixels within M / N (N << M) spatially non-adjacent regions are predictively decoded.

[0014] This figure shows an example of vertical 4-part slicing. This figure explains the rate control function. This figure explains the pixel positions referenced in predictive coding. This figure explains slicing in the smallest processing unit. This figure explains pixel referencing in the technology of this disclosure. This figure shows an example configuration of an image processing system according to the first embodiment of this disclosure. This block diagram shows an example configuration of an encoding device. This figure explains the processing order of predictive coding. This block diagram shows an example configuration of an encoding core. This figure shows an example of pixel referencing in the first embodiment. This block diagram shows an example configuration of a predictor, quantizer, and reconstructor. This figure shows another example of pixel referencing in the first embodiment. This block diagram shows yet another example configuration of a predictor, quantizer, and reconstructor. This figure shows yet another example of pixel referencing in the first embodiment. This figure explains a specific example of a prediction method. This figure explains a specific example of a prediction method. This figure explains a specific example of a prediction method. This figure explains a specific example of a prediction method. This figure explains a specific example of a prediction method. This figure explains a specific example of a prediction method. This block diagram explains a specific example of a prediction method. This block diagram explains a specific example of a decoding device. This block diagram shows an example configuration of a decoding core. This block diagram shows an example configuration of a predictor, quantizer, and reconstructor. This figure shows an example configuration of an image processing system according to the second embodiment of this disclosure. This block diagram shows an example configuration of an encoding device. This block diagram shows an example configuration of an encoding core. This figure shows an example of pixel referencing in the second embodiment. This figure shows another example of pixel referencing in the second embodiment. This figure shows yet another example of pixel referencing in the second embodiment. This is a block diagram showing an example of the configuration of a decoding device. This is a block diagram showing an example of the configuration of a decoding core. This figure shows a modified image processing system. This figure illustrates slicing at an arbitrary processing unit. This is a block diagram showing a modified encoding device. This is a block diagram showing a modified decoding device. This figure shows an example of a pixel block that serves as a processing unit.

[0015] The following describes the forms for implementing this disclosure (hereinafter referred to as "embodiments"). The explanation will be given in the following order.

[0016] 1. Background 2. Conventional Technology and its Problems 3. Overview of the Technology Related to This Disclosure 4. First Embodiment (Configuration with Shared Line Buffer) 5. Second Embodiment (Configuration without Shared Line Buffer) 6. Modifications 7. Effects of This Disclosure

[0017] <1. Background> In recent years, with the increase in image resolution, frame rate, and dynamic range, the amount of data has also increased. In particular, the bandwidth requirements for each system have become stricter in the interface section, and there are also challenges related to power consumption.

[0018] In response to this, methods are used to reduce bandwidth through data compression technology. For example, there is a standard called DSC (Display Stream Compression) for image data compression technology for displays, which was developed by VESA (Video Electronics Standards Association). DSC is a lossy compression transmission technology that reduces transmission bandwidth by applying irreversible compression to image data. This compression transmission technology is required to be at a level where the degradation is not perceptible to the human eye.

[0019] In DSC (Digital Screen Control), "slice division" is performed to divide the screen vertically and horizontally in order to achieve a predetermined throughput in hardware implementation. However, as shown in Figure 1, for example, when slicing is performed into four vertical sections, gaps in the compression mode occur at the boundaries between slices, and degradation can be perceived near these boundaries. Therefore, it is necessary to suppress image quality degradation at slice boundaries while maintaining throughput.

[0020] <2. Conventional Technology and its Challenges> (Slice Division and Rate Control) Rate control can be implemented in DSC. As shown in Figure 2, rate control is a function that determines high-difficulty regions such as edges and high-frequency components in a single frame, and assigns a high bitrate to the high-difficulty regions and a low bitrate to the low-difficulty regions, thereby increasing the amount of information transmitted in the high-difficulty regions and ensuring image quality. In the example in Figure 2, a transmission amount of 5 bpp (bits per pixel) is assigned to the high-difficulty regions, and a transmission amount of 3 bpp is assigned to the low-difficulty regions.

[0021] However, when slicing is performed, rate control functions for each divided slice. Therefore, as shown in Figure 2, if the slice is divided vertically into four sections and the bitrate fluctuates across high-difficulty regions such as slices #0, #1, and #2, the gap in bitrate may cause a difference in image quality, which may be perceived as degradation.

[0022] (Slice splitting and core assignment) When slice splitting is implemented in a multicore architecture in DSC, a line buffer is provided for each core, and buffer access is performed on a core-by-core basis. While this is a suitable implementation method for ensuring throughput, it cannot eliminate the degradation caused by rate control during slice splitting as described above.

[0023] (Pixels used for predictive coding) In DSC, a group is formed with three pixels as the smallest processing unit, and predictive coding is performed on a group basis. When coding each pixel, a predicted value is generated from surrounding pixels, and the difference between this and the actual pixel value is entropy coded and transmitted.

[0024] Now, with reference to Figure 3, we will explain the pixel positions referenced in predictive coding.

[0025] In Figure 3, the group to be coded consists of three pixels, P0, P1, and P2, and the surrounding pixels A to E are referenced during predictive coding. However, because it is necessary to reference pixel A, which is adjacent to the left of the group, this can lead to constraints on the slicing method, or, depending on the slicing position, it may not be possible to reference pixel A, resulting in a decrease in coding performance and potentially degradation.

[0026] Furthermore, pixels B through E adjacent to the group are held in the line buffer and can be read without delay. However, pixel A, located on the same line as the group being encoded, is the data being encoded up to that point, and when referenced, the result of inverse quantization of the quantized data is referenced. This is a hardware bottleneck and inefficient from a throughput standpoint.

[0027] <3. Overview of the Technology Disclosed> The technology disclosed herein enables suppression of image quality degradation while maintaining throughput, even when high-difficulty areas are concentrated locally.

[0028] In other words, as shown in Figure 4, the technology disclosed herein involves slicing the image into 3-pixel units, which is the smallest processing unit in DSC, and sequentially switching the core assigned to each divided slice. This distributes the cores assigned to high-difficulty areas, thereby distributing the range of data capacity flexibility provided by rate control and suppressing localized image quality degradation.

[0029] Furthermore, as shown in Figure 5, during predictive coding, only pixels held on the line buffer are referenced, without referencing pixels adjacent to the left of the smallest processing unit group (pixels P0, P1, P2). This improves the degree of freedom in slice division and increases efficiency in terms of throughput.

[0030] In the following, we will describe an embodiment of an image processing system that can be used, for example, in the interface portion of an image sensor, as an embodiment applying the technology described herein.

[0031] <4. First Embodiment> (Image Processing System) Figure 6 is a diagram showing an example configuration of the image processing system according to the first embodiment of the present disclosure.

[0032] As shown in Figure 6, the image processing system of this embodiment consists of an encoding device 100 and a decoding device 200.

[0033] The encoding device 100 receives an input image, performs compression and encoding processing on the input image, and generates and outputs a compressed stream (encoded stream) ST.

[0034] The decoding device 200 receives the input of the compressed stream ST, performs decoding processing on the compressed stream ST, generates a decoded image, and outputs it.

[0035] (Encoding device 100) Figure 7 is a block diagram showing an example configuration of the encoding device 100.

[0036] As shown in Figure 7, the encoding device 100 consists of a distributor 101, encoding cores 102-1 to 102-4, an aggregater 103, and a storage area 104.

[0037] The distributor 101 vertically divides (slices) the input image frame into groups of pixels that constitute the smallest processing unit for predictive coding. The smallest processing unit group is, for example, three pixels (pixels P0, P1, P2). The slices divided by the distributor 101 are sequentially transferred to the encoder cores 102-1 to 102-4.

[0038] The encoder cores 102-1 to 102-4 sequentially perform compression and encoding on each slice divided by the distributor 101. The streams encoded by each of the encoder cores 102-1 to 102-4 are output to the aggregater 103. Hereafter, when the encoder cores 102-1 to 102-4 are not distinguished, they will simply be referred to as encoder core 102.

[0039] The aggregater 103 combines the streams encoded by each of the encoder cores 102 and outputs them as a single stream of data.

[0040] The memory area 104 is connected to each of the encoder cores 102. The memory area 104 temporarily stores the compressed images and luminance values obtained in all the encoder cores 102. Each encoder core 102 can perform compression and encoding processing on a slice while referring to the compressed images and luminance values held in the memory area 104.

[0041] In the encoding device 100 configured as described above, each encoder core 102 sequentially switches for each group (pixels P0, P1, P2) divided by the distributor 101, and performs predictive encoding on the pixels within the group. That is, as shown in FIG. 8, raster scanning is performed for each group assigned to each encoder core 102, and predictive encoding for each group is sequentially performed. As will be described later, internal processing units such as rate control are for each group of pixels drawn separately by hatching in FIG. 8, but the positions of the pixels referred to in predictive encoding and the like are for the entire screen (picture frame).

[0042] (Encoder Core 102) FIG. 9 is a block diagram showing a configuration example of the encoder core 102.

[0043] As shown in FIG. 9, the encoder core 102 is configured to include a color space converter 111, a buffer 112, a predictor / quantizer / reconstructor 113, a rate controller 114, a plane detector 115, an entropy encoder 118, a stream generation unit 119, and a rate buffer 120. Further, the memory area 104 connected to each of the encoder cores 102 includes a line buffer 116 and a color history manager 117.

[0044] The color space converter 111 converts the color space of the image data. For example, the color space converter 111 converts image data in the RGB space to the YUV space.

[0045] The buffer 112 holds the image data whose color space has been converted by the color space converter 111.

[0046] Predictor / Quantizer / Reconstructor 113 performs predictive coding on the image data input from Buffer 112, outputs the obtained quantization values to Entropy Encoder 118, and outputs the image data (reconstructed data) reconstructed from the quantization values to Line Buffer 116.

[0047] Rate Controller 114 varies the bit rate based on the properties (such as difficulty level) of the group assigned to Encoder Core 102, and determines transmission parameters and quantization parameters (QP).

[0048] Plane Detector 115 detects flat regions and complex regions in the image data, extracts information used by Rate Controller 114 and Entropy Encoder 118, and supplies it to each.

[0049] Line Buffer 116 functions as a common line buffer that holds pixel data for each line processed in each Encoder Core 102 in a manner that can be commonly referred to by all Encoder Cores 102. The pixel data held in Line Buffer 116 is the reconstructed data of the line one above the group (3 pixels) being processed in Predictor / Quantizer / Reconstructor 113.

[0050] Color History Manager 117 indexes the color history of the pixel most recently processed in each Encoder Core 102 and holds it in a manner that can be commonly referred to by all Encoder Cores 102.

[0051] Entropy Encoder 118 entropy-encodes the quantization values output from Predictor / Quantizer / Reconstructor 113 based on the information supplied from Plane Detector 115 and the color history held in Color History Manager 117.

[0052] Stream Generation Unit 119 generates a bitstream based on the encoded data obtained by the entropy encoding in Entropy Encoder 118.

[0053] The rate buffer 120 buffers the bitstream generated by the stream generation unit 119 and outputs it according to the bitrate set by the rate controller 114.

[0054] The encoder core 102 configured as described above can refer to the reconstructed data of the line one level above all the groups held in the line buffer 116. In other words, as shown in Figure 10, the encoder core 102 of this embodiment can perform predictive coding for each group by referring to the pixel data of the line one level above held in the line buffer 116, regardless of the group assigned to each encoder core 102.

[0055] (Predictor, quantizer, and reconstructor 113) Next, the configuration of the predictor, quantizer, and reconstructor 113 will be explained in comparison between the case where the technology relating to this disclosure is not applied and the case where the technology relating to this disclosure is applied.

[0056] Figure 11 is a block diagram showing an example configuration of the predictor, quantizer, and reconstructor 113 when the technology described herein is not applied.

[0057] The predictor / quantizer / reconstructor 113 shown in Figure 11 comprises a subtractor 121, a quantizer 122, an inverse quantizer 123, an adder 124, and a predictor 125.

[0058] Here, the image of the current line is input from buffer 112 to the predictor, quantizer, and reconstructor 113, while the image of the vertically higher line that has already been processed is held in line buffer 116.

[0059] The subtractor 121 subtracts the predicted value of the current line image supplied by the predictor 125 from the current line image to be encoded, which is input from the buffer 112, and outputs the resulting difference value.

[0060] The quantizer 122 quantizes the difference value output from the subtractor 121 and outputs it to the entropy encoder 118 and the inverse quantizer 123.

[0061] The inverse quantizer 123 inversely quantizes the quantized value output from the quantizer 122, outputs it to the adder 124, and transmits the quantized value to the predictor 125.

[0062] The adder 124 restores the pixel data by adding the inverse quantized value output from the inverse quantizer 123 and the predicted value from the predictor 125. The restored pixel data is held in the line buffer 116 and supplied to the predictor 125.

[0063] The predictor 125 calculates a predicted value for the pixel to be processed according to a predetermined prediction method, based on the image (pixel data) of the line above held in the line buffer 116, the pixel data from the adder 124, and the quantized value from the inverse quantizer 123. For example, in DSC, prediction methods such as MMAP (Modified Median-Adaptive Prediction) and MPP (Mid-Point Prediction) are used.

[0064] In the predictor, quantizer, and reconstructor 113 shown in Figure 11, the transmission of data indicated by the dashed arrows in the figure may become a bottleneck in terms of processing timing. Specifically, regarding the data supplied to the predictor 125, as explained with reference to Figure 3, pixels B to E are the pixel data of the line above that has already been processed and is held in the line buffer 116, so they can be read out without delay. On the other hand, the quantized value from the inverse quantizer 123 and pixel A from the adder 124 cannot be accessed until all previous processing is completed.

[0065] Therefore, in the predictor, quantizer, and reconstructor 113 of this embodiment, pixel A from the adder 124 is not referenced. That is, as shown in Figure 12A, the encoder core 102 of this embodiment can perform predictive coding for each group by referencing only the pixel data of the line above held in the line buffer 116, without referencing the pixel data of the group that was processed immediately before by another encoder core 102. Also, as shown in Figure 12B, it is possible to perform predictive coding for each group by moving the pixel data referenced as pixel A to the pixel data of the line above held in the line buffer 116 (for example, the pixel adjacent to the left of pixel C).

[0066] Figure 13 is a block diagram showing an example configuration of the predictor, quantizer, and reconstructor 113 when the technology relating to this disclosure is applied.

[0067] The predictor / quantizer / reconstructor 113 shown in Figure 13 comprises a subtractor 121, a quantizer 122, an inverse quantizer 123, an adder 124, a predictor 125, and delay buffers 126 and 127. In other words, the predictor / quantizer / reconstructor 113 shown in Figure 13 differs from the predictor / quantizer / reconstructor 113 shown in Figure 11 in that it further comprises delay buffers 126 and 127.

[0068] The delay buffer 126 temporarily holds the quantized values ​​from the inverse quantizer 123 and supplies them to the predictor 125. The delay buffer 127 temporarily holds the pixel data from the adder 124 and supplies it to the predictor 125. The delay buffers 126 and 127 can hold one or more groups of data and supply them to the predictor 125 at the appropriate timing.

[0069] Thus, when delay buffers are inserted between the inverse quantizer 123 and the predictor 125, and between the adder 124 and the predictor 125, when predicting the pixels of the group to be encoded, in addition to the pixel data of the line above held in the line buffer 116, it is possible to refer to pixel data of the same horizontal position (line), albeit remotely. In other words, as shown in Figure 14, the encoder core 102 of this embodiment can perform predictive encoding for each group by further referring to the pixel data (pixel A') of groups that were processed two or more times before, without referring to the pixel data of the group that was processed immediately before.

[0070] With the above configuration, there is more leeway in the processing timing of the predictor, quantizer, and reconstructor 113, enabling a more flexible circuit design.

[0071] (Specific example of prediction method) A specific example of the prediction method for pixels P0, P1, and P2 in the predictor 125 will be described. In DSC, the prediction of pixels P0, P1, and P2 is performed using pixel data (pixel values) such as BlendB, BlendC, BlendD, and BlendE, which are obtained by applying a filter to pixels B, C, D, and E. In this embodiment, the prediction of pixels P0, P1, and P2 can be performed using the pixel values ​​of pixels B, C, D, E, and F without applying such a filter.

[0072] (First Specific Example) Figure 15 is a diagram illustrating the first specific example of the prediction method for pixels P0, P1, and P2. As explained with reference to Figure 12A, Figure 15 shows four examples of prediction methods based on MMAP when pixel A is not referenced.

[0073] [1] Directly Above Prediction Directly above prediction is a prediction method that refers only to the pixel directly above pixels P0, P1, and P2 in the line one level above, which is held in the line buffer. That is, pixel P0 is the pixel data of the pixel B directly above it, pixel P1 is the pixel data of the pixel D directly above it, and pixel P2 is the pixel data of the pixel E directly above it. This prediction method does not refer to pixels C and F outside the left and right edges of pixels P0, P1, and P2, so it can be used even at the edges of the frame. Alternatively, the number of pixels referred can be increased by padding the pixels at the left and right edges.

[0074] [2] Three-pixel filter summation Three-pixel filter summation is a prediction method that calculates a weighted average of the three pixels directly above and to the left and right of pixels P0, P1, and P2 in the line above, which are held in the line buffer. That is, pixel P0 is defined as the sum of twice the pixel data of the pixel B directly above it and the pixel data of pixels C and D to its left and right, divided by 4. Pixels P1 and P2 are calculated in the same way.

[0075] [3] Median / Average The median / average is a prediction method that calculates the median or average of the three pixels directly above and to the left and right of pixels P0, P1, and P2 in the line above, which are held in the line buffer. That is, pixel P0 is taken as the median or average of the pixel data of the pixel B directly above it and the pixel data of pixels C and D to its left and right. Pixels P1 and P2 are calculated similarly.

[0076] [4] C / F Unreferenced Filter Addition C / F unreferenced filter addition is a prediction method in the three-pixel filter addition described above that does not refer to pixels C and F that are not directly above any of the pixels P0, P1, and P2. That is, pixel P0 is set to the value obtained by dividing the sum of three times the pixel data of the pixel B directly above it and the pixel data of the pixel D to its right by 4. Pixel P1 is set to the value obtained by dividing the sum of two times the pixel data of the pixel D directly above it and the pixel data of the pixels B and E to its left and right by 4. Pixel P2 is set to the value obtained by dividing the sum of three times the pixel data of the pixel E directly above it and the pixel data of the pixel D to its left by 4. This prediction method also does not refer to pixels C and F that are outside the left and right edges of pixels P0, P1, and P2, so it can be used at the edges of the frame, etc. Alternatively, the number of referenced pixels can be increased by padding the pixels at the left and right edges.

[0077] (Second Specific Example) Figure 16 illustrates a second specific example of the prediction method for pixels P0, P1, and P2. As explained with reference to Figure 12B, Figure 16 shows three examples of prediction methods based on MMAP when pixel A is moved to the line above (pixel A') held in the line buffer. In Figure 16, solid arrows represent addition of pixel data, dashed arrows represent subtraction of pixel data, and dotted arrows represent addition of the difference values ​​of two pixel data.

[0078] [1] Three-direction prediction with fixed A' and C The three-direction prediction with fixed A' and C is a prediction method that refers to the pixels directly above pixels P0, P1, and P2 in the line above, which are held in the line buffer, as well as pixels A' and C. That is, pixel P0 is the value obtained by subtracting the pixel data of pixel C from the sum of the pixel data of the pixel B directly above it and the pixel data of pixel A'. Pixels P1 and P2 are determined in the same way.

[0079] [2] A' Fixed Three-Direction Prediction The A' fixed three-direction prediction is a prediction method that refers to the pixels directly above and to the left of pixels P0, P1, and P2 in the line above, which are held in the line buffer, and to pixel A'. That is, pixel P0 is the sum of the pixel data of the pixel B directly above it and the pixel data of pixel A', minus the pixel data of pixel C to the left of the pixel B directly above it. Pixel P1 is the sum of the pixel data of the pixel D directly above it and the pixel data of pixel A', minus the pixel data of pixel B to the left of the pixel D directly above it. Pixel P2 is the sum of the pixel data of the pixel E directly above it and the pixel data of pixel A', minus the pixel data of pixel D to the left of the pixel E directly above it.

[0080] [3] Method of adding up residuals of the upper line The method of adding up residuals of the upper line is a prediction method in which the difference values ​​of the pixel directly above and its adjacent pixels are sequentially added up in the three-direction prediction with A' and C fixed as described above. That is, pixel P0 is the same value obtained by the three-direction prediction with A' and C fixed. Pixel P1 is the value obtained by the three-direction prediction with A' and C fixed, plus the difference value of the pixel directly above D and its adjacent pixel B. Pixel P2 is the value obtained by the three-direction prediction with A' and C fixed, plus the difference value of the pixel directly above E and its adjacent pixel D, and the difference value of adjacent pixel D and its further adjacent pixel B.

[0081] (Third Specific Example) Figure 17 illustrates a third specific example of the prediction method for pixels P0, P1, and P2. As explained with reference to Figure 14, Figure 17 shows three examples of prediction methods based on MMAP when pixel A', which is located at the same horizontal position (line) but at a distance, is specified as pixel A. Note that the three prediction methods shown in Figure 17 are the same as the three prediction methods explained with reference to Figure 16, except that the position of the referenced pixel A' is different, so the explanation will be omitted.

[0082] (Fourth Specific Example) Figure 18 illustrates a fourth specific example of the prediction method for pixels P0, P1, and P2. Figure 18 shows an example of a prediction method based on MPP.

[0083] [1] Upward reference is a prediction method that references the midpoint value of pixels P0, P1, and P2 and the sample pR of the three pixels (group) directly above pixels P0, P1, and P2 in the line above, which is held in the line buffer. That is, if the bit length per pixel is cpntBitDepth and the number of bits to quantize is qLevel, then pixels P0, P1, and P2 can be obtained as (1 << (cpntBitDepth - 1)) + (pR & (1 << (qLevel - 1))).

[0084] (Fifth Specific Example) Figure 19 illustrates a fifth specific example of the prediction method for pixels P0, P1, and P2. The three prediction methods shown in Figure 19 can be used as both an MMAP-based prediction method when the line buffer cannot be referenced at the top of the frame, and an MPP-based prediction method at the top of the frame.

[0085] [1] Zero-filling Zero-filling is a prediction method in which the pixel data of all pixels P0, P1, and P2 is set to 0. That is, pixels P0, P1, and P2 are all 0.

[0086] [2] External Parameters The external parameter is a prediction method in which all pixel data of pixels P0, P1, and P2 are used as external parameters. When the external parameter is RegisteredValue, pixels P0, P1, and P2 will all be RegisteredValue. The external parameter RegisteredValue may be, for example, a sensor parameter such as the optical black of the image sensor that captured the input image.

[0087] [3] Median bitDepth The median bitDepth is a prediction method in which the median bitDepth, which indicates the bit length per pixel, is used for all pixel data of pixels P0, P1, and P2. That is, pixels P0, P1, and P2 are all 2 to the power of (bitDepth-1).

[0088] (Decoding device 200) Figure 20 is a block diagram showing an example configuration of the decoding device 200.

[0089] As shown in Figure 20, the decoding device 200 consists of a distributor 201, decoder cores 202-1 to 202-4, an aggregater 203, and a storage area 204.

[0090] The distributor 201 vertically divides (slices) the stream data output by the encoding device 100 into groups of pixels that constitute the smallest processing unit for predictive coding. The smallest processing unit group is, for example, three pixels (pixels P0, P1, P2). The slices divided by the distributor 201 are sequentially transferred to the decoder cores 202-1 to 202-4.

[0091] Decoder cores 202-1 to 202-4 sequentially perform decoding on each slice divided by the distributor 201. The images decoded by each of the decoder cores 202-1 to 202-4 are output to the aggregater 203. Hereafter, when decoder cores 202-1 to 202-4 are not distinguished, they will simply be referred to as decoder core 202.

[0092] The aggregater 203 combines the images decoded by each of the decoder cores 202 and outputs them as a single decoded image.

[0093] The memory area 204 is connected to each of the decoder cores 202. The memory area 204 temporarily stores the decoded images and brightness values ​​obtained by all decoder cores 202. Each decoder core 202 can perform decoding on a slice while referring to the decoded images and brightness values ​​held in the memory area 204.

[0094] In the decoding device 200 configured as described above, each decoder core 202 sequentially switches to each group (pixels P0, P1, P2) divided by the distributor 201 to predict and decode the pixels within the group. That is, as shown in Figure 8, each group assigned to each decoder core 202 is raster-scanned, and predictive decoding is performed sequentially for each group. Here again, the internal processing unit, such as rate control, is set to each group of pixels, but the pixel positions referenced in predictive decoding are set to the entire screen (frame).

[0095] (Decoder core 202) Figure 21 is a block diagram showing an example configuration of the decoder core 202.

[0096] As shown in Figure 21, the decoder core 202 is configured to include a rate buffer 211, a stream decoder 212, an entropy decoder 213, a predictor / quantizer / reconstructor 214, a rate controller 215, and a color space converter 218. In addition, the memory area 204 connected to each decoder core 202 includes a color history manager 216 and a line buffer 217.

[0097] The rate buffer 211 buffers the bitstream transmitted from the distributor 201 and outputs it according to the bitrate set by the rate controller 215.

[0098] The stream decoding unit 212 decodes the bitstream output by the rate buffer 211 and transmits the resulting encoded data to the entropy decoder 213.

[0099] The entropy decoder 213 reconstructs quantized values ​​(quantized difference values), color history index values, and predicted residual information by entropy decoding the encoded data from the stream decoding unit 212.

[0100] The predictor / quantizer / reconstructor 214 performs predictive decoding of the quantized difference value or color history index value reconstructed by the entropy decoder 213, and outputs the obtained decoded data (image data) to the color space converter 218 and also to the line buffer 217.

[0101] The rate controller 215 varies the bit rate based on the properties (such as difficulty) of the group assigned to the decoder core 202, and determines the transmission parameters and quantization parameters (QP).

[0102] The color history manager 216 stores the brightness value of the most recently processed pixel in each decoder core 202, making it accessible to all decoder cores 202.

[0103] The line buffer 217 functions as a common line buffer that holds the pixel data for each line processed by each decoder core 202, making it accessible to all decoder cores 202. The pixel data held in the line buffer 217 is the reconstructed data of the line one level above the group (3 pixels) being processed by the predictor, quantizer, and reconstructor 214.

[0104] The color space converter 218 converts the color space of the image data. For example, the color space converter 218 converts image data in YUV space to RGB space.

[0105] The decoder core 202 configured as described above can refer to the reconstruction data of the line one level above all the groups held in the line buffer 217. In other words, as shown in Figure 10, the decoder core 202 of this embodiment can perform predictive decoding for each group by referring to the pixel data of the line one level above held in the line buffer 217, regardless of the group assigned to each decoder core 202.

[0106] (Predictor, quantizer, and reconstructor 214) Figure 22 is a block diagram showing an example configuration of the predictor, quantizer, and reconstructor 214.

[0107] The predictor / quantizer / reconstructor 214 shown in Figure 22 comprises a selector 221, a color history selector 222, an inverse quantizer 223, a predictor 224, an adder 225, a selector 226, and delay buffers 227 and 228.

[0108] In the predictor, quantizer, and reconstructor 214, the input of either the quantized difference value from the entropy decoder 213 or the color history index value depends on the stream input to the decoder 200. The predictor, quantizer, and reconstructor 214 then perform different operations in each case.

[0109] When a quantized difference value is input to the predictor / quantizer / reconstructor 214, the data is transmitted from the selector 221 to the inverse quantizer 223. The inverse quantizer 123 performs inverse quantization processing and transmits the inverse quantized value to the adder 225 and the delay buffer 227. The delay buffer 227 has the same function as the delay buffer 126 described with reference to Figure 13, and can supply data to the predictor 224 at the appropriate timing.

[0110] The predictor 224, like the predictor 125 of the encoder core 102, calculates the predicted value of the pixel to be processed and supplies the result to the adder 225. The adder 225 restores the pixel data by adding the inverse quantized value from the inverse quantizer 123 and the predicted value from the predictor 224. The restored pixel data is supplied to the selector 226 and also stored in the color history manager 216.

[0111] On the other hand, when a color history index value is input to the predictor / quantizer / reconstructor 214, data is transmitted from the selector 221 to the color history selector 222. Based on the index value from the selector 221, the color history selector 222 selects a luminance value held in the color history manager 216 and supplies it to the selector 226.

[0112] In all of the above cases, the image data is output from the selector 226 and also supplied to and held in the delay buffer 228 and the line buffer 217. The delay buffer 228 has the same function as the delay buffer 127 described with reference to Figure 13, and can supply data to the predictor 224 at the appropriate timing.

[0113] In this way, by inserting delay buffers between the inverse quantizer 223 and the predictor 224, and between the selector 226 and the predictor 224, when predicting the pixels of the group to be decoded, it is possible to refer to pixel data at the same horizontal position (line), albeit remotely, in addition to the pixel data of the line above that is held in the line buffer 217. That is, as shown in Figure 14, the decoder core 202 of this embodiment can perform predictive decoding for each group by referring to the pixel data of groups that were processed two or more steps ago, rather than referring to the pixel data of the group that was processed immediately before.

[0114] Furthermore, in the predictor, quantizer, and reconstructor 214, delay buffers may not be provided between the inverse quantizer 223 and the predictor 224, or between the selector 226 and the predictor 224. That is, as shown in Figure 12A, the decoder core 202 of this embodiment can perform predictive decoding for each group by referring only to the pixel data of the line above held in the line buffer 217, without referring to the pixel data of the group that was processed immediately before in another decoder core 202. Also, as shown in Figure 12B, it is possible to move the pixel data to be referred to as pixel A to the pixel data of the line above held in the line buffer 217 (for example, the pixel adjacent to the left of pixel C) and perform predictive decoding for each group.

[0115] <5. Second Embodiment> (Image Processing System) Figure 23 is a diagram showing an example configuration of an image processing system according to the second embodiment of the present disclosure.

[0116] As shown in Figure 23, the image processing system of this embodiment consists of an encoding device 300 and a decoding device 400.

[0117] The encoding device 300 receives an input image, performs compression and encoding processing on the input image, and generates and outputs a compressed stream ST.

[0118] The decoding device 400 receives the input of the compressed stream ST, performs decoding processing on the compressed stream ST, generates a decoded image, and outputs it.

[0119] (Encoding device 300) Figure 24 is a block diagram showing an example configuration of the encoding device 300.

[0120] As shown in Figure 24, the encoding device 300 consists of a distributor 301, encoding cores 302-1 to 302-4, and an aggregater 303.

[0121] The distributor 301 vertically divides (slices) the input image frame into groups of pixels that constitute the smallest processing unit for predictive coding. The smallest processing unit group is, for example, three pixels (pixels P0, P1, P2). The slices divided by the distributor 301 are sequentially transferred to the encoder cores 302-1 to 302-4.

[0122] The encoder cores 302-1 to 302-4 sequentially perform compression and encoding on each slice divided by the distributor 301. The streams encoded by each of the encoder cores 302-1 to 302-4 are output to the aggregater 303. Hereafter, when the encoder cores 302-1 to 302-4 are not distinguished, they will simply be referred to as encoder core 302.

[0123] The aggregater 303 combines the streams encoded by each of the encoder cores 302 and outputs them as a single stream of data.

[0124] Thus, the encoding device 300 of this embodiment differs from the encoding device 100 described with reference to Figure 7 in that it does not have a storage area connected to each of the encoding cores 302.

[0125] (Encoder core 302) Figure 25 is a block diagram showing an example configuration of the encoder core 302.

[0126] As shown in Figure 25, the encoder core 302 is configured to include a color space converter 311, a buffer 312, a predictor / quantizer / reconstructor 313, a rate controller 314, a plane detector 315, a line buffer 316, a color history manager 317, an entropy encoder 318, a stream generation unit 319, and a rate buffer 320.

[0127] In the encoder core 302 shown in Figure 25, the configurations other than the line buffer 316 and the color history manager 317 are the same as those of the encoder core 102 described with reference to Figure 9, so their explanation will be omitted.

[0128] In other words, in this embodiment, each encoder core 302 has a line buffer 316 and a color history manager 317.

[0129] The line buffer 316 functions as an individual line buffer that holds the pixel data for each line processed by each encoder core 302, making it accessible to each encoder core 302 individually. The pixel data held in the line buffer 316 is the reconstructed data of the line one level above the group (3 pixels) being processed by the predictor, quantizer, and reconstructor 313.

[0130] The color history manager 317 indexes the color history of the most recently processed pixel in each of the encoder cores 302 and stores it so that each encoder core 302 can individually refer to it.

[0131] The encoder core 302 configured as described above can refer to the reconstruction data of the line one level above each group held in the line buffer 316. That is, as shown in Figure 26, the encoder core 302 of this embodiment can perform predictive coding for each group assigned to each encoder core 302 by referring to the pixel data of the line one level above held in the line buffer 316.

[0132] Furthermore, as shown in Figure 27A, the encoder core 302 of this embodiment can perform predictive coding for each group by referring only to the pixel data of the line above it, which is held in the line buffer 316, without referring to the pixel data of the group that the encoder core 302 itself processed the previous time. Also, as shown in Figure 27B, it is possible to move the pixel data to be referred to as pixel A to the pixel data of the line above it, which is held in the line buffer 316 (for example, the pixel adjacent to the left of pixel C), and then perform predictive coding for each group.

[0133] Furthermore, the encoder core 302 is equipped with a predictor, quantizer, and reconstructor 313 that has the same function as the predictor, quantizer, and reconstructor 113 described with reference to Figure 13. That is, as shown in Figure 28, the encoder core 302 of this embodiment does not refer to the pixel data of the group that it processed immediately before, but further refers to the pixel data (pixel A') of groups that were processed two or more steps prior, and can perform predictive coding for each group.

[0134] (Decoding device 400) Figure 29 is a block diagram showing an example configuration of the decoding device 400.

[0135] As shown in Figure 29, the decoding device 400 consists of a distributor 401, decoder cores 402-1 to 402-4, and an aggregater 403.

[0136] The distributor 401 vertically divides (slices) the stream data output by the encoding device 300 into groups of pixels that constitute the smallest processing unit for predictive coding. The smallest processing unit group is, for example, three pixels (pixels P0, P1, P2). The slices divided by the distributor 401 are sequentially transferred to the decoder cores 402-1 to 402-4.

[0137] Decoder cores 402-1 to 402-4 sequentially perform decoding on each slice divided by the distributor 401. The images decoded by each of the decoder cores 402-1 to 402-4 are output to the aggregater 403. Hereafter, when decoder cores 402-1 to 402-4 are not distinguished, they will simply be referred to as decoder core 402.

[0138] The aggregater 403 combines the images decoded by each of the decoder cores 402 and outputs them as a single decoded image.

[0139] Thus, the decoding device 400 of this embodiment differs from the decoding device 200 described with reference to Figure 20 in that it does not have a storage area connected to each of the decoding cores 402.

[0140] (Decoder core 402) Figure 30 is a block diagram showing an example configuration of the decoder core 402.

[0141] As shown in Figure 30, the decoder core 402 is configured to include a rate buffer 411, a stream decoder 412, an entropy decoder 413, a predictor / quantizer / reconstructor 414, a rate controller 415, a color history manager 416, a line buffer 417, and a color space converter 418.

[0142] In the decoder core 402 shown in Figure 30, the components other than the color history manager 416 and the line buffer 417 are the same as those of the decoder core 202, as explained with reference to Figure 21, so their explanation will be omitted.

[0143] In other words, in this embodiment, each decoder core 402 has a color history manager 416 and a line buffer 417.

[0144] The color history manager 416 stores the brightness value of the most recently processed pixel in each decoder core 402, making it accessible to each decoder core 402 individually.

[0145] The line buffer 417 functions as an individual line buffer that holds the pixel data for each line processed by each decoder core 402, making it accessible to each decoder core 402 individually. The pixel data held in the line buffer 417 is the reconstructed data of the line one level above the group (3 pixels) being processed by the predictor, quantizer, and reconstructor 414.

[0146] The decoder core 402 configured as described above can refer to the reconstruction data of the line one level above each group held in the line buffer 417. That is, as shown in Figure 26, the decoder core 402 of this embodiment can perform predictive decoding for each group by referring to the pixel data of the line one level above each group held in the line buffer 417 for each group assigned to the decoder core 402.

[0147] Furthermore, as shown in Figure 27A, the decoder core 402 of this embodiment can perform predictive decoding for each group by referring only to the pixel data of the line above it, which is held in the line buffer 417, without referring to the pixel data of the group that the decoder core 402 itself processed the previous time. Also, as shown in Figure 27B, it is possible to move the pixel data to be referred to as pixel A to the pixel data of the line above it, which is held in the line buffer 417 (for example, the pixel adjacent to the left of pixel C), and perform predictive decoding for each group.

[0148] Furthermore, the decoder core 402 is equipped with a predictor, quantizer, and reconstructor 414 that has the same functions as the predictor, quantizer, and reconstructor 214 described with reference to Figure 22. That is, as shown in Figure 28, the decoder core 402 of this embodiment does not refer to the pixel data of the group that it processed immediately before, but further refers to the pixel data of groups that it processed two or more times before, and can perform predictive decoding for each group.

[0149] <6. Modified Examples> (Image Processing System) Figure 31 shows a modified example of the image processing system according to the embodiment of the present disclosure.

[0150] As shown in Figure 31, this modified image processing system consists of an encoding device 500 and a decoding device 600.

[0151] The encoding device 500 receives an input image, performs compression and encoding processing on the input image, and generates and outputs a compressed stream ST.

[0152] The decoding device 600 receives the input of the compressed stream ST, performs decoding processing on the compressed stream ST, generates a decoded image, and outputs it.

[0153] In this modified image processing system, as shown in Figure 32, the image is sliced ​​into M regions at a unit of arbitrary pixel count, which is the processing unit for predictive coding, and the N cores assigned to each of the divided slices are switched sequentially. Here, the number of divisions M is assumed to be sufficiently larger than the number of cores N (N << M). Even in this configuration, by distributing the cores assigned to high-difficulty regions, the range of data capacity flexibility due to rate control can be distributed, and locally occurring image quality degradation can be suppressed.

[0154] (Encoding device 500) Figure 33 is a block diagram showing an example configuration of the encoding device 500.

[0155] As shown in Figure 33, the encoding device 500 consists of a distributor 501, encoding cores 502-1 to 502-4, an aggregater 503, and a storage area 504.

[0156] The distributor 501 divides the input image frame into M regions, which will be processing units for predictive coding. The M regions divided by the distributor 501 are sequentially transferred to the encoder cores 502-1 to 502-4.

[0157] The encoder cores 502-1 to 502-4 sequentially perform compression and encoding processing on each region divided by the distributor 501. Specifically, each of the encoder cores 502-1 to 502-4 predictively encodes pixels within M / N spatially non-adjacent regions. The streams encoded by each of the encoder cores 502-1 to 502-4 are output to the aggregater 503. Hereafter, when the encoder cores 502-1 to 502-4 are not distinguished, they will simply be referred to as encoder core 502.

[0158] The aggregater 503 combines the streams encoded by each of the encoder cores 502 and outputs them as a single stream of data.

[0159] The memory area 504 is connected to each of the encoder cores 502. The memory area 504 temporarily stores the compressed images and brightness values ​​obtained by all of the encoder cores 502. Each of the encoder cores 502 can perform compression and encoding processing on a region while referring to the compressed images and brightness values ​​held in the memory area 504.

[0160] In the encoding device 500, the number of encoder cores 502 (number of cores N) is not limited to four, but can be set as appropriate as needed. Also, the encoding device 500 may not have a storage area 504, similar to the encoding device 300 described with reference to Figure 24.

[0161] (Decoding device 600) Figure 34 is a block diagram showing an example configuration of the decoding device 600.

[0162] As shown in Figure 34, the decoding device 600 consists of a distributor 601, decoder cores 602-1 to 602-4, an aggregater 603, and a storage area 604.

[0163] The distributor 601 divides the stream data output by the encoding device 500 into M regions, which will be the processing units for predictive coding. The M regions divided by the distributor 601 are sequentially transferred to the decoder cores 602-1 to 602-4.

[0164] Decoder cores 602-1 to 602-4 sequentially perform decoding on each region divided by the distributor 601. Specifically, each of the decoder cores 602-1 to 602-4 predicts and decodes pixels within M / N spatially non-adjacent regions. The images decoded by each of the decoder cores 602-1 to 602-4 are output to the aggregater 603. Hereafter, when the decoder cores 602-1 to 602-4 are not distinguished, they will simply be referred to as decoder core 602.

[0165] The aggregater 603 combines the images decoded by each of the decoder cores 602 and outputs them as a single decoded image.

[0166] The memory area 604 is connected to each of the decoder cores 602. The memory area 604 temporarily stores the decoded images and brightness values ​​obtained by all decoder cores 602. Each decoder core 602 can perform decoding on a region while referring to the decoded images and brightness values ​​held in the memory area 604.

[0167] In the decoding device 600, the number of decoder cores 602 (number of cores N) is not limited to four, but can be set as appropriate as needed. Also, the decoding device 600 may not have a storage area 604, similar to the decoding device 400 described with reference to Figure 29.

[0168] In the encoding device 500 and the decoding device 600, the group that serves as the processing unit for predictive coding is not limited to a 3-pixel unit, but may be a 6-pixel unit as shown in Figure 35A, or a 9-pixel unit (not shown), for example. Furthermore, the group that serves as the processing unit for predictive coding may be a two-dimensionally arranged pixel unit, such as a 2x3 pixel unit as shown in Figure 35B, or a 2x4 pixel unit (not shown). Thus, according to this embodiment, the frame of the input image can be divided into arbitrary pixel units according to the processing unit for predictive coding.

[0169] <7. Effects of the Disclosure> According to the technology disclosed herein, the input image frame is divided into pixel groups that serve as the smallest processing unit for predictive coding, making it possible to suppress image quality degradation at slice boundaries while maintaining throughput.

[0170] In other words, according to the technology disclosed herein, for example, it is possible to slice the image into 3 pixels, which is the smallest processing unit of a DSC. Furthermore, by improving the degree of freedom of slice division while maintaining throughput and distributing the cores allocated to high-difficulty areas, the range of data capacity flexibility through rate control can be distributed, and localized image quality degradation can be suppressed.

[0171] In this specification, a system means a collection of multiple components (devices, modules (parts), etc.), regardless of whether all components are located in the same enclosure. Therefore, multiple devices housed in separate enclosures and connected via a network, and a single device containing multiple modules in one enclosure, are both considered systems.

[0172] Furthermore, embodiments applying the technology described herein are not limited to those described above, and various modifications are possible without departing from the gist of the technology described herein.

[0173] Furthermore, the present disclosure can take the following configurations: (1) An encoding device comprising a distributor that divides a frame of an input image into groups of pixels that constitute the smallest processing unit for predictive coding, and a plurality of encoders that sequentially switch between each of the divided groups to predictively code the pixels within the group. (2) The encoding device according to (1), further comprising a common line buffer that holds pixel data for each line processed by each of the encoders so that all of the encoders can refer to it in common. (3) The encoding device according to (2), wherein the encoder predictively codes the pixels within the group by referring only to the pixel data held in the common line buffer, without referring to the pixel data of the group that was processed immediately before by another encoder. (4) The encoding device according to (3), wherein the encoder predictively codes the pixels within the group by further referring to the pixel data of the group that was processed two or more steps prior. (5) The encoding device according to (1), further comprising an individual line buffer which holds pixel data for each line processed by each of the encoders in a manner that each encoder can individually refer to. (6) The encoding device according to (5), wherein the encoder predictively encodes the pixels in the group by referring only to the pixel data held in the individual line buffer, without referring to the pixel data of the group that was processed one step earlier. (7) The encoding device according to (6), wherein the encoder predictively encodes the pixels in the group by further referring to the pixel data of the group that was processed two or more steps earlier. (8) The encoding device according to any one of (1) to (7), further comprising a color history manager which holds the color history of the pixels processed by each of the encoders in a manner that all of the encoders can commonly refer to. (9) A decoding device comprising a distributor which divides an encoded stream into groups of pixels which are the smallest processing units for predictive encoding, and a plurality of decoders which sequentially switch between each of the divided groups to predictively decode the pixels in the group.(10) The decoding apparatus according to (9), further comprising a common line buffer that holds pixel data for each line processed by each of the decoders in a manner that can be commonly referenced by all of the decoders. (11) The decoding apparatus according to (10), wherein the decoder predicts and decodes the pixels in the group by referring only to the pixel data held in the common line buffer, without referring to the pixel data of the group that was processed immediately before by another decoder. (12) The decoding apparatus according to (11), wherein the decoder predicts and decodes the pixels in the group by further referring to the pixel data of the group that was processed two or more steps prior. (13) The decoding apparatus according to (9), further comprising individual line buffers that hold pixel data for each line processed by each of the decoders in a manner that can be individually referenced by each of the decoders. (14) The decoding device according to (13), wherein the decoder predicts and decodes the pixels in the group by referring only to the pixel data held in the individual line buffer, without referring to the pixel data of the group that was processed one step earlier. (15) The decoding device according to (14), wherein the decoder further predicts and decodes the pixels in the group by referring to the pixel data of the group that was processed two or more steps earlier. (16) The decoding device according to any one of (9) to (15), further comprising a color history manager that holds the color history of the pixels that were processed by each of the decoders in a manner that can be commonly referred to by all of the decoders. (17) An encoding device comprising a distributor that divides a frame of an input image into M regions that become processing units for predictive coding, and N encoders that predictively code M / N (N << M) pixels in the regions that are not spatially adjacent. (18) A decoding device comprising a distributor that divides an encoded stream into M regions that serve as processing units for predictive coding, and N decoders that predictively decode M / N (N << M) pixels within the regions that are not spatially adjacent. (19) An encoding method that includes dividing a frame of an input image into groups of pixels that serve as the smallest processing units for predictive coding, and sequentially switching between the divided groups to predictively code the pixels within the groups.(20) A decoding method comprising: vertically dividing an encoded stream into groups of pixels that constitute the smallest processing unit for predictive coding; and sequentially switching between each of the divided groups to predictively decode the pixels within the group.

[0174] 100 Encoder, 101 Distributor, 102-1 to 102-4, 102 Encoder core, 103 Aggregator, 104 Memory area, 116 Line buffer, 117 Color history manager, 200 Decoder, 201 Distributor, 202-1 to 202-4, 202 Decoder core, 203 Aggregator, 204 Memory area, 216 Color history manager, 217 Line buffer, 300 Encoder, 301 Distributor, 302-1 to 302-4, 302 Encoder core, 303 Aggregator, 316 Line buffer, 317 Color history manager, 400 Decoder, 401 Distributor, 402-1 to 402-4, 402 Decoder core, 403 Aggregator, 416 Color history manager, 417 Line buffer, 500 Encoder, 501 Distributor, 502-1 to 502-4, 502 Encoder core, 503 Aggregator, 504 Memory area, 600 Decoder, 601 Distributor, 602-1 to 602-4, 602 Decoder core, 603 Aggregator, 604 Memory area

Claims

1. An encoding device comprising: a distributor that divides an input image frame into groups of pixels that constitute the smallest processing unit for predictive coding; and a plurality of encoders that sequentially switch between each of the divided groups to predictively encode the pixels within each group.

2. The encoding apparatus according to claim 1, further comprising a common line buffer that holds pixel data for each line processed by each of the encoders in a manner that can be commonly referenced by all of the encoders.

3. The encoding device according to claim 2, wherein the encoder predictively encodes the pixels in the group by referring only to the pixel data held in the common line buffer, without referring to the pixel data of the group that was processed immediately before by another encoder.

4. The encoding device according to claim 3, wherein the encoder further references the pixel data of the group that was processed two or more steps prior to the encoding device, and predictively encodes the pixels within the group.

5. The encoding apparatus according to claim 1, further comprising an individual line buffer that holds pixel data for each line processed by each of the encoders in a manner that each encoder can individually access.

6. The encoding device according to claim 5, wherein the encoder predictively encodes the pixels in the group by referring only to the pixel data held in the individual line buffer, without referring to the pixel data of the group that was processed in the previous step.

7. The encoding device according to claim 6, wherein the encoder further references the pixel data of the group that was processed two or more steps prior to the encoding device, and predictively encodes the pixels within the group.

8. The encoding apparatus according to claim 1, further comprising a color history manager that maintains the color history of the pixels processed by each of the encoders in a manner that can be commonly referenced by all of the encoders.

9. A decoding device comprising a distributor that divides an encoded stream into groups of pixels that constitute the smallest processing unit for predictive coding, and a plurality of decoders that sequentially switch between each of the divided groups to predictively decode the pixels within the group.

10. The decoding apparatus according to claim 9, further comprising a common line buffer that holds pixel data for each line processed by each of the decoders in a manner that can be commonly referenced by all of the decoders.

11. The decoding apparatus according to claim 10, wherein the decoder predicts and decodes the pixels in the group by referring only to the pixel data held in the common line buffer, without referring to the pixel data of the group that was processed immediately before by another decoder.

12. The decoding device according to claim 11, wherein the decoder further refers to the pixel data of the group that was processed two or more steps prior to predict and decode the pixels in the group.

13. The decoding apparatus according to claim 9, further comprising an individual line buffer that holds pixel data for each line processed by each decoder in a manner that each decoder can individually access.

14. The decoding device according to claim 13, wherein the decoder predicts and decodes the pixels in the group by referring only to the pixel data held in the individual line buffer, without referring to the pixel data of the group that was processed in the previous step.

15. The decoding device according to claim 14, wherein the decoder further refers to the pixel data of the group that was processed two or more steps prior to predict and decode the pixels within the group.

16. The decoding apparatus according to claim 9, further comprising a color history manager that maintains the color history of the pixels processed by each of the decoders in a manner that can be commonly referenced by all of the decoders.

17. An encoding device comprising a distributor that divides an input image frame into M regions that serve as processing units for predictive coding, and N encoders that predictively encode M / N (N << M) pixels within the regions that are not spatially adjacent.

18. A decoding device comprising a distributor that divides an encoded stream into M regions that serve as processing units for predictive coding, and N decoders that predictively decode M / N (N << M) pixels within the regions that are not spatially adjacent.

Images