Wiring board and electrical connection device

Abstract

[Problem] The present invention makes it possible to reduce the coefficient of thermal expansion of a substrate in association with a temperature change and to follow changes in a semiconductor wafer without significantly impairing the electric properties. [Solution] A wiring board according to the present invention comprises a thin film wiring unit that electrically connects to a plurality of connection terminals of a contactor that is to be brought into contact with an electrode terminal on a semiconductor wafer. The thin film wiring unit has a first conductive layer and a second conductive layer having a lower coefficient of thermal expansion than the first conductive layer. At least, the conductive layer farthest from the semiconductor wafer is the first conductive layer, and the conductive layer closest to the semiconductor wafer is the second conductive layer.

Description

Wiring board and electrical connection device

[0001] The present invention relates to a wiring board and can be applied to an electrical connection device such as a probe card for electrically inspecting a semiconductor integrated circuit (hereinafter also referred to as a "semiconductor device") formed on a semiconductor wafer.

[0002] For inspecting the electrical characteristics of semiconductor devices on a semiconductor wafer, a probe card having a plurality of electrical contacts such as probes is used. The probe card is attached to the test head of a semiconductor inspection device (tester). During inspection, the electrode terminals of the semiconductor device are electrically contacted with the electrical contacts of the probe card, and the semiconductor inspection device inspects the electrical characteristics of the semiconductor device through the probe card.

[0003] As described in Patent Document 1, the probe card includes a probe substrate having a plurality of electrical contacts. Depending on the type of probe substrate, there is one having a space transformer substrate (ST substrate) that converts the wiring pitch to the pitch of the fine electrode terminals of the semiconductor device without degrading the electrical characteristics on the front and back surfaces of the substrate.

[0004] For example, in a high-temperature environment of about 150°C to 200°C, as the temperature changes, the length and volume of the semiconductor wafer expand, so the space transformer substrate also needs to follow the semiconductor wafer. For example, the coefficient of thermal expansion (CTE) of the semiconductor wafer is about 2 to 3 ppm / °C. Generally, the semiconductor wafer is near the heat source, and the space transformer substrate is slightly away from the heat source, so a thermal expansion coefficient of about 5 to 9 ppm / °C is required for the space transformer substrate.

[0005] Figure 2 shows an example of a conventional space transformer substrate. The conventional space transformer substrate 100 comprises a core substrate 120 and a thin-film laminated portion 110 that contacts a semiconductor wafer 83. The thin-film laminated portion 110 is made by alternately laminating insulating layers 21 and conductive layers 22, and further laminating an insulating layer 21 on the contact surface with the electrode pad 61 of the electrical contactor 6. Conventionally, the core substrate 120 is made of a material with a low coefficient of thermal expansion, such as ceramics, to control the coefficient of thermal expansion of the thin-film laminated portion 110 that contacts the semiconductor wafer 83.

[0006] Another conventional technique involves the use of metal substrates. In this type of substrate, it is common to control the thermal expansion coefficient of the space transformer substrate by placing a metal with a low thermal expansion coefficient in the center of the substrate's thickness. However, because the metal is placed in the center, the substrate becomes thicker, making it difficult to form fine circuits.

[0007] Japanese Patent Publication No. 2023-97314

[0008] As mentioned above, the core substrate with a low coefficient of thermal expansion controls the coefficient of thermal expansion of the thin film layer. However, as the number of layers increases, the coefficient of thermal expansion becomes dominated by the insulating and conductive layers. In other words, as the number of layers increases, the contact surface with the semiconductor wafer moves away from the core substrate, so the difference in thermal expansion near the contact surface with the semiconductor wafer becomes larger (see Figure 2).

[0009] Although synthetic resins with low thermal expansion coefficients have been developed, copper is generally used as the conductive material for the conductive layer. Therefore, the thermal expansion coefficient of the entire thin-film laminate is close to that of copper (approximately 17 ppm / °C), resulting in a difference from semiconductor wafers, making it difficult to use as a space transformer substrate for probe cards.

[0010] Therefore, there is a need for a wiring board and electrical connection device that can reduce the thermal expansion coefficient of the substrate due to temperature changes without significantly impairing its electrical properties, and that can follow changes in the semiconductor wafer.

[0011] To solve these problems, the first wiring substrate of the present invention comprises a thin-film wiring portion that is electrically connected to a plurality of connection terminals of a contactor that contacts electrode terminals on a semiconductor wafer, the thin-film wiring portion having a first conductive layer and a second conductive layer having a lower coefficient of thermal expansion than the first conductive layer, wherein at least the conductive layer furthest from the semiconductor wafer is the first conductive layer and the conductive layer closest to the semiconductor wafer is the second conductive layer.

[0012] The second electrical connection device of the present invention is an electrical connection device for electrically connecting an inspection device and a semiconductor wafer, and comprises a wiring board having a plurality of contacts that electrically contact electrode terminals on the semiconductor wafer and electrically connect substrate electrodes connected to the inspection device and electrode terminals, characterized in that the wiring board is the wiring board of the first present invention.

[0013] According to the present invention, the thermal expansion coefficient of the substrate due to temperature changes can be reduced without significantly impairing its electrical properties, and it can follow changes in the semiconductor wafer.

[0014] This is a configuration diagram showing the configuration of a space transformer substrate (wiring substrate) according to an embodiment. This is a configuration diagram showing the configuration of a conventional space transformer substrate (wiring substrate). This is a configuration diagram showing the configuration of an electrical connection device according to an embodiment. This is an explanatory diagram (part 1) illustrating the method of laminating the second conductive layer according to an embodiment. This is an explanatory diagram (part 2) illustrating the method of laminating the second conductive layer according to an embodiment. This is an explanatory diagram (part 3) illustrating the method of laminating the second conductive layer according to an embodiment. This is an explanatory diagram (part 4) illustrating the method of laminating the second conductive layer according to an embodiment. This is an explanatory diagram showing an example of a laminated structure of a thin film laminate formed by laminating the basic layers of the embodiment.

[0015] (A) Main Embodiments Below, embodiments of the wiring board and electrical connection device according to the present invention will be described in detail with reference to the drawings.

[0016] In this embodiment, an example is given in which the electrical connection device of the present invention is applied to a probe card used when inspecting the electrical characteristics of multiple semiconductor integrated circuits (semiconductor devices) formed on a semiconductor wafer.

[0017] Furthermore, an example is given in which the wiring board of the present invention is applied to the probe board mounted on the probe card.

[0018] (A-1) Diagram 3 of the electrical connection device configuration is a diagram showing the configuration of the electrical connection device according to the embodiment. Figure 1 is a diagram showing the configuration of the wiring board according to the embodiment.

[0019] Each figure illustrates the main components, but the actual system includes components not shown, not limited to those depicted. In each figure, identical or corresponding components are denoted by the same or corresponding reference numerals. Each figure is a schematic diagram, and it should be noted that the dimensions, thickness, etc., of each component differ from those of reality. Furthermore, the dimensions and proportions of corresponding components may differ between drawings. The embodiments shown below are illustrative examples of devices and methods for realizing the technical concept of the present invention, and do not limit the materials, shapes, structures, arrangements, etc., of the components of the present invention.

[0020] In Figure 3, the electrical connection device 9 according to the embodiment mainly comprises a main board 2 and a probe board 1.

[0021] The electrical connection device 9 is used for electrical testing of semiconductor devices by exchanging electrical signals between the electrode terminals 84 of a semiconductor device formed on a semiconductor wafer 83 and a semiconductor testing device (tester) TE.

[0022] The electrical connection device 9 has an electrical contact (hereinafter also referred to as "probe") 6 that electrically contacts each of the multiple electrode terminals 84 on the semiconductor wafer 83.

[0023] The electrical connection device 9 is mounted on the test head of the semiconductor inspection device TE, and during inspection, the corresponding electrical contacts 6 are electrically brought into contact with each electrode terminal 84 on the semiconductor wafer 83, thereby electrically connecting the semiconductor inspection device TE and the electrode terminals 84 of the semiconductor wafer 83.

[0024] In other words, during inspection, the electrical connection device 9 supplies electrical signals from the semiconductor inspection device TE to each electrode terminal 84 of the semiconductor device via the electrical contact 6, and also supplies electrical signals from the semiconductor device to the semiconductor inspection device TE via the electrical contact 6. As a result, the semiconductor inspection device TE can inspect the electrical characteristics of the semiconductor device via the electrical connection device 9.

[0025] The object under inspection is an object whose electrical characteristics are to be inspected by the semiconductor inspection apparatus TE, and is, for example, a semiconductor device formed on a semiconductor wafer 83 before dowsing.

[0026] The semiconductor wafer 83 is placed on one surface 82a of a chuck 82, which is connected to a drive unit 81 such as a multi-axis stage, and the position of the semiconductor wafer 83 on the chuck 82 can be adjusted by the drive of the drive unit 81.

[0027] During inspection, the position of the semiconductor wafer 83 on the chuck 82 is moved to ensure that each electrode terminal 84 of the semiconductor device makes electrical contact with the corresponding electrical contact 6.

[0028] [Main substrate 2] The main substrate 2 is a printed circuit board formed from a synthetic resin material such as glass epoxy or polyimide. The main substrate 2 is formed from, for example, a substantially circular plate-shaped member.

[0029] Printed wiring is formed on the first surface 2a of the main board 2, and electronic components such as resistors and capacitors are provided. Multiple tester connection points are provided on the outer edge of the first surface 2a of the main board 2, and the semiconductor testing equipment TE and the main board 2 are connected via each of these tester connection points.

[0030] Multiple contact terminals (interposers), such as pogo pins, are provided between the second surface 2b of the main board 2 and the probe board 1, electrically connecting the probe board 1 and the main board 2. Multiple conductors are provided on the main board 2 in the thickness direction (Z-axis direction), and these conductors electrically connect the printed circuit boards on the first surface 2a of the main board 2 to the connection terminals on the second surface 2b.

[0031] [Probe substrate 1, electrical contacts 6] The probe substrate 1 is a substrate having a plurality of electrical contacts 6. A plurality of electrical contacts 6 are provided on the second surface 1b of the probe substrate 1, and the first surface 1a of the probe substrate 1 is electrically connected to the second surface 2b of the main substrate 2.

[0032] The electrical contact 6 is exemplified as a vertical probe, but is not limited to this, and may be a cantilever probe. The other end of the electrical contact 6 (for example, the upper end) is connected to an electrode pad 61 disposed on the second surface 1b of the probe substrate 1, and during inspection, one end of the electrical contact 6 (for example, the lower end) electrically contacts the electrode terminal 84 of the semiconductor wafer 83.

[0033] (A-2) Configuration of the Space Transformer Substrate 10 Next, the configuration of the probe substrate 1 according to the embodiment will be described in detail with reference to Figure 1.

[0034] In Figure 1, the probe substrate 1 includes a space transformer substrate 10, a plurality of electrode pads 61, and a plurality of electrical contacts 6. In this embodiment, the substrate with the electrical contacts 6 is referred to as the probe substrate 1, and the substrate without the electrical contacts 6 is referred to as the space transformer substrate 10.

[0035] The space transformer substrate 10 has a core substrate 12 and a thin film laminated portion 11 as a thin film wiring portion. The space transformer substrate 10 is a substrate that converts the wiring spacing between the first surface 1a and the second surface 1b of the probe substrate 1 into the pitch of the fine electrode terminals of a semiconductor device without impairing the electrical properties.

[0036] The core substrate 12 is a substrate provided on the side of the space transformer substrate 10 that connects to the main substrate 2. The core substrate 12 is formed from a material with a low coefficient of thermal expansion, such as ceramics, or a material with a coefficient of thermal expansion that can follow the thermal expansion of the semiconductor wafer 83, which is the object under inspection. For example, the coefficient of thermal expansion of ceramics is about 5 ppm / °C. By providing a core substrate 12 made of such a material, the thermal expansion of the entire space transformer substrate 10 can be suppressed at high temperatures of about 150°C to 200°C. The core substrate 12 may also be a substrate with a multilayer wiring structure.

[0037] The core substrate 12 has vias 121 for electrical communication between the first surface 1a of the probe substrate 1 (i.e., the first surface 12a of the core substrate 12) and the thin film laminate 11. The vias 121 can be of various types, sizes, and structures and are not particularly limited.

[0038] The thin-film laminated section 11 is provided on the side of the space transformer substrate 10 that comes into contact with the semiconductor wafer 83. The thin-film laminated section 11 alternately laminates an insulating layer 21 and a first conductive layer 22 on the second surface 12b of the core substrate 12. In addition, the thin-film laminated section 11 has a second conductive layer 31 with a low coefficient of thermal expansion laminated on top of the insulating layer 21 on the side that comes into contact with the semiconductor wafer 83.

[0039] Furthermore, in order to ensure insulation between the electrical contact 6 and the electrode pad 61 that connects to it, an insulating layer 32 is laminated on top of the second conductive layer 31.

[0040] Although insulating layer 21 and insulating layer 32 are basically the same, insulating layer 32 ensures insulation from the electrode pad 61, so for the sake of explanation, they will be described using different symbols.

[0041] The number of layers in the thin film laminate 11 is not particularly limited; for example, it could be around 7 to 8 layers, or the number of layers could be increased to around 20 to 30 layers. For example, if the thickness of the core substrate 12 (thickness in the Z-axis direction) is about 5 mm, the thickness of the thin film laminate 11 with 20 to 30 layers can be about 0.5 to 1 mm. The thickness of the thin film laminate 11 will vary depending on the number of layers, so the thickness given here is just an example.

[0042] The thin film stack portion 11 has vias formed therein to enable electrical connection between the main substrate 2 and the electrode pad 61 (and the electrical contact 6). By electrically connecting the vias in the thin film stack portion 11 and the vias 121 in the core substrate 12, electrical conductivity can be achieved between the main substrate 2 and the electrode pad 61.

[0043] The insulating layer 21 is for ensuring insulation from the first conductive layer 22 sandwiched therebetween vertically. The insulating layer 32 is for ensuring insulation from the electrode pad 61 on the second surface 10b of the space transformer substrate 10. The insulating layer 21 and the insulating layer 32 are insulating thin film layers formed of an insulating material such as liquid crystal polymer (LCP), polyimide, polyethylene terephthalate, etc. For example, the thermal expansion coefficient of liquid crystal polymer (LCP) is about 10 ppm / °C. The materials of the insulating layer 21 and the insulating layer 32 are not particularly limited, but thermoplastic resins can be used.

[0044] The first conductive layer 22 is a conductive thin film layer formed of a conductive material such as copper (Cu), copper alloy, gold, etc. A conductive material is used to improve the electrical conductivity between the main substrate 2 and the electrode pad 61. Generally, a metal such as copper is used as the conductive material, but it has a higher thermal expansion coefficient than that of the semiconductor wafer 83, and the amount of thermal expansion with the semiconductor wafer 83 becomes large. Therefore, by providing the first conductive layer 22 on the side closer to the core substrate 12 with a low thermal expansion amount, the core substrate 12 can control the amount of thermal expansion of the entire space transformer substrate 10. For example, the thermal expansion coefficient of copper is about 17 ppm / °C.

[0045] The second conductive layer 31 is a conductive thin film layer formed of a conductive material having a lower coefficient of thermal expansion than the conductive material of the first conductive layer 22. For the second conductive layer 31, for example, an FeNi-based alloy in which nickel is blended with iron can be applied, and more preferably, 42 alloy (an FeNi alloy containing 42% by weight of nickel) can be applied. Thus, by providing the second conductive layer 31 on the second surface 10b of the space transformer substrate 10 on the contact surface side with the semiconductor wafer 83, the amount of thermal expansion of the entire space transformer substrate 10 at high temperatures can be suppressed. Further, since the FeNi alloy has conductivity, it does not impair electrical connection. For example, the coefficient of thermal expansion of 42 alloy is about 5 ppm / °C.

[0046] Incidentally, the FeNi alloy may contain not only iron and nickel but also other metals (for example, copper, manganese, etc.). Since the FeNi alloy (especially 42 alloy) has a low coefficient of thermal expansion at high temperatures of about 150°C to 200°C and has conductivity, the amount of thermal expansion at high temperatures can be suppressed, and electrical contact between the fine pitch electrode terminals 84 on the semiconductor wafer 83 and the electrical contactors 6 becomes possible. Therefore, any conductive material that has a low coefficient of thermal expansion at high temperatures and has conductivity and can obtain an effect similar to that of the FeNi alloy can be widely applied.

[0047] Here, the thin film laminated portion 11 includes at least "the insulating layer 21 and the first conductive layer 22" at the position closest to the second surface 12b of the core base material 12, and at the position farthest from the second surface 12b of the core base material 12 (the side close to the semiconductor wafer 83), "the insulating layer 21 and the second conductive layer 31". And the laminated structure between "the insulating layer 21 and the first conductive layer 22" on the core base material 12 side and "the insulating layer 21 and the second conductive layer 31" away from the core base material 12 can have various laminated structures as long as it can suppress the amount of thermal expansion at high temperatures.

[0048] That is, the conductive layer closest to the core base material 12 is the first conductive layer 22, and the conductive layer farthest from the core base material 12 is the second conductive layer 31.

[0049] In other words, the conductive layer farthest from the semiconductor wafer 83 is the first conductive layer 22, and the conductive layer closest to the semiconductor wafer 83 as the inspection object is the second conductive layer 31.

[0050] Furthermore, the structure between the first conductive layer 22, which is closest to the core substrate 12, and the second conductive layer 31, which is furthest from the core substrate 12, can be various laminated structures as long as the amount of thermal expansion can be suppressed.

[0051] For example, in the example shown in Figure 1, the structure between the "insulating layer 21 and the first conductive layer 22" on the core substrate 12 side and the "insulating layer 21 and the second conductive layer 31" away from the core substrate 12 is illustrated by the case where the insulating layer 21 and the first conductive layer 22 are alternately laminated.

[0052] However, the arrangement is not limited to alternating lamination of the insulating layer 21 and the first conductive layer 22. The insulating layer 21 and the second conductive layer 31 may be present at any position in the laminated structure. For example, multiple "insulating layers 21 and second conductive layers 31" may be present between the "insulating layer 21 and first conductive layer 22" on the core substrate 12 side and the "insulating layer 21 and second conductive layer 31" away from the core substrate 12. Alternatively, the entire structure may consist of "insulating layers 21 and second conductive layers 31".

[0053] For example, although an example of how to form the thin film laminated section 11 will be described later, the "insulating layer 21 and the first conductive layer 22" or the "insulating layer 21 and the second conductive layer 31" is used as a single basic layer (single layer), and these basic layers are stacked to form the thin film laminated section 11. This allows for the efficient formation of the thin film laminated section 11 after the formation of the basic layers (single layers). Furthermore, by forming the basic layers in advance, various combinations of laminated structures can be efficiently formed.

[0054] For the basic layer (single layer), the basic layer can be a group of layers that form the smallest repeating unit in the thin film laminated section 11, and the thin film laminated section 11 may be formed by laminating multiple such basic layers.

[0055] Here, the thickness (length in the Z-axis direction) of the layers constituting the thin film laminate 11 is increased as it moves further away from the core substrate 12. This makes the second conductive layer 31, which is further away from the core substrate 12, thicker, thereby increasing the volume of the second conductive layer 31 and allowing control of the thermal expansion coefficient of the space transformer substrate 10. For example, the second conductive layer 31, which has a low thermal expansion coefficient and is made of 42 alloy, is made thicker than the other first conductive layers 22.

[0056] Furthermore, for the same reasons as described above, the thickness of each layer in the thin-film laminate 11 is made the same, and the area of ​​the layers is increased as they move further away from the core substrate 12. For example, the area of ​​the second conductive layer 31, which has a low coefficient of thermal expansion and is made of 42 alloy, is increased compared to the area of ​​the other first conductive layers 22. By increasing the area of ​​the second conductive layer 31 that is farther from the core substrate 12, the volume of the second conductive layer 31 can be increased, thereby controlling the coefficient of thermal expansion of the space transformer substrate 10.

[0057] In other words, in the laminated structure of the thin film laminate 11 sandwiched between the first conductive layer 22 and the second conductive layer 31, the volume occupied by the second conductive layer 31, which has a low coefficient of thermal expansion, is increased to lower the coefficient of thermal expansion of the thin film laminate 11.

[0058] Furthermore, in the laminated structure of the thin film laminated portion 11 sandwiched between the first conductive layer 22 and the second conductive layer 31, the thermal expansion coefficient of the thin film laminated portion 11 is reduced by increasing the number of layers of the second conductive layer 31, which has a low thermal expansion coefficient.

[0059] Furthermore, in the laminated structure of the thin film laminate 11 sandwiched between the first conductive layer 22 and the second conductive layer 31, the thickness of the second conductive layer 31, which has a low coefficient of thermal expansion, is increased to lower the coefficient of thermal expansion of the thin film wiring portion. At this time, the thickness of the second conductive layer closest to the semiconductor wafer is made greater than the thickness of the other layers in the thin film wiring portion.

[0060] (A-3) Example of method for forming the space transformer substrate 10 Next, a method for forming the space transformer substrate 10, in particular a method for laminating the second conductive layer 31, will be described with reference to the drawings.

[0061] Figures 4 to 7 are explanatory diagrams illustrating the lamination method of the second conductive layer 31 in an embodiment. Figures 4 to 7 show a plan view and a side view of the substrate according to the lamination procedure.

[0062] For the sake of clarity, the planar shapes of the insulating layer 21, the first conductive layer 22, and the second conductive layer 31 are assumed to be square. An example is given where the first conductive layer 22 is made of copper, the insulating layer 21 is made of LCP, and the second conductive layer 31 is made of 42 alloy.

[0063] [S1] In Figure 4(A), in order to form a conductive passage in the insulating layer 21 of the LCP formed on one surface of the first conductive layer 22, a laser is irradiated onto the insulating layer 21 to create vias 51 of a predetermined diameter (S1).

[0064] For example, a flexible copper-clad laminate in which an LCP film and copper foil are laminated can be used, but it is not limited to a flexible copper-clad laminate; various materials can be applied as long as an insulating layer 21 is formed on one surface of a sheet-like first conductive layer 22. Also, in this example, a case where holes are made by laser processing is shown, but the processing method is not limited to this.

[0065] [S2] In Figure 4(B), tin (Sn) 52 is filled into the vias 51 provided in the insulating layer 21 by tin plating (electroplating) (S2).

[0066] [S3] In Figure 5(A), a sheet-like 42 alloy with a thickness of approximately 0.01 to 0.02 mm is welded to one surface of the insulating layer 21 by pressurized heating (pressure 4 MPa, 300°C) (S3).

[0067] [S4] In Figure 5(B), a thin film DFR (dry film resist) is laminated to each of the two sides of the substrate in Figure 5(A), and exposed by irradiation with ultraviolet light (S4).

[0068] At this time, in order to use the via 51 filled with tin 52 as a guideway, a circular portion 53 with a diameter slightly larger than the diameter of the via 51 is exposed by irradiating it with ultraviolet light.

[0069] [S5] In Figure 6(A), the remaining thin film DFR that has not hardened is removed from each of the two sides of the substrate, and the exposed areas are developed (S5).

[0070] For example, exposure causes the thin film DFR to react with ultraviolet light and harden (circular portion 53), while the portion that remains unhardened due to the absence of ultraviolet light irradiation is dissolved and removed.

[0071] [S6] In Figure 6(B), the exposed portions of the first conductive layer 22 and the second conductive layer 31 are dissolved by etching (S6).

[0072] As a result, copper as the first conductive layer 22 and the 42 alloy as the second conductive layer 31 remain at the location of the via 51 filled with tin 52, and a conductive passage 54 is formed.

[0073] [S7] In Figure 7(A), an insulating adhesive film 21 is laminated to one surface of the second conductive layer 31 (S7).

[0074] [S8] Then, as shown in Figure 7(B), holes are made in the adhesive film laminated to the second conductive layer 31 by laser processing at positions corresponding to the vias 51, and conductive paste 55 is filled into the holes (S8).

[0075] Thus, the thin film laminate 11 is equipped with vias 51, and the 42 alloy as the second conductive layer 31 can form conductive passages 54 at desired locations. In other words, in a plan view of the thin film laminate 11, the second conductive layer 31 does not cover the entire surface, but is arranged in the region where the conductive passages 54 are formed. This ensures conductivity through the vias 51 of the thin film laminate 11.

[0076] Figure 8 is an explanatory diagram showing an example of a laminated structure of a thin film laminated portion 11 formed by stacking the basic layers of the embodiment.

[0077] As illustrated in Figure 8, the layer constructed using the procedure shown in Figures 4 to 7 is considered the base layer. For the sake of explanation, the base layer is assumed to include a first conductive layer 22 and a second conductive layer 31.

[0078] As shown in Figure 8, a thin film laminated section 11 can be formed by stacking multiple (five in the example in Figure 8) basic layers. When stacking the basic layers alternately, an insulating layer 21 (or insulating layer 32) may be stacked on the top or bottom layer.

[0079] (A-4) Effects of the Embodiment As described above, according to this embodiment, the thin film laminate includes a second conductive layer made of a FeNi alloy with a low coefficient of thermal expansion, in addition to a first conductive layer made of a metal such as copper, so that the coefficient of thermal expansion of the space transformer substrate can be controlled without significantly impairing the electrical properties. For example, the coefficient of thermal expansion of the space transformer substrate can be controlled by changing the thickness and number of the second conductive layer with a low coefficient of thermal expansion (e.g., number of layers, area, volume).

[0080] As a result, even if the pitch spacing of the electrode terminals on the semiconductor wafer changes due to temperature changes, for example at high temperatures of around 150°C to 200°C, the space transformer substrate can follow the change, maintaining the alignment between the electrode terminals and the electrical contacts, and enabling proper inspection.

[0081] (B) Other Embodiments Although various modified embodiments have been mentioned in the embodiments described above, the present invention can also be applied to the following modified embodiments.

[0082] (B-1) In the above-described embodiment, an example was given in which a thin film laminate having a second conductive portion is provided on a core substrate, but a core substrate-less substrate may also be used. By providing a thin film laminate having a second conductive portion on a core substrate-less substrate, the same effects as described above can be obtained.

[0083] 1...Probe substrate, 1a...First surface of probe substrate, 1b...Second surface of probe substrate, 2...Main substrate, 2a...First surface of wiring substrate, 2b...Second surface of wiring substrate, 6...Electrical contact, 9...Electrical connection device, 10 and 100...Space transformer substrate, 10a...First surface of space transformer substrate, 10b...Second surface of space transformer substrate, 11 and 110...thin film laminated section, 12 and 120...core substrate, 12a...first surface of core substrate, 12b...second surface of core substrate, 121...via, 18...connection terminal, 21...insulating layer, 22...first conductive layer, 31...second conductive layer, 32...insulating layer, 51...via, 52...tin, 53...circular section, 54...conducting passage, 55...conductive paste, 61...electrode pad, 81...drive unit, 82...chuck, 82a...surface of chuck, 83...semiconductor wafer, 84...electrode terminal, TE...semiconductor inspection device.

Claims

1. A wiring substrate comprising a thin-film wiring section that electrically connects to a plurality of connection terminals of a contactor that contacts electrode terminals on a semiconductor wafer, wherein the thin-film wiring section comprises a first conductive layer and a second conductive layer having a lower coefficient of thermal expansion than the first conductive layer, and at least the conductive layer furthest from the semiconductor wafer is the first conductive layer, and the conductive layer closest to the semiconductor wafer is the second conductive layer.

2. The wiring board according to claim 1, comprising a substrate made of a material with a low coefficient of thermal expansion that suppresses the amount of thermal expansion of the wiring board, wherein the thin film wiring portion is formed on one surface of the substrate.

3. The wiring substrate according to claim 1, characterized in that, in the laminated structure of the thin film wiring portion sandwiched between the first conductive layer and the second conductive layer, the volume occupied by the second conductive layer, which has a low coefficient of thermal expansion, is increased, thereby lowering the coefficient of thermal expansion of the thin film wiring portion.

4. The wiring substrate according to claim 1, characterized in that, in the laminated structure of the thin film wiring portion sandwiched between the first conductive layer and the second conductive layer, the number of laminated second conductive layers, which have a low coefficient of thermal expansion, is increased to lower the coefficient of thermal expansion of the thin film wiring portion.

5. The wiring substrate according to claim 1, characterized in that, in the laminated structure of the thin film wiring portion sandwiched between the first conductive layer and the second conductive layer, the thickness of the second conductive layer, which has a low coefficient of thermal expansion, is increased to lower the coefficient of thermal expansion of the thin film wiring portion.

6. The wiring substrate according to claim 1, characterized in that the thickness of the second conductive layer closest to the semiconductor wafer is greater than the thickness of the other layers in the thin-film wiring portion.

7. The wiring substrate according to claim 1, characterized in that the second conductive layer contains an FeNi-based alloy.

8. An electrical connection device for electrically connecting an inspection device and a semiconductor wafer, comprising a wiring board having a plurality of contacts that electrically contact electrode terminals on the semiconductor wafer and electrically connect substrate electrodes that connect to the inspection device with the electrode terminals, wherein the wiring board is the wiring board described in any one of claims 1 to 7.

Images