Gate driving circuit for temperature compensation considering transistor-based power semiconductor

Abstract

The present disclosure relates to a gate driving circuit for temperature compensation considering a transistor-based power semiconductor, and more particularly, to a gate driving circuit capable of quickly adjusting heat generated in a power semiconductor in real time and improving a delay time due to a high-frequency driving command signal using a transistor.

Description

Temperature compensation gate driving circuit considering transistor-based power semiconductors

[0001] The present disclosure relates to a temperature-compensated gate driving circuit for transistor-based power semiconductors, and more specifically, to a gate driving circuit capable of rapidly controlling heat generated in a power semiconductor in real time while simultaneously improving delay time caused by high-frequency driving command signals using a transistor.

[0002] Technology and development for the stable operation of power semiconductors are active.

[0003] Figure 1 is a circuit diagram of a conventional power semiconductor, and Figure 2 is a circuit diagram of a conventional gate driving circuit.

[0004] Referring to Fig. 1, a plurality of power semiconductors used in an inverter are connected in parallel with each other, and the plurality of power semiconductors connected in parallel are connected to other plurality of power semiconductors in a totem-pole structure.

[0005] Referring to FIG. 2, a conventional gate driving circuit is provided for each of the power semiconductors of FIG. 1 and drives the power semiconductor by applying a gate voltage to the gate of the power semiconductor. In the conventional method of generating the gate voltage, when a PWM signal is applied from an IC circuit to a totem-pole circuit, the totem-pole circuit applies a gate driving voltage to the gate of the power semiconductor according to the PWM signal.

[0006] However, as shown in Fig. 1, when power semiconductors are connected in parallel in an inverter, various problems may occur.

[0007] First, due to differences in characteristics between power semiconductor devices connected in parallel, the current flowing through each power semiconductor device may not be uniform. This current imbalance causes excessive current to flow through a specific power semiconductor device, leading to problems such as overheating, electrical damage, or insulation breakdown of the power semiconductor device.

[0008] In addition, temperature imbalances may occur due to current imbalances or differences in the heat generation characteristics of each power semiconductor device. These temperature differences can cause thermal overload, leading to performance degradation or a shortened lifespan of the device.

[0009] Furthermore, depending on the characteristics of power semiconductor devices, if temperature imbalance is accelerated, power semiconductor devices with higher temperatures may absorb more current, leading to a thermal vicious cycle where heat generation becomes even more severe.

[0010] To solve the above problem, there is a technique for generating a gate voltage using an operational amplifier. Specifically, a driving command signal is applied to the enable terminal of the operational amplifier to generate a gate voltage to compensate for the temperature of the power semiconductor.

[0011] However, the operational amplifier has an inactive state where no output signal is generated and an active state where an output signal is generated, and the enable time, which is the time it takes to switch from the inactive state to the active state when applied to the enable terminal, generally takes tens of microseconds or more, and the shutdown time, which is the time it takes to switch from the active state to the inactive state, also takes time in the microsecond range.

[0012] In other words, there is a problem in that responsiveness is significantly reduced due to the delay time required for the operational amplifier's state transition, even when a driving command signal is applied to the operational amplifier. In particular, when the driving command signal is a high-speed switching PWM waveform, this delay time has a significant impact on the overall operating cycle, causing the gate driving circuit to operate inefficiently or the power semiconductor to be damaged, resulting in a significant decrease in the stability, reliability, and efficiency of the gate driving circuit.

[0013] Therefore, as described above, when the driving command signal is a high-speed switching PWM waveform, technology and development are required to stably drive the power semiconductor device in response to this, while simultaneously efficiently managing the heat generated in the power semiconductor.

[0014] [Prior Art Literature]

[0015] [Patent Literature]

[0016] (Patent Document 1) Published Patent Application No. 10-2015-0050777 (May 11, 2015)

[0017] The present disclosure is devised to solve the problems described above, and the purpose of the gate driving circuit according to the present disclosure is to provide a gate driving circuit that can rapidly drive a power semiconductor without delay when the driving command signal is a high-frequency PWM waveform, and at the same time, perform thermal management of the power semiconductor in real time by adjusting the magnitude of the gate voltage according to the temperature of the power semiconductor.

[0018] A gate driving circuit according to the present disclosure for solving the problems described above comprises a gate driving circuit that provides a variable gate voltage based on a thermistor for measuring the temperature of a power semiconductor, a temperature compensation circuit that provides a temperature compensation signal based on the resistance value of the thermistor, and an output circuit that varies the gate voltage output to the power semiconductor according to the temperature compensation signal, wherein the temperature compensation circuit comprises at least one transistor that provides a temperature compensation signal according to a driving command signal of the power semiconductor.

[0019] In addition, the temperature compensation circuit provides a temperature compensation signal of a lower potential based on the resistance value of the thermistor when the driving command signal is ON, and a temperature compensation signal of a predetermined zero potential when the temperature of the power semiconductor is higher.

[0020] Additionally, the temperature compensation circuit provides a temperature compensation signal of a predetermined normal gate potential when the drive command signal is ON and the thermistor has a resistance value corresponding to the temperature of the power semiconductor being below a predetermined standard, provides a temperature compensation signal of a potential lower than the normal gate potential when the thermistor has a resistance value corresponding to the temperature of the power semiconductor being above a predetermined standard, and provides a temperature compensation signal of the normal gate potential when the connection with the thermistor is disconnected.

[0021] Additionally, the temperature compensation circuit includes an input circuit that receives and outputs a thermistor voltage, which is a voltage applied to the thermistor, a control circuit that is provided between the input circuit and the output circuit and controls the magnitude of the thermistor voltage to output, and a relay circuit that is provided between the control circuit and the output circuit and includes at least one transistor, and when a driving command signal is applied ON to at least one transistor, the relay circuit outputs a temperature compensation signal proportional to the output of the control circuit.

[0022] Additionally, the input circuit includes a first-1 resistor, one end of which is connected to a predetermined positive power supply and the other end of which is connected to the input terminal of the control circuit, and a first-2 resistor, one end of which is connected to a predetermined ground, wherein the other end of the first-1 resistor is connected to one end of the thermistor and the other end of the first-2 resistor is connected to the other end of the thermistor.

[0023] In addition, the resistance values ​​of 1-1 and 1-2 have values ​​that satisfy the following mathematical formula 1.

[0024] [Mathematical Formula 1]

[0025]

[0026] (Here, Av is the gain of the control circuit, R11 is the first-1 resistance value, R12 is the first-2 resistance value, Vp is the positive power supply, Rntcmin is the thermistor resistance value at the highest operating temperature of the power semiconductor, and Vdmin is the lowest voltage capable of driving the output circuit)

[0027] In addition, the first-1 resistor is set to a value calculated by the following mathematical formula 2.

[0028] [Mathematical Formula 2]

[0029]

[0030] (Here, R11 is the first-1 resistance value, Vp is the positive power supply, Vinmin is the lowest input voltage of the control circuit where the output circuit can operate, Vinmax is the maximum input voltage of the control circuit where the output circuit can operate, Rntcmin is the lowest resistance value of the thermistor in the temperature range where the power semiconductor can operate, and Rntcmax is the maximum resistance value of the thermistor in the temperature range where the power semiconductor can operate)

[0031] In addition, the first and second resistors are set to the values ​​calculated by the following mathematical formula 3.

[0032] [Mathematical Formula 3]

[0033]

[0034] (Here, R11 is the first-1 resistance value, Vinmin is the lowest input voltage of the control circuit at which the output circuit can operate, Vp is the positive power supply, R12 is the first-2 resistance value, and Rntcmin is the lowest thermistor resistance value within the temperature range at which the power semiconductor can operate)

[0035] Additionally, the control circuit includes an operational amplifier with a non-inverting terminal connected to the output terminal of the input circuit, a second-1 resistor connected between the inverting terminal of the operational amplifier and the output terminal of the operational amplifier, and a second-2 resistor connected between the output terminal of the operational amplifier and the relay circuit.

[0036] Additionally, the control circuit further includes a second and third resistor connected between the inverting terminal of the operational amplifier and a predetermined ground terminal.

[0037] Additionally, the control circuit further includes a second-4 resistor connected between the non-inverting terminal of the operational amplifier and the common node of the first-1 resistor and the thermistor, and a second-5 resistor connected between the non-inverting terminal of the operational amplifier and a predetermined ground terminal.

[0038] Additionally, the relay circuit includes a first transistor provided between the output terminal of the temperature compensation circuit and the input terminal of the output circuit, and a third resistor provided between one end of the first transistor and a predetermined ground, and the first transistor transmits the output of the temperature compensation circuit to the output circuit according to a driving command signal.

[0039] Additionally, the output circuit includes transistors 2-1 and 2-2 connected in series between a predetermined positive power supply and a predetermined negative power supply, a temperature compensation signal is applied to the control terminal of transistor 2-1, and a gate voltage is provided to a power semiconductor based on a driving command signal applied to the control terminal of transistor 2-2.

[0040] According to the gate driving circuit of the present disclosure as described above, heat generated in the power semiconductor is controlled in real time according to the temperature of the power semiconductor, thereby maintaining a temperature balance between each power semiconductor. Accordingly, thermal imbalance between power semiconductors connected in parallel can be eliminated.

[0041] In addition, thermal stress can be relieved due to the uniform heat distribution between the devices, thereby extending the lifespan of power semiconductor devices connected in parallel.

[0042] In addition, when the driving command signal is a high-frequency PWM waveform, the output of the temperature compensation signal is controlled by receiving the driving command signal through a transistor with a delay time in the nanosecond range to minimize the delay time (enable time and shutdown time), thereby improving the responsiveness and stability of the power semiconductor control.

[0043] In addition, it is designed to provide a normal gate voltage even when a thermistor malfunctions, such as when the connection is severed, thereby improving the reliability and stability of the gate driving circuit.

[0044] Figure 1 is a circuit diagram of a conventional power semiconductor.

[0045] Figure 2 is a circuit diagram of a conventional power semiconductor driving circuit.

[0046] FIG. 3 is a graph of the resistance characteristics of a thermistor according to one embodiment of the present disclosure as a function of temperature.

[0047] FIG. 4 is a schematic diagram of a gate driving circuit according to one embodiment of the present disclosure.

[0048] FIG. 5 is a circuit diagram of a gate driving circuit according to a first embodiment of the present disclosure.

[0049] Figure 6 is a timing diagram according to the drive command signal.

[0050] FIG. 7 is a circuit diagram of a gate driving circuit according to the first embodiment of the present disclosure when the thermistor is disconnected.

[0051] FIG. 8 is a graph of Vin and Vout according to the resistance value of the thermistor according to the first embodiment of the present disclosure when V_inmin=11V and V_inmax=14V.

[0052] FIG. 9 is a graph of Vin and Vout according to the resistance value of the thermistor according to the first embodiment of the present disclosure when V_inmin=11V and V_inmax=15V.

[0053] FIG. 10 is a graph of Vin and Vout according to the resistance value of the thermistor according to the first embodiment of the present disclosure when V_inmin=9.5V and V_inmax=14V.

[0054] FIG. 11 is a graph of Vin and Vout according to the resistance value of the thermistor according to the first embodiment of the present disclosure when V_inmin=10V and V_inmax=14V.

[0055] FIG. 12 is a circuit diagram of a gate driving circuit according to a second embodiment of the present disclosure.

[0056] FIG. 13 is a graph of Vin and Vout according to the resistance value of the thermistor according to the second embodiment of the present disclosure when V_inmin=5V and V_inmax=7.5V.

[0057] FIG. 14 is a circuit diagram of a gate driving circuit according to a third embodiment of the present disclosure.

[0058] FIG. 15 is a graph of the driving command signal when the driving command signal is applied using the enable terminal of the operational amplifier.

[0059] FIG. 16 is a graph of the switching signal of a power semiconductor when a driving command signal is applied using the enable terminal of an operational amplifier.

[0060] FIG. 17 is a graph of the switching signal of the output circuit when a driving command signal is applied using the enable terminal of the operational amplifier.

[0061] FIG. 18 is a graph of the driving command signal of the present disclosure.

[0062] The purpose, features, and advantages of the foregoing disclosure will become more apparent through the following embodiments in conjunction with the accompanying drawings. The following specific structural or functional descriptions are merely illustrative for the purpose of explaining embodiments according to the concept of the present disclosure, and embodiments according to the concept of the present disclosure may be implemented in various forms and should not be interpreted as being limited to the embodiments described in this specification or application. Since embodiments according to the concept of the present disclosure may be subject to various modifications and may take various forms, specific embodiments are illustrated in the drawings and described in detail in this specification or application. However, this is not intended to limit embodiments according to the concept of the present disclosure to specific disclosed forms, and should be understood to include all modifications, equivalents, and substitutions that fall within the spirit and scope of the present disclosure. Terms such as first and / or second may be used to describe various components, but components are not limited to these terms. Terms may be used solely for the purpose of distinguishing one component from other components, for example, without departing from the scope of rights according to the concept of the present disclosure, such that the first component may be named the second component, and similarly, the second component may be named the first component. Where it is stated that a component is connected to or coupled with another component, it should be understood that it may be directly connected to or coupled with that other component, or that there may be other components in between. On the other hand, where it is stated that a component is directly connected to or directly coupled with another component, it should be understood that there are no other components in between. Other expressions used to describe the relationship between components, such as between, directly between, adjacent to, and directly adjacent to, should be interpreted in the same way.The terms used in this specification are used merely to describe specific embodiments and are not intended to limit the disclosure. Singular expressions include plural expressions unless the context clearly indicates otherwise. Terms such as "include" or "have" in this specification are intended to specify the existence of the described features, numbers, steps, actions, components, parts, or combinations thereof, and should not be understood as precluding the existence or addition of one or more other features, numbers, steps, actions, components, parts, or combinations thereof. Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as generally understood by those skilled in the art to which this disclosure pertains. Terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology and should not be interpreted in an ideal or overly formal sense unless explicitly defined in this specification. Hereinafter, the disclosure will be described in detail by describing preferred embodiments of the disclosure with reference to the accompanying drawings. Identical reference numerals in each drawing indicate identical components.

[0063] A preferred embodiment of the gate driving circuit (1) according to the present disclosure will be described in detail below with reference to the attached drawings.

[0064] FIG. 3 is a graph of the resistance characteristics of a thermistor (Rntc) according to one embodiment of the present disclosure.

[0065] A gate driving circuit (1) according to one embodiment of the present disclosure provides a variable gate voltage to a power semiconductor (2) based on a temperature measuring thermistor (Rntc) of the power semiconductor (2). Here, the power semiconductor (2) may be any one of a plurality of power semiconductors (2) connected in parallel with each other as shown in FIG. 1. In addition, the temperature measuring thermistor (Rntc) is a device whose resistance value varies according to temperature. The thermistor (Rntc) is provided in each of the plurality of power semiconductors (2) so that its resistance can vary according to the temperature of the power semiconductor (2). For example, the power semiconductor (2) may be any one of a BJT (Bipolar Junction Transistor), FET (Field Effect Transistor), JFET (Junction Field Effect Transistor), MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor), Enhancement MOSFET (Enhancement Mode Metal-Oxide-Semiconductor Field Effect Transistor), Depletion MOSFET (Depletion Mode Metal-Oxide-Semiconductor Field Effect Transistor) and an IGBT (Insulated Gate Bipolar Transistor).

[0066] The thermistor (Rntc) may be either an NTC type thermistor having a resistance value that decreases as the temperature rises or a PTC type thermistor having a resistance value that increases as the temperature rises, and the present specification describes based on an NTC type thermistor having resistance characteristics as shown in FIG. 3. The thermistor (Rntc) of the present disclosure uses the FP75R12KT4 model thermistor (Rntc) and may have resistance characteristics as shown in FIG. 3. However, it is not limited to the model, and any thermistor may be adopted in the present disclosure without limitation.

[0067] That is, the gate driving circuit (1) of the present disclosure can control the heat generated in the power semiconductor (2) by providing different magnitudes of gate voltages according to the resistance value of the thermistor (Rntc) when the resistance value of the thermistor (Rntc) changes according to the temperature of the power semiconductor (2).

[0068] FIG. 4 is a schematic diagram of a gate driving circuit (1) according to one embodiment of the present disclosure, FIG. 5 is a circuit diagram of a gate driving circuit (1) according to a first embodiment of the present disclosure, and FIG. 6 is a timing diagram according to a driving command signal.

[0069] Referring to FIGS. 4 to 6, the temperature compensation circuit (110) and the output circuit (120) will be described.

[0070] A gate driving circuit (1) according to one embodiment of the present disclosure includes a temperature compensation circuit (110) and an output circuit (120).

[0071] The temperature compensation circuit (110) provides a temperature compensation signal based on the resistance value of the thermistor (Rntc). Specifically, the temperature compensation circuit (110) outputs a temperature compensation signal according to a driving command signal, and when the driving command signal is ON, it provides a temperature compensation signal of a lower potential as the temperature of the power semiconductor (2) increases based on the resistance value of the thermistor (Rntc), and when it is OFF, it provides a temperature compensation signal of a predetermined zero potential.

[0072] Here, the temperature compensation circuit (110) can control the output of the temperature compensation circuit (110) based on a driving command signal. Specifically, the driving command signal can be generated and output from a predetermined controller (3) provided separately from the gate driving circuit (1) of the present disclosure.

[0073] The controller (3) can provide at least one of a predetermined positive power supply (Vp), a predetermined negative power supply (Vn), and a driving command signal to the temperature compensation circuit (110) and the output circuit (120). Specifically, the controller (3) can generate a predetermined positive power supply (Vp) or a predetermined negative power supply (Vn) and provide it to the temperature compensation circuit (110) and the output circuit (120).

[0074] Additionally, the controller (3) can receive an external command and generate a driving command signal. In one embodiment, as shown in FIG. 6, the driving command signal may have a PWM waveform, and the PWM waveform may be applied to a temperature compensation circuit (110) and an output circuit (120).

[0075] The temperature compensation circuit (110) includes at least one transistor that provides a temperature compensation signal according to a driving command signal of a power semiconductor (2). That is, conventionally, a driving command signal is applied to an operational amplifier with a large delay time, and accordingly, the temperature compensation circuit (110) provides a temperature compensation signal to an output circuit (120), but the gate driving circuit (1) of the present disclosure applies a driving command signal to a control terminal of at least one transistor to provide a temperature compensation signal to an output circuit (120).

[0076] To this end, the temperature compensation circuit (110) includes a relay circuit (113) comprising a first transistor (Q1) which is at least one transistor, and the relay circuit (113) will be described later.

[0077] That is, when the driving command signal is a high-frequency PWM waveform, the driving command signal is received using a transistor with a lower delay time than a conventional operational amplifier to minimize delay time and control the output of the temperature compensation signal, thereby improving the responsiveness and stability of power semiconductor control.

[0078] More specifically, the operation of the temperature compensation circuit (110) is described. Referring to FIG. 6, Rntc is the resistance value of the thermistor (Rntc), Vin is the voltage of the thermistor (Rntc) measured based on the resistance value of the thermistor (Rntc), and Vout is the output voltage of the control circuit (112).

[0079] When the thermistor (Rntc) type is NTC, Rntc and Vin vary according to the temperature of the power semiconductor (2), and when the driving command signal is ON, Vout is output based on Vin. That is, the higher the temperature of the power semiconductor (2), the lower the potential temperature compensation signal is provided, and the lower the temperature of the power semiconductor (2), the higher the potential temperature compensation signal is provided. In addition, when the driving command signal is OFF, the voltage of Vout has a zero potential and provides a temperature compensation signal having a predetermined zero potential.

[0080] When the driving command signal is On, the operation of the temperature compensation circuit (110) is explained in more detail.

[0081] The temperature compensation circuit (110) provides a temperature compensation signal of a predetermined normal gate potential when the driving command signal is ON and the thermistor (Rntc) has a resistance value corresponding to the temperature of the power semiconductor (2) being below a predetermined standard. Additionally, the temperature compensation circuit (110) provides a temperature compensation signal of a potential lower than the normal gate potential when the driving command signal is ON and the thermistor (Rntc) has a resistance value corresponding to the temperature of the power semiconductor (2) being above a predetermined standard.

[0082] Specifically, referring to FIG. 6, when the temperature of the power semiconductor (2) is Tr, which is a predetermined standard, the resistance value of the thermistor (Rntc) can be denoted as Rr. The temperature compensation circuit (110) can provide a temperature compensation signal of a predetermined normal gate potential when the resistance value of the thermistor (Rntc) is less than or equal to Rr. Additionally, the temperature compensation circuit (110) can provide a temperature compensation signal of a potential lower than the predetermined normal gate potential when the resistance value of the thermistor (Rntc) exceeds Rr.

[0083] Through this, the temperature compensation circuit (110) can significantly improve the performance and reliability of the gate driving circuit (1) of the present disclosure by effectively controlling the gate potential according to the temperature of the power semiconductor (2).

[0084] FIG. 7 is a circuit diagram of a gate driving circuit (1) according to the first embodiment of the present disclosure when the thermistor (Rntc) is disconnected.

[0085] The temperature compensation circuit (110) provides a temperature compensation signal of normal gate potential when the drive command signal is ON and the connection with the thermistor (Rntc) is disconnected. Specifically, referring to FIG. 7, when the connection between the thermistor (Rntc) and the gate drive circuit (1) of the present disclosure is disconnected, a predetermined positive power supply (Vp) is applied as the input voltage Vin of the control circuit (112). Therefore, since Vin, which is the input voltage of the control circuit (112), is not in a floating state, a temperature compensation signal of normal gate potential, rather than a temperature compensation signal based on the temperature of the thermistor (Rntc), can be provided to the output circuit (120) through the relay circuit (113).

[0086] The output circuit (120) varies the gate voltage output to the power semiconductor (2) according to the temperature compensation signal. Specifically, the output circuit (120) receives the temperature compensation signal output from the temperature compensation circuit (110) and varies the gate voltage output to the power semiconductor (2) according to the temperature compensation signal.

[0087] Next, based on the first embodiment, the configurations of the input circuit (111), control circuit (112), relay circuit (113), and output circuit (120) included in the temperature compensation circuit (110) of the gate driving circuit (1) of the present disclosure will be described.

[0088] [Input circuit (111)]

[0089] The input circuit (111) measures and outputs the thermistor (Rntc) voltage, which is the voltage applied to the thermistor (Rntc). In one embodiment, the input circuit (111) may include a first-1 resistor (R11) and a first-2 resistor (R12). Specifically, referring to FIG. 5, the first-1 resistor (R11) of the input circuit (111) has one end connected to a predetermined positive power supply (Vp) and the other end connected to the input terminal of the control circuit (112). At the same time, the other end of the first-1 resistor (R11) is connected to one end of the thermistor (Rntc). The first-2 resistor (R12) has one end connected to a predetermined ground and the other end connected to the other end of the thermistor (Rntc). In this case, the thermistor (Rntc) voltage refers to the common node voltage of the first-1 resistor (R11) and the thermistor (Rntc).

[0090] That is, the first-1 resistor (R11) is a pull-up resistor, and the first-2 resistor (R12) is a resistor required to apply the minimum voltage capable of driving the output circuit (120) to the control circuit (112) to compensate for the case where the thermistor (Rntc) voltage becomes very low and does not reach the voltage capable of driving the output circuit (120). Therefore, in order to output a stable temperature compensation signal to the output circuit (120), it is necessary to set the resistance values ​​of the first-1 and first-2 resistors (R11, R12).

[0091] To solve the above problems, in one embodiment, the values ​​of the 1-1 and 1-2 resistors (R11, R12) may have values ​​satisfying the following mathematical formula 1.

[0092] [Mathematical Formula 1]

[0093]

[0094] Here, Av is the gain of the control circuit (112), R11 is the value of the first-1 resistor (R11), R12 is the value of the first-2 resistor (R12), Vp is the positive power supply (Vp), Rntcmin is the resistance value of the thermistor (Rntc) at the highest temperature at which the power semiconductor (2) can operate, and Vdmin is the lowest voltage capable of driving the output circuit (120).

[0095] Specifically, referring to FIG. 5, when the driving command signal is ON, Vout, which is the output voltage of the control circuit (112), must be greater than Vdmin, which is the lowest voltage capable of driving the output circuit (120). Therefore, the common node voltage of the first-1 resistor (R11) and thermistor (Rntc) The gain of the control circuit (112) amplified by It must be greater than this Vdmin.

[0096] Next, the method for setting the values ​​of the 1-1 and 1-2 resistors (R11, R12) will be explained.

[0097] In one embodiment, the first-1 resistor (R11) can be set to a value calculated by the following mathematical formula 2.

[0098] [Mathematical Formula 2]

[0099]

[0100] Here, R11 is the value of the first-1 resistor (R11), Vp is the positive power supply (Vp), Vinmin is the lowest input voltage of the control circuit (112) in which the output circuit (120) can operate, Vinmax is the maximum input voltage of the control circuit (112) in which the output circuit (120) can operate, Rntcmin is the lowest resistance value of the thermistor (Rntc) in the temperature range in which the power semiconductor (2) can operate, and Rntcmax is the maximum resistance value of the thermistor (Rntc) in the temperature range in which the power semiconductor (2) can operate.

[0101] In addition, in one embodiment, the first-2 resistor (R12) is set to a value calculated by the following mathematical formula 3.

[0102] [Mathematical Formula 3]

[0103]

[0104] Here, R11 is the first-1 resistor (R11) value, Vinmin is the lowest input voltage of the control circuit (112) in which the output circuit (120) can operate, Vp is the positive power supply (Vp), R12 is the first-2 resistor (R12) value, and Rntcmin is the lowest resistance value of the thermistor (Rntc) in the temperature range in which the power semiconductor (2) can operate.

[0105] Specifically, the method for deriving mathematical formulas 2 and 3 will be explained.

[0106] In order to derive mathematical formulas 2 and 3, the actual operating temperature range of the power semiconductor (2) can be specified. For example, the actual operating temperature range can be specified as 20°C or higher and 80°C or lower.

[0107] In addition, the resistance value of the thermistor (Rntc) in the actual operating temperature range is calculated based on the resistance characteristics of the thermistor (Rntc). Within the actual operating temperature range, the resistance value of the thermistor (Rntc) Rntcmax can be calculated when the temperature is the lowest and the resistance value of the thermistor (Rntc) Rntcmin can be calculated when the temperature is the highest. For example, the resistance value of the thermistor (Rntc) can be set to Rntcmax when the temperature is 20℃, and the resistance value of the thermistor (Rntc) Rntcmin when the temperature is 80℃. Such the resistance value of the thermistor (Rntc) according to temperature can be calculated through the graph shown in FIG. 3.

[0108] In addition, Voutmin, which is the lowest output voltage of the control circuit (112) that the output circuit (120) can operate, and Voutmax, which is the highest output voltage of the control circuit (112) that the output circuit (120) can operate, are calculated, respectively. These are values ​​that may vary depending on the circuit structure of the output circuit (120).

[0109] In this case, since the lowest input voltages Vinmin and Voutmin of the control circuit (112) capable of operating the output circuit (120) are related according to the following mathematical formula, Vinmin can be calculated.

[0110] Vinmin=(Voutmin) / Av

[0111] In addition, since the maximum input voltage Vinmax and Voutmax of the control circuit (112) capable of operating the output circuit (120) are related according to the following mathematical formula, Vinmax can be calculated.

[0112] Vinmax=(Voutmax) / Av

[0113] Here, referring to FIG. 5, Vinmin and Vinmax can be expressed as Equations 4 and 5 below, respectively, by the voltage divider rule of Rntc and the first-1 and second-2 resistors (R11, R12) connected in series.

[0114] [Mathematical Formula 4]

[0115]

[0116] [Mathematical Formula 5]

[0117]

[0118] When Equation 4 is rearranged for R12, Equation 3 can be derived, and when this is substituted into Equation 5 and rearranged for R11, Equation 2 can be derived.

[0119] [Mathematical Formula 2]

[0120]

[0121] [Mathematical Formula 3]

[0122]

[0123] Through this, the output circuit (120) can be operated stably, so there is an effect of improving the reliability of the gate driving circuit (1).

[0124] [Control circuit (112)]

[0125] The control circuit (112) is provided between the input circuit (111) and the output circuit (120) and controls and outputs the magnitude of the thermistor (Rntc) voltage. As an example, the control circuit (112) may be provided between the input circuit (111) and the relay circuit (113).

[0126] Specifically, the control circuit (112) receives the voltage of the common node of the first-1 resistor (R11) and the thermistor (Rntc) as the input voltage Vin of the control circuit (112), adjusts the voltage of the thermistor (Rntc) by a predetermined gain Av, and outputs Vout. Here, when Av is the gain of the control circuit (112), Vin and Vout have a relationship as shown in the following mathematical formula.

[0127] Vout = Av·Vin

[0128] Here, since the temperature compensation signal is proportional to Vout, which is the output voltage of the control circuit (112), it is important to set the value of Vout, which is the output voltage of the control circuit (112), to drive the output circuit (130).

[0129] The control circuit (112) may have first to third embodiments, and each embodiment will be described.

[0130] [1st Example]

[0131] The control circuit (112) may include a voltage follower.

[0132] In one embodiment, referring to FIG. 5, the control circuit (112) may include an operational amplifier (OP Amp), a second-1 resistor (R21), and a second-2 resistor (R22). Specifically, the non-inverting terminal of the operational amplifier (OP Amp) is connected to the output terminal of the input circuit (111). More specifically, the non-inverting terminal of the operational amplifier (OP Amp) is connected to a common node between the first-1 resistor (R11) and the thermistor (Rntc) of the input circuit (111). Additionally, the second-1 resistor (R21) is connected between the inverting terminal of the operational amplifier (OP Amp) and the output terminal of the operational amplifier (OP Amp). Additionally, the second-2 resistor (R22) is connected between the output terminal of the operational amplifier (OP Amp) and the relay circuit (113).

[0133] FIG. 8 is a graph of Vin and Vout according to the resistance value of the thermistor (Rntc) according to the first embodiment of the present disclosure when Vinmin=11V and Vinmax=14V, and Table 1 is the parameter value of the gate driving circuit (1) according to the first embodiment of the present disclosure when Vinmin=11V and Vinmax=14V.

[0134]

[0135] Referring to FIG. 8, as the temperature (Temp) of the thermistor (Rntc) decreases, the resistance value Rntc of the thermistor (Rntc) increases, and as Rntc increases, the input voltage Vin of the control circuit (112) and the output voltage Vout of the control circuit (112) increase together.

[0136] Through this, since the temperature compensation circuit (110) outputs a temperature compensation signal that varies according to the temperature change of the power semiconductor (2), the output circuit (120) can output a gate voltage that varies according to the temperature change of the power semiconductor (2).

[0137] For accurate driving of the output circuit (120), it is desirable that Vout be applied with the same value as the positive power supply (Vp). However, referring to FIG. 5, in the case of the first embodiment, a predetermined positive power supply (Vp) is voltage divided and applied to the control circuit (112) due to the first-1 and first-2 resistors (R11, R12) of the input circuit (111). In this case, since the voltage follower of the first embodiment has Av of 1, there is a problem that a voltage lower than Vp is output to Vout.

[0138] FIG. 9 is a graph of Vin and Vout according to the resistance value of the thermistor (Rntc) according to the first embodiment of the present disclosure when Vinmin=11V and Vinmax=15V, and Table 2 is the parameter value of the gate driving circuit (1) according to the first embodiment of the present disclosure when Vinmin=11V and Vinmax=15V.

[0139]

[0140] Referring to Figure 9 and Table 2, if Vinmax is set to 15V to compensate for the problem where a voltage lower than Vp is output to Vout, the value of the first-2 resistor (R12) is calculated as a negative number, so actual implementation is impossible.

[0141] FIG. 10 is a graph of Vin and Vout according to the resistance value of the thermistor (Rntc) according to the first embodiment of the present disclosure when Vinmin=9.5V and Vinmax=14V, and Table 3 is the parameter value of the gate driving circuit (1) according to the first embodiment of the present disclosure when Vinmin=9.5V and Vinmax=14V.

[0142]

[0143] In order to precisely output a temperature compensation signal according to the change in the resistance value of the thermistor (Rntc), the input voltage range of the control circuit (112) must be wide so that the temperature compensation signal is also output over a wider voltage range, thereby allowing the output circuit (120) to be controlled more precisely.

[0144] Referring to FIG. 10 and Table 3, when the input voltage range of the control circuit (112) is set wide by setting the minimum value of the input voltage to 9.5V, the value of the first-second resistor (R12) is calculated as a negative number, making actual implementation impossible. In addition, since the change in output voltage according to the thermistor (Rntc) resistor value is not large, there is a problem that it is difficult to control the gate voltage more precisely.

[0145] FIG. 11 is a graph of Vin and Vout according to the resistance value of the thermistor (Rntc) according to the first embodiment of the present disclosure when Vinmin=10V and Vinmax=14V, and Table 4 is the parameter value of the gate driving circuit (1) according to the first embodiment of the present disclosure when Vinmin=10V and Vinmax=14V.

[0146]

[0147] Referring to Figure 11 and Table 4, when the input voltage range of the control circuit (112) is set as wide as possible, the value of the first and second resistors (R12) becomes very small, so there is a problem that it is difficult to implement in an actual circuit.

[0148] Therefore, to solve the above problems, an amplifier having a value greater than 1 Av can be provided in the control circuit (112) as in the second and third embodiments described below.

[0149] [2nd Example]

[0150] FIG. 12 is a circuit diagram of a gate driving circuit (1) according to a second embodiment of the present disclosure.

[0151] The control circuit (112) of the second embodiment may include a non-inverting amplifier.

[0152] In one embodiment, referring to FIG. 12, the control circuit (112) may include an operational amplifier (OP Amp), a second-1 resistor (R21), a second-2 resistor (R22), and a second-3 resistor (R23). Specifically, the non-inverting terminal of the operational amplifier (OP Amp) is connected to the output terminal of the input circuit (111). More specifically, the non-inverting terminal of the operational amplifier (OP Amp) is connected to a common node between the first-1 resistor (R11) and the thermistor (Rntc) of the input circuit (111). Additionally, the second-1 resistor (R21) is connected between the inverting terminal of the operational amplifier (OP Amp) and the output terminal of the operational amplifier (OP Amp). Additionally, the second-2 resistor (R22) is connected between the output terminal of the operational amplifier (OP Amp) and the relay circuit (113). Additionally, the second-third resistor (R23) is connected between the inverting terminal of the operational amplifier (OP Amp) and a predetermined ground terminal.

[0153] The control circuit (112) of the second embodiment has a gain Av according to the following mathematical formula, and preferably Av can be 2 or more.

[0154] Av = 1 + (R21 / R23)

[0155] Here, Av is the gain of the control circuit (112), R21 is the value of the second-1 resistor (R21), and R23 is the value of the second-3 resistor (R23).

[0156] In the case of power semiconductors (2) connected in parallel, there is a difference in the characteristics of the thermistors (Rntc) provided in each. That is, when a deviation occurs in the resistance value of the thermistor (Rntc) even at the same temperature, the voltage follower of the first embodiment cannot vary the gain and therefore cannot correct the deviation of each thermistor (Rntc), whereas the non-inverting amplifier of the second embodiment can vary the gain by adjusting the values ​​of the 2-1 and 2-3 resistors (R21, R23), so there is an effect of correcting the deviation of each thermistor (Rntc).

[0157] As such, correction of deviations in the thermistor (Rntc) resistance characteristics is impossible with only the voltage follower of the first embodiment, and by adopting the second embodiment, a more flexible and precise design becomes possible. Through this, malfunctions that may occur due to differences between parallel power semiconductor (2) devices can be prevented, and the reliability and efficiency of the gate driving circuit (1) can be greatly improved.

[0158] FIG. 13 is a graph of Vin and Vout according to the resistance value of the thermistor (Rntc) according to the second embodiment of the present disclosure when Vinmin=5V and Vinmax=7.5V, and Table 5 is the parameter value of the gate driving circuit (1) according to the second embodiment of the present disclosure when Vinmin=5V and Vinmax=7.5V.

[0159]

[0160] Referring to FIG. 13 and Table 5, it can be seen that compared to the first embodiment, the range of the output voltage is wider, allowing the output Vout and temperature compensation signal of the control circuit (112) to be output more precisely. In addition, the values ​​of the 1-1 and 1-2 resistors (R11, R12) can be designed to have a value of 4 [kΩ] or more, making implementation easier, and accordingly, the difficulty of the manufacturing process is significantly reduced and the manufacturing cost is also reduced.

[0161] [3rd Example]

[0162] FIG. 14 is a circuit diagram of a gate driving circuit (1) according to a third embodiment of the present disclosure.

[0163] The control circuit (112) of the third embodiment may include a differential amplifier.

[0164] In one embodiment, referring to FIG. 14, the control circuit (112) may include an operational amplifier (OP Amp), a second-1 resistor (R21), a second-2 resistor (R22), a second-3 resistor (R23), a second-4 resistor (R24), and a second-5 resistor (R25). Specifically, the non-inverting terminal of the operational amplifier (OP Amp) is connected to the output terminal of the input circuit (111). More specifically, the non-inverting terminal of the operational amplifier (OP Amp) is connected to a common node between the first-1 resistor (R11) and the thermistor (Rntc) of the input circuit (111). Additionally, the second-1 resistor (R21) is connected between the inverting terminal of the operational amplifier (OP Amp) and the output terminal of the operational amplifier (OP Amp). Additionally, the second-2 resistor (R22) is connected between the output terminal of the operational amplifier (OP Amp) and the relay circuit (113). Additionally, the second-third resistor (R23) is connected between the inverting terminal of the operational amplifier (OP Amp) and a predetermined ground terminal. Additionally, the second-fourth resistor (R24) is connected between the non-inverting terminal of the operational amplifier (OP Amp) and the common node of the first-first resistor (R11) and thermistor (Rntc). Additionally, the second-fifth resistor (R25) is connected between the non-inverting terminal of the operational amplifier (OP Amp) and a predetermined ground terminal.

[0165] The control circuit (112) of the third embodiment has a gain Av according to the following mathematical formula, and preferably Av can be 2 or more.

[0166] Av = R21 / R23

[0167] Here, Av is the gain of the control circuit (112), R21 is the value of the second-1 resistor (R21), and R23 is the value of the second-3 resistor (R23).

[0168] Generally, since the differential amplifier has a high Common Mode Reduction Ratio (CMRR), it has excellent noise reduction performance and can maximize the stability of signal transmission. By employing this in the control circuit (112), accuracy in the signal transmission process can be secured and the reliability of the system can be greatly improved.

[0169] In addition, the control circuit (112) of the third embodiment can flexibly respond to various resistance values ​​through a differential amplifier even when the NTC characteristics between parallel-connected power semiconductor (2) elements are different.

[0170] In addition, unlike the second embodiment, the control circuit (112) of the third embodiment can set Av lower than 1, thereby expanding the range of correction possible for the thermistor (Rntc) resistance value. This reduces constraints on resistance selection, increases design flexibility, and maintains balance between power semiconductor (2) devices connected in parallel.

[0171] [Relay circuit (113)]

[0172] A relay circuit (113) is provided between a control circuit (112) and an output circuit (120) and includes at least one transistor. The relay circuit (113) uses at least one transistor to provide a temperature compensation signal to the output circuit (120) according to a driving command signal and the output of the control circuit (112).

[0173] In one embodiment, the relay circuit (113) may include a first transistor (Q1) and a third resistor (R3). Specifically, referring to FIGS. 5, 12 and 14, the first transistor (Q1) is provided between the output terminal of the control circuit (112) and the input terminal of the output circuit (120). Additionally, the third resistor (R3) is provided between one end of the first transistor (Q1) and a predetermined ground. Furthermore, the control terminal of the first transistor (Q1) receives a driving command signal.

[0174] Here, the first transistor (Q1) transmits the output of the temperature compensation circuit (110) to the output circuit (120) according to the driving command signal. The first transistor (Q1) may be any one of a BJT (Bipolar Junction Transistor), FET (Field Effect Transistor), JFET (Junction Field Effect Transistor), MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor), Enhancement MOSFET (Enhancement Mode Metal-Oxide-Semiconductor Field Effect Transistor), Depletion MOSFET (Depletion Mode Metal-Oxide-Semiconductor Field Effect Transistor), and IGBT (Insulated Gate Bipolar Transistor). As an example, the first transistor (Q1) may be an npn type BJT.

[0175] Referring to FIGS. 5, 12 and 14, when the first transistor (Q1) is a BJT, the collector of the first transistor (Q1) is connected to the output terminal of the temperature compensation circuit (110), the emitter is connected to the input terminal of the output circuit (120) and one end of the third resistor (R3), and a driving command signal can be applied to the base.

[0176] The operation of the relay circuit (113) is explained in detail.

[0177] The relay circuit (113) can control the output of a temperature compensation signal based on a driving command signal. Specifically, when the driving command signal is applied ON to at least one transistor, the relay circuit (113) outputs a temperature compensation signal proportional to the output of the control circuit (112). Additionally, when the driving command signal is OFF, it provides a zero-potential temperature compensation signal.

[0178] Referring to FIG. 6, when the driving command signal is ON, the relay circuit (113) provides the driving signal Vr3 to the output circuit (120) in proportion to the output Vout of the control circuit (112) because the first transistor (Q1) is ON. Additionally, when the driving command signal is OFF, the relay circuit (113) provides the zero-potential temperature compensation signal to the output circuit (120) because the third resistor (R3) connected to a predetermined ground is OFF.

[0179] Conventionally, a temperature compensation circuit (110) includes an operational amplifier (OP Amp) to adjust the magnitude of the voltage across a specific thermistor (Rntc), and receives a driving command signal through the enable terminal of the operational amplifier (OP Amp) and outputs a temperature compensation signal. However, when the driving command signal is a high-frequency PWM waveform, the delay time of the operational amplifier (OP Amp) increases to the unit of tens of microseconds, causing a problem in which the gate voltage of the power semiconductor is not applied correctly.

[0180] Accordingly, the relay circuit (113) can improve the responsiveness and stability of gate drive control by receiving a drive command signal using a BJT transistor with a delay time, such as a rise time and a fall time, in the order of tens of nanoseconds and outputting a temperature compensation signal.

[0181] [Output circuit (120)]

[0182] The output circuit (120) varies the gate voltage output to the power semiconductor (2) according to the temperature compensation signal.

[0183] In one embodiment, the output circuit (120) may include second-1 and second-2 transistors (Q21, Q22) and a gate resistor (Rg). Specifically, referring to FIGS. 5, 7 and 12, the second-1 and second-2 transistors (Q21, Q22) are connected in series with each other between a predetermined positive power supply (Vp) and a predetermined negative power supply (Vn). Additionally, a temperature compensation signal is applied to the control terminal of the second-1 transistor (Q21), and a gate voltage is provided to the power semiconductor (2) based on a driving command signal applied to the control terminal of the second transistor (Q22). Additionally, the gate resistor (Rg) is connected between the common node of the second-1 transistor (Q21) and the second-2 transistor (Q22) and the gate of the power semiconductor (2).

[0184] The 2-1 and 2-2 transistors (Q21, Q22) may be any one of a BJT (Bipolar Junction Transistor), FET (Field Effect Transistor), JFET (Junction Field Effect Transistor), MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor), Enhancement MOSFET (Enhancement Mode Metal-Oxide-Semiconductor Field Effect Transistor), Depletion MOSFET (Depletion Mode Metal-Oxide-Semiconductor Field Effect Transistor), and IGBT (Insulated Gate Bipolar Transistor). For example, the 2-1 transistor (Q21) may be an npn type BJT, and the 2-2 transistor (Q22) may be a pnp type BJT.

[0185] When the 2-1 and 2-2 transistors (Q21, Q22) are BJTs, the collector of the 2-1 transistor (Q21) is connected to a positive power supply (Vp), the emitter is connected to the collector of the 2-2 transistor (Q22), and the base can be connected to the output terminal of the temperature compensation circuit (110). Additionally, the emitter of the 2-2 transistor (Q22) is connected to a predetermined negative power supply (Vn), and a driving command signal can be input to the base.

[0186] The output circuit (120) provides a gate voltage to the power semiconductor (2) through a gate resistor (Rg) based on a driving command signal. Specifically, the gate resistor (Rg) is connected between the common node of the second-1 transistor (Q21) and the second-2 transistor (Q22) and the gate of the power semiconductor (2). The driving command signal is applied as a PWM waveform to the base of the second-2 transistor (Q2-2), so that the output circuit (120) can provide a gate voltage to the power semiconductor (2) through the gate resistor (Rg) based on the driving command signal.

[0187] In such an output circuit (120), a totem-pole circuit structure is adopted to efficiently control the gate voltage through a combination of the second-1 and second-2 transistors (Q21, Q22). Additionally, heat generation and power loss can be minimized through a combination of npn-type BJTs and pnp-type BJTs.

[0188] [Effects of the present disclosure]

[0189] Figure 15 is a graph of a driving command signal when a driving command signal is applied using the enable terminal of an operational amplifier (OP Amp).

[0190] Referring to FIG. 15, when a driving command signal is output from a predetermined controller (3), the actual driving command signal suffers loss due to delay times such as the rise time and fall time of an operational amplifier (OP Amp). In the output-impossible section where the driving command signal suffers loss, the gate voltage cannot be applied to the power semiconductor (2), so the power semiconductor (2) cannot output.

[0191] FIG. 16 is a graph of the switching signal of a power semiconductor (2) when a driving command signal is applied using the enable terminal of an operational amplifier (OP Amp).

[0192] Specifically, FIG. 16 is a voltage graph across the power semiconductor (2) of FIG. 1 when a driving command signal is applied to the enable terminal of an operational amplifier (OP Amp) to drive the gate.

[0193] Referring to FIG. 16, when a driving command signal is applied, in the totem-pole circuit of FIG. 1 and 2, the power semiconductor (2) located at the top relative to the drawing is denoted as Qtop and the power semiconductor (2) located at the bottom is denoted as Qbtm. Due to the non-output section, a delay time, which is a rise time Tr and a fall time Tf, occurs in the voltages of Qtop and Qbtm, respectively. In this case, Tr is generally larger than Tf, and this causes a problem in which the dead time Tdead between Qtop and Qbtm increases excessively. When the dead time Tdead increases in the power semiconductor (2), output voltage distortion of the power semiconductor (2) occurs, switching losses increase, and the power conversion efficiency of the power semiconductor (2) may decrease.

[0194] FIG. 17 is a graph of the switching signal of the output circuit (120) when a driving command signal is applied using the enable terminal of the operational amplifier (OP Amp).

[0195] Specifically, FIG. 17 is a voltage graph across the 2-1 and 2-2 transistors (Q21, Q22) of the output circuit (120) of FIG. 5 when a gate is driven by applying a driving command signal to the enable terminal of an operational amplifier (OP Amp) without a relay circuit.

[0196] Referring to FIG. 17, when the output terminal of the control circuit (112) is connected to the base of the second-1 transistor (Q21) of the output circuit (120) without a relay circuit (113), a driving command signal is applied to the operational amplifier (OP Amp), resulting in an output-unavailable section, and the second-1 transistor (Q21) experiences a delay time due to the operational amplifier (OP Amp), and the signal of the second-1 transistor (Q21) takes the form of a waveform that is delayed overall.

[0197] In this case, during the rise time of the second-1 transistor (Q21), a dead time T occurs with the second-2 transistor (Q22), causing a problem of increased switching loss. Additionally, during the fall time of the second-1 transistor (Q21), it turns on simultaneously with the second-2 transistor (Q22), causing a short circuit between the second-1 transistor (Q21) and the second-2 transistor (Q22), resulting in damage to the transistor.

[0198] FIG. 18 is a graph of the driving command signal of the present disclosure.

[0199] In the case of Fig. 15, a problem occurred in which the power semiconductor (2) could not be driven due to the unusable output section, but in the case of Fig. 18, the unusable output section is greatly reduced so that a gate signal can be stably provided to the power semiconductor (2).

[0200] That is, the present disclosure can improve the switching speed of the power semiconductor (2) and improve the switching efficiency of the power semiconductor (2) by reducing delay times, such as rise time and fall time, caused by an operational amplifier (OP Amp) as shown in FIG. 15 and 18, and by minimizing dead time (Tdead).

[0201] In addition, output voltage distortion is reduced due to the reduction in delay time, and power conversion efficiency can be increased by minimizing switching losses. Through this design, stable and efficient operation can be achieved even in a high-speed switching environment, and the reliability and performance of the gate driving circuit (1) can be improved.

[0202] In one embodiment of the present disclosure, the controller (3) may be a processor. A processor refers to a central processing unit (CPU) responsible for computational operations and data processing. The processor interprets and executes instructions and performs various calculations and logic operations to process the work of a program. The processor may be a microcontroller and may perform operations according to the algorithms of a program provided in a storage medium (not shown). The processor may output a calculated value through a user interface device such as a display device.

[0203] The technical concept of this disclosure should not be interpreted as being limited to the embodiments described above. Not only is the scope of application diverse, but various modifications are possible at the level of a person skilled in the art without departing from the essence of this disclosure as claimed in the claims. Accordingly, such improvements and modifications fall within the scope of protection of this disclosure insofar as they are obvious to a person skilled in the art.

[0204]

[0205] Industrial applicability

[0206] This invention is a result of the following national research and development project.

[0207] 1. Project No.: 20024464

[0208] 2. Ministry Name: Ministry of Trade, Industry and Energy

[0209] 3. Project Management (Specialized) Agency Name: Korea Institute for Industrial Technology Evaluation and Management

[0210] 4. Research Project Name: Materials and Components Technology Development Project

[0211] 5. Research Project Title: Development of Inverter Technology for 600kW-Class Motor Dynamo

[0212] 6. Name of Project Performing Organization: Seoho Drive Co., Ltd.

[0213] 7. Research Period: July 1, 2023 - December 31, 2026 (3 years and 6 months)

[0214]

[0215] [Explanation of the symbol]

[0216] 1 : Gate driving circuit

[0217] 110: Temperature compensation circuit

[0218] 111 : Input circuit

[0219] 112: Control circuit

[0220] 113 : Relay circuit

[0221] 120: Output circuit

[0222] 2 : Power Semiconductor

[0223] 3 : Controller

[0224] Rntc : Thermistor

Claims

1. A gate driving circuit that provides a variable gate voltage based on a thermistor for measuring the temperature of a power semiconductor, A temperature compensation circuit that provides a temperature compensation signal based on the resistance value of the thermistor; and An output circuit that varies the gate voltage output to the power semiconductor according to the temperature compensation signal; The above temperature compensation circuit is, A gate driving circuit comprising at least one transistor that provides a temperature compensation signal according to a driving command signal of the power semiconductor.

2. In Paragraph 1, The above temperature compensation circuit is, A gate driving circuit that, when the above driving command signal is ON, provides a temperature compensation signal of a lower potential as the temperature of the power semiconductor increases based on the resistance value of the above thermistor, and when it is OFF, provides a temperature compensation signal of a predetermined zero potential.

3. In Paragraph 2, The above temperature compensation circuit is, When the above drive command signal is ON, When the thermistor has a resistance value corresponding to a temperature of the power semiconductor below a predetermined standard, it provides a temperature compensation signal of a predetermined normal gate potential. When the thermistor has a resistance value corresponding to the temperature of the power semiconductor exceeding a predetermined standard, it provides a temperature compensation signal with a potential lower than the normal gate potential. A gate driving circuit that provides a temperature compensation signal of the normal gate potential when the connection with the thermistor is disconnected.

4. In Paragraph 3, The above temperature compensation circuit is An input circuit that receives and outputs the thermistor voltage, which is the voltage applied to the above thermistor; A control circuit provided between the input circuit and the output circuit, which controls and outputs the magnitude of the thermistor voltage; and A relay circuit provided between the control circuit and the output circuit and including at least one transistor; The above relay circuit is A gate driving circuit that outputs a temperature compensation signal proportional to the output of the control circuit when the driving command signal is applied ON to at least one transistor.

5. In Paragraph 4, The above input circuit is The first resistor, one end of which is connected to a predetermined positive power source and the other end of which is connected to the input terminal of the control circuit; and Includes first and second resistors, each connected to a predetermined ground; The other end of the above-mentioned first-1 resistor is connected to one end of the above-mentioned thermistor, and A gate driving circuit in which the other end of the first and second resistors is connected to the other end of the thermistor.

6. In Paragraph 5, A gate driving circuit having the above 1-1 and 1-2 resistance values ​​satisfying the following mathematical formula 1. [Mathematical Formula 1] (Here, Av is the gain of the control circuit, R11 is the first-1 resistance value, R12 is the first-2 resistance value, Vp is the positive power supply, Rntcmin is the thermistor resistance value at the highest temperature at which the power semiconductor can operate, and Vdmin is the lowest voltage capable of driving the output circuit) 7. In Paragraph 6, A gate driving circuit in which the above-mentioned first-1 resistor is set to a value calculated by the following mathematical formula 2. [Mathematical Formula 2] (Here, R11 is the first-1 resistance value, Vp is the positive power supply, Vinmin is the lowest input voltage of the control circuit in which the output circuit can operate, Vinmax is the maximum input voltage of the control circuit in which the output circuit can operate, Rntcmin is the lowest resistance value of the thermistor in the temperature range in which the power semiconductor can operate, and Rntcmax is the maximum resistance value of the thermistor in the temperature range in which the power semiconductor can operate) 8. In Paragraph 6, A gate driving circuit in which the first and second resistors are set to values ​​calculated by the following mathematical formula 3. [Mathematical Formula 3] (Here, R11 is the first-1 resistance value, Vinmin is the lowest input voltage of the control circuit in which the output circuit can operate, Vp is the positive power supply, R12 is the first-2 resistance value, and Rntcmin is the lowest resistance value of the thermistor in the temperature range in which the power semiconductor can operate) 9. In Paragraph 4, The above control circuit is An operational amplifier having a non-inverting terminal connected to the output terminal of the input circuit; A second-1 resistor connected between the inverting terminal of the operational amplifier and the output terminal of the operational amplifier; and A gate driving circuit comprising a second-2 resistor connected between the output terminal of the above operational amplifier and the above relay circuit.

10. In Paragraph 9, The above control circuit is A gate driving circuit further comprising a second and third resistor connected between the inverting terminal and a predetermined ground terminal of the above operational amplifier.

11. In Paragraph 10, The above control circuit is A second-fourth resistor connected between the non-inverting terminal of the above operational amplifier and the common node of the first-1 resistor and the thermistor; and A gate driving circuit further comprising a second-fifth resistor connected between the non-inverting terminal and a predetermined ground terminal of the above operational amplifier.

12. In Paragraph 4, The above relay circuit is, A first transistor provided between the output terminal of the control circuit and the input terminal of the output circuit; and A third resistor provided between one end of the first transistor and a predetermined ground; comprising The first transistor above A gate driving circuit that transmits the output of the control circuit to the output circuit according to the above driving command signal.

13. In Paragraph 1, The above output circuit is, It includes 2-1 and 2-2 transistors connected in series between a predetermined positive power source and a predetermined negative power source, The temperature compensation signal is applied to the control terminal of the above 2-1 transistor, and A gate driving circuit that provides a gate voltage to the power semiconductor based on the driving command signal applied to the control terminal of the second-2 transistor.

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