Scan chain diagnosis with clock control for improving diagnosis coverage

Abstract

A circuit comprises scan chains. The scan chains comprise a plurality of scan cells configured to operate in one of a plurality of test-related modes based on a scan enable signal for the plurality of scan cells and a diagnosis clock control signal provided by a storage device while the circuit is being tested. The plurality of test-related modes comprises a clock-inactive capture mode and a clock-active capture mode. In the clock-inactive capture mode, the scan enable signal is inactive, the diagnosis clock control signal is inactive, and the plurality of scan cells receive no clock signals. In the clock-active capture mode, the scan enable signal is inactive, the diagnosis clock control signal is active, and the plurality of scan cells receive a clock signal. The storage device may be a scan cell in the scan chains or a shadow register of a scan cell in the scan chains.

Description

[0001] SCAN CHAIN DIAGNOSIS WITH CLOCK CONTROL FOR IMPROVING DIAGNOSIS COVERAGE

[0002] FIELD OF THE DISCLOSED TECHNOLOGY

[0003]

[0001] The present disclosed technology relates to the field of circuit test and diagnosis. Various implementations of the disclosed technology may be particularly useful for scan chain diagnosis.

[0004] BACKGROUND OF THE DISCLOSED TECHNOLOGY

[0005]

[0002] Modem integrated circuits are complex. At leading technology nodes, feature sizes have shrunk to a few nrn wide. Non-planar or “three-dimensional” transistors (FinFET and GAA (gate-all-around)) are being used to achieve higher performance with lower power consumption. The non-planar transistors and transistor connections have more complicated structures with more layers and thus require more process steps. More process steps and smaller feature sizes can result in more root causes of defects. For these integrate circuits to be commercially viable, the manufacture yield needs to reach and maintain above a certain threshold. Therefore, accurately identifying yield-limiting root causes becomes highly critical. In the past, bitmapping static random-access memories (SRAMs) has been employed as a “yield learning vehicle”. For leading technology nodes, however, being capable of manufacturing these regular structures does not guarantee that a product with irregular structures can be successfully manufactured.

[0006]

[0003] Software-based diagnosis of scan test failures has proven to be of enormous value for yield learning. Scan testing is commonly used in a manufacturing process to ensure that integrated circuits are fabricated correctly. Diagnosis uses failure data from scan testing along with circuit design information to determine the most likely defect locations and mechanisms for failing circuits (dies). The diagnosis results can guide physical failure analysis (PF A) to focus on a much smaller area in a failing circuit, leading to higher success rates of PFA with reduced turnaround time and costs. Based on the yield loss mechanism obtained by PFA, circuit design or manufacture process can be adjusted to improve manufacture yields.

[0007]

[0004] The PFA process is destructive to integrated circuits. It is thus important for diagnosis to provide a target area for PFA that is as precise as possible. The resolution or diagnosis coverage of a diagnostic tool is related to the number of suspected defect locations identified. The larger the number of suspect locations reported, the larger the area for PFA to work on. The demand for diagnosis resolution / coverage has increased, especially for chain diagnosis, where, due to the complexity of scan cell structures, PFA needs a diagnosis tool to report a single scan cell for PFA to work on. Recent data shows that diagnosis based directly on manufacture test patterns does not consistently achieve the required diagnostic quality. Even using test patterns specifically generated for diagnosis cannot pinpoint specific faulty scan cells in many cases.

[0008] BRIEF SUMMARY OF THE DISCLOSED TECHNOLOGY

[0009]

[0005] Various aspects of the present disclosed technology relate to techniques for diagnosis clock control for improving diagnosis coverage. There is a circuit comprising: scan chains, the scan chains comprising a plurality of scan cells, wherein the plurality of scan cells are configured to operate in one of a plurality of test-related modes based on a scan enable signal for the plurality of scan cells and a diagnosis clock control signal provided by a storage device while the circuit is being tested, the plurality of test-related modes comprises a clock-inactive capture mode and a clock-active capture mode, wherein in the clock-inactive capture mode, the scan enable signal is inactive, the diagnosis clock control signal is inactive, and the plurality of scan cells receive no clock signals, and wherein in the clock-active capture mode, the scan enable signal is inactive, the diagnosis clock control signal is active, and the plurality of scan cells receive a clock signal.

[0006] The storage device may be a scan cell in the scan chains or a shadow register of a scan cell in the scan chains. The plurality of scan cells may be identified based on design rule checking, diagnosability analysis, test pattern generation for diagnosis, or any combination thereof. The clock signal may be a scan clock signal.

[0010]

[0007] The circuit may further comprise: a controllable inverting device placed on a shift path of one of the scan chains and between a serial output of a scan cell (K + 1) and a serial input of a scan cell K, numbers (K+ 1) and K being scan cell indices, wherein the controllable inverting device is configured to output an inverted version or an original version of a bit received at a data input of the controllable inverting device based on an inversion-control signal, and wherein the scan cell K is configured to operate in a diagnosis capture mode based on a modified scan enable signal and the inversion-control signal. The controllable inverting device may be an XOR gate. The scan cells (X+l) and K may be in the plurality of scan cells. The scan cell K may be identified based on design rule checking, diagnosability analysis, test pattern generation for diagnosis, or any combination thereof.

[0011]

[0008] The modified scan enable signal may be derived by a logical OR operation of a diagnosis mode signal and the scan enable signal, and the inversion-control signal may be derived by inverting the scan enable signal, the diagnosis mode signal being provided by another storage device.

[0012]

[0009] Alternatively, the modified scan enable signal may be derived by a logical OR operation of a diagnosis mode signal and the scan enable signal, and the inversion-control signal may be derived by a logical AND operation of the diagnosis mode signal and a signal derived by inverting the scan enable signal, the diagnosis mode signal being provided by another storage device.

[0010] Certain inventive aspects are set out in the accompanying independent and dependent claims. Features from the dependent claims may be combined with features of the independent claims and with features of other dependent claims as appropriate and not merely as explicitly set out in the claims.

[0013]

[0011] Certain objects and advantages of various inventive aspects have been described herein above. Of course, it is to be understood that not necessarily all such objects or advantages may be achieved in accordance with any particular embodiment of the disclosed technology. Thus, for example, those skilled in the art will recognize that the disclosed technology may be embodied or carried out in a manner that achieves or optimizes one advantage or group of advantages as taught herein without necessarily achieving other objects or advantages as may be taught or suggested herein.

[0014] BRIEF DESCRIPTION OF THE DRAWINGS

[0015]

[0012] Figure 1 illustrates an example of a scan cell.

[0016]

[0013] Figure 2 illustrates an example of a scan chain.

[0017]

[0014] Figure 3 A illustrates an example of two neighboring scan cells forming a part or a whole of a shift register.

[0018]

[0015] Figure 3B illustrates another example of two neighboring scan cells forming a part or a whole of a shift register.

[0019]

[0016] Figure 4 illustrates an example of a circuit implementing adaptive diagnosis clock control according to various embodiments of the disclosed technology.

[0020]

[0017] Figure 5 illustrates an example of a scan cell that can be used to implement a storage device for storing the diagnosis clock control signal according to various embodiments of the disclosed technology.

[0018] Figure 6 illustrates a table listing some test-related modes in which a scan cell can operate based on a scan enable signal and a diagnosis clock control signal according to various embodiments of the disclosed technology.

[0021]

[0019] Figure 7 illustrates an example of a circuit having inserted diagnosis points that may be implemented according to various embodiments of the disclosed technology.

[0022]

[0020] Figure 8 illustrates an example of a control signal generation device that may be implemented according to various embodiments of the disclosed technology.

[0023]

[0021] Figure 9 illustrates another example of a control signal generation device that may be implemented according to various embodiments of the disclosed technology.

[0024]

[0022] Figure 10 illustrates an example of diagnosis point insertion for a scan chain that may be implemented according to various embodiments of the disclosed technology.

[0025]

[0023] Figure 11 illustrates another example of diagnosis point insertion for a scan chain that may be implemented according to various embodiments of the disclosed technology.

[0026] DETAILED DESCRIPTION OF THE DISCLOSED TECHNOLOGY

[0027] General Considerations

[0028]

[0024] Various aspects of the present disclosed technology relate to techniques for diagnosis clock control for improving diagnosis coverage. In the following description, numerous details are set forth for the purpose of explanation. However, one of ordinary skill in the art will realize that the disclosed technology may be practiced without the use of these specific details. In other instances, well-known features have not been described in detail to avoid obscuring the present disclosed technology.

[0025] Some of the techniques described herein can be implemented in software instructions stored on a computer-readable medium, software instructions executed on a computer, or some combination of both. Some of the disclosed techniques, for example, can be implemented as part of an electronic design automation (EDA) tool. Such methods can be executed on a single computer or on networked computers.

[0029]

[0026] Although the operations of the disclosed methods are described in a particular sequential order for convenient presentation, it should be understood that this manner of description encompasses rearrangements, unless a particular ordering is required by specific language set forth below. For example, operations described sequentially may in some cases be rearranged or performed concurrently. The detailed description sometimes uses terms like “configure”, “provide,” “invert,” “derive,” and “capture” to describe the disclosed methods / systems. Such terms are high-level descriptions of the actual operations that are performed. The actual operations that correspond to these terms will vary depending on the particular implementation and are readily discernible by one of ordinary skill in the art.

[0030]

[0027] As used in this disclosure, the singular forms “a,” “an,” and “the” include the plural forms unless the context clearly dictates otherwise. Additionally, the term “includes” means “comprises.” Moreover, unless the context dictates otherwise, the term “coupled” means electrically or electromagnetically connected or linked and includes both direct connections or direct links and indirect connections or indirect links through one or more intermediate elements not affecting the intended operation of the circuit.

[0031]

[0028] Also, as used herein, the term “design” is intended to encompass data describing an entire integrated circuit device. This term also is intended to encompass a smaller group of data describing one or more components of an entire device, however, such as a portion of an integrated circuit device. Still further, the term “design” also is intended to encompass data describing more than one microdevice, such as data to be used to form multiple microdevices on a single wafer.

[0032] Design For Test, Test Pattern Generation, Testing And Diagnosis

[0033]

[0029] The reduction in feature size increases the probability that a manufacture defect in an integrated circuit will result in a faulty chip. A very small defect can result in a faulty transistor or interconnecting wire. Even a single faulty transistor or wire can cause the entire chip to function improperly. Manufacture defects are unavoidable nonetheless, no matter whether the manufacturing process is at the prototype stage or the high-volume manufacturing stage. It is thus necessary to test chips during the manufacturing process. Diagnosing faulty chips is also needed to ramp up and to maintain the manufacturing yield.

[0034]

[0030] Testing typically includes applying a set of test stimuli (test patterns) to the circuit-under- test and then analyzing responses generated by the circuit-under-test. Functional testing attempts to validate that the circuit-under-test operates according to its functional specification while structural testing tries to ascertain that the circuit-under-test has been assembled correctly from some low-level building blocks as specified in a structural netlist and that these low-level building blocks and their wiring connections have been manufactured without defect. For structural testing, it is assumed that if functional verification has shown the correctness of the netlist and structural testing has confirmed the correct assembly of the structural circuit elements, then the circuit should function correctly. Structural testing has been widely adopted at least in part because it enables the test (test pattern) generation to focus on testing a limited number of relatively simple circuit elements rather than having to deal with an exponentially exploding multiplicity of functional states and state transitions.

[0031] To make it easier to develop and apply test patterns, certain testability features are added to circuit designs, which is referred to as design for test or design for testability (DFT). Scan testing is the most common DFT method. In a basic scan testing scheme, all or most of internal sequential state elements (latches, flip-flops, et al.) in a circuit design are made controllable and observable via a serial interface. These functional state elements are usually replaced with dual-purpose state elements called scan cells. Scan cells are connected together to form scan chains - serial shift registers for shifting in test patterns and shifting out test responses. A scan cell can operate as originally intended for functional purposes (functional / mission mode) and as a unit in a scan chain for scan testing (scan mode). A widely used type of scan cell includes an edge-trigged flip-flop with two-way multiplexer for the data input. The two-way multiplexer is typically controlled by a single control signal called scan enable, which selects the input signal for a scan cell from either a scan signal input port or a system signal input port. The scan signal input port is typically connected to an output of another scan cell while the system signal input port is connected to the functional logic. Scan cells can serve as both a control point and an observation point. Control points can be used to set certain logic values at some locations of the circuit-under-test, exciting (activating) a fault and propagating the incorrect value to an observation point. Scan testing allows the test equipment to access gates deeply embedded through the primary inputs / outputs and / or some physical test points and can remove the need for complicated state transition sequences when trying to control or observe what is happening at some internal circuit element.

[0035]

[0032] In a typical scan test, a series of known values (test stimuli or test pattern) are shifted-in (or loaded into) scan cells through their sequential inputs. The shifting-in occurs by placing the integrated circuit in a special mode, known as shift mode, and then applying a series of clock pulses, called “shift pulses” or “shift clock pulses.” Each shift clock pulse pushes a bit of test stimuli into a scan cell in each of the scan chains. This continues until all scan cells in the scan chains are filled with test pattern bits. Then, one or more clock pulses, called “capture pulses” or “capture clock pulses,” are applied to the circuit as they would be in normal operation. This is referred to as capture mode. After the test pattern bits are injected into the circuit, the results of the test (test responses) are “captured” and stored in the scan cells. The circuit then returns to shift mode, and with each additional clock pulse, a bit of the test responses is pushed or shifted out as each bit of new test pattern is pushed or shifted in. The shifted-out test responses are then compared with expected results to determine and locate any errors. Shift mode and capture mode together may be called as test mode.

[0036]

[0033] Test patterns for scan testing are typically generated through an automatic test pattern generation (ATPG) process. ATPG usually focuses on a set of faults derived from a gatelevel fault model. A defect is a flaw or physical imperfection caused in a device during the manufacturing process. A fault model (or briefly a fault) is a description of how a defect alters design behavior. For a given target fault, ATPG comprises two phases: fault activation and fault propagation. Fault activation establishes a signal value at the fault site opposite that produced by the fault (e.g., for a stuck-at-0 fault, the fault activation process will try to establish a logic '1' at that site). Fault propagation propagates the fault effect (e.g., stuck at 0) forward by sensitizing a path from a fault site to a scan cell or a primary output. A fault at a site is said to be detected by a test pattern if a test response value captured by a scan cell or a primary output is different than the expected value. The objective of ATPG is to find a test pattern that, when applied to the circuit, enables testers to distinguish between the correct circuit behavior and the faulty circuit behavior caused by one or more particular faults. Effectiveness of ATPG is measured by the fault coverage achieved for the fault model and the number of generated vectors (test pattern counts), which should be directly proportional to test application time. Here, the fault coverage is defined as a ratio of the number of detected faults vs. the total number of faults.

[0034] A popular fault model used in practice is the single stuck-at fault model. In this model, one of the signal lines in a circuit is assumed to be stuck at a fixed logic value, regardless of what inputs are supplied to the circuit. The stuck-at fault model is a logical fault model because no delay information is associated with the fault definition. Delay faults cause errors in the functioning of a circuit based on its timing. They are caused by the finite rise and fall time periods of the signals in the gates, as well as the propagation delay of interconnects between the gates. Transition faults are used for their simplicity in modeling spot defects that affect delays at inputs or outputs of gates. Under scan-based tests, the transition faults are associated with an extra delay that is large enough to cause the delay of any path through the fault site to exceed the clock period. Cell internal fault models can be derived using transistor-level circuit simulations (analog simulations). This approach can pinpoint the defect location within a cell for various cell internal defects.

[0037]

[0035] During the circuit design and manufacturing process, a manufacturing test screens out chips (dies) containing defects. The test itself, however, does not identify the reason for the unacceptable low or fluctuating yield that may be observed. Physical failure analysis (PF A) can inspect the faulty chip to locate the defect location(s) and to discover the root cause. The process usually includes etching away certain layers and then imaging the silicon surface by scanning electronic microscopy or focused ion beam systems. This PFA process is laborious and time consuming. To facilitate the PFA process, diagnosis (also referred to as scan diagnosis) is often employed to narrow down possible locations of the defect(s) based on analyzing the fail log (fail file, failure file). The fail log typically contains information about when (e.g., tester cycle), where (e.g., at what tester channel), and how (e.g., at what logic value) the test failed and which test patterns generate expected test responses. The layout information of the circuit design may also be employed to further reduce the number of defect suspects.

[0036] Diagnosis includes logic diagnosis (sometimes referred to as scan diagnosis) and chain diagnosis. Logic diagnosis may employ a fault dictionary or directly examine the syndrome (i.e., the effect) of the failing chip to determine likely defect locations (defect suspects). The latter approach may include structural pruning (back tracing), fault injection and evaluation (fault simulation for both failing and passing test patterns).

[0038]

[0037] Chain diagnosis determines scan cells that are likely to be defective. Scan elements and related clocking circuitry can take up about 30% of silicon area of an IC chip. It has been reported that scan chain failures account for almost 50% of chip failure in some cases. Chain diagnosis is thus important to guide physical failure analysis and yield learning process. In a chain diagnosis process, two types of test patterns may be used. The first type is called chain patterns. A chain pattern is a pattern used in a process comprising shift-in and shift-out without pulsing capture clocks. The other type is often referred to as scan patterns. A scan pattern is a pattern used in a process comprising shift-in, one or multiple capture clock cycles, and shift-out, and the scan patterns include patterns generated by ATPG for testing system logic, special chain diagnostic patterns generated only for scan chain diagnosis purpose and some special functional patterns. Chain patterns can be used to test the integrity of scan chains and / or determine fault models associated with faulty scan chains while scan patterns can be used to inject certain values to some scan cells for locating defective scan cells.

[0039]

[0038] The quality of diagnosis can be measured by diagnostic resolution (the number of the real defects vs. the number of the defect suspects). Diagnostic resolution is linked not only to the algorithm used for diagnosis but also to the test patterns used for the manufacturing test (manufacturing test patterns). The quality of diagnosis can also be measured by diagnosis coverage. Diagnosis coverage may be determined in several ways. A simple way is to divide the number of equivalent fault groups by the number of faults. Faults in an equivalent fault group cannot be separated or distinguished under a certain condition by a diagnosis technique. To enhance the quality of diagnosis, a diagnostic test pattern generation process may be employed. This process generates test patterns that can increase the number of equivalent fault groups or reduce the average number of faults in the equivalent fault groups.

[0040]

[0039] Test application in chip manufacturing test is normally performed by automatic test equipment (ATE) (a type of testers). Scan-based tests consume significant amounts of storage and test time on ATE. The data volume increases with the number of logic gates on the chip and the same holds for the number of scan cells. Yet, practical considerations and ATE specifications often limit both the number of pins available for scan in / out and the maximum scan frequency. It is highly desirable to reduce the amount of test data that need to be loaded onto ATE and ultimately to the circuit under test. Fortunately, test patterns are compressible mainly because only 1% to 5% of test pattern bits are typically specified bits (care bits) while the rest are unspecified bits (don't-care bits). Unspecified bits can take on any values with no impact on the fault coverage. Test compression may also take advantage of the fact that test cubes tend to be highly correlated. A test cube is a deterministic test pattern in which the don't-care bits are not filled by ATPG. The correlation exists because faults are structurally related in the circuit.

[0041]

[0040] Various test compression techniques have been developed. In general, additional on-chip hardware before and after scan chains is inserted. The hardware (decompressor) added before scan chains is configured to decompress test stimulus coming from ATE, while the hardware (compactor) added after scan chains is configured to compact test responses captured by the scan chains. The decompressor expands the data from n tester channels to fill greater than n scan chains. The increase in the number of scan chains shortens each scan chain and thus reduces the number of clock cycles needed to shift in each test pattern. Thus, test compression can not only reduce the amount of data stored on the tester but also reduce the test time for a given test data bandwidth. Clocks For Chain Diagnosis

[0042]

[0041] Fig. 1 illustrates an example of a scan cell 100. The scan cell 100 comprises a state element 110 and a two-way multiplexer 120. The state element 110 can be implemented using an edge-trigged flip-flop. The two-way multiplexer 120 selects a signal from either a serial input port 130 or a parallel input port 140 of the scan cell 100 as the data input signal for the state element 110. The selection is based on a scan enable signal supplied from a scan enable port 150 of the scan cell 100. The serial input port 130 can be coupled to an output of another scan cell in the same scan chain and the parallel input port 140 can be coupled to functional circuitry 170.

[0043]

[0042] When the scan enable signal 150 is asserted (active), the serial input port 130 is coupled to the data input for the state element 110. As a result, the scan cell 100 operates in a shift mode (normal shift mode). When the scan enable signal 150 is deasserted (inactive), the parallel input port 140 is coupled to the data input for the state element 110. As a result, the scan cell 100 operates in a capture mode (normal capture mode). The scan cell 100 fans out into two outputs: a serial output 160 and a parallel output 180. The serial output 160 can be coupled to the serial input port of the next scan cell in the same scan chain. The parallel output 180 can be coupled to the functional circuitry 170.

[0044]

[0043] The scan cell 100 also has a clock input 190, which provides a clock signal for the state element 110. State elements like flip-flops or latches use the clock signal to control when they capture and store data. The clock signal plays a critical role in synchronizing the behavior of the circuit, ensuring that data is transferred and processed at the correct times.

[0045]

[0044] In a circuit design, scan cells are stitched together to form scan chains. Fig. 2 illustrates an example of a scan chain 200. The scan chain 200 has no shadow register and thus data bits stored in scan cells 210, 220, 230 are being applied to the functional circuitry 240 continuously even in the shift mode. During a test, scan chains can shift in test stimuli bits of a test pattern in the shift mode, capture test response bits for the test pattern from the functional circuitry in the capture mode, and shift out the test response bits again in the shift mode.

[0046]

[0045] A clock signal 250 for the scan chain 200 typically is coupled to two different clock signal sources for two different operations. In a normal operation (functional operation), the scan cells 210, 220, 230 behave like regular flip-flops in the functional circuit and the clock signal 250 uses a functional clock signal (often referred to as a system clock signal) which controls the timing of data capture in the flip-flops as per the functional logic. The functional clock signal is also used for a capture operation in a circuit test. In a scan operation (shift operation) in a circuit test, the clock signal 250 is typically coupled to a slower clock signal (a scan clock signal) to shift test-related data in and out of the scan cells 210, 220, 230. The low clock frequency for this operation not only ensures that the scan cells correctly shift data without timing violations, but also helps reduce the temperature rise in the chip, mitigating the risk of thermal damage or performance degradation due to excessive heat. A significant amount of switching activity can occur when test-related data bits are being shifted through a large number of scan cells at each clock cycle. A scan enable signal 260 is often used to determine whether the clock signal is coupled to the functional clock signal or the scan clock signal.

[0047]

[0046] To reduce the power consumption, a circuit may shut off different parts in different times periods. For example, many systems have various low-power modes to conserve energy when full performance is not needed, particularly in battery-powered or energy-efficient devices. A circuit may have multiple clock domains. A clock domain refers to a group of state elements that are controlled by the same clock signal (or signals that are derived from the same source). When using multiple clock domains, low-power techniques can be applied selectively, allowing certain parts of the system to operate at full performance, while others are in a power-saving mode.

[0047] The low power management, however, can create challenges for achieving high diagnosis coverage. Some scan cells are used to control clock gating devices for low power management or on-chip clock generators. When these scan cells are faulty, it significantly impacts circuit behavior, complicating chain diagnosis. Even when these scan cells are not faulty, lack of capture clocks due to the low power mode can prevent scan cells from being distinguished during chain diagnosis.

[0048]

[0048] The diagnosis coverage can be calculated based on how many equivalent fault groups have a single fault. A simple way to compute the diagnosis coverage is to divide the number of equivalent fault groups by the number of faults. Faults in an equivalent fault group are faults that cannot be separated or distinguished under a certain condition or using one or more specific diagnosis techniques. In chain diagnosis, two equivalent faults are often associated with two scan cells, particularly two neighboring ones.

[0049]

[0049] When the production test patterns are insufficient to achieve 100% diagnosis coverage, additional test patterns may be generated for diagnosis to ensure as many faults as possible to have unique failing bits. This type of ATPG may be referred to as diagnosis ATPG or diagnosis (test) pattern generation. Two diagnosis test pattern generation algorithms may be employed to create two kinds of test patterns for separating faults at two neighboring scan cells, namely scan cell K and scan cell (K + 1). One is referred to as observe-unload test patterns and the other is referred to as observe-load test patterns. To distinguish whether the scan cell K or the scan cell (7C + 1) has the stuck-at-v fault, for example, the observe-unload test generation algorithm tries to create a test pattern to determine specifically whether the scan cell K has the stuck-at-v fault. In this algorithm, each of scan cells (K + 1 ), K, (K - 1 ),..., 0 is constrained to a bit value v and an ATPG process is performed to ensure that the scan cell K can capture a bit value (1 - v). If the unloaded test response bit for the scan cell K is (1 - v), then the scan cell K does not have the stuck-at-v fault. Otherwise, the scan cell K has the stuck-at-v fault. The captured value (1 - v) is referred to as clean bit data. For a scan pattern, scan loading operations are performed before the capture operations. To ensure the capture data is clean, each of the scan cells from cell (K + 1) to its downstream scan cells in the same scan chain is loaded with a value v to ensure no loading failures due to the stuck-at-v fault in either of the scan cells (K+ 1) and K The diagnosis ATPG process decides how to supply the clean bit data. Without loading errors due to the constraints, the capture value (1 - v) at the scan cell K can be guaranteed to be clean. The unloaded value at scan cell K is referred to as an output care bit because its value indicates whether or not the scan cell K has the stuck- at-v fault.

[0050]

[0050] On the other hand, to distinguish whether the scan cell K or the scan cell (K + 1) has the stuck-at-v fault, the observe-load test generation algorithm tries to create a test pattern to determine specifically whether the scan cell (K+ 1) has the stuck-at-v fault. In this algorithm, the scan cell (K + 1) is loaded with a value (1 - v) and each of scan cells K, (K - 1),..., 0 is constrained to a value v; and a diagnosis ATPG process is performed to propagate the fault effect at the scan cell (K + 1) output, which should excite the fault at the scan cell ( + 1) due to the last load cycle having a value (1 - v) at the scan cell (K + 1) but not the fault at the scan cell K due to its load value v, to a clean observation value. The clean observation value should be captured by either a scan cell in other good scan chains or any scan cell downstream of the scan cell K, referring to as a clean observation point, This algorithm constrains the scan cell K and its downstream scan cells to value v. These constraints ensure that all these loading values are unaffected by the fault in either of the scan cells (K + 1) and K. If the fault is at the scan cell (K + 1), this test pattern can observe a failing bit at the clean observation point. If the fault is at the scan cell K, this pattern cannot have a failing bit at the clean observation point. This clean observation point is the output care bit that needs to be observed.

[0051]

[0051] For design with test response compaction, it is necessary to ensure that unknown values from other chains do not mask the output care bit. Both observe-unload and observe-load patterns have one output care bit each.

[0052] There are several reasons why diagnosis ATPG cannot always generate the abovedescribed two types of test patterns. One reason is that diagnosis ATPG cannot find a test pattern that can distinguish the two scan cells under the abovementioned constraints. As noted previously, scan cells can be used to control circuit behavior, such as scan wrapper cells in core boundaries for hierarchical tests, low-power clock management scan cells, and on-chip clock generator control scan cells. When these scan cells are faulty, it significantly impacts circuit behavior, complicating chain diagnosis. As described in the requirements to generate observe-unload and observe-load test patterns for a target cell, scan cells downstream of the target cell need to be constrained to ensure clean data. These constraints may shut off hierarchical test capability or capture clock operations. Without proper capture operations, neither of the two types of test patterns can be created.

[0052]

[0053] Another reason why diagnosis ATPG cannot always generate the above-described two types of test patterns is that the test generation program can reach a user-defined CPU (central processing unit) time limit or backtracking limit. Due to constraints on loading values, scan cells do not have complete controllability, such that more capture clock cycles may be needed to get specific values at certain scan cells. Using more capture clock cycles increases ATPG complexity exponentially. In other words, some test patterns are expected to fail to be created due to sequential depth limits. In modem designs, it is impractical to expect ATPG to use more than four capture clock cycles in its test generation search space. For designs with test compression, since there are many constraints on loading value, many input care bits may exceed the test compression capacity.

[0053]

[0054] Still another reason why diagnosis ATPG cannot always generate the above-described two types of test patterns is that two neighboring scan cells are in a shift register. For example, some scan cells are often added to test chips without functional usage. Fig. 3A illustrates an example of two neighboring scan cells 310 and 320 forming a part or a whole of a shift register. All failing bits created from the shift register are independent of fault location. As such, the two neighboring scan cells 310 and 320 are not distinguishable using any test patterns. Fig. 3B illustrates another example of two neighboring scan cells 330 and 340 forming a part or a whole of a shift register. They are also not distinguishable using any test patterns even through each of the two neighboring scan cells 330 and 340 has a parallel input and a scan enable input.

[0054]

[0055] To overcome some of the limitations of diagnosis test pattern generation like those described above and to further increase the diagnosis coverage, the disclosed technology employs adaptive diagnosis clock control methods. Fig. 4 illustrates an example of a circuit 400 implementing adaptive diagnosis clock control according to various embodiments of the disclosed technology. The circuit 400 comprises scan chains 405, The scan chains 405 comprise a plurality of scan cells 410, which are configured to operate in one of a plurality of test-related modes based on a scan enable signal 440 and a diagnosis clock control signal 450. The diagnosis clock control signal 450 is provided by a storage device 420 while the circuit 400 is being tested. With various implementations of the disclosed technology, the storage device 420 may be a scan cell or a shadow register of a scan cell in the scan chains 405 or a test data register in an IJTAG network (IEEE P1687 Internal JTAG). If a scan cell in the scan chains 405 is used, the diagnosis clock control signal 450 can be loaded with a test pattern. Fig. 5 illustrates an example of a scan cell 500 that can be used to implement a storage device for storing a diagnosis clock control signal 580 according to various embodiments of the disclosed technology. Like the scan cell 100 in Fig. 1, the scan cell 500 comprises a state element 510 and a two-way multiplexer 520. To make the diagnosis clock control signal 580 stable during a capture mode, the parallel output 560 of the scan cell 500 is connected to the parallel input 540.

[0055]

[0056] Referring back to Fig. 4, the plurality of test-related modes in which the plurality of scan cells 410 can operate comprise a clock-inactive capture mode and a clock-active capture mode. The clock-inactive capture mode is activated when both the scan enable signal 440 and the diagnosis clock control signal 450 are inactive (deasserted in various implementations). The clock-active capture mode is activated when the scan enable signal 440 is inactive and the diagnosis clock control signal 450 is active (asserted in various implementations). For scan cells other than the plurality of scan cells 410, the assertion of the scan enable signal 440 makes them operate in a normal shift mode and be clocked by a scan clock signal 460, and the deassertion of the scan enable signal 440 makes them operate in a normal capture mode and be clocked by a functional clock signal 470. In a functional mode, the scan enable signal 440 is also deasserted. Fig. 6 illustrates a table 600 listing some test-related modes in which a scan cell can operate based on a scan enable signal and a diagnosis clock control signal according to various embodiments of the disclosed technology. The listed test-related modes include the clock-inactive capture mode and the clock-active capture mode which are described above. The listed test-related modes also include two shift modes corresponding to two statuses of the diagnosis clock control signal. These two shift modes are the same as a normal shift mode.

[0056]

[0057] Referring back to Fig.4, the circuit 400 further comprises clock gating / selection circuitry 490. The output of the clock gating / selection circuitry 490 is coupled to clock inputs of the plurality of scan cells 410. One function of the clock gating / selection circuitry 490 is to block the functional clock signal 470 based on a functional clock control signal 480. The functional clock control signal 480 may be provided by a storage device such as a scan cell 430 in the scan chains 405. Assuming that the functional clock signal 470 is blocked from reaching the plurality of scan cells 410 by the functional clock control signal 480 during a test, the plurality of scan cells 410 receive no clock signals and thus cannot perform a normal capture operation in the clock-inactive capture mode. However, the assertion of the diagnosis clock control signal 450 allows the plurality of scan cells 410 to receive a clock signal in the clock-active capture mode. In some embodiments of the disclosed technology, the received clock signal is the scan clock signal 460. In some other embodiments of the disclosed technology, the received clock signal is the functional clock signal 470.

[0057]

[0058] It should be noted that while being shown to be in one of the scan chains 405, the plurality of scan cells 410 can be in more than one scan chains. It should also be noted that while being shown to be part of one of the scan chains 405, the plurality of scan cells 410 include every scan cell of one scan chain.

[0058]

[0059] The plurality of scan cells 410 may be the scan cells in the scan chains 405 that not only lack a clock signal during a normal capture operation but also impact the diagnosis coverage. The plurality of scan cells 410 may be identified based on design rule checking, diagnosability analysis, test pattern generation for diagnosis, or any combination thereof. The clock gating / selection circuitry 490 may be identified by tracing backwards from the clock inputs of the plurality of scan cells 410.

[0059]

[0060] Adaptive diagnosis clock control alone may not be able to solve all of the diagnosis coverage problems. According to various embodiments of the disclosed technology, controllable inverting devices may be inserted into scan paths as clean bit data sources. Here, an inserted controllable inverting device can be referred to as a diagnosis point. By adding a diagnosis point between a pair of scan cells (K + 1) and K, an observe-unload test pattern can be created successfully for the scan cell K so that the scan cells (K + 1) and K can be distinguished. For the stuck-at-0 fault, for example, value 0 are loaded to both the scan cells (K + 1) and K. As such, the scan cell (K+ 1) loading value 0 will provide the clean bit value 1 at the scan cell K after the capture cycle in the diagnosis capture mode due to the inversion at the shift path of the scan cell K. Diagnosis points can also be employed to solve diagnosis coverage problems associated with other types of chain faults.

[0061] Fig. 7 illustrates an example of a circuit 700 having inserted diagnosis points that may be implemented according to various embodiments of the disclosed technology. The circuit 700 comprises scan chains 710. The scan chains 710 are formed by stitching scan cells together. A scan chain 720 in the scan chains 710 comprises a pair of neighboring scan cells 730 and 740, and a controllable inverting device 750 inserted into the shift path of the scan chain 720 and between a serial output of the scan cell 730 and a serial input of the scan cell 740. In some situations, the controllable inverting device 750 may be placed on an overlap portion of the shift path and the capture path (from functional circuitry to the data input of the state element) of the scan cell 740. In the present disclosure, the scan cells 730 and 740 are also referred to as scan cells (K+ 1) and K, respectively. The indices of (K+ 1) and K show scan cell positions on the scan chains 710. In this disclosure, scan cells in a scan chain are numbered incrementally from the scan output to the scan input, with the first scan cell assigned an index of 0, the second assigned an index of 1, and so on. This convention is widely used in the industry. The scan cells between the scan input of the scan chain and the serial input of a scan cell are called “upstream scan cells” of the scan cell, while the scan cells between the scan output of the scan chain and the serial output of the scan cell are called “downstream scan cells” of the scan cell.

[0060]

[0062] The controllable inverting device 750 is configured to output an inverted version (“v”) or an original version (“1 - v”) of a bit (“v”) received at its data input based on an inversioncontrol signal 770. The inversion-control signal 770 is coupled to the control input of the controllable inverting device 750. The controllable inverting device 750 may be implemented using an XOR gate. The scan enable input of the scan cell 740 (scan cell K) is coupled to a modified scan enable signal 760. A control signal generation device 795 is configured to derive the modified scan enable signal 760 based on a diagnosis mode signal 790 and a regular scan enable signal 780. In addition, the control signal generation device 795 can also generate the inversion-control signal 770. The regular scan enable signal 780 is the conventional scan enable signal that is typically used to control in which mode, the conventional shift mode or the conventional capture mode, a scan cell operates. The diagnosis mode signal 790 is provided by a storage device 797. With various implementations of the disclosed technology, the storage device 797 may be a scan cell or a shadow register of a scan cell in the scan chains 710 or a test data register in an IJTAG network (IEEE P1687 Internal JTAG). If a scan cell in the scan chains 710 is used, the diagnosis mode signal 790 can be loaded with a test pattern. The scan cell for providing the diagnosis mode signal 790 may be implemented using the scan cell 500 in Fig. 5.

[0061]

[0063] By using the modified scan enable signal 760 along with the inversion-control signal 770, the scan cell 740 can operate in at least one additional mode, diagnosis capture mode. In the diagnosis capture mode, the scan cell 740 is configured to capture the inverted version (“1 - v”) of a bit (“v”) received at the data input of the controllable inverting device 750. The diagnosis capture mode may be activated by asserting not only the inversion-control signal 770 but also the modified scan enable signal 760.

[0062]

[0064] Fig. 8 illustrates an example of a control signal generation device 800 that may be implemented according to various embodiments of the disclosed technology. The control signal generation device 800 comprises an inverter 810 and an OR gate 820. The inverter 810 is configured to generate an inversion-control signal 850 by inverting a regular scan enable signal 830. The OR gate 820 is configured to generate a modified scan enable signal 860 by performing a logical OR operation of the regular scan enable signal 830 and a diagnosis mode signal 840. When the regular scan enable signal 830 is asserted and the diagnosis mode signal 840 is deasserted, the modified scan enable signal 860 is asserted and the inversion-control signal 850 is deasserted, activating the normal shift mode for the scan cell. When both the regular scan enable signal 830 and the diagnosis mode signal 840 are deasserted, the modified scan enable signal 860 is deasserted, activating the normal capture mode for the scan cell. When both the regular scan enable signal 830 and the diagnosis mode signal 840 are asserted, the modified scan enable signal 860 is asserted and the inversion-control signal 850 is deasserted, activating the diagnosis shift mode for the scan cell. It should be noted that the diagnosis shift mode is essentially the same as the normal shift mode. When the regular scan enable signal 830 is deasserted and the diagnosis mode signal 840 is asserted, both the modified scan enable signal 860 and the inversion-control signal 850 are asserted, activating the diagnosis capture mode for the scan cell. In the diagnosis capture mode, the scan cell is to capture the inverted version (“1 - v”) of a bit (“v”) received at the data input of the controllable inverting device. A table 870 in Fig. 8 summarizes the above-described four test-related modes in which a scan cell can operate based on the regular scan enable signal 830 and the diagnosis mode signal 840.

[0063]

[0065] Fig. 9 illustrates another example of a control signal generation device 900 that may be implemented according to various embodiments of the disclosed technology. The control signal generation device 900 comprises an inverter 910, an OR gate 920 and an AND gate 980. Similar to the OR gate 820 in Fig. 8, the OR gate 920 is configured to generate a modified scan enable signal 960 by performing a logical OR operation of a regular scan enable signal 930 and a diagnosis mode signal 940. Also similar to the inverter 810 in Fig. 8, the inverter 910 is configured to invert a regular scan enable signal 930. Unlike the control signal generation device 800 in Fig. 8, however, the output of the inverter 910 is not the output of the control signal generation device 900. Rather, the AND gate 980 is configured to combine the output of the inverter 910 with the diagnosis mode signal 940 to generate the inversion-control signal 950. When the regular scan enable signal 930 is asserted and the diagnosis mode signal 940 is deasserted, the modified scan enable signal 960 is asserted and the inversion-control signal 950 is deasserted, activating the normal shift mode for the scan cell. When both the regular scan enable signal 930 and the diagnosis mode signal 940 are deasserted, the modified scan enable signal 960 is deasserted, activating the normal capture mode for the scan cell. When both the regular scan enable signal 930 and the diagnosis mode signal 940 are asserted, the modified scan enable signal 960 is asserted and the inversion-control signal 950 is deasserted, activating the diagnosis shift mode for the scan cell. It should be noted that the diagnosis shift mode is essentially the same as the normal shift mode. When the regular scan enable signal 930 is deasserted and the diagnosis mode signal 940 is asserted, both the modified scan enable signal 960 and the inversion-control signal 950 are asserted, activating the diagnosis capture mode for the scan cell. In the diagnosis capture mode, the scan cell is to capture the inverted version (“1 - v”) of a bit (“v”) received at the data input of the controllable inverting device. A table 970 in Fig. 9 summarizes the above-described four test-related modes in which a scan cell can operate based on the regular scan enable signal 930 and the diagnosis mode signal 940.

[0064]

[0066] A comparison of the table 970 in Fig. 9 with the table 870 in Fig. 8 shows one difference between them. In the normal capture mode: the inversion-control signal is deasserted in the table 970 but asserted in the table 870. The assertion of the inversion-control signal in the normal capture mode may not matter in many cases since the inversion happens on the shift path of the scan cell and should not affect the capture operation. In some situations, however, the inserted controllable inverting devices may impact the circuit behavior in capture cycles. As noted previously, a scan cell may serve as a part or a whole of a shift register. When the controllable inverting device is placed on the shift path and in front of the scan cell to improve diagnosis coverage, such a scan cell can capture the inversion rather than the original version of the bit that it is supposed to capture in the normal capture mode. The same problem may also exist when the controllable inverting device is inserted into a common section of the shift path and the capture path of a scan cell. This placement may occur when the multiplexer for mode controlling is not inside the scan cell or when there no clear separation between shift path and capture path. The unwanted inversion during the normal capture mode can be avoided using the control signal generation device 900 in Fig. 9. The inversion-control signal 950 is produced by a logical AND operation (performed by the AND gate 980) of the inversion of the regular scan enable signal 930 and the diagnosis mode signal 940. The deassertion of the diagnosis mode signal 940 during the normal capture mode ensures that the inversioncontrol signal 950 is also deasserted and no inversion can occur.

[0065]

[0067] Fig. 10 illustrates an example of diagnosis point insertion for a scan chain 1000 that may be implemented according to various embodiments of the disclosed technology. Stuck- at faults associated with scan cells 1010, 1011 and 1012 are in an equivalent fault group, and stuck-at faults associated with scan cells 1013 and 1015 are in another equivalent fault group. Controllable inverting devices 1020 and 1030 are inserted in front of the scan cells 1010 and 1011, respectively, to make the stuck-at faults associated with the scan cells 1010, 1011 and 1012 unique. A controllable inverting device 1040 is inserted in front of the scan cell 1013 to make the stuck-at faults associated with the scan cells 1013 and 1015 unique. The three controllable inverting devices 1020, 1030 and 1040 are controlled by an inversion-control signal 1070, scan enable inputs of the three corresponding diagnosable scan cells 1010, 1011 and 1013 are coupled to a modified scan enable signal 1050, and scan enable inputs of the rest of scan cells are coupled to a regular scan enable signal 1060. The modified scan enable signal 1050 and the inversioncontrol signal 1070 can be generated locally based on the regular scan enable signal 1060 and a diagnosis mode signal 1080. As will be discussed below, the diagnosis mode signal 1080 can be a static signal provided by a scan cell such as the first one counted from the input of the scan chain 1000. This kind of setup can reduce area overhead and makes the diagnosis-related mode control flexible.

[0066]

[0068] Fig. 11 illustrates another example of diagnosis point insertion for a scan chain 1100 that may be implemented according to various embodiments of the disclosed technology. Stuck-at faults associated with scan cells 1110, 1111 and 1112 are in an equivalent fault group, and stuck-at faults associated with scan cells 1113 and 1115 are in another equivalent fault group. Controllable inverting devices 1120 and 1130 are inserted in front of the scan cells 1110 and 1111, respectively, to make the stuck-at faults associated with the scan cells 1110, 1111 and 1112 unique. A controllable inverting device 1140 is inserted in front of the scan cell 1113 to make the stuck-at faults associated with the scan cells 1113 and 1115 unique. The diagnosis point insertion in Fig. 11 is similar to the one shown in Fig. 10. Also similar is the controlling of the three controllable inverting devices 1120, 1130 and 1140 by an inversion-control signal 1170. A difference between Fig. 11 and Fig. 10 is that scan enable inputs of the scan cells in the scan chain 1100 are all coupled to a modified scan enable signal 1150 whereas only the diagnosable scan cells 1010, 1011, and 1013 in the scan chain 1000 are controlled by the modified scan enable signal 1060. This arrangement is beneficial to scan cells that do not have clear separation between shift path and capture path and it is challenging to locate scan enable inputs for diagnosable scan cells.

[0067]

[0069] Scan cells being selected for controllable inverting device insertion (diagnosis point insertion) can be determined based on a diagnosis coverage analysis process. The diagnosis coverage analysis process may comprise design rule checking, diagnosability analysis, test pattern generation for diagnosis, or any combination thereof. In some cases, however, some scan cells determined to impact diagnosis coverage using the above methods can become diagnosable based on adaptive diagnosis clock control alone without diagnosis point insertion. In some other cases, some scan cells determined to impact diagnosis coverage using the above methods may still not be distinguishable after diagnosis point insertion unless adaptive diagnosis clock control is also employed. A combination of adaptive diagnosis clock control with diagnosis point insertion can not only increase diagnosis coverage but also reduce silicon area overhead by reducing the number of diagnosis points needed. According to various embodiments of the disclosed technology, two storage devices are used together, one for providing the diagnosis clock control signal and the other for providing the diagnosis mode signal. If the two storage devices are scan cells or shadow registers of two scan cells, the two signals can be loaded using test patterns. They can be active simultaneously or separately. Test data registers in an IJTAG network (IEEE P1687 Internal JTAG) may also be used for one or both of the diagnosis clock control signal and the diagnosis mode signal.

[0068] Conclusion

[0069]

[0070] Having illustrated and described the principles of the disclosed technology, it will be apparent to those skilled in the art that the disclosed embodiments can be modified in arrangement and detail without departing from such principles. In view of the many possible embodiments to which the principles of the disclosed technologies can be applied, it should be recognized that the illustrated embodiments are only preferred examples of the technologies and should not be taken as limiting the scope of the disclosed technology. Rather, the scope of the disclosed technology is defined by the following claims and their equivalents. We therefore claim as our disclosed technology all that comes within the scope and spirit of these claims.

Claims

What is claimed is:

1. A circuit, comprising:scan chains, the scan chains comprising a plurality of scan cells,wherein the plurality of scan cells are configured to operate in one of a plurality of test-related modes based on a scan enable signal for the plurality of scan cells and a diagnosis clock control signal provided by a storage device while the circuit is being tested, the plurality of test-related modes comprises a clock-inactive capture mode and a clock-active capture mode, wherein in the clock-inactive capture mode, the scan enable signal is inactive, the diagnosis clock control signal is inactive, and the plurality of scan cells receive no clock signals, and wherein in the clock-active capture mode, the scan enable signal is inactive, the diagnosis clock control signal is active, and the plurality of scan cells receive a clock signal.

2. The circuit recited in claim 1, wherein the storage device is a scan cell in the scan chains or a shadow register of a scan cell in the scan chains.

3. The circuit recited in claim 1, wherein the plurality of scan cells are identified based on design rule checking, diagnosability analysis, test pattern generation for diagnosis, or any combination thereof.

4. The circuit recited in claim 1, wherein the clock signal is a scan clock signal.

5. The circuit recited in claim 1, further comprising:a controllable inverting device placed on a shift path of one of the scan chains and between a serial output of a scan cell (K + 1) and a serial input of a scan cell K, numbers (K+ 1) and K being scan cell indices,wherein the controllable inverting device is configured to output an inverted version or an original version of a bit received at a data input of the controllable inverting device based on an inversion-control signal, andwherein the scan cell K is configured to operate in a diagnosis capture mode based on a modified scan enable signal and the inversion-control signal.

6. The circuit recited in claim 5, wherein the modified scan enable signal is derived by a logical OR operation of a diagnosis mode signal and the scan enable signal, and the inversioncontrol signal is derived by inverting the scan enable signal, the diagnosis mode signal being provided by another storage device.

7. The circuit recited in claim 5, wherein the modified scan enable signal is derived by a logical OR operation of a diagnosis mode signal and the scan enable signal, and the inversioncontrol signal is derived by a logical AND operation of the diagnosis mode signal and a signal derived by inverting the scan enable signal, the diagnosis mode signal being provided by another storage device.

8. The circuit recited in claim 5, wherein the scan cell K is identified based on design rule checking, diagnosability analysis, test pattern generation for diagnosis, or any combination thereof.

9. The circuit recited in claim 5, wherein the scan cells (K+1) and K are in the plurality of scan cells.

10. The circuit recited in claim 5, wherein the controllable inverting device is an XOR gate.

Images