Target deconstruction using graph analysis

Abstract

A method includes collecting one or more index database files for a first target including a first file and a second file; creating a mapping graph of declarations and references for the first file and the second file, at least in part based on the one or more index database files; creating a representation of a directed graph of the first target, at least in part based on the mapping graph, the representation including a first node of the first file and a second node of the second file; and performing a graph analysis on the representation of the directed graph to determine a degree level of the first node and a degree level of the second node, the second node having a higher degree level than the first node.

Description

Target Deconstruction Using Graph AnalysisBACKGROUNDTECHNICAL FIELD

[0001] This disclosure relates to transformation of program code in software engineering and, in particular, to deconstruction of a software target using graph analysis.RELATED ART

[0002] Computer development projects often have an overly large target, such as an application program.

[0003] Application programs can be built in alternative styles, such as multitier architectures, distributed computing, microservices, or as a monolith. A monolith is a single, unified, self-contained software application. A monolith can include several hundreds, if not thousands, of files. These files generally depend on and / or are depended upon by other files in the monolith.

[0004] When a target in a software development project, such as an application program, is unnecessarily large, problems can arise. For example, a large target can take an undesirably long time to compile from its source files. In addition, storage of the target can unnecessarily consume memory resources, and communication of such a target can unnecessarily consume network resources. Further, if the target is executed, the size of the target can also unnecessarily consume processing resources.

[0005] Such a large target sometimes arises in the critical path of a build. Accordingly, meaningful build time improvements cannot be made until the target is reduced in size.

[0006] However, the target might include some of the least-tested code and / or contain critical features. The reason for this situation is that usage of a particular source file might all but eliminate the possibility for meaningful coverage. For example, components can use real objects to do everything, and entire test suites can be based on the behaviors of code that is not the subject of the test.

[0007] Monoliths can also challenge the culture of software teams since behaviors allowed in the target are not allowed in other components of the software. Contributors can be constantly drawn to these monoliths since the oversight over the target is much lower than better isolated components in the code. Simply the existence of the monolith provides a constant challenge to build engineering teams and must be resolved to improve the build velocity and quality for all components in the application.’

[0008] These issues are common in software engineering and are widely faced by all software development teams.BRIEF SUMMARY

[0009] In a first implementation, a method includes collecting one or more index database files for a first target including a first source file and a second source file; creating a mapping graph of declarations and references for the first source file and the second source file, at least in part based on the one or more index database files; creating a representation of a directed graph of the first target, at least in part based on the mapping graph, the representation including a first node of the first source file and a second node of the second source file; and performing a graph analysis on the representation of the directed graph to determine a degree level of the first node and a degree level of the second node, the second node having a higher degree level than the first node.

[0010] In a second implementation, a system includes at least one memory that stores at least one instruction; and at least one processor configured, with the at least one memory, to cause the system to at least collect one or more index database files for a first target including a first source file and a second source file, create a mapping graph of declarations and references for the first source file and the second source file, at least in part based on the one or more index database files, create a representation of a directed graph of the first target, at least in part based on the mapping graph, the representation including a first node of the first source file and a second node of the second source file, and perform a graph analysis on the representation of the directed graph to determine adegree level of the first node and a degree level of the second node, the second node having a higher degree level than the first node.[oon] In a third implementation, a computer-readable medium is encoded with a computer program that, when executed by a system including at least one processor, causes the system to perform operations. The operations include collecting one or more index database files for a first target including a first source file and a second source file; creating a mapping graph of declarations and references for the first source file and the second source file, at least in part based on the one or more index database files; creating a representation of a directed graph of the first target, at least in part based on the mapping graph, the representation including a first node of the first source file and a second node of the second source file; and performing a graph analysis on the representation of the directed graph to determine a degree level of the first node and a degree level of the second node, the second node having a higher degree level than the first node.BRIEF DESCRIPTION OF DRAWINGS

[0012] Fig. 1 illustrates a visualization of a monolith, according to an implementation of the present disclosure.

[0013] Fig. 2 illustrates a visualization in a second phase of a decomposition of a monolith, according to an implementation of the present disclosure.

[0014] Fig. 3 illustrates a visualization in a first phase of a decomposition of a monolith, according to an implementation of the present disclosure.

[0015] Fig. 4 illustrates an algorithm for deconstruction of a target using graph analysis, according to an implementation of the present disclosure.

[0016] Fig. 5 illustrates data regarding source files in various decomposition phases, according to an implementation of the present disclosure.

[0017] Fig. 6 illustrates build time improvements at the beginning of each of a plurality of decomposition phases, according to an implementation of the present disclosure.

[0018] Fig. 7 illustrates build time reduction percentage reductions at the beginning of each of a plurality of decomposition phases, according to an implementation of the present disclosure.

[0019] Fig. 8 illustrates a computing device, according to an implementation of the present disclosure.DETAILED DESCRIPTION

[0020] Various implementations of the present disclosure can implement a system and method for target deconstruction using graph analysis, as described herein.

[0021] In particular, select implementations of the present disclosure can solve the issue of having an overly large target in a software project. For example, some implementations can visualize a target by its source files and can determine a course of action for reducing the size of the target.

[0022] Select implementations of the present disclosure also provide the ability to create visualizations that allow a developer to view, at a file level, a network of file dependencies of the target. This visualization can provide for observation of potential optimizations of the target.

[0023] Fig. 1 illustrates a visualization of a monolith, according to an implementation of the present disclosure. In the visualization, each circle represents a file in the monolith, and each line extends between two files to represent a dependency between the two files.

[0024] In the visualization of Fig. 1, there are four files without any dependencies on nor from other files. These four “orphan” files are defined as having degree zero. Other than these four files, the files all depend on and / or are depended upon by at least one other file in the monolith. The respective degree of each of these other files is dictated by the number of files on which that file depends and the number of files that depend on that file. It is estimated that the visualization in Fig. 1 is of the ninth degree.

[0025] As represented by the complexity of the visualization, it is essentially impossible for a human without the visualization to simplify the monolith by arbitrarily selecting a file and trying to reduce its dependencies on other files and other files’dependencies on that file. Indeed, such an effort might require hours of labor, only to determine that it is impossible to remove the file from the monolith. Given that there are hundreds of files, the odds of selecting a file that can successfully be removed are perhaps 10% and much lower than that for an arbitrary selection without the aid of a visualization.

[0026] A more understandable representation is shown in Fig. 2. Fig. 2 illustrates a visualization in a second phase of a decomposition of a monolith, according to an implementation of the present disclosure. In Fig. 2, the circles represent files or groups of files in the monolith that depend on or are depended upon by only one other file. By advantageously identifying these files, the files can be selected for removal with a 100% rate of success.

[0027] More to the point, Fig. 3 illustrates a visualization in a first phase of a decomposition of a monolith, according to an implementation of the present disclosure. The circles represent files in the monolith that depend on or are depended upon by only one other file. Because these files depend on or are depended upon by only one other file, they were illustrated in Fig. 1 as a leaf of the visualization. After removing the “orphan files,” the leaves of the monolith are identified for removal.

[0028] As shown in Fig. 3, the structures having multiple nodes are still degree 0. None of these files depend on one another, and this entire set can be removed in a single step.

[0029] Because the dependencies associated with these files are straightforward, it is relatively easy to remove these files from the monolith. For example, these “leaf’ files can simply be included in the one file upon which they depend or that is dependent on the “leaf’ file. Thus, in the first phase of the decomposition, the leaves of the monolith are targeted.

[0030] The analysis would then revert to Fig. 2, which was illustrated prior to Fig. 3 for the purpose of illustrating aspects of the monolith at a reasonable level of complexity.

[0031] Fig. 4 illustrates an algorithm for deconstruction of a target using graph analysis, according to an implementation of the present disclosure.

[0032] The algorithm 400 begins at 410 and advances to 420.

[0033] In 420, a processor of the computer executes a build system to build the target from source files. The build system can be, for example, Bazel® or Blaze by Google® LLC. In some implementations, the build system can be Ant™ or Maven™ by the Apache® Software Foundation or the Make tool.

[0034] Building a target generally includes compiling the source files into executable code or source code in a different language. In addition, building a target can include cleaning previous packages, pre-processing the source files, compiling test sources, linking object code, converting data files, running automated tests, and / or packaging.

[0035] Thus, the collecting can be performed by executing a compiler on a target including a plurality of files. The plurality can include a first source file and a second source file, for example.

[0036] The plurality of source files can be written in any programming language, such as Swift or Python. Thus, the compiler can be a Swift compiler, for example. The compiler can then output (e.g., emit) one or more index database files during builds, such as a first index database file corresponding to the first source file and a second index database file corresponding to the second source file. In various implementations, these index database files can be in a file format called an IndexStore. An IndexStore is a database of the compiled code that shows declarations and references from one file to another file. An IndexStore can contain a full ledger of all symbols defined in the source code.

[0037] In several implementations, after Bazel builds the target, the computer collects the IndexStore files. Thus, the computer can determine how symbols are related to one another in a source graph. This determination can create entries called a unified symbol resolution (USR), and they allow an indexer to search these entries like a database. The computer can also understand how many references a source file has to types in the monolith.

[0038] The algorithm 400 then advances to 430.

[0039] In 430, the computer can create a mapping graph of all declarations and references for each source file in the target, at least in part based on the IndexStorefiles. For example, the computer can create a map for each source file to all types it consumes and which targets contain those types.

[0040] The mapping graph can be made for the first file and the second file, at least in part based on the first index database file and the second index database file. Thus, various implementations can create a representation of the defined and referenced symbols for every file in the target.

[0041] The algorithm 400 then advances to 440.

[0042] In 440, the computer creates a directed graph representation of every file in the target, at least in part based on the mapping graph. For example, the directed graph contains data for all files for the target. The representation includes a first node of the first file and a second node of the second file.

[0043] During this phase, set theory can be used on every file in the graph to develop a directed graph. For example, set theory can be used to determine the intersection of references for every file in the target. In many implementations, the directed graph is weighted.

[0044] In select implementations, the computer can optionally perform a display of the directed graph of the target. The directed graph can be or include visualizations, such as shown in Figs. 1-3.

[0045] In many such implementations, the display of the directed graph includes the first node and the second node. However, because this operation is optional, it is not necessary for the display of the directed graph to include the first node nor the second node.

[0046] The algorithm 400 then advances to 450.

[0047] In 450, the computer performs a graph analysis on the representation of the directed graph to determine a degree level of the first node and a degree level of the second node. For example, the computer can run a NetworkX graph analysis tooling to create visualizations and / or strategies for how to deconstruct the target in a series of discrete phases. For example, NetworkX can perform graph analysis work and create output formats that visualization tools can determine and process.

[0048] During the graph analysis, the computer can determine the degree levels of files (nodes). For example, the computer can determine that the first node has a predetermined degree level, such as one or two. The computer additionally or alternatively can determine the relative degree levels of files (nodes), such as that a second node has a higher degree level than a first node.

[0049] The algorithm 400 then advances to 460.

[0050] In 460, the computer can modify a source file in the target or delete a source file from the target, at least in part based on the directed graph representation. In various implementations, this modification or deletion occurs, at least in part, based on a human interaction with the computer. For example, a human can instruct the computer to delete a first source file from the target or merge a first source file in the target into another source file in the target.

[0051] Thus, in some implementations, the first source file can be moved into a second target. In many implementations, the second target is the most adjacent target of the first source file. That is, the second target is the target that contains the greatest number of external references and / or declarations from the first source file. Thus, the second target can include a third source file that includes a reference and / or a declaration to the first source file. The computer can determine the number of external references and / or declarations from a single directed graph of a plurality of targets. The second target can be determined, at least in part based on such a single directed graph. Thus, the first target typically does not include the third source file, as the references and / or declarations of the third source file for the first source file would moot the move of the first source file to the second target.

[0052] In this situation, if the target is re-built without modifying a source file that depends on the first file, then the target will not compile, as long as the first file was not an orphan (e.g., if the degree level of the first node is zero). Thus, if the second file contains any declarations and / or references to the first file, then any declarations and / or references of the second file to the first file are modified in 460.

[0053] The algorithm 400 then advances to 470.

[0054] In 470, the computer re-builds the target from its source files.

[0055] If the hrst source file is deleted from the target or merged into another source file in 460, then the target is re-built without the first source file.

[0056] If the degree level of the first node is at least one, then a declaration and / or a reference of a second file is modified in 460. Thus, in some implementations, the target is built, at least in part based on a modified version of the second file.

[0057] As discussed previously, in some implementations, the first source file is moved into a second target. If the first source file is moved into the second target, the computer can build the second target, at least in part based on the first source file and the third source file.

[0058] The algorithm 400 then advances to 480 and concludes.

[0059] Fig. 5 illustrates data regarding source files in various decomposition phases, according to an implementation of the present disclosure. This data can be output from the graph analysis tooling. The first four rows of Fig. 5 identify source files to be deleted or merged in the first phase of the decomposition. The next three rows of Fig. 5 identify source files to be deleted or merged in the second phase of the decomposition. The final two rows of Fig. 5 identify source files to be deleted or merged in the third phase of the decomposition.

[0060] As shown in Fig. 5, the source files in the target can be arranged in different folders and can be arranged in different folder depths. Further, the source files can have unrelated names. Additionally, the source files can have significantly different numbers of lines (line counts) in the source files and, as such, can contribute various percentages of the total number of lines of the target. That is, it would be substantially impossible for a human to guess which source files can be merged or deleted at which stage of the decomposition, based on considerations like name, folder name, folder depth, line count, or percentage of lines of the target.

[0061] Fig. 6 illustrates build time improvements at the beginning of each of a plurality of decomposition phases, according to an implementation of the present disclosure. As illustrated in Fig. 6, before decomposition (e.g., at the beginning of phase 0), the build time was 160 seconds. At the beginning of phase 1 (e.g., after completion of phase 0), the build time was 149 seconds for an improvement of about 6.9%. At thebeginning of phase 2 (e.g., after completion of phase 1), the build time was 128 seconds for an additional improvement of about 14%. At the beginning of phase 3 (e.g., after completion of phase 2), the build time was 79 seconds for a further improvement of about 38%. At the beginning of phase 4 (e.g., after completion of phase 3), the build time was 59 seconds for a further improvement of about 25%. Thus, from the beginning of phase 0 to the beginning of phase 4, the build time improved by 101 seconds.

[0062] Fig. 7 illustrates build time reduction percentage reductions at the beginning of each of the plurality of decomposition phases, according to an implementation of the present disclosure. As illustrated in Fig. 7, before decomposition (e.g., at the beginning of phase 0), the baseline improvement was 0%. At the beginning of phase 1 (e.g., after completion of phase 0), the reduction in the build time was 6.88%, as discussed above. At the beginning of phase 2 (e.g., after completion of phase 1), the total reduction in the build time was 20%. At the beginning of phase 3 (e.g., after completion of phase 2), the total reduction in build time was 50.63%. At the beginning of phase 4 (e.g., after completion of phase 3), the total reduction in build time was 63.13%.

[0063] A particular implementation of the present disclosure reduced the size of the largest target in a repository by 75% in a few months. No other effort reduced the size of this target in such a fast, safe and repeatable manner.

[0064] Select implementations of the present disclosure can achieve a variety of advantages. For example, by determining and performing target deconstruction using graph analysis as disclosed herein, the problem of identifying which files to delete and merge becomes solvable, and targets remain re-buildable. Further, this re-building can be performed in a lower number of edits, and a lower number of builds can be invoked in doing so. Further, build errors can be prevented from looping on themselves.

[0065] The teachings of the present disclosure can be implemented with various programming languages, build tools, and graphing software. One implementation of the present disclosure uses the Swift and Python programming languages, the Bazel software build tool, and the NetworkX library for graphs.[oo66] Fig. 8 illustrates a computing device 800, according to an implementation of the present disclosure. The computer that implements the algorithm 400 can be implemented with the computing device 800.

[0067] The computing device 800 can include a network interface 810, a user input interface 820, a memory 830, a program 835, a processor 840, a user output interface 850, and a bus 855.

[0068] Although illustrated within a single housing, the computing device 800 can be distributed across plural housings or sub-systems that cooperate in executing program instructions. In some implementations, the computing device 800 can include one or more blade server devices, standalone server devices, personal computers (including laptop computers and tablet computers), routers, hubs, switches, bridges, firewall devices, intrusion detection devices, mainframe computers, network-attached storage devices, smartphones and other mobile telephones, and other computing devices. Although the computing device executes the Windows OS, macOS, or Linux in many implementations, the hardware can be configured according to a Symmetric Multiprocessing (SMP) architecture or a Non-Uniform Memory Access (NUMA) architecture.

[0069] The network interface 810 provides one or more communication connections and / or one or more devices that allow for communication between the computing device 800 and other computing systems (not shown) over a communication network, collection of networks (not shown), or the air, to support the target deconstruction using graph analysis, outlined herein. The network interface 810 can communicate using various networks (including both internal and external networks) such as near-field communications (NFC), Wi-Fi™, Bluetooth, Ethernet, cellular (e.g., 3G, 4G, 5G), white space, 802.11X, satellite, LTE, GSM / HSPA, CDMA / EVDO, DSRC, CAN, GPS, facsimile, or any other wired or wireless interface. Other interfaces can include physical ports (e.g., Ethernet, USB, HDMI, etc.), interfaces for wired and wireless internal subsystems, and the like. Similarly, nodes and user equipment (e.g., mobile devices) of a computing system that includes the computing device 800 can also include suitable interfaces for receiving, transmitting, and / or otherwise communicating data or information in a network environment.

[0070] The user input interface 820 can receive one or more inputs from a human. The user input interface 820 can be or include a mouse, a touchpad, a keyboard, a touchscreen, a trackball, a camera, a microphone, a joystick, a game controller, a scanner, and / or any other input device.

[0071] The memory 830, also termed a “storage,” can include or be one or more computer-readable storage media readable by the processor 840 and that store software. The memory 830 can be implemented as one storage device or across multiple co-located or distributed storage devices or sub-systems. The memory 830 can include additional elements, such as a controller, that communicate with the processor 840. The memory 830 can also include storage devices and / or sub-systems on which data and / or instructions are stored. The computing device 800 can access one or more storage resources to access information to carry out any of the processes indicated in this disclosure and, in particular, Fig. 4. In various implementations, the memory 830 stores the program 835 to execute at least a portion of the algorithm illustrated in Fig. 4. Further, the program 835, when executed by the computing device 800 generally and / or the processor 840 specifically, can direct, among other functions, performance of the target deconstruction using graph analysis, as described herein.

[0072] The memory 830 can be or include a read-only memory (ROM), a programmable ROM (PROM), an erasable PROM (EPROM), an electrically erasable PROM (EEPROM), a random-access memory (RAM), a dynamic RAM (DRAM), a static RAM (SRAM), a field programmable gate array (FPGA), a hard drive, a cache memory, a flash memory, a removable disk, or a tape reel. The memory 830 can be or include resistive RAM (RRAM) or a magneto-resistive RAM (MRAM). The information being tracked, sent, received, or stored in the computing device can be provided in any database, register, table, cache, queue, control list, or storage structure, based on particular implementations, all of which could be referenced in any suitable timeframe.

[0073] The processor 840 (e.g., a processing unit) can be or include one or more hardware processors and / or other circuitry that retrieve and execute software, especially the program 835, from the memory 830. The processor 840 can be implemented within one processing device, chip, or package and can also be distributedacross multiple processing devices, chips, packages, or sub-systems that cooperate. In some implementations, the processor 840 is or includes a Graphics Processing Unit (GPU) or neural processing unit (NPU).

[0074] The processor 840 can have any register size, such as a 32-bit register or a 64-bit register, among others. The processor 840 can include multiple cores. Implementations of the processor 840 are not limited to any particular number of threads. The processor 840 can be fabricated by any process technology, such as i4nm process technology.

[0075] The user output interface 850 outputs information to a human user. The user output interface 850 can be or include a display (e.g., a screen), a touchscreen, speakers, a printer, or a haptic feedback unit. In many implementations, the user output interface 850 can be combined with the user input interface 820. For example, some such implementations include a touchscreen, a headset including headphones and a microphone, or a joystick with haptic feedback.

[0076] In implementations including multiple computing devices, a server of a system or, in a serverless implementation, a peer can use one or more communications networks that facilitate communication among the computing devices to achieve the target deconstruction using graph analysis, as outlined herein. For example, the one or more communications networks can include or be a local area network (LAN) or wide area network (WAN) that facilitate communication among the computing devices. One or more direct communication links can be included between the computing devices. In addition, in some cases, the computing devices can be installed at geographically distributed locations. In other cases, the multiple computing devices can be installed at one geographic location, such as a server farm or an office.

[0077] As used herein, the terms “storage media” or “computer-readable storage media” can refer to non-transitory storage media, such as non-limiting examples of a hard drive, a memory chip, an ASIC, and cache memory, and to transitory storage media, such as carrier waves or propagating signals.

[0078] Aspects of the system can be implemented in various manners, e.g., as a method, a system, a computer program product, or one or more computer-readablestorage media. Accordingly, aspects of the present disclosure can take the form of a hardware implementation, a software implementation (including firmware, resident software, or micro-code) or an implementation combining software and hardware aspects that can generally be referred to herein as a “module” or a “system.” Functions described in this disclosure can be implemented as an algorithm executed by one or more hardware processing units, e.g., the processor 840. In various embodiments, different operations and portions of the operations of the algorithms described can be performed by different processing units. In some implementations, the operations can be achieved by reciprocating software in one or more computing devices, as shown in Fig. 8. The program 835 can be implemented using reciprocating software. Furthermore, aspects of the present disclosure can take the form of a computer program product embodied in one or more computer-readable media having computer-readable program code embodied, e.g., encoded or stored, thereon. In various implementations, such a computer program can, for example, be downloaded (or updated) to existing devices and systems or be stored upon manufacture of these devices and systems.

[0079] Any suitable permutation can be applied to a physical implementation, including the design of the communications network in which the system is implemented. In one embodiment, the bus 855 can share hardware resources with the memory 830 and the processor 840. In this alternative implementation, the computing device 800 can be provided with separate hardware resources including one or more processors and memory elements.

[0080] In example implementations, various other components of the computing device 800 can be installed in different physical areas or can be installed as single units.

[0081] The computing device 800 can be configured to facilitate communication with machine devices (e.g., vehicle sensors, instruments, electronic control units (ECUs), embedded devices, actuators, displays, etc.) through the bus 855. Other suitable communication interfaces can also be provided for an Internet Protocol (IP) network, a user datagram protocol (UDP) network, or any other suitable protocol or communication architecture enabling network communication with machine devices.

[0082] The innovations in this detailed description can be implemented in a multitude of different ways, for example, as defined and covered by the claims and / or select examples. In the description, reference is made to the drawings where like reference numerals can indicate identical or functionally similar elements. Elements illustrated in the drawings are not necessarily drawn to scale. Additionally, certain implementations can include more elements than illustrated in a drawing and / or a subset of the elements illustrated in a drawing. Further, some implementations can incorporate a suitable combination of features from two or more drawings.

[0083] The disclosure describes various illustrative implementations and examples for implementing the features and functionality of the present disclosure. The components, arrangements, and / or features are described in connection with various implementations and are merely examples to simplify the present disclosure and are not intended to be limiting. In the development of actual implementations, implementationspecific decisions can be made to achieve specific goals, including compliance with system, business, and / or legal constraints, which can vary from one implementation to another. Additionally, while such a development effort might be complex and timeconsuming, it would be a routine undertaking for those of ordinary skill in the art having the benefit of this disclosure.

[0084] The systems, methods and devices of this disclosure have several innovative aspects, no one of which is solely responsible for the attributes disclosed herein. Some objects or advantages might not be achieved by implementations described herein. Thus, for example, certain implementations can operate in a manner that achieves or optimizes one advantage or group of advantages as taught herein and not other objects or advantages as taught or suggested herein.

[0085] In one example implementation, electrical circuits of the drawings can be implemented on a board of an associated electronic device. The board can be a general circuit board that can hold various components of the internal electronic system of the electronic device and, further, provide connectors for other peripherals. More specifically, the board can provide the electrical connections by which other components of the system can communicate electrically. Any processors (inclusive of digital signalprocessors, microprocessors, supporting chipsets, etc.) and computer-readable, non- transitory memory elements can be coupled to the board based on configurations, processing demands, and computer designs. Other components such as external storage, additional sensors, controllers for audio / video display, and peripheral devices can be attached to the board as plug-in cards, via cables, or integrated into the board itself. In various implementations, the functionalities described herein can be implemented in emulation form as software or firmware running within one or more configurable (e.g., programmable) elements arranged in a structure that supports these functions. A non- transitory, computer-readable storage medium can include instructions to allow one or more processors to carry out the emulation.

[0086] In another example implementation, the electrical circuits of the drawings can be implemented as stand-alone modules (e.g., a device with associated components and circuitry configured to perform a specific application or function) or implemented as plug-in modules into application specific hardware of electronic devices. Implementations of the present disclosure can be readily included in a system-on-chip (SOC) package. An SOC represents an integrated circuit (IC) that integrates components of a computer or other electronic system into one chip. The SOC can contain digital, analog, mixed-signal, and often radio frequency functions on one chip substrate. Other implementations can include a multi-chip-module (MCM), with a plurality of separate ICs located within one electronic package and that interact through the electronic package. In various other implementations, the processors can be implemented in one or more silicon cores in Application Specific Integrated Circuits (ASICs), Field Programmable Gate Arrays (FPGAs), programmable array logic (PAL), generic array logic (GAL), and other semiconductor chips.

[0087] The specifications, dimensions, and relationships outlined herein (e.g., the number of processors and logic operations) have been offered for non-limiting purposes of example and teaching. For example, various modifications and changes can be made to the arrangements of components. The description and drawings are, accordingly, to be regarded in an illustrative sense, not in a restrictive sense.[oo88] The numerous examples provided herein described interaction in terms of two, three, or more electrical components for purposes of clarity and example. The computing device or a system including the computing device can be consolidated in any manner. Along similar design alternatives, the illustrated components, modules, and elements of the drawings can be combined in various possible configurations within the scope of this disclosure. In certain cases, one or more of the functionalities of a given set of flows might be more clearly described by referencing a limited number of electrical elements. The electrical circuits of the drawings are readily scalable and can accommodate many components, as well as more complicated / sophisticated arrangements and configurations. Accordingly, the provided examples do not limit the scope or inhibit the teachings of the electrical circuits as potentially applied to a myriad of other architectures.

[0089] In this disclosure, references to various features (e.g., elements, structures, modules, components, steps, operations, characteristics, etc.) included in “one implementation,” “example implementation,” “an implementation,” “another implementation,” “some implementations,” “various implementations,” “other implementations,” “alternative implementation,” and the like are intended to mean that any such features can be included in one or more implementations of the present disclosure and might or might not necessarily be combined in the same implementations. Some operations can be deleted or omitted where appropriate, or these operations can be modified or changed considerably. In addition, the timing of these operations can be altered considerably. The preceding operational flows have been offered for purposes of example and discussion. Implementations described herein provide flexibility in that any suitable arrangements, chronologies, configurations, and timing mechanisms can be provided.Examples

[0090] In Example Ml, a method includes collecting one or more index database files for a first target including a first source file and a second source file; creating a mapping graph of declarations and references for the first source file and the secondsource file, at least in part based on the one or more index database files; creating a representation of a directed graph of the first target, at least in part based on the mapping graph, the representation including a first node of the first source file and a second node of the second source file; and performing a graph analysis on the representation of the directed graph to determine a degree level of the first node and a degree level of the second node, the second node having a higher degree level than the first node.

[0091] Example M2 is the method of Example Ml, further comprising: building the first target without the first source file, wherein the degree level of the first node is zero.

[0092] Example M3 is the method of any of Examples M1-M2, further comprising: building the first target without the first source file, at least in part based on a modified version of the second source file, wherein the degree level of the first node is at least one.

[0093] Example M4 is the method of any of Examples M1-M3, further comprising: building a second target, at least in part based on the first source file and a third source file, wherein the first target does not include the third source file.

[0094] Example M5 is the method of any of Examples M1-M4, further comprising: performing a display of the directed graph of the first target, wherein the display includes the first node and the second node.

[0095] Example M6 is the method of any of Examples M1-M5, wherein the collecting is performed by executing a compiler on at least the first source file and the second source file to output the one or more index database files.

[0096] Example M7 is the method of any of Examples M1-M6, wherein the one or more index database files are IndexStore files.

[0097] In Example Si, a system includes at least one memory that stores at least one instruction; and at least one processor configured, with the at least one memory, to cause the system to at least collect one or more index database files for a first target including a first source file and a second source file, create a mapping graph of declarations and references for the first source file and the second source file, at least in part based on the one or more index database files, create a representation of a directedgraph of the first target, at least in part based on the mapping graph, the representation including a first node of the first source file and a second node of the second source file, and perform a graph analysis on the representation of the directed graph to determine a degree level of the first node and a degree level of the second node, the second node having a higher degree level than the first node.

[0098] Example S2 is the system of Example Si, wherein the at least one processor is further configured, with the at least one memory, to cause the system to at least build the first target without the first source file, and the degree level of the first node is zero.

[0099] Example S3 is the system of any of Examples S1-S2, wherein the at least one processor is further configured, with the at least one memory, to cause the system to at least build the first target without the first source file, at least in part based on a modified version of the second source file, and the degree level of the first node is at least one.

[0100] Example S4 is the system of any of Examples S1-S3, wherein the at least one processor is further configured, with the at least one memory, to cause the system to at least build a second target, at least in part based on the first source file and a third source file, and the first target does not include the third source file.

[0101] Example S5 is the system of any of Examples S1-S4, wherein the at least one processor is further configured, with the at least one memory, to cause the system to at least perform a display of the directed graph of the first target, and the display includes the first node and the second node.

[0102] Example S6 is the system of any of Examples S1-S5, wherein the collecting is performed by executing a compiler on at least the first source file and the second source file to output the one or more index database files.

[0103] Example S7 is the system of any of Examples S1-S6, wherein the one or more index database files are IndexStore files.

[0104] In Example Ci, a computer-readable medium is encoded with a computer program that, when executed by a system including at least one processor, causes the system to perform operations. The operations include collecting one or moreindex database files for a first target including a first source file and a second source file; creating a mapping graph of declarations and references for the first source file and the second source file, at least in part based on the one or more index database files; creating a representation of a directed graph of the first target, at least in part based on the mapping graph, the representation including a first node of the first source file and a second node of the second source file; and performing a graph analysis on the representation of the directed graph to determine a degree level of the first node and a degree level of the second node, the second node having a higher degree level than the first node.

[0105] Example C2 is the medium of Example Ci, the operations further comprising: building the first target without the first source file, wherein the degree level of the first node is zero.

[0106] Example C3 is the medium of any of Examples C1-C2, the operations further comprising: building the first target without the first source file, at least in part based on a modified version of the second source file, wherein the degree level of the first node is at least one.

[0107] Example C4 is the medium of any of Examples C1-C3, the operations further comprising: building a second target, at least in part based on the first source file and a third source file, wherein the first target does not include the third source file.

[0108] Example C5 is the medium of any of Examples C1-C4, the operations further comprising: performing a display of the directed graph of the first target, wherein the display includes the first node and the second node.

[0109] Example C6 is the medium of any of Examples C1-C5, wherein the collecting is performed by executing a compiler on at least the first source file and the second source file to output the one or more index database files.

[0110] Example C7 is the medium of any of Examples C1-C6, wherein the one or more index database files are IndexStore files.

[0111] In Example Fl, an apparatus includes means for storing at least one instruction; and processing means for collecting one or more index database files for a first target including a first source file and a second source file, for creating a mappinggraph of declarations and references for the first source file and the second source file, at least in part based on the one or more index database files, for creating a representation of a directed graph of the first target, at least in part based on the mapping graph, the representation including a first node of the first source file and a second node of the second source file, and for performing a graph analysis on the representation of the directed graph to determine a degree level of the first node and a degree level of the second node, the second node having a higher degree level than the first node, wherein the processing means execute the at least one instruction.

[0112] Example F2 is the apparatus of Example Fl, wherein the processing means build the first target without the first source file, and the degree level of the first node is zero.

[0113] Example F3 is the apparatus of any of Examples F1-F2, wherein the processing means builds the first target without the first source file, at least in part based on a modified version of the second source file, and the degree level of the first node is at least one.

[0114] Example F4 is the apparatus of any of Examples F1-F3, wherein the processing means builds a second target, at least in part based on the first source file and a third source file, and the first target does not include the third source file.

[0115] Example F5 is the apparatus of any of Examples F1-F4, further comprising: means for performing a display of the directed graph of the first target, wherein the display includes the first node and the second node.

[0116] Example F6 is the apparatus of any of Examples F1-F5, wherein the collecting is performed by executing a compiler on at least the first source file and the second source file to output the one or more index database files.

[0117] Example F7 is the apparatus of any of Examples F1-F6, wherein the one or more index database files are IndexStore files.

Claims

ClaimsI claim:

1. A method, comprising: collecting one or more index database files for a first target including a first source file and a second source file; creating a mapping graph of declarations and references for the first source file and the second source file, at least in part based on the one or more index database files; creating a representation of a directed graph of the first target, at least in part based on the mapping graph, the representation including a first node of the first source file and a second node of the second source file; and performing a graph analysis on the representation of the directed graph to determine a degree level of the first node and a degree level of the second node, the second node having a higher degree level than the first node.

2. The method of Claim 1, further comprising: building the first target without the first source file, wherein the degree level of the first node is zero.

3. The method of Claim 1, further comprising: building the first target without the first source file, at least in part based on a modified version of the second source file, wherein the degree level of the first node is at least one.

4. The method of Claim 1, further comprising: building a second target, at least in part based on the first source file and a third source file, wherein the first target does not include the third source file.

5. The method of Claim 1, further comprising:performing a display of the directed graph of the first target, wherein the display includes the first node and the second node.

6. The method of Claim i, wherein the collecting is performed by executing a compiler on at least the first source file and the second source file to output the one or more index database files.

7. The method of Claim 1, wherein the one or more index database files are IndexStore files.

8. A system, comprising: at least one memory that stores at least one instruction; and at least one processor configured, with the at least one memory, to cause the system to at least collect one or more index database files for a first target including a first source file and a second source file, create a mapping graph of declarations and references for the first source file and the second source file, at least in part based on the one or more index database files, create a representation of a directed graph of the first target, at least in part based on the mapping graph, the representation including a first node of the first source file and a second node of the second source file, and perform a graph analysis on the representation of the directed graph to determine a degree level of the first node and a degree level of the second node, the second node having a higher degree level than the first node.

9. The system of Claim 8, wherein the at least one processor is further configured, with the at least one memory, to cause the system to at least build the first target without the first source file, and the degree level of the first node is zero.

10. The system of Claim 8, wherein the at least one processor is further configured, with the at least one memory, to cause the system to at least build the first target without the first source file, at least in part based on a modified version of the second source file, and the degree level of the first node is at least one.

11. The system of Claim 8, wherein the at least one processor is further configured, with the at least one memory, to cause the system to at least build a second target, at least in part based on the first source file and a third source file, and the first target does not include the third source file.

12. The system of Claim 8, wherein the at least one processor is further configured, with the at least one memory, to cause the system to at least perform a display of the directed graph of the first target, and the display includes the first node and the second node.

13. The system of Claim 8, wherein the collecting is performed by executing a compiler on at least the first source file and the second source file to output the one or more index database files.

14. The system of Claim 8, wherein the one or more index database files are IndexStore files.

15. A computer-readable medium encoded with a computer program that, when executed by a system including at least one processor, causes the system to perform operations comprising: collecting one or more index database files for a first target including a first source file and a second source file; creating a mapping graph of declarations and references for the first source file and the second source file, at least in part based on the one or more index database files;creating a representation of a directed graph of the first target, at least in part based on the mapping graph, the representation including a first node of the first source file and a second node of the second source file; and performing a graph analysis on the representation of the directed graph to determine a degree level of the first node and a degree level of the second node, the second node having a higher degree level than the first node.

16. The medium of Claim 15, the operations further comprising: building the first target without the first source file, wherein the degree level of the first node is zero.

17. The medium of Claim 15, the operations further comprising: building the first target without the first source file, at least in part based on a modified version of the second source file, wherein the degree level of the first node is at least one.

18. The medium of Claim 15, the operations further comprising: building a second target, at least in part based on the first source file and a third source file, wherein the first target does not include the third source file.

19. The medium of Claim 15, wherein the collecting is performed by executing a compiler on at least the first source file and the second source file to output the one or more index database files.

20. The medium of Claim 15, wherein the one or more index database files are IndexStore files.

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