Simultaneously supplying positive and negative voltages based on a single inductor

Abstract

Simultaneously supplying positive and negative voltages based on a single inductor is disclosed. Herein, the single inductor is coupled between a positive voltage rail that supplies a positive voltage and a negative voltage rail that supplies a negative voltage. The single inductor is first magnetized to store energy in a magnetic field. Subsequently, depending on whether the positive voltage or the negative voltage is at a deficit, the single inductor is demagnetized to provide a charge current exclusively to the positive voltage rail or the negative voltage rail. Thereafter, the single inductor will continue to demagnetize to provide the charge current to both the positive voltage rail and the negative voltage rail. By exclusively providing the charge current to either the positive voltage rail or the negative voltage rail, it is possible to accommodate a larger load current variation to thereby improve robustness of the overall operating conditions.

Description

SIMULTANEOUSLY SUPPLYING POSITIVE AND NEGATIVE VOLTAGES BASED ONA SINGLE INDUCTORRelated Applications

[0001] This application claims the benefit of U.S. provisional patent application serial number 63 / 714,174, filed on October 31 , 2024, and U.S. provisional patent application serial number 63 / 752,993, filed on February 3, 2025, the disclosures of which are hereby incorporated herein by reference in their entireties.Field of the Disclosure

[0002] The present disclosure is related to simultaneously supplying positive and negative voltages in an electronic device (e.g., a wireless device) based on a single inductor.Background

[0003] Today’s electronic devices (e.g., smartphones and tablets) typically include a form of display, such as an active-matrix organic light emitting diode (AMOLED) display, for user interaction. The AMOLED display requires many kinds of power supplies to drive thin-film transistors and organic light emitting diodes (LEDs). Some of the power supplies are required to concurrently provide a positive voltage on a positive voltage rail and a negative voltage on a negative voltage rail. The loads that are coupled to the positive voltage rail and the negative voltage rail may be close to being symmetrical but can vary under various operating conditions. The loads are typically current sources that can draw a maximum load current of 20 mA. As such, it is necessary to magnetize and demagnetize an inductor(s) to provide the needed load current at the positive voltage rail and the negative voltage rail. Given the increasing emphasis on miniaturizing solution size of the power supplies for the AMOLED display, it is thus desirable to employ as few inductors as possible to concurrently provide the positive voltage and the negative voltage.

[0004] Embodiments of the disclosure relate to simultaneously supplying positive and negative voltages based on a single inductor. Herein, the single inductor is coupled between a positive voltage rail that supplies a positive voltage and a negative voltage rail that supplies a negative voltage. The single inductor is first magnetized to store energy in a magnetic field. Subsequently, depending on whether the positive voltage or the negative voltage is at a deficit, the single inductor is demagnetized to provide a charge current exclusively to the positive voltage rail or the negative voltage rail. Thereafter, the single inductor will continue to demagnetize to provide the charge current to both the positive voltage rail and the negative voltage rail. By exclusively providing the charge current to either the positive voltage rail or the negative voltage rail, it is possible to accommodate a larger load current variation to thereby improve robustness of the overall operating conditions. Further, by sharing the single inductor between the positive voltage rail and the negative voltage rail, it is possible to reduce a solution size without power efficiency degradation.

[0005] In one aspect, a positive and negative voltage circuit is provided. The positive and negative voltage circuit includes a single-inductor voltage bridge. The single-inductor voltage bridge includes a single inductor. The single-inductor voltage bridge is configured to supply a positive voltage on a positive voltage rail and a negative voltage on a negative voltage rail based on an input voltage. The positive and negative voltage circuit also includes a control circuit. The control circuit is configured to magnetize the single inductor in response to receiving any of a request for the positive voltage and a request for the negative voltage. The control circuit is also configured to demagnetize the single inductor to provide a charge current exclusively to the positive voltage rail in response to determining a positive voltage deficit. The control circuit is also configured to demagnetize the single inductor to provide the charge current exclusively to the negative voltage rail in response to determining a negative voltage deficit.

[0006] In another aspect, an electronic device is provided. The electronic device includes a positive and negative voltage circuit. The positive and negativevoltage circuit includes a single-inductor voltage bridge. The single-inductor voltage bridge includes a single inductor. The single-inductor voltage bridge is configured to supply a positive voltage on a positive voltage rail and a negative voltage on a negative voltage rail based on an input voltage. The positive and negative voltage circuit also includes a control circuit. The control circuit is configured to magnetize the single inductor in response to receiving any of a request for the positive voltage and a request for the negative voltage. The control circuit is also configured to demagnetize the single inductor to provide a charge current exclusively to the positive voltage rail in response to determining a positive voltage deficit. The control circuit is also configured to demagnetize the single inductor to provide the charge current exclusively to the negative voltage rail in response to determining a negative voltage deficit.

[0007] In another aspect, a method for simultaneously supplying positive and negative voltages based on a single inductor is provided. The method includes magnetizing the single inductor in response to receiving any of a request for a positive voltage on a positive voltage rail and a request for a negative voltage on a negative voltage rail. The method also includes demagnetizing the single inductor to provide a charge current exclusively to the positive voltage rail in response to determining a positive voltage deficit. The method also includes demagnetizing the single inductor to provide the charge current exclusively to the negative voltage rail in response to determining a negative voltage deficit.

[0008] Those skilled in the art will appreciate the scope of the present disclosure and realize additional aspects thereof after reading the following detailed description of the preferred embodiments in association with the accompanying drawing figures.Briefof the

[0009] The accompanying drawing figures incorporated in and forming a part of this specification illustrate several aspects of the disclosure and, together with the description, serve to explain the principles of the disclosure.

[0010] Figure 1 is a schematic diagram of an exemplary positive and negative voltage circuit configured according to an embodiment of the present disclosure to simultaneously provide positive and negative voltages based on a single inductor;

[0011] Figure 2 is a schematic diagram of an exemplary state machine for simultaneously providing the positive and negative voltages based on the single inductor in Figure 1 ;

[0012] Figure 3 is a schematic diagram of an exemplary communication device wherein the positive and negative voltage circuit of Figure 1 can be provided; and

[0013] Figure 4 is a flowchart of an exemplary process for simultaneously supplying the positive and negative voltages based on the single inductor in Figure 1 .Detailed Description

[0014] The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims.

[0015] It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0016] It will be understood that when an element such as a layer, region, or substrate is referred to as being "on" or extending "onto" another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or extending "directly onto" another element, there are no intervening elements present. Likewise, it will be understood that when an element such as a layer, region, or substrate is referred to as being "over" or extending "over" another element, it can be directly over or extend directly over the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly over" or extending "directly over" another element, there are no intervening elements present. It will also be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.

[0017] Relative terms such as "below" or "above" or "upper" or "lower" or "horizontal" or "vertical" may be used herein to describe a relationship of one element, layer, or region to another element, layer, or region as illustrated in the Figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures.

[0018] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises," "comprising," "includes," and / or "including" when used herein specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0019] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0020] Embodiments are described herein with reference to simultaneously supplying positive and negative voltages based on a single inductor. Herein, the single inductor is coupled between a positive voltage rail that supplies a positive voltage and a negative voltage rail that supplies a negative voltage. The single inductor is first magnetized to store energy in a magnetic field. Subsequently, depending on whether the positive voltage or the negative voltage is at a deficit, the single inductor is demagnetized to provide a charge current exclusively to the positive voltage rail or the negative voltage rail. Thereafter, the single inductor will continue to demagnetize to provide the charge current to both the positive voltage rail and the negative voltage rail. By exclusively providing the charge current to either the positive voltage rail or the negative voltage rail, it is possible to accommodate a larger load current variation to thereby improve robustness of the overall operating conditions. Further, by sharing the single inductor between the positive voltage rail and the negative voltage rail, it is possible to reduce a solution size without power efficiency degradation.

[0021] Figure 1 is a schematic diagram of an exemplary positive and negative voltage circuit 10 configured according to an embodiment of the present disclosure. Specifically, the positive and negative voltage circuit 10 includes a single-inductor voltage bridge 12 that can simultaneously provide a positive voltage VGH at a positive voltage rail 14 and a negative voltage VGL at a negative voltage rail 16 based on a single inductor 18 provided between the positive voltage rail 14 and the negative voltage rail 16. In a non-limiting example, the positive voltage VGH can be between 4.6 V and 8 V, whereas thenegative voltage VGL can be between -12 V and -5 V. As such, the positive voltage VGH and the negative voltage VGL are asymmetrical.

[0022] The positive voltage rail 14 can be configured to provide the positive voltage VGH to a first load 20 and the negative voltage rail 16 can be configured to provide the negative voltage VGL to a second load 22. Herein, each of the first load 20 and the second load 22 can be a current source that can deliver or absorb a load current independent of the positive voltage VGH and the negative voltage VGL. In this regard, the load current flowing across the first load 20 and the second load 22 can be largely symmetrical despite the asymmetrical nature of the positive voltage VGH and the negative voltage VGL.

[0023] In an embodiment, the single-inductor voltage bridge 12 includes a first transistor S1 , a second transistor S2, a third transistor S3, and a fourth transistor S4. Herein, each of the first transistor S1 , the second transistor S2, the third transistor S3, and the fourth transistor S4 can be biased to function as a switch. The first transistor S1 is coupled between an input voltage VIN and a first middle node 24, the second transistor S2 is coupled between the positive voltage rail 14 and a second middle node 26, the third transistor S3 is coupled between the first middle node 24 and the negative voltage rail 16, and the fourth transistor S4 is coupled between the second middle node 26 and a ground (GND).

[0024] The single inductor 18 is coupled between the first middle node 24 and the second middle node 26. In this regard, the single inductor 18 is shared between the positive voltage rail 14 and the negative voltage rail 16. By sharing the single inductor 18 between the positive voltage rail 14 and the negative voltage rail 16, the single-inductor voltage bridge 12 can simultaneously provide the positive voltage VGH and the negative voltage VGL based on a smaller footprint compared to a conventional voltage converter based on multiple inductors. Moreover, studies have shown that the single-inductor voltage bridge 12 can achieve a similar power efficiency as the conventional voltage converter.

[0025] In an embodiment, the positive and negative voltage circuit 10 can include a first gate driver 28 and a second gate driver 30. The first gate driver 28 can provide one or more bias voltages VBIASI , VBIASS to turn on the first transistor51 and the third transistor S3, respectively. The second gate driver 30 can provide one or more bias voltages VBIAS2, VBIAS4 to turn on the second transistor52 and the fourth transistor S4, respectively.

[0026] The positive and negative voltage circuit 10 also includes a control circuit 32, which can be any type of control circuit as appropriate. The control circuit 32 can control the first gate driver 28 and the second gate driver 30 via a control signal 34 to thereby turn any one or more of the first transistor S1 , the second transistor S2, the third transistor S3, and the fourth transistor S4.

[0027] In an embodiment, the positive voltage VGH and the negative voltage VGL can be used to power an active-matrix organic light emitting diode (AMOLED) display in an electronic device (e.g., smartphone, tablet, etc.). The positive and negative voltage circuit 10 may include a positive rail monitor 36 and a negative rail monitor 38 to help determine whether there is a demand for the positive voltage VGH and / or the negative voltage VGL (e.g., the AMOLED display is turned on). Specifically, the positive rail monitor 36 can provide a respective request VGH_REQ to the control circuit 32 when the positive voltage VGH is needed, and the negative rail monitor 38 can provide a respective request VGL_REQ to the control circuit 32 when the negative voltage VGL is needed.

[0028] In response to receiving any one or more of the requests VGH_REQ and VGL_REQ, the control circuit 32 will magnetize the single inductor 18 to thereby store energy in a magnetic field. Specifically, the control circuit 32 can control the first gate driver 28 and the second gate driver 30 to turn on the first transistor S1 and the fourth transistor S4, while turning off the second transistor S2 and the third transistor S3, to thereby magnetize the single inductor 18 with a charge current h (a.k.a. “first charge current”).

[0029] Subsequently, the control circuit 32 will demagnetize the single inductor 18 to provide a charge current I2 (a.k.a. “second charge current) exclusively to the positive voltage rail 14 when the control circuit 32 determines that there exists a deficit in the positive voltage VGH (a.k.a. “positive voltage deficit”). In this regard, the control circuit 32 can control the first gate driver 28and the second gate driver 30 to turn on the first transistor S1 and the second transistor S2, while turning off the third transistor S3 and the fourth transistor S4.

[0030] Alternatively, the control circuit 32 will demagnetize the single inductor 18 to provide a charge current h (a.k.a. “third charge current) exclusively to the negative voltage rail 16 when the control circuit 32 determines that there exists a deficit in the negative voltage VGL (a.k.a. “negative voltage deficit”). In this regard, the control circuit 32 can control the first gate driver 28 and the second gate driver 30 to turn on the third transistor S3 and the fourth transistor S4, while turning off the first transistor S1 and the second transistor S2.

[0031] Thereafter, the control circuit 32 can control the first gate driver 28 and the second gate driver 30 to turn on the second transistor S2 and the third transistor S3, while turning off the first transistor S1 and the fourth transistor S4 to thereby continue to demagnetize the single inductor 18 with a charge current k (a.k.a. “fourth charge current”) that flows between the positive voltage rail 14 and the negative voltage rail 16, thus delivering charges to the positive voltage VGH and the negative voltage VGL simultaneously.

[0032] In an embodiment, the control circuit 32 can include a timer circuit 40 that provides an always-on timer TON, a positive voltage timer TVGH, and a negative voltage timer TVGL. Herein, the control circuit 32 can set the always-on timer TON concurrently in response to receiving any one or more of the requests VGH_REQ and VGL_REQ. Accordingly, the control circuit 32 can magnetize the single inductor 18 with the first charge current h until an expiration of the always- on timer TON.

[0033] The control circuit 32 will set the positive voltage timer TVGH concurrently in response to determining that there exists the positive voltage deficit. Accordingly, the control circuit 32 will demagnetize the single inductor 18 to provide the second charge current I2 exclusively to the positive voltage rail 14 until an expiration of the positive voltage timer TVGH.

[0034] Alternatively, the control circuit 32 will set the negative voltage timer TVGL concurrently in response to determining that there exists the negative voltage deficit. Accordingly, the control circuit 32 will demagnetize the singleinductor 18 to provide the third charge current h exclusively to the negative voltage rail 16 until an expiration of the negative voltage timer TVGL.

[0035] Thereafter, the control circuit 32 will continue to demagnetize the single inductor 18 until all the energy stored in the magnetic field is depleted.

[0036] The control circuit 32 can set the positive voltage timer TVGH or the negative voltage timer TVGL based on a ratio COMP between the positive voltage VGH and the negative voltage VGL. In this regard, the positive and negative voltage circuit 10 can further include a feedback loop 42 configured to determine the ratio COMP. The feedback loop 42 can include a voltage divider 44 coupled between the positive voltage rail 14 and the negative voltage rail 16. The feedback loop 42 also includes an integrator 46 that is coupled to the voltage divider 44 and the control circuit 32. In an embodiment, the integrator 46 will increase the ratio COMP in response to the positive voltage deficit or decrease the ratio COMP in response to the negative voltage deficit. Accordingly, the control circuit 32 can set up the positive voltage timer TVGH or the negative voltage timer TVGL.

[0037] In an embodiment, the control circuit 32 can control the single-inductor voltage bridge 12 based on a state machine. Figure 2 is a schematic diagram of an exemplary illustration of the state machine whereby the control circuit 32 in the positive and negative voltage circuit 10 of Figure 1 can control the singleinductor voltage bridge 12 to simultaneously provide the positive voltage VGH and the negative voltage VGL. Common elements between Figures 1 and 2 are shown therein with common element numbers and will not be re-described herein.

[0038] The single-inductor voltage bridge 12 will be in an IDLE state when the positive and negative voltage circuit 10 is not providing the positive voltage VGH and the negative voltage VGL to the first load 20 and the second load 22. In a non-limiting example, the single-inductor voltage bridge 12 can be in the IDLE state when the AMOLED display is completely off.

[0039] During the IDLE state, the control circuit 32 turns off the first transistor S1 , the second transistor S2, and the third transistor S3. Herein, the controlcircuit 32 may turn off the first transistor S1 and the third transistor S3 by applying the control signal 34 to the first gate driver 28. The control circuit 32 may further turn on the fourth transistor S4 during the IDLE state to thereby keep the first middle node 24 and the second middle node 26 from being high impedance and not at a defined voltage.

[0040] The control circuit 32 will control the single-inductor voltage bridge 12 to enter a PHASE 1 state in response to receiving any one or more of the requests VGH_REQ and VGL_REQ. Herein, the control circuit 32 will concurrently set the always-on timer TON to thereby magnetize the single inductor 18 until the expiration of the always-on timer TON.

[0041] Upon the expiration of the always-on timer TON, the control circuit 32 can determine which of the positive voltage VGH and the negative voltage VGL is in the deficit based on the ratio COMP provided by the feedback loop 42. If the positive voltage VGH is in the deficit, the control circuit 32 will set the positive voltage timer TVGH and control the single-inductor voltage bridge 12 to enter a PHASE 2 state. Alternatively, if the negative voltage VGL is in the deficit, the control circuit 32 will set the negative voltage timer TVGL and control the singleinductor voltage bridge 12 to enter a PHASE 3 state. In case none of the positive voltage VGH and the negative voltage VGL is in the deficit, the control circuit 32 may stay in the PHASE 1 state.

[0042] In an embodiment, the control circuit 32 can determine which of the positive voltage VGH and the negative voltage VGL is in the deficit based on a reference voltage VREF. Specifically, when the ratio COMP is higher than the reference voltage VREF (COMP > VREF), the control circuit 32 can determine that the positive voltage VGH is in the deficit. Accordingly, the control circuit 32 can determine the positive voltage timer TVGH in accordance with the positive voltage deficit. As such, during the PHASE 2 state, the single inductor 18 is demagnetized to provide the second charge current L exclusively to the positive voltage rail 14 until the expiration of the positive voltage timer TVGH.

[0043] In contrast, when the ratio COMP is lower than the reference voltage VREF (COMP < VREF), the control circuit 32 can determine that the negativevoltage VGL is in the deficit. Accordingly, the control circuit 32 can determine the negative voltage timer TVGL in accordance with the negative voltage deficit. As such, during the PHASE 3 state, the single inductor 18 is demagnetized to provide the third charge current h exclusively to the negative voltage rail 16 until the expiration of the negative voltage timer TVGL.

[0044] In an embodiment, the reference voltage VREF can be determined based on the input voltage VIN. In a non-limiting example, if the input voltage VIN is confined between a lowest value of 2.3 V and a highest value of 5 V, the reference voltage VREF can be arbitrarily set to be approximately one-half (1 / 2) of the lowest value (e.g., 1 V) of the input voltage VIN.

[0045] Upon the expiration of the positive voltage timer TVGH or the negative voltage timer TVGL, the control circuit 32 will control the single-inductor voltage bridge 12 to enter a PHASE 4 state. In the PHASE 4 state, the single inductor 18 is continually demagnetized to provide the fourth charge current k between the positive voltage rail 14 and the negative voltage rail 16, until the stored energy is completely depleted. Thereafter, the single-inductor voltage bridge 12 will return to the IDLE state.

[0046] The positive and negative voltage circuit 10 of Figure 1 can be provided in a communication device to support the embodiments described above. In this regard, Figure 3 is a schematic diagram of an exemplary communication device 100 wherein the positive and negative voltage circuit 10 of Figure 1 can be provided.

[0047] Herein, the communication device 100 can be any type of communication devices, such as mobile terminals, smart watches, tablets, computers, navigation devices, access points, base stations (e.g., eNB, gNB, etc.), and like wireless communication devices that support wireless communications, such as cellular, wireless local area network (WLAN), Ultra- wideband (UWB), Bluetooth, and near-field communications. The communication device 100 will generally include a control system 102, a baseband processor 104, transmit circuitry 106, receive circuitry 108, antenna switching circuitry 1 10, multiple antennas 1 12, and user interface circuitry 114. In a non-limitingexample, the control system 102 can be a field-programmable gate array (FPGA), as an example. In this regard, the control system 102 can include at least a microprocessor, an embedded memory circuit, and a communication bus interface. The receive circuitry 108 receives radio frequency signals via the antennas 1 12 and through the antenna switching circuitry 110 from one or more base stations. A low-noise amplifier and a filter cooperate to amplify and remove broadband interference from the received signal for processing.Downconversion and digitization circuitry (not shown) will then downconvert the filtered, received signal to an intermediate or baseband frequency signal, which is then digitized into one or more digital streams using analog-to-digital converters (ADCs).

[0048] The baseband processor 104 processes the digitized received signal to extract the information or data bits conveyed in the received signal. This processing typically comprises demodulation, decoding, and error correction operations, as will be discussed in greater detail below. The baseband processor 104 is generally implemented in one or more digital signal processors (DSPs) and application-specific integrated circuits (ASICs).

[0049] For transmission, the baseband processor 104 receives digitized data, which may represent voice, data, or control information, from the control system 102, which it encodes for transmission. The encoded data is output to the transmit circuitry 106, where a digital-to-analog converter (DAC) converts the digitally encoded data into an analog signal and a modulator modulates the analog signal onto a carrier signal that is at a desired transmit frequency or frequencies. A power amplifier will amplify the modulated carrier signal to a level appropriate for transmission and deliver the modulated carrier signal to the antennas 1 12 through the antenna switching circuitry 110. The multiple antennas 1 12 and the replicated transmit 106 and receive circuitry 108 may provide spatial diversity. Modulation and processing details will be understood by those skilled in the art.

[0050] In an embodiment, the user interface circuitry 1 14 can include a form of display (e.g., AMOLED display). As such, the positive and negative voltagecircuit 10 can be configured to simultaneously provide the positive voltage VGH and the negative voltage VGL to power the display in the user interface circuitry 1 14.

[0051] In an embodiment, the positive and negative voltage circuit 10 of Figure 1 can simultaneously provide the positive voltage VGH and the negative voltage VGL in accordance with a process. In this regard, Figure 4 is a flowchart of an exemplary process 200 for simultaneously supplying the positive VGH and negative VGL voltages based on the single inductor 18 in Figure 1.

[0052] Herein, the process 200 includes magnetizing the single inductor 18 in response to receiving any of the request VGH_REQ for the positive voltage VGH on the positive voltage rail 14 and the request VGL_REQ for the negative voltage VGL on the negative voltage rail 16 (step 202). The process 200 also includes demagnetizing the single inductor 18 to provide the charge current L exclusively to the positive voltage rail 14 in response to determining the positive voltage deficit (step 204). The process 200 also includes demagnetizing the single inductor 18 to provide the charge current I3 exclusively to the negative voltage rail 16 in response to determining the negative voltage deficit (step 206).

[0053] Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.

Claims

ClaimsWhat is claimed is:1 . A positive and negative voltage circuit comprising: a single-inductor voltage bridge comprising a single inductor and configured to supply a positive voltage on a positive voltage rail and a negative voltage on a negative voltage rail based on an input voltage; and a control circuit configured to: magnetize the single inductor in response to receiving any of a request for the positive voltage and a request for the negative voltage; demagnetize the single inductor to provide a charge current exclusively to the positive voltage rail in response to determining a positive voltage deficit; and demagnetize the single inductor to provide the charge current exclusively to the negative voltage rail in response to determining a negative voltage deficit.

2. The positive and negative voltage circuit of claim 1 , wherein the control circuit is further configured to: set an always-on timer in response to receiving any of the request for the positive voltage and the request for the negative voltage; and demagnetize the single inductor at an expiration of the always-on timer and in response to determining any of the positive voltage deficit and the negative voltage deficit.

3. The positive and negative voltage circuit of claim 1 , wherein the control circuit is further configured to: set a positive voltage timer in response to determining the positive voltage deficit and demagnetize the single inductor to provide the chargecurrent exclusively to the positive voltage rail until an expiration of the positive voltage timer; and set a negative voltage timer in response to determining the negative voltage deficit and demagnetize the single inductor to provide the charge current exclusively to the negative voltage rail until an expiration of the negative voltage timer.

4. The positive and negative voltage circuit of claim 3, wherein the control circuit is further configured to continue to demagnetize the single inductor to provide the charge current to both the positive voltage rail and the negative voltage rail in response to the expiration of any of the positive voltage timer and the negative voltage timer.

5. The positive and negative voltage circuit of claim 1 , further comprising: a positive rail monitor configured to provide the request for the positive voltage to the control circuit; and a negative rail monitor configured to provide the request for the negative voltage to the control circuit.

6. The positive and negative voltage circuit of claim 1 , further comprising a feedback loop configured to determine a ratio between the positive voltage and the negative voltage.

7. The positive and negative voltage circuit of claim 6, wherein the control circuit is further configured to: determine the positive voltage deficit when the ratio between the positive voltage and the negative voltage is above a reference voltage; and determine the negative voltage deficit when the ratio between the positive voltage and the negative voltage is below the reference voltage.

8. The positive and negative voltage circuit of claim 1 , wherein the singleinductor voltage bridge comprises: a first transistor coupled between the input voltage and a first middle node; a second transistor coupled between the positive voltage rail and a second middle node; a third transistor coupled between the first middle node and the negative voltage rail; a fourth transistor coupled between the second middle node and a ground; and the single inductor coupled between the first middle node and the second middle node.

9. The positive and negative voltage circuit of claim 8, wherein the control circuit is further configured to: bias the first transistor and the fourth transistor to thereby magnetize the single inductor; bias the first transistor and the second transistor to thereby demagnetize the single inductor to provide the charge current exclusively to the positive voltage rail; bias the third transistor and the fourth transistor to thereby demagnetize the single inductor to provide the charge current exclusively to the negative voltage rail; and bias the second transistor and the third transistor to thereby demagnetize the single inductor to provide the charge current to both the positive voltage rail and the negative voltage rail.

10. An electronic device comprising a positive and negative voltage circuit, the positive and negative voltage circuit comprises: a single-inductor voltage bridge comprising a single inductor and configured to supply a positive voltage on a positive voltage rail anda negative voltage on a negative voltage rail based on an input voltage; and a control circuit configured to: magnetize the single inductor in response to receiving any of a request for the positive voltage and a request for the negative voltage; demagnetize the single inductor to provide a charge current exclusively to the positive voltage rail in response to determining a positive voltage deficit; and demagnetize the single inductor to provide the charge current exclusively to the negative voltage rail in response to determining a negative voltage deficit.1 1 . The electronic device of claim 10, wherein the control circuit is further configured to: set an always-on timer in response to receiving any of the request for the positive voltage and the request for the negative voltage; and demagnetize the single inductor at an expiration of the always-on timer and in response to determining any of the positive voltage deficit and the negative voltage deficit.

12. The electronic device of claim 10, wherein the control circuit is further configured to: set a positive voltage timer in response to determining the positive voltage deficit and demagnetize the single inductor to provide the charge current exclusively to the positive voltage rail until an expiration of the positive voltage timer; and set a negative voltage timer in response to determining the negative voltage deficit and demagnetize the single inductor to provide the charge current exclusively to the negative voltage rail until an expiration of the negative voltage timer.

13. The electronic device of claim 12, wherein the control circuit is further configured to continue to demagnetize the single inductor to provide the charge current to both the positive voltage rail and the negative voltage rail in response to the expiration of any of the positive voltage timer and the negative voltage timer.

14. The electronic device of claim 10, further comprising an active-matrix organic light emitting diode (AMOLED) display configured to operate based on the positive voltage and the negative voltage.

15. A method for simultaneously supplying positive and negative voltages based on a single inductor comprising: magnetizing the single inductor in response to receiving any of a request for a positive voltage on a positive voltage rail and a request for a negative voltage on a negative voltage rail; demagnetizing the single inductor to provide a charge current exclusively to the positive voltage rail in response to determining a positive voltage deficit; and demagnetizing the single inductor to provide the charge current exclusively to the negative voltage rail in response to determining a negative voltage deficit.

16. The method of claim 15, further comprising: setting an always-on timer in response to receiving any of the request for the positive voltage and the request for the negative voltage; and demagnetizing the single inductor at an expiration of the always-on timer and in response to determining any of the positive voltage deficit and the negative voltage deficit.

17. The method of claim 15, further comprisingsetting a positive voltage timer in response to determining the positive voltage deficit and demagnetizing the single inductor to provide the charge current exclusively to the positive voltage rail until an expiration of the positive voltage timer; and setting a negative voltage timer in response to determining the negative voltage deficit and demagnetizing the single inductor to provide the charge current exclusively to the negative voltage rail until an expiration of the negative voltage timer.

18. The method of claim 17, further comprising continuing to demagnetize the single inductor to provide the charge current to both the positive voltage rail and the negative voltage rail in response to the expiration of any of the positive voltage timer and the negative voltage timer.

19. The method of claim 15, further comprising determining a ratio between the positive voltage and the negative voltage.

20. The method of claim 19, further comprising: determining the positive voltage deficit when the ratio between the positive voltage and the negative voltage is above a reference voltage; and determining the negative voltage deficit when the ratio between the positive voltage and the negative voltage is below the reference voltage.

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