Compact RF switch stack with high vpeak

Abstract

MOSFET devices that operate with high linearity under a high RF voltage swing. MOSFETs in accordance with the invention have increased bandwidth and maximum-voltage handling ability compared to conventional designs and are particularly well suited for use as RF switches. Embodiments utilize an integrated circuit (IC) structure that includes modification of the active region beneath a gate structure (the channel) to be thinner than the active region utilized for the source and drain regions, without needing epitaxy. The differentiated channel versus source-drain thickness of the active region enables a simultaneous improvement in reducing ON-resistance RON while increasing the operating RF voltage swing (breakdown voltage VBD), and additionally reduces the form factor or area of the RF switch, resulting in high-performing devices. An IC may include at least one device stack unit (DSU) having at least one thin-gate MOSFET.

Description

Attorney Docket No.: P3117-PCTCompact RF Switch Stack with High VPEAKCROSS REFERENCE TO RELATED APPLICATIONS

[0001] The present application claims priority to U.S. Provisional Application No. 63 / 714,054, filed on October 30, 2024 and entitled “Compact RF Switch Stack with High VPEAK”, with attorney docket number P3117-USP, the content of which is incorporated by reference in its entirety.BACKGROUND(1) Technical Field

[0002] This invention relates to transistor device structures, and more particularly to field effect transistor structures.(2) Background

[0003] Virtually all modern electronic products - including laptop computers, mobile telephones, and electric cars - utilize metal-oxide-semiconductor field-effect transistors (MOSFETs) fabricated as part of integrated circuits (ICs). In many cases, MOSFET ICs are fabricated using a semiconductor-on-insulator (SOI) structure in place of conventional “bulk” silicon substrates in semiconductor manufacturing. More specifically, SOI transistors are generally fabricated in and on a crystalline semiconductor layer formed on an electrically insulating layer (often called a “buried oxide” or “BOX” layer), which in turn is formed on a bulk substrate. The BOX layer reduces certain parasitic effects typical of bulk silicon MOSFET processes, thereby improving performance, particularly for radio frequency (RF) applications. SOI substrates have many benefits over bulk silicon substrates, including higher speed, lower power consumption, improved RF performance, and improved radiation resistance.

[0004] FIG. 1 is a cross-sectional stylized view of a typical prior art enhancement-mode N- type MOSFET (“nFET”) 100 (note that the dimensions of various elements are not to scale). In the illustrated example, an active region 102 is formed on a BOX layer 104 (e.g., SiO2) formed on top of a substrate 106. The active region 102 may comprise, for example, crystalline Si, Ge, or an SiGe alloy or layered mixture. The substrate 106 may comprise, for example, silicon or sapphire.Attorney Docket No.: P3117-PCTThe BOX layer 104 and active region 102 may be considered to be a substructure 107 formed on the substrate 106.

[0005] An N-type source region 108 and an N-type drain region 110 are formed in the active region 102 adjacent to an overlying gate structure 112 and between isolation structures 114. The isolation structures 114 may be, for example, shallow trench isolation (STI) structures formed from, for example, SiCh. Some optional regions 113 may be fabricated within the active region 102 near the side edges of the gate structure 112, such as halo implants and / or lightly-doped drain (LDD) implants (for example, to control short-channel effects).

[0006] The gate structure 112 overlies a channel region 116 (also referred to as the “body”) between the source region 108 and the drain region 110 comprising a doped semiconductor region (P-type in this example, commonly referred to as a “P-well”) within the active region 102. The gate structure 112 generally comprises an insulator 118 (e.g., an SiC>2 layer, commonly referred to as a “gate oxide” or “GOX”) and overlaying gate material 120 (e.g., N+ or P+ polysilicon, or a replacement metal gate). Offset dielectric spacers 122 along both sides of the gate structure 112 may also be formed as part of the fabrication process for making the gate structure 112. In some applications, the dielectric spacers 122 may be formed from multiple dielectric layers.

[0007] Generally, respective salicide (self-aligned silicide) layers 124S, 124G, 124D are formed as part of the source region 108, the gate structure 112, and the drain region 110, to reduce the series resistance to those features. Salicides may include nickel silicide (NiSi). titanium silicide, cobalt silicide, and other metal-silicides.

[0008] A superstructure (not shown) may be fabricated on top of the substructure 107 to complete the IC. A superstructure may include, for example, conductive vias, insulating layers (dielectrics), metallization layers, and electrical contacts (pads) for die-to-package connections. FIG. 1 shows stylized electrically conductive contacts S, D, and G made to the source region 108, the drain region 110, and the gate structure 112, respectively, that typically would be fabricated as part of the IC superstructure. Other common IC structures are omitted for clarity. The multiple steps needed for making elements and features of the MOSFET 100 structure, such as masking, doping (via implantation, diffusion, etc.), epitaxy, cleaving, polishing, etc., are well known in the art.Attorney Docket No.: P3117-PCT

[0009] In an nFET, application of suitable control voltage to the gate contact G causes a conductive channel 126 to form in the channel region 116 beneath the gate structure 112 and places the MOSFET in a conductive ON state with an ON-resistance of RON. Voltages that do not equal or exceed the threshold voltage VTH of the MOSFET place the device in an OFF state having a capacitance of Corr.

[0010] In many IC applications, pairs of N-type MOSFETs (“nFETs”) and P-type MOSFETs (“pFETs”) form complementary metal-oxide-semiconductor (CMOS) FETs. CMOS FETs are often the preferred building blocks for RF and logic circuits due to their scalability, low power, and design flexibility. Enhancement mode pFETS have a structure similar to nFETs, but with different doping characteristics, as do depletion mode nFETs and pFETs.

[0011] Improving the performance of MOSFETs, particularly as MOSFET structures within ICs shrink to ever smaller dimensions, is of importance to the electronics industry. The present invention encompasses new and improved MOSFET structures and methods for making such structures.Attorney Docket No.: P3117-PCTSUMMARY

[0012] Embodiments of the present invention encompass MOSFETs that operate with high linearity under a high RF voltage swing. MOSFETs made in accordance with the present invention have increased bandwidth and maximum-voltage handling ability compared to conventional designs and are particularly well suited for use as RF switches. Embodiments utilize an integrated circuit (IC) structure that includes modification of the active region beneath a gate structure (the channel) to be thinner than the active region utilized for the source and drain regions, without needing epitaxy. The differentiated channel versus source-drain thickness of the active region enables a simultaneous improvement in reducing ON-resistance RON while increasing the operating RF voltage swing (including breakdown voltage VBD), and additionally reduces the form factor or area of the RF switch, resulting in high-performing devices.

[0013] Device stack units (DSUs) of one or more MOSFETs may be configured to have one or more gate “fingers” interspersed between adjacent source and drain regions and generally configured to behave as a single transistor. Multiple DSUs may be coupled in series and / or parallel for various applications. Series connection of multiple DSUs provides higher VBD values, while parallel connection of multiple DSUs provides higher current carrying capability. Selective usage within one or more DSUs of thin sub-gate regions in accordance with the present invention may improve the peak voltage (VPEAK) and OFF capacitance (COFF) characteristics of such DSUs with little or no adverse impact on ON resistance (RON), and potentially improving current leakage.

[0014] In one aspect, the invention encompasses an integrated circuit including one or more DSUs, each comprising one or more MOSFETs, wherein at least one of the one or more DSUs is a thin-gate DSU. In another aspect, the invention encompasses a stack of one or more DSUs in which at least one DSU includes one or more gate fingers fabricated with a thin sub-gate region, wherein each of the one or more gate fingers includes an associated VPEAK value and the associated thin sub-gate region includes an associated bottom length LTHIN_SD and a sidewall angle <t>, wherein the associated bottom length LTHIN_SD and / or sidewall angle <t> may be selected to adjust the associated VPEAK value.Attorney Docket No.: P3117-PCT

[0015] In another aspect, the invention encompasses a method of making a DSU comprising one or more MOSFETs, wherein at least one MOSFET of the one or more MOSFET is fabricated with a thin sub-gate region.

[0016] The details of one or more embodiments of the invention are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the invention should be apparent from the description and drawings, and from the claims.Attorney Docket No.: P3117-PCTDESCRIPTION OF THE DRAWINGS

[0017] FIG. 1 is a cross-sectional stylized view of a typical prior art enhancement-mode N- type MOSFET (“nFET”).

[0018] FIG. 2A is a stylized cross-sectional view of a MOSFET device in which a thinned gate- adjacent active region trench has a top length LTHICK_SD and a bottom length LTHIN_SD that is approximately equal to the gate length EG of the device.

[0019] FIG. 2B is a stylized cross-sectional view showing only a profile of the active region of the MOSFET device of FIG. 2A.

[0020] FIG. 3A is a stylized cross-sectional view of a MOSFET device in which a thinned gate-adjacent active region trench has a top length LTHICKJSD and a bottom length LTHIN_SD that is less than the gate length EG of the device.

[0021] FIG. 3B is a stylized cross-sectional view showing only a profile of the active region of the MOSFET device of FIG. 3A.

[0022] FIG. 4A is a stylized cross-sectional view of a MOSFET device in which a thinned gate-adjacent active region trench has a top length LTHICK_SD and a bottom length LTHIN_SD that is greater than the gate length LG of the device.

[0023] FIG. 4B is a stylized cross-sectional view showing only a profile of the active region of the MOSFET device of FIG. 4A.

[0024] FIGS. 5A-5D are stylized cross-sectional views of different stages in the formation of a thinned gate-adjacent active region trench of the types shown in FIGS. 2A-2B, 3A-3B, and 4A- 4B, utilizing a LOCOS process as one example method of fabrication.

[0025] FIG. 6 is a process flow chart summarizing the method illustrated in FIGS. 5A-5D.

[0026] FIG. 7 is a stylized plan view of a MOSFET DSU having a single gate “finger” G positioned between an adjacent source region S and an adjacent drain region D.Attorney Docket No.: P3117-PCT

[0027] FIG. 8 is a stylized plan view of a stack of two serially-connected DSUs each having multiple gate fingers G interspersed between adjacent source region and drain regions S, D.

[0028] FIG. 9 is a stylized plan view of a stack of four series-connected single-gate DSUs.

[0029] FIG. 10 is a stylized plan view of a first example stack of two series-connected multigate thin-gate DSUs.

[0030] FIG. 11 is a stylized plan view of a second example stack of two series-connected multigate thin-gate DSUs.

[0031] FIG. 12 is a stylized plan view of a third example stack of two series-connected multigate DSUs.

[0032] FIG. 13 is a stylized plan view of a fourth example stack of two series-connected multigate thin-gate DSUs.

[0033] FIG. 14A is a stylized plan view of a fifth example stack of two series-connected multigate thin-gate DSUs.

[0034] FIG. 14B is a stylized cross-sectional view of the example of FIG. 14A, showing just the substrate. BOX layer, and partially thinned active region.

[0035] FIG. 15A is a stylized plan view of a sixth example stack of two series-connected multigate DSUs.

[0036] FIG. 15B is a stylized cross-sectional view of the example of FIG. 15 A, showing just the substrate, BOX layer, and partially thinned active region.

[0037] FIG. 16 is a stylized cross-sectional view of an example stack of DSUs showing three MOSFET devices with different configurations (the source and drain regions are not marked to avoid clutter).

[0038] FIG. 17 is a top plan view of a substrate that may be, for example, a printed circuit board or chip module substrate (e.g., a thin-film tile).Attorney Docket No.: P3117-PCT

[0039] Like reference numbers and designations in the various drawings indicate like elements unless the context requires otherwise.Attorney Docket No.: P3117-PCTDETAILED DESCRIPTION

[0040] Embodiments of the present invention encompass MOSFETs that operate with high linearity under a high RF voltage swing. MOSFETs made in accordance with the present invention have increased bandwidth and maximum-voltage handling ability compared to conventional designs and are particularly well suited for use as RF switches. Embodiments utilize an integrated circuit (IC) structure that includes modification of the active region beneath a gate structure (the channel region) to be thinner than the active region utilized for the source and drain regions, without needing epitaxy. The differentiated channel thickness versus source-drain thickness of the active region enables a simultaneous improvement in reducing ON-resistance RON while increasing the operating RF voltage swing (including breakdown voltage VBD), and additionally reduces the form factor or area of the RF switch, resulting in high-performing devices.

[0041] Device stack units (DSUs) of one or more MOSFETs may be configured as segmented devices having one or more gate “fingers” interspersed between adjacent source and drain regions and generally configured to behave as a single transistor. Multiple DSUs may be coupled in series and / or parallel for various applications. Series connection of multiple DSUs provides higher VBD values, while parallel connection of multiple DSUs provides higher current carrying capability. Selective usage within one or more DSUs of thin sub-gate regions in accordance with the present invention may improve the peak voltage (VPEAK) and OFF capacitance (COFF) characteristics of such DSUs with little or no adverse impact on ON resistance (RON), and potentially improving current leakage. VPEAK is the maximum applied RF voltage that a device can withstand, and VBD is the maximum applied DC voltage that a device can withstand; usually they are similar values for a particular device.

[0042] In a conventional MOSFET of the type shown in FIG. 1, the drain-to- source breakdown voltage VBD is improved by thinning the entire active region 102 for a MOSFET device (including beneath the gate structure and in the source and drain regions). Thinning the active region 102 for an entire MOSFET device may be accomplished, for example, by using a local oxidation of silicon (LOCOS) process to reduce the thickness IAR of the active region 102. Such device-wide thinning enables better control by the gate structure 112 of conduction within the channel 126, and thus provides a higher VBD value. However, thinning the active region 102 in the source and drain regions increases RON, thus reducing performance.Attorney Docket No.: P3117-PCT

[0043] Further, as the active region 102 is thinned, less active region material remains between the bottom-edge of the source and drain salicide layers 124S, 124D and the top-edge of the BOX layer 104 (this separation is denoted as IAR_SD in FIG. 1). Smaller values of t,\i< so lead to increasingly unfavorable interaction between the source and drain salicide layers 124S, 124D and the BOX layer 104 and resultant increases in RON and charge leakage, to the point where the MOSFET device becomes non-functional as IAR_SD approaches zero (at which point the source and drain salicide layers 124S, 124D contact the BOX layer 104).

[0044] Salicide piping is another adverse effect, where the salicide laterally encroaches on the channel underneath the gate structure and adversely impacts reliability and gate-length scaling.

[0045] Embodiments of the present invention overcome the limitations of conventional MOSFET designs by thinning the active region 102 only under the gate structure 112, while maintaining thicker active region material in the source region 108 and drain region 110 in order to space the source and drain salicide layers 124S, 124D away from the BOX layer 104. The gate structure 112 of a MOSFET device is thus fabricated within a trench formed in the active region 102 between the source region 108 and drain region 110. The inventive structure reduces RON compared to conventional MOSFET designs due to the thicker layer of active region material in the source region 108 and drain region 110, while maintaining a high breakdown voltage VBD due to the thin layer of active region material underneath the gate structure 112. Importantly, no epitaxial regrowth of active region material (e.g., Si or SiGe) is required to create raised source and drain contacts. Further, MOSFETs fabricated in accordance with the present invention can have shorter gate lengths LG.

[0046] MOSFET devices in accordance with the present invention may be implemented in at least three variants, differing with respect to the bottom length LTHIN_SD of the thinned gate- adjacent active region trench compared to the gate length LG of the device. Selective thinning of the gate-adjacent active region may be accomplished using a LOCOS process and / or by dry or wet etching as described in greater detail below.

[0047] FIG. 2A is a cross-sectional view of a MOSFET device 200 in which a thinned gate- adjacent active region trench 202 (within the dashed oval in FIG. 2B) has a top length LTHICK_SD and a bottom length LTHIN_SD that is approximately equal to the gate length LG of the device. FIG.Attorney Docket No.: P3117-PCT2B is a cross-sectional view showing only a profile of the active region 102 of the MOSFET device of FIG. 2A. In the illustrated example, the active region 102 has a thickness (in the Z dimension) of tAR. The bottom of the trench 202 is spaced a distance AtAR from the top-surface of the active region 102 (that is, the depth of the trench 202 is AIAR). Depending on the etching process selected to form the trench 202, the sidewalls of the trench may slope at an angle <t> that may be designed to be within the range of about 5° to about 90° (at which point LTHIN_SD is approximately equal to LTIIICK_SD). The sloped regions of the trench 202 fall between the overlaying gate material 120 (e.g., polysilicon) and the source and drain salicide layers 124S, 124D.

[0048] In the configuration shown in FIGS. 2A and 2B, the gate structure 112 is fabricated within the thinned gate-adjacent active region trench 202 closer to the BOX layer 104, thus providing for a relatively high breakdown voltage VBD. Notably, the adverse effects of conventional designs are avoided by not overly thinning the source region 108 and drain region 110, thus avoiding increased RON.

[0049] FIG. 3A is a cross-sectional view of a MOSFET device 300 in which a thinned gate- adjacent active region trench 302 (within the dashed oval in FIG. 3B) has a top length LTHICKJSD and a bottom length ETHIN_SD that is less than the gate length EG of the device. FIG. 3B is a cross- sectional view showing only a profile of the active region 102 of the MOSFET device of FIG. 3A. The active region 102 has a thickness of tAR and the bottom of the trench 302 is spaced a distance AtAR from the top-surface of the active region 102. Depending on the etching process selected to form the trench 302, the sidewalls of the trench may slope at an angle that may be designed to be within the range of about 5° to about 90°. The sloped regions of the trench 302 fall underneath the gate material 120, with the active region being thicker at the edges of the gate material 120.

[0050] In the configuration shown in FIGS. 3A and 3B, the gate structure 112 is fabricated within the thinned gate-adjacent active region trench 202 closer to the BOX layer 104, thus providing for a relatively high breakdown voltage VBD. Notably, the adverse effects of conventional designs are avoided by not overly thinning the source region 108 and drain region 110, thus avoiding increased RON. The gate structure 112 (particularly the insulator 118) deposition will conform to the slope of the sidewalls of the trench 302. This configuration helps in reducing the peak electric field at the gate-drain edge as the gate material 120 extension over the sidewallAttorney Docket No.: P3117-PCT slopes behaves as a gate-connected field plate. In variants, the insulator 118 may be formed to be thicker or thinner in the sloped regions versus the bottom region of the trench 302. Further, the insulator 118 may comprise materials with different dielectric constants in the sloped regions versus the bottom region of the trench 302, since the crystal plane of the active region 102 material (e.g., Si) may be different along the slopes compared to the region. Electric field profiles may be adjusted via etching across the different crystal plane in the sloped regions, and off-axis cut substrates may also be used to adjust the electric field profiles along the sloped regions. In some embodiments, a second thinning (e.g., by a LOCOS process) may be performed to further adjust the slope profiles to make a T-shaped gate with a gate-connected extension or field-plate.

[0051] FIG. 4A is a cross-sectional view of a MOSFET device 400 in which a thinned gate- adjacent active region trench 402 (within the dashed oval in FIG. 4B) has a top length LTHICKJSD and a bottom length LTHIN_SD that is greater than the gate length LG of the device. FIG. 4B is a cross-sectional view showing only a profile of the active region 102 of the MOSFET device of FIG. 4A. The active region 102 has a thickness of tAR and the top-surface of the trench 402 is spaced a distance AtAR from the bottom of the active region 102. Depending on the etching process selected to form the trench 402, the sidewalls of the trench may slope at an angle that may be designed to be within the range of about 5° to about 90°. The sloped regions of the trench 402 fall within the source and drain salicide layers 124S, 124D, spaced away from the gate material 120. The source and drain salicide layers 124S, 124D and overlying metal source S and drain D contacts (shown only schematically) will generally conform to the slope regions of the trench 402, which helps in reducing RON as LG is scaled down.

[0052] In example embodiments of MOSFET devices fabricated in accordance with the present invention on an active region 102 having a thickness tAR of about 55 nm, the device gate length LG has been within the range of 5-200 nm, LTHIN_SD has been in the range of 5-200 nm, and AtAR has been in the range of about 2-45 nm (about 3.6% to 81.8% of tAR in this example). In some of these examples, for a gate length LG of about 180 nm, an approximately 6% improvement in VBD has been measured with a AtAR of about 8 nm (about 14.6% of tAR in this example), and it is estimated by extrapolation of a linear fit that an approximately 12% improvement in VBD can be achieved with a AtAR of about 16 nm (about 29.1% of tAR in this example). As LG is reduced, VBDAttorney Docket No.: P3117-PCT will increase. This invention thus enables ultra-low LG and improved VBD performance MOSFET devices compared to conventional designs.

[0053] FIGS. 5A-5D are cross-sectional views of different stages in the formation of a thinned gate-adjacent active region trench of the types shown in FIGS. 2A-2B, 3A-3B, and 4A-4B, utilizing a EOCOS process as one example method of fabrication.

[0054] FIG. 5A shows a Si active region 102 formed on a BOX layer 104 (e.g.. SiO2) which in turn is formed on top of a substrate 106 (e.g., Si).

[0055] FIG. 5B shows a SiO2 layer 502 (often called a pad oxide) formed on the Si active region 102, such as by thermal oxidation. A masking layer 504 (e.g., silicon nitride SislS ) is formed on the SiO2 layer 502, such as by chemical-vapor deposition (CVD), and masked and etched (patterned) to define an opening 506 for the gate structure 112 of a MOSFET device (see FIGS. 2A, 3A, 4A). Across an integrated circuit die, there may be hundreds to millions or more of such openings 506 for MOSFET device gates.

[0056] FIG. 5C shows that the structure shown in FIG. 5B is subjected to thermal oxidation, which transforms part of the active region Si material underneath the opening 506 into SiO2. As the SiO2 forms, it may expand upwards and sideways sufficiently to deform adjacent edges of the masking layer 504 and will generally form sloped edges (also referred to as “bird beak” profile). Other etching techniques, such as dry or wet etching, will generally leave similar sloped edges (but, as noted above, the sidewall angle that may be about 90°, typically produced by etching techniques other than the LOCOS process).

[0057] FIG. 5D shows that the masking layer 504 and SiO2 layer 502 have been stripped away, leaving a thinned gate-adjacent active region trench 508 (within the dashed oval). A gate structure 112 and remaining MOSFET regions and structures may then be formed in conventional fashion to create the structures shown in FIGS. 2 A, 3 A, and 4A.

[0058] FIG. 6 is a process flow chart 600 summarizing the method illustrated in FIGS. 5A-5D. The example process includes: forming a Si active region on a BOX layer (e.g., SiO2) formed on top of a substrate (e.g., Si) [Block 602]; forming a S1O2 layer on the Si active region [Block 604]; forming a masking layer on the SiO2 layer [Block 606]; patterning the masking layer to define anAttorney Docket No.: P3117-PCT opening for the gate structure of at least one MOSFET device [Block 608]; applying a thermal oxidation process to thin the active region under the opening [Block 610]; and stripping away the masking layer and S1O2 layer, leaving a thinned gate-adjacent active region trench [Block 612],

[0059] FIG. 7 is a stylized plan view of a MOSFET DSU 700 having a single gate “finger” G positioned between an adjacent source region S and an adjacent drain region D. FIG. 8 is a stylized plan view of a stack of two serially-connected DSUs 802, 804 each having multiple gate fingers G interspersed between adjacent source region and drain regions S, D. As illustrated, some regions between adjacent gate fingers G are shared, comprising a drain region D with respect to a first adjacent gate finger G and a source region S with respect to a second adjacent gate finger G. Each gate finger G has an associated gate length LG (measured in the X dimension).

[0060] The stack of DSUs 802, 804 generally would be fabricated as part of the same IC. An electrical connection 806 (shown schematically) connecting the stacked serially-connected DSUs 802, 804 may be implemented, for example, within the superstructure of the IC. The DSUs in the examples illustrated in FIGS. 7 and 8 may be conventional MOSFETs or MOSFETs having thin sub-gate regions, as described in this disclosure (a thin sub-gate region in the latter case is generally not visually apparent in a top plan view). More than two DSUs may be serially-connected as needed, for example, to handle larger applied voltages in a switch circuit.

[0061] With decreasing IC die size and / or denser layouts, parasitic capacitance can increase, which degrades VPEAK and COFF for at a specified RON. For example, IC electrical connection bumps may overlap some or all DSUs within a stack in order to achieve a smaller IC footprint. Resulting parasitic capacitance degrades the VPEAK characteristic of the entire stack. For example, FIG. 9 is a stylized plan view of a stack of four series-connected single-gate DSUs 902a-902d. The end DSUs 902a, 902d are overlaid by electrical connection bumps 904, 906, which would be fabricated as part of the IC superstructure. As should be apparent, the conductive bumps 904, 904 can present as parasitic capacitances influencing the underlying DSUs 902a, 902d, but may present little or no parasitic capacitance with respect to the other DSUs 902b, 902c. Further, in a multigate DSU, some gate fingers may be affected by such parasitic capacitance while other gate fingers may be less affected or not affected at all. Other sources of parasitic capacitance with respect to a DSU may include adjacent circuitry and internal circuit connections within an IC superstructure.Attorney Docket No.: P3117-PCTOne or more similar stacks of series-connected (with single or multiple gate fingers) DSUs may be coupled in parallel with the stack illustrated in FIG. 9.

[0062] The adverse effect on VPEAK due to parasitic capacitance may be overcome in part by using capacitive compensation circuitry known in the art. However, capacitive compensation to optimize VPEAK becomes harder to implement as transistor and device stack sizes scale down to smaller areas.

[0063] Another behavior that may be exhibited by a multi-gate DSU is high electric fields near some gate fingers, when all gate fingers should exhibit the same VPEAK value.

[0064] One aspect of the present invention is the ability to tailor DSUs to have one or more thin sub-gate regions of the types shown in FIGS. 2A-2B (LTHIN_SD = LG), FIGS. 3A-3B (LTHIN_SD < LG), and / or FIGS. 4A-4B (LTHIN_SD > LG). By judicious use of thin sub-gate regions, the VPEAK, COFF, and / or RON characteristics of one or more DSUs, standing alone or as part of a stack of DSUs, can be adjusted to compensate for parasitic capacitances and / or equalize internal VPEAK values among gate fingers. In the general case, embodiments of this aspect of the invention include a stack of one or more DSUs in which at least one DSU has one or more gate fingers fabricated with a thin sub-gate region that has an LTHIN_SD dimension selected to be less than, equal to, or greater than the associated gate length LG, and in which the sidewall angle <t> for one or more gate fingers G may be selected to adjust VPEAK as may be needed. A DSU having at least one gate finger G fabricated over an associated thin sub-gate region (including a single gate-finger DSU) may be referred to as a “thin-gate DSU”.

[0065] FIG. 10 is a stylized plan view of a first example stack of two series-connected multigate thin-gate DSUs 1002a, 1002b. In the illustrated example, each gate finger G is fabricated over an associated thin sub-gate region, as indicated by the shading of each gate finger G. This type of configuration improves VPEAK for the entire stack height without needing adjustments to mitigate RON tradeoff and is simple to fabricate due to the uniformity of each DSU. As should be clear, additional similar thin-gate DSUs may be included in the stack.

[0066] FIG. 11 is a stylized plan view of a second example stack of two series-connected multigate thin-gate DSUs 1102, 1104. In the illustrated example, only some gate fingers G are fabricatedAttorney Docket No.: P3117-PCT over an associated thin sub-gate region, as indicated by the darker shading of such gate fingers G. In the illustrated example, the left-most DSU 1102 has two thin sub-gate regions, while the rightmost DSU 1104 has one thin sub-gate region. The remaining unshaded gate fingers G are conventional (e.g., having equal-thickness source, drain, and gate regions within the substrate). As the example shows, the thin-gate DSUs 1102, 1104 need not have (but may have) the same number of gate fingers G fabricated over an associated thin sub-gate region. This type of configuration allows designing for non-uniform voltage distributions in order to increase the VPEAK of any gate fingers G that are in high electric field regions by using a thin sub-gate region for such gate fingers G.

[0067] FIG. 12 is a stylized plan view of a third example stack of two series-connected multigate DSUs 1202, 1204. In the illustrated example, all of the gate fingers G of the left-most DSU 1202 are conventional (e.g., having equal-thickness source, drain, and gate regions within the substrate). In contrast, the right-most DSU 1204 is a thin-gate DSU in which some or all of the gate fingers G are fabricated over an associated thin sub-gate region, as indicated by the darker shading of such gate fingers G. In the illustrated example, the right-most DSU 1204 has two thin sub-gate regions. This type of configuration allows for selective sub-gate thinning for some or all of the gate fingers G in certain DSUs that experience higher peak electric fields (e.g., due to parasitic capacitances) while using conventional gates for DSUs experiencing lower peak electric fields field. This type of configuration also extends the range of capacitive compensation while keeping COFF low, improving VPEAK, and exhibiting lower leakage.

[0068] Another design variable that may be beneficially used to compensate for parasitic capacitance and / or local variations in VPEAK is the bottom length LTHIN_SD of a thinned gate- adjacent active region trench relative to the associated gate length LG. For example, FIG. 13 is a stylized plan view of a fourth example stack of two series-connected multi-gate thin-gate DSUs 1302, 1304. In the illustrated example, some of the gate fingers G 1306 of the left-most thin-gate DSU 1302 are fabricated with a first relationship between LTHIN_SD and LG (e.g., LTHIN.SD = LG, indicated by the dark shading of such gate fingers G 1306), while the remaining fingers 1308 are conventional, having equal-thickness source, drain, and gate regions within the substrate. Some of the gate fingers G 1310 of the right-most thin-gate DSU 1304 are fabricated with a secondAttorney Docket No.: P3117-PCT relationship between LTHIN_SD and LG (e.g., LTHIN SD < LG, indicated by the even darker shading of such gate fingers G 1310), while the remaining fingers 1308 are conventional.

[0069] Varying LTHINJSD with respect to LG provides for fine adjustment of the VPEAK of a thin- gate DSU as a whole, as an alternative or in addition to capacitive compensation. Each of multiple fingers within a single thin-gate DSU may have a different relationship between LTHIN_SD and LG, allowing for an additional fine adjustment control. Varying the sidewall angle 0 of a thin sub-gate region for a gate finger G (particularly where LTHIN_SD < LG, as in FIGS. 3A-3B) also provides for additional control of VPE K.

[0070] Another design variable that may be beneficially used to improve VPEA is the thickness of the active region 102. FIG. 14A is a stylized plan view of a fifth example stack of two series- connected multi-gate thin-gate DSUs 1402, 1404. In the illustrated example, each DSU 1402, 1404 has two thin sub-gate regions 1406 and two conventional devices 1408, and in that regard - mixing of thin sub-gate regions 1406 and conventional devices 1408 - the embodiment of FIG. 14A is similar to the embodiment of FIG. 11. FIG. 14B is a stylized cross-sectional view of the example of FIG. 14A, showing just the substrate 106, BOX layer 104, and partially-thinned active region 102.

[0071] In the embodiment shown in FIGS. 14A and 14B, the active region 102 has been selectively thinned under the gate structures 112 and at least one of the associated source region 108 and drain region 110 for at least one device (see also FIGS. 2A, 3A, 4A). For example, in FIG. 14A, dotted outlines 1412 and 1414 indicate MOSFETs for which the active region 102 has been thinned. FIG. 14B shows the thinned sub-gate regions 1406 within the partially-thinned active region 102 (but otherwise omits the details of the overlying gate structures 112). The adjacent regions of each DSU 1402, 1404 have a thicker active region 102. Note that thin sub-gate regions 1406 may also be fabricated in the portions of a DSU that have a thicker active region 102, but generally would have different VPE K and RON characteristics compared to thin sub-gate regions 1406 fabricated in the portions of a DSU that have a thin active region 102. MOSFETs having thin sub-gate regions 1406 that are fabricated on a thinned portion 1412, 1414 of the active region 102 may be referred to as “doubly-thinned MOSFETs”. Such active region thinning for an entire MOSFET device improves VPEAK for the device. When combining conventional devices 1408Attorney Docket No.: P3117-PCT(e.g., having equal-thickness source, drain, and gate regions within the substrate) with thin subgate regions 1406, RON can be kept low, and accordingly both VPEAK and RON improve compared to conventional stacks with no thinning at all.

[0072] Such “entire device” thinning of the active region 102 may be selectively limited to certain areas of an IC layout that may differ from one stack to another stack in order to manage leakage. For instance, the circuit regions in one stack that are known to have high leakage can be fabricated on a thick active region 102 while the active region 102 for other circuit regions in that stack can be thinned.

[0073] Additionally, which “entire device” active regions are thin and which “entire device” active regions are thick can change from one DSU to another DSU. For example, FIG. 15A is a stylized plan view of a sixth example stack of two series-connected multi-gate DSUs 1502, 1504. FIG. 15B is a stylized cross-sectional view of the example of FIG. 15A, showing just the substrate 106, BOX layer 104, and partially thinned active region 102. In the illustrated example, DSU 1502 has two thin sub-gate regions 1506 and two conventional devices 1508 (e.g., having equalthickness source, drain, and gate regions within the substrate), while DSU 1504 has all conventional devices 1508, and is thus similar to the embodiment of FIG. 12 (DSU 1502 may also comprise only thin sub-gate regions 1506). However, DSU 1502 may have a thin overall active region 102 (indicated by a dotted outline 1512) while DSU 1504 may have a thicker overall active region 102. FIG. 15B also shows the thinned sub-gate regions 1506 within the active region 102 (but otherwise omits the details of the overlying gate structures 112). Such a configuration will generally improve overall VPEAK from having thin sub-gate regions 1506 in DSU 1502 and overall RON should improve from including DSU 1504 with a thicker active region 102.

[0074] Many other configurations of thin-gate MOSFETs, doubly-thinned MOSFETs, and conventional MOSFETs are possible. As just one example, FIG. 16 is a stylized cross-sectional view of an example stack of DSUs showing three MOSFET devices with different configurations (the source and drain regions are not marked to avoid clutter). In the illustrated example, a thin portion of the active region 102 (with thickness tl) includes a thin-gate MOSFET 1602 (which is thus a doubly-thinned MOSFET) and a conventional MOSFET 1604. A thicker portion of the active region 102 (with thickness t2) includes a thin-gate MOSFET 1606 and a conventionalAttorney Docket No.: P3117-PCTMOSFET 1608. Of course, either or both of the thin portion and the thick portion of the active region 102 may have many instances of the devices shown in FIG. 16.

[0075] While FIGS. 10-15 each illustrate two serially-connected DSUs, more than two DSUs may be serially-connected as needed, for example, to handle larger applied voltages in a switch circuit, and / or may be parallel-connected as needed, for example, to handle larger current flow in a switch circuit. Further, for thin-gate DSUs having multiple gate fingers G, the pattern and number of gate fingers G fabricated over an associated thin sub-gate region may vary from the illustrated examples. Thus, for a thin-gate DSU having N gate fingers G, where N > 1, any number of gate fingers G up to and including N may each be fabricated over an associated thin sub-gate region, wherein the associated thin sub-gate region has a specified relationship between LTHIN_SD and EG and / or sidewall angle <t>.

[0076] Table 1 below shows the relative performance values for three different stack-of-2 DSU configurations using modeled circuits. A conventional stack-of-2 DSUs is shown in Row 1. Compared to Row 1, Row 2 shows higher VPEAK and lower COFF values for a stack-of-2 DSUs in the configuration shown in FIG. 10 (all gate fingers G in both DSUs are fabricated over associated thin sub-gate regions). Compared to Row 1, Row 3 also shows higher VPEAK and lower COFF values for a stack-of-2 DSUs in the configuration shown in FIG. 12 (serially-connected conventional DSU and thin-gate DSU, where some or all gate fingers G in the thin-gate DSU are fabricated over associated thin sub-gate regions). Use of thin-gate DSUs has no negative impact on RON, and exhibits up to a 5% improvement in VPEAK and up to a 6% improvement in COFF.TABLE 1Attorney Docket No.: P3117-PCT

[0077] Circuits and devices in accordance with the present invention may be used alone or in combination with other components, circuits, and devices. Embodiments of the present invention may be fabricated as integrated circuits (ICs), which may be encased in IC packages and / or in modules for ease of handling, manufacture, and / or improved performance. In particular, IC embodiments of this invention are often used in modules in which one or more of such ICs are combined with other circuit components or blocks (e.g., filters, amplifiers, passive components, and possibly additional ICs) into one package. The ICs and / or modules are then typically combined with other components, often on a printed circuit board, to form part of an end-product such as a cellular telephone, laptop computer, or electronic tablet, or to form a higher-level module which may be used in a wide variety of products, such as vehicles, test equipment, medical devices, etc. Through various configurations of modules and assemblies, such ICs typically enable a mode of communication, often wireless communication.

[0078] As one example of further integration of embodiments of the present invention with other components, FIG. 17 is a top plan view of a substrate 1700 that may be, for example, a printed circuit board or chip module substrate (e.g., a thin-film tile). In the illustrated example, the substrate 1700 includes multiple ICs 1702a- 1702d having terminal pads 1704 which would be interconnected by conductive vias and / or traces on and / or within the substrate 1700 or on the opposite (back) surface of the substrate 1700 (to avoid clutter, the surface conductive traces are not shown and not all terminal pads are labelled). The ICs 1702a-1702d may embody, for example, signal switches, active and / or passive filters, amplifiers (including one or more LNAs), and other circuitry. For example, ICs 1702a- 1702d may incorporate one or more instances of a circuit that includes MOSFET devices such as are shown in FIGS. 2A, 3 A, and 4A.

[0079] The substrate 1700 may also include one or more passive devices 1706 embedded in, formed on, and / or affixed to the substrate 1700. While shown as generic rectangles, the passive devices 1706 may be, for example, filters, capacitors, inductors, transmission lines, resistors, antennae elements, transducers (including, for example, MEMS-based transducers, such as accelerometers, gyroscopes, microphones, pressure sensors, etc.), batteries, etc., interconnected by conductive traces on or in the substrate 1700 to other passive devices 1706 and / or the individual ICs 1702a-1702d.Attorney Docket No.: P3117-PCT

[0080] The front or back surface of the substrate 1700 may be used as a location for the formation of other structures. For example, one or more antennae may be formed on or affixed to the front or back surface of the substrate 1700; one example of a front-surface antenna 1708 is shown, coupled to an IC die 1702b, which may include RF front-end circuitry. Thus, by including one or more antennae on the substrate 1700, a complete radio may be created.

[0081] Embodiments of the present invention are useful in a wide variety of larger radio frequency (RF) circuits and systems for performing a range of functions, including (but not limited to) impedance matching circuits, RF power amplifiers, RF low-noise amplifiers (LNAs), phase shifters, attenuators, antenna beam-steering systems, charge pump devices, RF switches, etc. Such functions are useful in a variety of applications, such as radar systems (including phased array and automotive radar systems), radio systems (including cellular radio systems), and test equipment.

[0082] Radio system usage includes wireless RF systems (including base stations, relay stations, and hand-held transceivers) that use various technologies and protocols, including various types of orthogonal frequency-division multiplexing (“OFDM”), quadrature amplitude modulation (“QAM”), Code-Division Multiple Access (“CDMA”), Time-Division Multiple Access (“TDMA”), Wide Band Code Division Multiple Access (“W-CDMA”), Global System for Mobile Communications (“GSM”), Long Tenn Evolution (“LTE”), 5G, 6G. and WiFi (e.g., 802.11a, b, g, ac, ax, be) protocols, as well as other radio communication standards and protocols.

[0083] The term “MOSFET”, as used in this disclosure, includes any field effect transistor (FET) having an insulated gate whose voltage or charge level determines the conductivity of the transistor, and encompasses insulated gates having a metal or metal-like, insulator, and / or semiconductor structure. The terms “metal” or “metal-like” include at least one electrically conductive material (such as aluminum, copper, or other metal, or highly doped polysilicon, graphene, or other electrical conductor), “insulator” includes at least one insulating material (such as silicon oxide or other dielectric material), and “semiconductor” includes at least one semiconductor material.

[0084] As used in this disclosure, the term “radio frequency” (RF) refers to a rate of oscillation in the range of about 3 kHz to about 300 GHz. This term also includes the frequencies used inAttorney Docket No.: P3117-PCT wireless communication systems. An RF frequency may be the frequency of an electromagnetic wave or of an alternating voltage or current in a circuit.

[0085] With respect to the figures referenced in this disclosure, the dimensions for the various elements are not to scale; some dimensions may be greatly exaggerated vertically and / or horizontally for clarity or emphasis. In addition, references to orientations and directions (e.g., “top”, “bottom”, “above”, “below”, “lateral”, “vertical”, “horizontal”, etc.) are relative to the example drawings, and not necessarily absolute orientations or directions.

[0086] Various embodiments of the invention can be implemented to meet a wide variety of specifications. Unless otherwise noted above, selection of suitable component values is a matter of design choice. Various embodiments of the invention may be implemented in any suitable integrated circuit (IC) technology (including but not limited to MOSFET structures), or in hybrid or discrete circuit forms. Integrated circuit embodiments may be fabricated using any suitable substrates and processes, including but not limited to standard bulk silicon, high-resistivity bulk CMOS, silicon-on-insulator (SOI), and silicon-on-sapphire (SOS). Unless otherwise noted above, embodiments of the invention may be implemented in other transistor technologies, such as BiCMOS, LDMOS, BCD, GaAs HBT, GaN HEMT, GaAs pHEMT, MESFET, InP HBT, InP HEMT, FinFET, GAAFET, trench-gate vertical FETs (VDMOS), and SiC-based device technologies, using 2-D, 2.5-D, and 3-D structures. However, embodiments of the invention are particularly useful when fabricated using an SOI or SOS based process, or when fabricated with processes having similar characteristics. Fabrication in CMOS using SOI or SOS processes enables circuits with low power consumption, the ability to withstand high power signals during operation due to FET stacking, good linearity, and high frequency operation (i.e., radio frequencies up to and exceeding 300 GHz). Monolithic IC implementation is particularly useful since parasitic capacitances generally can be kept low (or at a minimum, kept uniform across all units, permitting them to be compensated) by careful design.

[0087] A number of embodiments of the invention have been described. It is to be understood that various modifications may be made without departing from the spirit and scope of the invention. For example, some of the steps described above may be order independent, and thus can be performed in an order different from that described. Further, some of the steps describedAttorney Docket No.: P3117-PCT above may be optional. Various activities described with respect to the methods identified above can be executed in repetitive, serial, and / or parallel fashion.

[0088] It is to be understood that the foregoing description is intended to illustrate and not to limit the scope of the invention, which is defined by the scope of the following claims, and that other embodiments are within the scope of the claims. In particular, the scope of the invention includes any and all feasible combinations of one or more of the processes, machines, manufactures, or compositions of matter set forth in the claims below. (Note that the parenthetical labels for claim elements are for ease of referring to such elements, and do not in themselves indicate a particular required ordering or enumeration of elements; further, such labels may be reused in dependent claims as references to additional elements without being regarded as starting a conflicting labeling sequence).

Claims

Attorney Docket No.: P3117-PCTCLAIMSWHAT IS CLAIMED IS:

1. An integrated circuit including one or more device stack units (DSUs), each comprising one or more MOSFETs, wherein at least one of the one or more DSUs is a thin-gate DSU.

2. The integrated circuit of claim 1, wherein at least two DSUs are coupled in series.

3. The integrated circuit of claim 1, wherein at least two DSUs are coupled in parallel.

4. The integrated circuit of claim 1, wherein the integrated circuit includes a thin active region, and the thin-gate DSU is fabricated on the thin active region.

5. The integrated circuit of claim 1, wherein the integrated circuit includes a thick active region, and the thin-gate DSU is fabricated on the thick active region.

6. The integrated circuit of claim 1, wherein the integrated circuit includes a thin active region and a thick active region, and the thin-gate DSU is fabricated on the thin active region.

7. The integrated circuit of claim 1, wherein the integrated circuit includes a thin active region and a thick active region, and the thin-gate DSU is fabricated on the thick active region.

8. The integrated circuit of claim 1, wherein the integrated circuit includes a thin active region and a thick active region, and a first thin-gate DSU is fabricated on the thin active region and a second thin-gate DSU is fabricated on the thick active region.

9. A device stack unit (DSU) comprising one or more MOSFETs, the DSU having at least one gate finger fabricated over an associated thin sub-gate region.

10. The DSU of claim 9, wherein the DSU includes A / gate fingers G, where N> 1 , wherein up to and including N gate fingers may each be fabricated over an associated thin sub-gate region.

11. The DSU of claim 10, wherein each gate finger has a gate length LG and wherein the associated thin sub-gate region has an associated bottom length LTHIN_SD having a specified relationship to the associated gate length LG.Attorney Docket No.: P3117-PCT12. The DSU of claim 1 1 , wherein a first gate finger has a first specified relationship between the associated bottom length LTHIN_SD of the associated thin sub-gate region and the associated gate length LG of the first gate finger, and a second gate finger has a second specified relationship between the associated bottom length LTHIN_SD of the associated thin sub-gate region and the associated gate length LG of the second gate finger.

13. The DSU of claim 9, wherein each gate finger includes an associated gate length LG and wherein, for each gate finger fabricated over an associated thin sub-gate region, the associated thin sub-gate region has a bottom length LTHIN_SD selected to be less than, equal to, or greater than the associated gate length LG.

14. The DSU of claim 9, wherein each gate finger includes an associated VPEAK value, and wherein, for each gate finger fabricated over an associated thin sub-gate region, the associated VPEAK value may be adjusted by varying an associated bottom length LTHIN SD of the associated thin sub-gate region in relation to an associated gate length LG of the gate finger.

15. The DSU of claim 9, wherein each gate finger includes an associated VPEAK value, and wherein, for each gate finger fabricated over an associated thin sub-gate region, the VPEAK value may be adjusted by varying a sidewall angle <t> of the associated thin sub-gate region associated with the gate finger.

16. A stack of one or more device stack unit (DSUs) in which at least one DSU includes one or more gate fingers fabricated with a thin sub-gate region, wherein each of the one or more gate fingers includes an associated VPEAK value and the associated thin sub-gate region includes an associated bottom length LTHIN_SD, wherein the associated bottom length LTHIN_SD may be selected to adjust the associated VPEAK value.

17. The stack of one or more DSUs of claim 16, wherein for at least one gate finger of the one or more gate fingers, the associated VPEAK value may be adjusted by varying the associated bottom length LTHIN_SD in relation to an associated gate length LG of the at least one gate finger.

18. The stack of one or more DSUs of claim 16, wherein for at least one gate finger of the one or more gate fingers, the associated VPEAK value may be adjusted by varying a sidewall angle of the associated thin sub-gate region associated with the at least one gate finger.Attorney Docket No.: P3117-PCT19. A device stack unit (DSU) comprising one or more MOSFETs, wherein at least one MOSFET of the one or more MOSFETs includes:(a) an active region formed on an insulating layer and having a first thickness;(b) a gate structure formed in a trench of the active region, the trench having a second thickness less than the first thickness;(c) a source region formed within the first thickness of the active region and adjacent a first side of the gate structure; and(d) a drain region formed within the first thickness of the active region and adjacent a second side of the gate structure.

20. The DSU of claim 19. wherein the gate structure has a gate length of LG, and the trench has a bottom length LTHIN_SD that is approximately equal to the gate length LG.

21. The DSU of claim 19. wherein the gate structure has a gate length of LG. and the trench has a bottom length LTHIN_SD that is less than the gate length LG.

22. The DSU of claim 19, wherein the gate structure has a gate length of LG, and the trench has a bottom length LTHIN_SD that is greater than the gate length LG.

23. The DSU of claim 19, wherein the trench is formed by a local oxidation of silicon process.

24. The DSU of claim 19. wherein the trench is formed by a wet etching process.

25. The DSU of claim 19, wherein the trench is formed by a dry etching process.

26. The DSU of claim 19, wherein the trench has sidewalls that slope at an angle within the range of about 5° to about 90°.

27. The DSU of claim 19, wherein the trench has a depth of between about 3.6% and 81.8% of the first thickness of the active region.

28. A method of making a device stack unit (DSU) comprising one or more MOSFETs, wherein at least one MOSFET of the one or more MOSFET is fabricated with a thin sub-gate region, the method including, for each such at least one MOSFET:(a) forming an active region on an insulating layer, the active region having a first thickness;Attorney Docket No.: P3117-PCT(b) forming a gate structure in a trench of the active region, the trench having a second thickness less than the first thickness;(c) forming a source region within the first thickness of the active region and adjacent a first side of the gate structure; and(d) forming a drain region within the first thickness of the active region and adjacent a second side of the gate structure.

29. The method of claim 28, wherein the gate structure has a gate length of LG, and the trench has a bottom length LTHIN_SD that is approximately equal to the gate length LG.

30. The method of claim 28, wherein the gate structure has a gate length of LG. and the trench has a bottom length LTHIN_SD that is less than the gate length LG.

31. The method of claim 28, wherein the gate structure has a gate length of LG. and the trench has a bottom length LTHIN_SD that is greater than the gate length LG.

32. The method of claim 28, wherein the trench is formed by a local oxidation of silicon process.

33. The method of claim 28, wherein the trench is formed by a wet etching process.

34. The method of claim 28, wherein the trench is formed by a dry etching process.

35. The method of claim 28, wherein the trench has sidewalls that slope at an angle within the range of about 5° to about 90°.

36. The method of claim 28, wherein the trench has a depth of between about 3.6% and 81.8% of the first thickness of the active region.

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