Differential clock signal adjustment

Abstract

Methods, devices, and systems for clock circuit correction. In one aspect, a circuit includes a first input configured to receive a first signal and a second input configured to receive a second signal. The circuit includes a first line coupled to the first input, the first line includes a plurality of first inverters and a second line coupled to the second input, the second line includes a plurality of second inverters. The circuit includes a crossover circuit coupled to the first line at a first node and the second line at a second node. The crossover circuit generates a first correction signal with the first signal from the first node passing through a crossover inverter within the crossover circuit and provides the first correction signal to the second node on the second line to correct the second signal.

Description

[0001] Attorney Docket No. 07136-0126WO1

[0002] DIFFERENTIAL CLOCK SIGNAL ADJUSTMENT

[0003] CROSS-REFERENCE TO RELATED APPLICATION

[0004] This application claims priority to Provisional Application No. 18 / 934,986, originally filed as a Non-Provisional Application on November 1, 2024, titled “Methods and Systems for Adjusting Differential Clock Signals,” previously assigned Serial No. 18 / 934,986, the entire contents of which are incorporated herein by reference.

[0005] TECHNICAL FIELD

[0006] This specification generally relates to electrical circuits, and more specifically, adjusting a differential clock signal in electrical circuits.

[0007] BACKGROUND

[0008] In high-speed communication systems and other digital applications, the integrity and timing of clock signals are crucial for ensuring accurate data transmission and reception. Clock signals serve as a timing reference that coordinates a sequence of operations within electronic circuits, such as data sampling, data processing, data transmission, and data reception. In many modern, data can be transmitted as differential signals, where a pair of clock signals are used to reduce noise and improve signal integrity. However, in practice, these pair of clock signals are often subject to various forms of degradation as these signals propagate through a circuit. These forms of degradation can include, for example, phase misalignment, inter-symbol interference, and jitter, to name a few examples.

[0009] SUMMARY

[0010] To address degradation of differential clock signals in electrical circuits, the techniques described in this application perform various functions to adjust or correct for degradation in the differential clock signals. By adjusting or correcting the clock signal, such as correcting its timing, skew, amplitude, or other characteristics, the differential signals remain synchronized and ensure that the overall system performance is well maintained. By correcting skew misalignments, duty cycle distortions, and other forms of degradation, clock signal improves the reliability and accuracy of high-speed communication systems. Attorney Docket No. 07136-0126WO1

[0011] In some implementations, the specification can provide apparatus, systems and techniques of a clock compensation device that is configured to correct timing discrepancies in differential clock signals. The clock compensation device includes various components that work collectively to generate correction signals to ensure that the differential clock signals maintain synchronization with one another. For example, the clock compensation device can include a position line and a negative line. Each circuit line in the clock compensation device includes various inverters that introduces a specific delay on the signal and flips a logical value of the signal, e g., flips the signal from a logical “1” of high to a logical “0” of low or flights the signal from a logical “0” to a logical “1”.

[0012] In some implementations, the clock compensation device can utilize the signals from the positive line to correct delays detected on the negative line. Similarly, the clock compensation device can utilize the signals from the negative line to correct delays detected on the positive line. In this manner, the differential clock signals remain synchronized according to their respective components. The clock compensation device can be configured, on the fly, to introduce correction signals from the positive line to the negative line or vice versa, depending on the signal of the differential clock signal that is delayed or skewed.

[0013] For example, the clock compensation device can continuously measure clock synchronization between the differential clock signals. If the clock compensation device measures or detects a delay or particular delta between the differential clock signals, the clock compensation device can configure a crossover circuitry between the positive line and negative line to generate and inject appropriate correction signals one or more of the lines causing the delay. As will be further described below, the clock compensation device can configure one or more inverters in the crossover circuitry to connect in different configurations to reduce or remove the detected delay. Once the crossover circuitry is configured in the manner that will retain synchronization between the differential clock signals, then the signal from one line will be passed to the other line according to the configuration.

[0014] In this instance, the clock compensation device corrects the delay by injecting one or more signals from one line, e.g., the corrected signal, at a particular node on the other line. The injection of correction signals at a particular node can remove the delay by summing opposite and time delayed signals. The summation of the opposite and time delayed signals results in one Attorney Docket No. 07136-0126WO1 of the signals removing their overall delay, and correcting time synchronization between the differential clock signals.

[0015] In one general aspect, a circuit includes: a first input configured to receive a first signal; a second input configured to receive a second signal; a first line coupled to the first input, wherein the first line comprises a plurality of first inverters; a second line coupled to the second input, wherein the second line comprises a plurality of second inverters; and a crossover circuit coupled to the first line at a first node and the second line at a second node, wherein the crossover circuit is configured to: generate a first correction signal with the first signal from the first node passing through a crossover inverter within the crossover circuit; and provide the first correction signal to the second node on the second line to correct the second signal.

[0016] The foregoing and other embodiments can each optionally include one or more of the following features, alone or in combination. For example, one embodiment includes all the following features in combination.

[0017] In some implementations, the crossover circuit includes a plurality of switches configured to couple the crossover circuit to the first line at the first node and to the second line at the second node; and a matrix bus configured to set positions of the plurality of switches to select the first node and the second node.

[0018] In some implementations, the circuit includes: a plurality of first nodes along the first line, wherein each first node of the plurality of first nodes is positioned as an input to a corresponding first inverter of the plurality of first inverters; and a plurality of second nodes along the second line, wherein each second node of the plurality of second nodes is positioned as an input to a corresponding second inverter of the plurality of second inverters.

[0019] In some implementations, the circuit includes: a first output connected to an output of the first line; and a second output connected to an output of the second line.

[0020] In some implementations, the circuit includes: a controller coupled to the first output from the first line and the second output from the second line, wherein the controller is configured to: measure a difference between the first output and the second output; determine whether the difference between the first output and the second output satisfies a differential threshold; and in response to determining the difference between the first output and the second output does not satisfy the different threshold, determine a desired adjustment to at least one of the first output or the second output. Attorney Docket No. 07136-0126WO1

[0021] In some implementations, determining the desired adjustment to at least one of the first output or the second output, the circuit is configured to: determine a delay between the first output and the second output; select a configuration of the plurality of switches in the crossover circuit such that the correction signal generated from the first node and provided to the second node compensates for the determined delay, wherein the configuration of the plurality of switches is based on the crossover inverter and at least one of (i) a first inverter of the plurality of first inverters or (ii) a second inverter of the plurality of second inverters.

[0022] In some implementations, the controller is configured to dynamically adjust at least one of (i) a drive strength of the crossover inverter or (ii) a configuration of a plurality of switches in the crossover circuit.

[0023] In some implementations, the controller is configured to dynamically adjust at least one of (i) the drive strength of the crossover inverter or (ii) the configuration of a plurality of switches in the crossover circuit based on at least one of time, skew, or phase discrepancies between the first output and the second output.

[0024] In some implementations, determining the difference between the first output and the second output includes the circuit is configured to determine a slope of a voltage change of the first output and the second output.

[0025] In some implementations, the controller is configured to monitor at least one of an edge slope, a deviation in duty cycle, or a phase skew of the first output and the second output.

[0026] In some implementations, the circuit is configured to assign a configuration of the crossover circuit in response to detecting at least one of the edge slope, the deviation in duty cycle, or the phase skew of the first output and the second output do not satisfy a threshold value.

[0027] In some implementations, the crossover inverter in the crossover circuit is configured to perform duty cycle correction and inter-symbol inference (ISI) equalization.

[0028] In some implementations, the crossover inverter is configured to provide pre-tap equalization by generating the first correction signal based on a delayed and inverted version of the first signal from the first node.

[0029] In some implementations, the crossover inverter includes a programmable driver that is controlled by a set of digital control bits, the set of digital control bits configures the crossover inverter for a drive level strength of the first correction signal. Attorney Docket No. 07136-0126WO1

[0030] The subject matter described in this specification can be implemented in various embodiments and may result in one or more of the following advantages. In some implementations, the techniques described herein provide for a low power and inverter based equalization technique for differential clock signals. The equalization technique can simultaneously perform duty cycle correction and reduce inter-symbol interference (ISI). Typically, traditional approaches may perform these functions separately, requiring multiple inverters and increasing power consumption to perform the duty cycle correction and reducing the ISI. However, the techniques described in this specification can combine both of these functions into a single inverter stage. This improves efficiency, reduces overall power consumption, and ensures that the differential clock signals are corrected with minimal additional circuity.

[0031] For example, this circuitry leverages cross-coupled inverters to reinforce signal inversion and correct for duty cycle mismatches. Simultaneously, the cross-coupled inverters introduce pre-tap equalization. In pre-tap equalization, the components can cancel IS before a peak in the signal, rather than conventional equalization, such as in a post-tap equalization method. The preemptive correction not only reduces signal distortion earlier in the signal path, but also improves accuracy and reduces jitter overall in the differential clock signal.

[0032] Moreover, the techniques described in this specification can provide for a low complexity and high efficiency solution for differential clock signal equalization. This solution is particularly well suited for high speed and low power circuits where timing is of critical importance. For example, each inverter in this solution can perform both duty cycle correction and ISI cancellation, which reduces the number of components and overall power consumption. By performing the ISI cancellation using the pre-tap equalization, the circuitry provides for an earlier correction of signal distortion which improves signal accuracy and further latency. The circuitry can also include a controller that can adjust the gain of each of the equalization inverters proportionally, based on the slope of the output signal, e.g., output of the differential clock signal. This ensures that the controller can make constant adjustments depending on the slope of the output signal without requiring individual adjustments to the gain of selected inverters. Generally, this technique can be applied in both the transmitter and receiver paths, maintaining a clean differential clock signal on both sides of the system. Attorney Docket No. 07136-0126WO1

[0033] The details of one or more embodiments of the subject matter of this specification are set forth in the accompanying drawings and the description below. Other features, aspects, and advantages of the subject matter will become apparent from the description, the drawings, and the claims.

[0034] BRIEF DESCRIPTION OF THE DRAWINGS

[0035] FIG. l is a diagram schematically illustrating an example of a circuit package implementing an intra-chip bidirectional photonic channel.

[0036] FIG. 2 is a diagram schematically illustrating an example analog-mixed signal (AMS) module including an example interface circuitry coupled between an AMS circuitry and a flow control unit (FLIT) circuitry.

[0037] FIG. 3 is a diagram schematically illustrating an example of the AMS circuity illustrated in FIG. 2.

[0038] FIG. 4 is a diagram schematically illustrating an example of a transmitter circuit of the AMS circuitry of FIG. 3.

[0039] FIG. 5 is a diagram schematically illustrating an example of a receiver circuit of the AMS circuitry of FIG. 3.

[0040] FIG. 6 is a diagram schematically illustrating an example of a differential clock circuit that adjusts differential clock signals in the AMS circuitry.

[0041] FIG. 7 is a diagram illustrating an example of pre-cursor and post-cursor correction in the differential clock circuit.

[0042] FIG. 8 is a diagram schematically illustrating an example of a differential clock circuit that detects distortions and adjusts different clock signals in the AMS circuitry according to the detected delays.

[0043] FIG. 9 is a diagram schematically illustrating an example driver circuit that utilizes differential clock corrections.

[0044] FIG. 10 is a diagram schematically illustrating an electro-photonic network with differential clock corrections.

[0045] Like reference numbers and designations in the various drawings indicate like elements. The components shown here, their connections and relationships, and their functions, are meant to be examples only, and are not meant to limit the implementations described and / or claimed in Attorney Docket No. 07136-0126WO1 this document.

[0046] DETAILED DESCRIPTION

[0047] FIG. 1 is a diagram schematically illustrating an example of a circuit package 130 implementing an intra-chip bidirectional photonic channel. Specifically, FIG. 1 illustrates an example of a circuit package 130 implementing an intra-chip bidirectional photonic channel between a first compute node 134-1 and a second compute node 134-2.

[0048] The circuit package 130 can include a photonic integrated circuit (PIC), and an electronic integrated circuit (EIC) such as a digital and mixed-signal application-specific integrated circuit (ASIC). The EIC and PIC can be formed in different layers of the circuit package, which can be referred to as “electronic circuit layer” and “photonic circuit layer,” respectively, one stacked above the other, for example, using copper pillars, bump attachments, or other means to create an electrical interconnect to transmit and receive messages, packets, and / or other data between the EIC and the PIC.

[0049] In some implementations, the EIC includes multiple compute nodes. The compute nodes can communicate with each other over one or more intra-chip bidirectional channels. The intra- chip bidirectional channels can include one or more bidirectional photonic channels, e.g., implemented with optical waveguides in the PIC, and / or one or more electronic channels, e.g., implemented in the circuitry of the EIC. The compute nodes may but need not in all examples be electronic circuits identical or at least substantially similar in design, and as shown, may form “tiles” of the same size arranged in a grid or any other arrangement suitable for performing the computations described herein. Each compute node in the EIC can include one or more circuit blocks serving as processing engines, e.g., a dot product engine, DNN, or a tensor engine.

[0050] In some examples, the compute node can have any combination of processing units or processing elements or processing devices or processing systems such as CPUs, GPUs, TPUs, and the like, and the DNN and tensor engine can also be included or omitted depending on the application. Each compute node can include a message router. The message routers interface with channels, e.g., electronic and / or photonic channels to facilitate data flow to and from the compute nodes. Further, the compute node can have a memory system, e.g., including level-one static random-access memory (LI SRAM) and level-two static random access memory (L2SRAM). In some implementations, a compute node includes a compute block which may Attorney Docket No. 07136-0126WO1 include various processing, storage, and / or communication functions, and an Analog Mixed Signal (AMS) block that can include analog / mixed signal circuits for interfacing with the PIC. The compute block can include an interface for communicating with the AMS block, or more specifically, with the componentry of the AMS block.

[0051] A photonic integrated circuit (PIC) can include optical modulators and photodiodes, and an electronic integrated circuit (EIC), e.g., including an AMS block, can include modulator drivers and transimpedance amplifiers (TIAs). An optical modulator and a modulator driver can form an optical transmitter (TX), and a photodiode and a TIA can form an optical receiver (RX). In such a way, the circuit package can have at least one photonic transceiver (TX and RX) whose functionality resides partially in the PIC and / or partially in the EIC, which enables the photonic transceivers to send and receive data packets in the optical domain as modulated electromagnetic waves via photonic channels and / or as digital packets via electrical interconnections.

[0052] A photonic interface can include one or more transmitters and / or one or more receivers. The one or more transmitters can be referred to as an electrical-to-optical (EO) interface, and the one or more receivers can be referred to as an optical-to-electrical (OE) interface. That is, a photonic interface can include at least one of an EO interface or an OE interface. A transmitter in one photonic interface can connect with a receiver in another photonic interface to form a one- to-one unidirectional optical path (or an optical lane). Unidirectional optical paths form between the two photonic interfaces can be independent from each other, which can avoid crosstalk between different optical paths and / or avoid path length compensation between different optical paths, e.g., when light is continuous wave - CW light.

[0053] When each of the photonic interfaces includes both EO interface and OE interface, the photonic interface can provide bi-directional optical paths for optical signals modulated with data. A bi-directional optical path can include two unidirectional optical paths. As discussed with further details below, a photonic channel can include one or more unidirectional optical paths or one or more bidirectional optical paths.

[0054] To provide a large number of optical paths for high bandwidth data communication between photonic interfaces, circuit packages, and / or systems, wavelength-division multiplexing (WDM) or Dense wavelength-division multiplexing (DWDM) technology can be utilized, such that light with multiple wavelengths can be utilized. In some examples, a photonic channel includes multiple bidirectional optical paths, and a number of the multiple bidirectional optical Attorney Docket No. 07136-0126WO1 paths is identical to a number of the multiple wavelengths. A number of unidirectional optical paths can be twice of the number of multiple wavelengths.

[0055] To further increase the number of optical paths, optical splitting (or optical dividing) technology can be utilized, such that a light beam with a same wavelength can be split into multiple light portions with the same wavelength. In some examples, with the optical splitting technology, a same light source can provide input light for multiple photonic channels and / or multiple tiles each including multiple photonic channels.

[0056] In some implementations, each photonic interface (PIC) can receive input light from a corresponding light source via corresponding optical fibers. Each light source can include multiple light elements each providing a corresponding single wavelength of the multiple wavelengths. A number of the multiple light elements can be the number of the multiple wavelengths or multiple times of the number of the multiple wavelengths. A light element can be a laser diode or a laser. In some examples, the light element is configured to emit continuous wave (CW) light.

[0057] In some examples, the light element is configured to emit pulsed light. In some examples, the multiple wavelengths are in a range from 1,500 nm to 1,600 nm, e.g., in the band of the spectrum referred to as the C-band and / or L-band. In some examples, a difference between adjacent wavelengths is about 10 nm. Light transmitted in a unidirectional optical path can be polarized, e.g., with s polarization, in single mode. An optical fiber for transmission can be polarization-maintaining single-mode fibers (PM-SMFs).

[0058] In some implementations, a light source can be implemented into the PIC or implemented separately from the PIC either within or externally to the circuit package and coupled to the PIC by suitable optical couplers. For example, the light source can be integrated in a chip or a printed circuit board (PCB) coupled to the circuit package or the PIC, e.g., by suitable optical couplers.

[0059] An optical modulator can be an electro-absorption modulator (EAM), which is a semiconductor device that modulates the intensity of an optical signal by varying absorption of the optical signal as it traverses the modulator based on an electric voltage applied to the EAM. An operation of an EAM can be based on the Franz-Keldysh effect, e.g., a change in the absorption spectrum caused by an applied electric field, which changes the bandgap energy, and thus the photon energy of an absorption edge, but usually does not involve the excitation of Attorney Docket No. 07136-0126WO1 carriers by the electric field. EAMs can be made in the form of a waveguide with electrodes for applying an electric field in a direction perpendicular to the modulated optical signal. In some examples, the EAM is implemented in a layer of germanium silicon, e.g., an epitaxially-grown layer of GeSi. Germanium can stoichiometrically constitute 90% or more of the GeSi material, e.g., 95% or more, 96% or more, 97% or more, 98% or more, or 99% or more.

[0060] Each circuit package, e.g., circuit package 130, can include a corresponding PIC. Each PIC can include number of components, e.g., optical couplers such as grating couplers, optical guiding system, optical modulators such as EAMs, photodetectors such as photodiodes (PDs), optical multiplexer(s), and / or optical demultiplexer(s), that can be integrated in the PIC. For illustration, the photodetectors and the photodiodes may be used interchangeably in the specification. These components can be implemented at least partially as waveguides.

[0061] One or more photonic channels (unidirectional optical paths and / or bidirectional optical paths) can be formed between the multiple circuit packages, or the respective photonic interfaces. For example, light from a first light source can be coupled through optical fibers and grating couplers into a first PIC of the first circuit package and be further guided to optical modulators such as EAMs through an optical guiding system. The optical modulators can modulate the light with data by corresponding modulator drivers in a first EIC of the circuit package to generate modulated light.

[0062] When the light includes multiple light beams each with a single wavelength of multiple wavelengths, modulated light beams with single wavelengths from the optical modulators can be guided (optionally through an optical guiding system to a multiplexer. The multiplexer can multiplex the multiple light beams into a multiplexed light beam. The multiplexed light beam can be coupled out of the first PIC through grating couplers into the optical fibers, e.g., PM- SMFs, and then to the second circuit package. The multiplexed light beam can be coupled into a second PIC in the second circuit package through grating couplers into a demultiplexer. The demultiplexer can demultiplex the multiplexed light beam into multiple light portions each with a corresponding single wavelength. The multiple light portions each with the corresponding single wavelength can be guided (optionally through an optical guiding system) to photodiodes. The photodiodes can convert detected light into electrical data that can be transmitted to corresponding TIAs in the second EIC of the second circuit package. In such a way, one or more inter-chip unidirectional optical paths (or lanes) are formed from the optical modulators in the Attorney Docket No. 07136-0126WO1 first PIC to the corresponding PDs in the second PTC. Accordingly, one or more inter-package unidirectional data paths are formed from the modulator drivers in the first EIC to the TIAs in the second EIC.

[0063] In some implementations, one or more intra-chip unidirectional optical paths (or lanes) can be also formed from optical modulators to corresponding PDs in a same PIC, and accordingly, one or more intra-package unidirectional data paths can be also formed in a same circuit package.

[0064] In some implementations, the first PIC can include a further optical guiding system, e g., channel waveguides, that can be coupled with one or more EAMs to one or more corresponding PDs. Each of the one or more EAM can modulate light with a single wavelength with data from a corresponding modulator driver in a corresponding EIC stacked with the PIC in the same first circuit package and transmit the modulated light through a corresponding channel waveguide of the optical guiding system to a corresponding PD of the one or more corresponding PDs in the same PIC. The corresponding PD can convert detected light into electrical data that can be electrically transmitted to a corresponding TIA in the corresponding EIC of the first circuit package. Thus, an intra-chip unidirectional optical path (or lane) is formed from the EAM to the corresponding PD in the first PIC, and accordingly, an intra-package unidirectional data path is formed from the corresponding modulator driver in the corresponding EIC through the EAM, the corresponding channel waveguide in the optical guiding system, the corresponding PD to the corresponding TIA in the corresponding EIC of the first circuit package.

[0065] Similarly, light from a second light source can be coupled through optical fibers and grating couplers into the second PIC of the second circuit package and be further guided to optical modulators, such as EAMs, through an optical guiding system. The optical modulators modulate the light with data by corresponding modulator drivers in the second EIC of the second circuit package to generate modulated light. When the light includes multiple light beams each with a single wavelength of multiple wavelengths, modulated light beams with single wavelengths from the optical modulators can be guided (optionally through an optical guiding system to a multiplexer. The multiplexer can multiplex the multiple light beams into a multiplexed light beam. The multiplexed light beam can be coupled out of the second PIC through grating couplers into the optical fibers, e.g., PM-SMFs, and then to the first circuit package. Attorney Docket No. 07136-0126WO1

[0066] The multiplexed light beam can be coupled into the first PIC in the first circuit package through grating couplers into a demultiplexer. The demultiplexer can demultiplex the multiplexed light beam into multiple light portions each with a corresponding single wavelength. The multiple light portions each with the corresponding single wavelength can be guided (optionally through an optical guiding system) to photodiodes. The photodiodes can convert detected light into electrical data that can be transmitted to corresponding TIAs in the EIC of the first circuit package. In such a way, one or more unidirectional optical paths (or lanes) are formed from the optical modulators in the second PIC to the corresponding PDs in the first PIC. Accordingly, one or more unidirectional data paths are formed from the modulator drivers in the second EIC to the TIAs in the first EIC.

[0067] In some implementations, the second PIC can include a further optical guiding system, e g., channel waveguides, that can be coupled with one or more EAMs to one or more corresponding PDs in the second PIC. Each of the one or more EAM can modulate light with a single wavelength with data from a corresponding modulator driver in a corresponding EIC stacked with the second PIC in the same second circuit package and transmit the modulated light through a corresponding channel waveguide of the optical guiding system to a corresponding PD of the one or more corresponding PDs in the same second PIC. The corresponding PD can convert detected light into electrical data that can be electrically transmitted to a corresponding TIA in the corresponding EIC in the second circuit package. Thus, an intra-chip unidirectional optical path (or lane) is formed from the EAM to the corresponding PD in the second PIC. Accordingly, an intra-package unidirectional data path is formed from the corresponding modulator driver in the corresponding EIC through the EAM, the corresponding channel waveguide in the optical guiding system, the corresponding PD to the corresponding TIA in the corresponding EIC of the second circuit package.

[0068] In some implementations, the grating couplers in the first PIC can be arranged in an array, that can be coupled (in and out) with the optical fibers together using a first fiber array unit (FAU) or any other suitable coupling method, e g., using V grooves for edge-coupled fibers. Similarly, the grating couplers in the second PIC can be arranged in an array, that can be coupled (in and out) with the optical fibers together using a second fiber array unit (FAU) or any other suitable coupling method, e g., using V grooves for edge-coupled fibers.

[0069] In some implementations, the optical guiding systems in the first PIC can be configured Attorney Docket No. 07136-0126WO1 such that light can be guided in or out from corresponding components in the first PIC in an ordered, efficient way and in a miniaturized area. For example, optical modulators and PDs for each photonic channel are positioned in a same corresponding channel area, and light beams with corresponding single wavelengths can be guided as two groups respectively to the optical modulators and the PDs in the corresponding channel area. Channel areas for different photonic channels are arranged adjacent to each other. The multiplexers and the demultiplexers are arranged further from the channel areas and closer to the grating couplers and can be arranged parallel to one another.

[0070] A multiplexer and a demultiplexer for a same photonic channel can be arranged adjacent to each other. In such a way, light from the optical modulators to the multiplexer and light from the demultiplexer to the PDs can be guided in corresponding waveguides adjacent to each other between a corresponding channel area and an area close to the grating couplers. Similarly, the optical guiding systems in the second PIC can be configured such that light can be guided in or out from corresponding components in the second PIC in an ordered, efficient way and in a miniaturized area.

[0071] As illustrated in the example of FIG. 1, the circuit package 130 can include various electronic and optical components implemented across an EIC 110 and a PIC 121.

[0072] The circuit package 130 includes two compute nodes 134-1 and 134-2, collectively, compute nodes 134, which each include a respective compute block 158-1 and 158-2, which may include various processing, storage, and / or communication functions. The compute nodes 134 each include an Analog Mixed Signal (AMS) block 160-1 and 160-2, collectively AMS blocks 160, that includes analog / mixed signal circuits for interfacing with the PIC 121. The compute blocks 158 each include an interface 157-1 and 157-2, collectively interfaces 157, for communicating with the AMS blocks 160, or more specifically, with the componentry of the AMS blocks 160. Each compute block 158, 158-1, 158-2 can include a flow control unit (FLIT) circuitry 159, 159-1, 159-2, coupled to the interface 157, 157-1, 157-2. The FLIT circuitry is configured to create flits or segment data from large data packets, which allows for efficient and reliable data transfer across interconnect networks. The AMS block 160-1, 160-2 can receive data from or transmit data to a processing unit or a memory unit through the FLIT circuitry 159- 1, 159-2 and the interface 157-1, 157-2, e.g., as illustrated with further details in FIG. 2.

[0073] The AMS blocks 160 each include a modulator driver 162-1 and 162-2, collectively Attorney Docket No. 07136-0126WO1 drivers 162, and each include a transimpedance amplifier (TIA) 164-1 and 164-2, collectively TIAs 164. The PIC 121 includes a pair of modulators 156-1 and 156-2 and a pair of photodetectors 166-1 and 166-2. The PIC 121 also includes a grating coupler 154 or other optical interface (01) configured to receive and pass on light to one or more components and an optical splitter 126. The AMS blocks 160 each include a clock correction circuit 120-1 and 120- 2, collectively clock correction circuits 120. The clock correction circuits 120 seek to perform the correction of duty cycle and ISI correction of the clock signal, such as a differential clock signal.

[0074] In some implementations, the EIC 110 includes a reference clock source 131 configured to provide a reference clock signal, e.g., with a clock frequency 200 MHz, to one or more AMS blocks 160-1, 160-2 in the EIC 110. Each AMS block 160-1, 160-2 can generate an operation clock signal, e.g., with an operation frequency of 14 GHz, using the reference clock signal. The operation clock signal can be shared by a plurality of receiver circuits, including the TIAs, and transmitter circuits, including the modulator drivers, to generate TX data signals embedded with clock information to transmit over a photonic network or decode data signals received from a photonic network. In addition, each AMS block 160-1, 160-2 includes a set of receivers and transmitters, as will be further described with respect to FIG. 3 below. Within each receiver and transmitter of each AMS block 160-1, 160-2 is the clock correction circuit 120-1, 120-2. Each clock correction circuit 120-1, 120-2 receives the clock signal from the reference clock 131 and corrects the clock signal’s distortions, e g., duty cycle and intersymbol interference (ISI).

[0075] A light engine 150 can provide light as an optical carrier signal for communication between the first compute node 134-1 and second compute node 134-2. The light engine 150 provides the carrier signal to a FAU 132 of the circuit package 130 of FIG. 1, such as through an optical fiber. The FAU 132 is optically coupled to the grating coupler 154 which directs the optical carrier signal on to other components of the circuit package 130. The splitter 126 receives the optical carrier signal from the grating coupler 154 and splits the optical signal along two optical paths 170 and 172. More generally, the splitter 126 may distribute the optical carrier signal over any number of photonic paths. The optical paths 170 and 172 may be implemented as any suitable optical transmission medium and may include a mixture of waveguides and optical fibers, or any other suitable transmission medium. In the present example, the optical paths 170 and 172 can be implemented as waveguides in the PIC 121. Attorney Docket No. 07136-0126WO1

[0076] The optical paths 170 and 172 pass from the splitter 126 to the optical modulators 156-1 and 156-2, respectively. Each optical modulator modulates the optical carrier signal it receives from the splitter 126 based on information from its respective optical driver 162-1 and 162-2 and transmits the modulated signal along the respective optical path. A first photodetector 166-1 receives the modulated signal from the optical path, e.g., from the associated modulator 156-2. As depicted, the optical path from modulator 156-1 connects to photodetector 166-2 and the optical path from modulator 156-2 connects to photodetector 166-1. The photodetectors 166-1, 166-2 convert the received modulated signal into respective electrical signal and pass the electrical signals to a transimpedance amplifier 164-1, 164-2 through which the compute nodes 134-1 and 134-2 receive the information encoded in the signals. In this way, communication occurs between the compute nodes through the various components just described.

[0077] Accordingly, the PIC 121 described here includes an intra-chip bidirectional photonic channel, including two unidirectional photonic links for communicating both to and from each compute node. Here, the modulator driver 162-1 defines the first unidirectional photonic link, the optical modulator 156-1, the optical path 170, the photodiode 166-2, and the transimpedance amplifier 164-2. Similarly, the modulator driver 162-2 defines the second unidirectional link, the optical modulator 156-2, the optical path 170, the photodiode 166-1, and the transimpedance amplifier 164-1. The first and second unidirectional links operate in opposite directions. Additionally, one or more of the compute nodes 134-1, 134-2 may include one or more serializers and / or deserializers for communicating signals between the compute nodes 134-1, 134-2. In this way, the two unidirectional photonic links form the intra-chip bidirectional photonic channel.

[0078] With reference to FIG. 2, the FLIT circuitry 202 includes a FLIT generator 202a coupled to the interface circuitry 204 and configured to transmit a data signal, e.g., from a processing unit or a memory unit, to the interface circuitry 204. The interface circuitry 204 is coupled between the FLIT generator 202a and the AMS circuitry 206. The FLIT generator 202a can be configured to convert input data packets into segmented data in a FLIT format for data transfer.

[0079] The segmented data in the FLIT format can include control information for routing and error detection and correction. A flit is the smallest unit of data used in network-on-chip (NoC) and other high-performance computing interconnects, and is a part of a larger packet. Each packet can be divided into multiple flits for efficient data transfer. A structure of the Flits can Attorney Docket No. 07136-0126WO1 include a header Flit that contains routing information and sets up the path for the subsequent flits, body Flits: carry the actual payload or data, and a tail Flit that marks the end of the packet and may include error-checking information. In some examples, for data with 256 bits, in the FLIT format, cyclic redundancy check (CRC) codes can be arranged in a middle of the 256 bits, and error correction code (ECC) codes and / or other CRC codes can be arranged at the end of the 256 bits.

[0080] In some implementations, e.g., as illustrated in FIG. 2, the interface circuitry 200 includes a medium access control (MAC) sublayer 204a coupled to the FLIT generator 202a, and a plurality of physical coding sublayers (PCSs) 204b coupled between the MAC sublayer 204a and the AMS circuitry 206. Each of the plurality of PCSs 204b is coupled to a respective second AMS circuit of the plurality of second AMS circuits in the AMS circuitry 206. A number of the plurality of PCSs 204b can be identical to a number of second AMS circuits, e.g., 4. For transferring data with 256 bits, each PCS 204b can transmit 64 bits to the respective second AMS circuit.

[0081] The MAC sublayer 204a and the plurality of PCSs 204b are configured for data transmission from the FLIT generator 202a to the plurality of second AMS circuits. In some implementations, the MAC sublayer 204a is configured to identify and correct transmission errors, acknowledge transmission, and / or retransmit data. The MAC sublayer 204a can be coupled to an external memory device 203, e.g., SRAM, that is configured to store data for the MAC sublayer 204a. The external memory device 203 can include a first SRAM for odd bits and a second SRAM for even bits. The PCS 204b can be configured for at least one of data encoding and decoding, scrambling and descrambling, alignment marker insertion and removal, block and symbol redistribution, or lane block synchronization and deskew. For example, the PCS 204b can be configured to encode data to get sufficient rising / falling edges for transmission.

[0082] In some implementations, each of the plurality of PCSs 204b is configured to output a corresponding TX data signal to a corresponding second AMS circuit of the plurality of second AMS circuits. The corresponding second AMS circuit can be configured to generate a transmission clock signal, e.g., with 875 Mbps, and send the transmission clock signal to the PCS 204b, and the PCS 204b can be configured to transfer the corresponding TX data signal to the corresponding second AMS circuit using the transmission clock signal. In such a way, the local Attorney Docket No. 07136-0126WO1 frequency of the clock signals of the second AMS circuit and the PCS 204b matches, and signals are synchronized between the AMS circuitry 206 and the interface circuitry 204.

[0083] In some implementations, the FLIT circuitry 202 includes a flow control unit (FLIT) reader 202b coupled to the interface circuitry 204 and configured to convert a data signal from the interface circuitry 204 into segmented data in a FLIT format for data transfer. The interface circuitry 204 is coupled between the FLIT reader 202b and the AMS circuitry 206. The segmented data in the FLIT format can include control information for routing and error detection and correction.

[0084] As illustrated in FIG. 2, the interface circuitry 204 can include a medium access control (MAC) sublayer 204d coupled to the FLIT reader 202b and a plurality of physical coding sublayers (PCSs) 204c coupled between the MAC sublayer 204d and the AMS circuitry 206. Each of the plurality of PCSs 204c is coupled to a respective first AMS circuit or RX circuit of the plurality of first AMS circuits. A number of the PCSs 204c can be identical to a number of the first AMS circuits, e.g., 4. In some examples, each PCS 204c can receive 64 bits from the respective first AMS circuit, and the data from 4 PCSs 204c can be converted into 256 bits data.

[0085] The plurality of PCSs 204c and the MAC sublayer 204d are configured for data transmission from the plurality of first AMS circuits to the FLIT reader 202b. In some implementations, the MAC sublayer 204d is configured to identify and correct transmission errors, acknowledge transmission, and / or retransmit data. The MAC sublayer 204d can be coupled to an external memory device 205, e g., SRAM, that is configured to store data for the MAC sublayer 204d. The PCS 204c is configured for at least one of data encoding and decoding, scrambling and descrambling, alignment marker insertion and removal, block and symbol redistribution, or lane block synchronization and deskew.

[0086] In some implementations, each of the plurality of PCSs 204c is configured to receive a corresponding RX data signal from a corresponding first AMS circuit of the plurality of first AMS circuits, and the MAC sublayer 204d is configured to integrate corresponding RX data signals, e g., data with 64 bits, from the plurality of PCSs into an integrated data signal, e.g., data with 256 bits.

[0087] In some implementations, the interface circuitry 204 includes one or more other components, e.g., an interrupt request controller (IRQ) controller 204e, control / status registers 204f, and / or a finite state machine (FSM) 204g. The IRQ controller 204e can receive hardware Attorney Docket No. 07136-0126WO1 interrupt events from various sources and presents them to a processing unit, which allows the processing unit to handle real-time events efficiently without constantly polling.

[0088] In some implementations, the FLIT circuitry 202 and the interface circuitry 204 can be connected through an Advanced extensible Interface (AXI) interface 208. The AXI is a communication bus protocol that connects on-chip peripheral circuits to processor cores. The AXI interface 208 can include a first AXI bus 208a, through which the FLIT generator 202a transfer segmented data to the MAC sublayer 204a, and a second AXI bus 208b, through which the MAC sublayer 204d transfers data to the FLIT reader 202b.

[0089] FIG. 3 is a diagram schematically illustrating an example of the AMS circuitry 160-1 of FIG. 1. As illustrated in FIG. 3, the AMS circuitry 160-1 includes a plurality of first AMS circuits 304, e.g., RX circuit, and a plurality of second AMS circuits 306, e.g., TX circuit. Each AMS circuit 304 can be coupled to a respective photodiode in the PIC to form a receiver (RX). Each AMS circuit 306 can be coupled to a respective optical modulator, e.g., EAM, in the PIC to form a transmitter (RX). FIG. 4 is a diagram schematically illustrating an example of the second AMS circuit or TX circuit 306 of FIG. 3, and FIG. 5 is a diagram schematically illustrating an example of the first AMS circuit or RX circuit 304 of the AMS circuitry 160-1 of FIG. 3. Each receiver and transmitter includes a clock correction circuit 120. For example, RX1 includes clock correction circuit 120-1 and TX1 includes clock correction circuit 120-2.

[0090] In some examples, the AMS circuitry 160-1 is associated with a channel that can include 4 bi-directional optical paths or 8 unidirectional optical paths or lanes. For example, a first AMS circuit 304, e.g., RX1, and a second AMS circuit 306, e.g., TX1, can be associated with a bidirectional optical path. Similarly, RX2 and TX2, RX3 and TX3, RX4 and TX4 can be associated with respective bi-directional optical paths.

[0091] In some implementations, each first AMS circuit or RX circuit 304 is configured to receive a respective RX analog signal from a corresponding photodiode in the PIC and convert the respective RX analog signal into a corresponding RX data signal, and the interface circuitry is configured to convert the corresponding RX data signal into a data signal that can be delivered to the FLIT circuitry 202. In some implementations, the interface circuitry 204 is configured to convert the second data signal into a plurality of TX data signals for the plurality of second AMS circuits 306, and each of the plurality of second AMS circuits 306 is configured to convert a respective TX data signal into a corresponding TX analog signal and deliver the corresponding Attorney Docket No. 07136-0126WO1

[0092] TX analog signal to a corresponding optical modulator in the PIC for modulating an optical signal with the corresponding TX analog signal.

[0093] In some implementations, e.g., as illustrated in FIG. 3, the AMS circuitry 160-1 includes a clock signal generator 214 configured to receive a reference clock signal from a reference clock source 131. The reference clock source 131 can be integrated in the EIC and configured to provide the reference clock signal to one or more AMS circuitries 160-1 in the EIC.

[0094] The clock signal generator 214 is configured to generate an operation clock signal based on the reference clock signal. The operation clock signal has an operation frequency greater than a clock frequency of the reference clock signal. In some examples, the clock frequency of the reference clock signal is about 200 MHz, and the operation frequency is about 14 GHz. In some examples, the clock signal generator 214 includes an inductor-capacitor phase-locked loop (LCPLL) circuit. The LCPLL circuit can use an LC tank circuit to generate a stable oscillation frequency. The LCPLL circuit includes a closed-loop system that ensures that an output signal remains in phase with an input signal, maintaining a stable and accurate frequency. The LCPLL circuit can include a single-ended LCPLL, a differential LCPLL, a quadrature LCPLL, an injecti on-Locked LCPLL, or a fractional -N LCPLL.

[0095] In the AMS circuitry 160-1, each first AMS circuit or RX circuit 304 or second AMS circuit or TX circuit 306 can receive the operation clock signal with the operation frequency, e.g., 14 GHz, and can generate corresponding RX signal or TX signal with a corresponding frequency. For example, the second AMS circuit 306 can generate a high speed TX signal, e.g., with a frequency of 56 GHz, for the PIC, while the first AMS circuit 304 can generate a low speed RX signal, e.g., with a speed of 875 Mbps, for a processing unit or a memory unit.

[0096] In some implementations, e.g., as illustrated in FIG. 4, a second AMS circuit or TX circuit 306 is configured to receive the operation clock signal and a TX data signal, e.g., from a processing unit or a memory unit through the FLIT circuitry 302 and the interface circuitry 204, and generate a corresponding TX analog signal using the operation clock signal and the TX data signal. Thus, the corresponding TX analog signal includes both clock information and data information.

[0097] The operation frequency of the operation clock signal can be greater than a frequency associated with the TX data signal, and smaller than a frequency associated with the corresponding TX analog signal. In some examples, the operation clock frequency is 14 GHz, Attorney Docket No. 07136-0126WO1 the TX data signal is transferred with 875 Mbps, and the TX analog signal is 56 GHz. As noted above, the corresponding TX analog signal can be delivered to a corresponding optical modulator in the PIC for modulating an optical signal with the corresponding TX analog signal.

[0098] Thus, the AMS circuitry 160-1 can combine a low speed data signal from the processing unit or the transmitting unit into a high speed optical signal for the PIC, and the high speed optical signal includes data information embedded clock information. The clock information can be distributed over the photonic network, which can save a lot of power and cost compared to distributing the clock information electronically. The photonic network can connect a number of compute nodes. A compute node can be connected to a remote node, and each compute node is connected to the photonic network. Thus, as long as the photonic network has the clock information, every compute node can have the clock information.

[0099] In some implementations, e.g., as illustrated in FIG. 4, the second AMS circuit or TX circuit 306 includes a first multiplexer 403, an oscillator circuit 401, a second multiplexer 405, a clock correction circuit 120-2, and a modulator driver 408. The first multiplexer 403 is configured to convert the TX data signal into a plurality of digital data signals associated with a same transmission speed. The first multiplexer 403 can be a 64:4 multiplexer that can, for example, convert 875 Mbps data into 14 Gbps data. The oscillator circuit 401 is configured to convert the operation clock signal into a plurality of clock signals having the operation frequency with different phases, e.g., 4 clock signals having 14 GHz and 4 different phases. The oscillator circuit 401 can include an integrated logic oscillator (ILO) circuit. The second multiplexer 405 is configured to generate an integrated data signal based on the plurality of digital data signals, e.g., 4 digital data signals with 14 Gbps speed, and the plurality of clock signals, e.g., 4 clock signals having 14 GHz and 4 different phases. The second multiplexer 405 can be a 4: 1 multiplexer, and the integrated data signal can be 56 Gbps data.

[0100] The modulator driver 408 is configured to generate the corresponding TX analog signal based on the integrated data signal. The modulator driver 408 can be an EAM driver, and the TX analog signal can be delivered to a corresponding optical modulator, e.g., EAM, in the PIC for modulating an optical signal with the TX analog signal.

[0101] In some implementations, as the modulator driver 408 in the second AMS circuit can be in direct electrical connection, e.g., by conductive pillars, with the corresponding optical modulator in the PIC, the modulator driver 408 can directly transfer the corresponding TX Attorney Docket No. 07136-0126WO1 analog signal to the corresponding optical modulator in the PTC, without data processing on the corresponding TX analog signal, which can increase the transmission speed. The second AMS circuit can include no data processing unit, e.g., no digital signal processor (DSP). As discussed below with further details, a corresponding RX circuit that receives an RX analog signal generated based on the corresponding TX analog signal without processing can include a Feed- Forward Equalizer (FFE) circuit to process, e.g., correct, equalize, or compensate, the RX analog signal.

[0102] In some implementations, the second AMS circuit 306 further includes a correction circuitry 402 coupled to the oscillator circuit 401 and configured to correct timing among the plurality of clock signals having the operation frequency with the different phases. The correction circuitry 402 can include one or more duty cycle correction (DCC) circuits, one or more quadrature error correction (QEC) circuits, or a combination thereof. The second AMS circuit 306 can further include a retimer 404 that has inputs coupled to the correction circuitry 402 and the first multiplexer 403 and an output coupled to the second multiplexer 405. The retimer 404 is configured to retime the plurality of data signals and the plurality of clock signals and output the retimed data signals and the clock signals to the second multiplexer 405. The retimer 404 can include flip-flop logics. The clock correction circuit 120-2 is configured to correct the retimed clock signals prior to providing those corrected signals as input to the second multiplexer 405. The second AMS circuit 306 can further include a data buffer 406 coupled between the second multiplexer 405 and the modulator driver 408. In some examples, the data buffer 406 includes 4 inverters with a fan out of 2 to allow the 4: 1 multiplexer to drive the EAM driver input.

[0103] The correction circuitry 402 and the retimer 404 are configured to get the clock signals, e.g., 4-phase 14GHz clock signals, and the data signal, e.g., 14 Gbps data signals, to the second multiplexer 405, e.g., 4: 1 multiplexer, with correct timing. The correction circuitry 402 can be a DCC-QEC circuit that includes capacitance based programmable delays, for correcting quadrature error, and programmable loads for skewing a P / N ratio of an inverter for correcting duty cycle error. The DCC-QEC circuit can include one or more DCC sub-circuits and one or more QEC sub-circuits that are coupled together. The retimer 404 can include one or more levelshifters for shifting data from the 64:4 p2s and flops for selecting the correct time slot for the data and clocks going to the second multiplexer 405, e.g., 4: 1 multiplexer. The 4: 1 multiplexer Attorney Docket No. 07136-0126WO1 can include 25% duty cycle select clock generator and uses gated inverters to multiplex the data. The second multiplexer 405 can also use a dummy multiplexer to route clocks via a low pass filter (LPF) to a probe point that can be measured at a probe pad. Using this probe point, the average values of all clocks or Duty Cycle and the average delay between clocks (or skew) can be measured. Based on this measurement, selective delay can be applied to clocks to allow for duty-cycle and quadrature error correction.

[0104] With reference to FIG. 5, a first AMS circuit, e.g., RX circuit, 304 can receive the operation clock signal from the clock signal generator 214, e.g., LCPLL, and a RX analog signal, e.g., from a corresponding photodiode in the PIC, and generate a corresponding RX data signal using the operation clock signal and the RX analog signal. The corresponding RX data signal can be provided to a processing unit or a memory unit through the interface circuitry 204 and the FLIT circuitry 202, e.g., as illustrated in FIG. 2. The operation frequency of the operation clock signal can be greater than a frequency associated with the corresponding RX data signal and smaller than a frequency associated with the RX analog signal. In some examples, the operation frequency is 14 GHz, the RX analog signal has a transfer speed of 56 Gbps, and the RX analog signal has a transfer speed of 875 MHz. The first AMS circuit or RX circuit 304 is configured to convert a high speed optical signal to low speed digital signal for the processing unit or the memory unit.

[0105] In some implementations, e.g., as illustrated in FIG. 5, the first AMS circuit or RX circuit 304 includes a transimpedance amplifier (TIA) 501, a feed-forward equalizer (FFE) circuit 502, a plurality of samplers 504, and a serial-to-parallel (S2P) interface 507 that are coupled in series along a signal path.

[0106] The TIA 501 is configured to amplify a RX analog signal from the corresponding photodiode 500 in the PIC. The FFE circuit 502 is coupled to the TIA 501 and configured to convert the RX analog signal into a plurality of data signals with different phases. The TX analog signal has a higher transfer speed than the plurality of data signals. In some examples, the TX analog signal has a transfer speed of 56 Gbps, while the plurality of data signals has a transfer speed of 14 Gbps. The number of the plurality of data signals can be 4. The 4 data signals can have respective phases, e.g., 0°, 90°, 180°, 270°. The plurality of samplers 504 are coupled to the FFE circuit 502 and each sampler 504 is configured to sample a respective data signal with a corresponding phase. Attorney Docket No. 07136-0126WO1

[0107] A number of the samplers 504 can be identical to a number of the data signals, e.g., for non-retum-to-zero (NRZ) applications, or greater than the number of the data signals, e.g., for duobinary applications. For example, as the first AMS circuit or RX circuit 304 has a quarter rate architecture, each lane needs 4 data path samplers for NRZ applications. To support the duobinary each lane needs 12 samplers. That is, a data signal is sent to 3 samplers 504. A sampler 504 driven by a single phase clock signal can include a double-tail dynamic comparator followed by an SR latch. The comparator determines input differential data either high or low, and generates differential retum-to-zero (RZ) shaped output signals. Then, the SR latch converts comparator outputs to the single-ended rail-to-rail non-return-to-zero (NRZ) data.

[0108] The serial-to-parallel (S2P) interface 507 is coupled to the plurality of samplers 504 and configured to generate a corresponding RX data signal based on outputs from the plurality of samplers 504. The S2P interface 507 can include a digital circuit that converts serial data, e.g., data sent one bit at a time, into parallel data, e.g., multiple bits sent simultaneously. In some examples, the first AMS circuit 304 further includes a retimer between the samplers 504 and the S2P interface 507. The retimer can align 4-phase output data from the samplers 504 to support synchronized operation. Incoming Data stream can be demultiplexed by either 8 or 16. There can be 12 input streams for 4 phases, each phase having 3 samples. Output words can be retimed on a common word clock and sent to digital. The S2P interface 507 can feature a 1 : 16 deserializer core, and the 12 data streams can go into 12 cores to generate 192 parallel bits to the digital. With the 1 : 16 deserializer core, data with 14 Gbps can be converted into data with 875 Mbps.

[0109] In some implementations, the first AMS circuit, e.g., RX circuit 304, further includes a reference signal generator 505 configured to generate a reference direct current (DC) signal for the plurality of samplers 504.

[0110] In some implementations, the FFE circuit 502 includes a plurality of thread circuits 503 coupled to the plurality of samplers 504, and each thread circuit 503 is configured to convert the RX analog signal into a respective data signal with a corresponding phase and output the respective data signals with the corresponding phase to one or more corresponding samplers.

[0111] In some implementations, e.g., as illustrated in FIG. 5, the first AMS circuit or RX circuit 304 includes a deskew circuit 510 and a second oscillator circuit 512. The deskew circuit 510 includes the clock correction circuit 120-1. The deskew circuit 510 is configured to receive the Attorney Docket No. 07136-0126WO1 operation clock signal generator, e.g., LCPLL 214, into a plurality of first clock signals having the operation frequency with different phases and adjust timing of the signals that may have become misaligned or skewed, e.g., phase offset, due to path delays or other distortions. The deskew circuit 510 may utilize one or more circuits, including the clock correction 120-1, to correct the misaligned timing signals.

[0112] The second oscillator circuit 512 is configured to generate a plurality of second clock signals with second different phases based on the single-phase, adjustable clock signal from the deskew circuit 510. Each of the plurality of thread circuits 503 is configured to generate the respective data signal based on a corresponding second clock signal. In some examples, the deskew circuit 510 can be an integrated logic oscillator (ILO) circuit, e.g., the oscillator circuit 401 of FIG. 4. In some examples, the deskew circuit 510 receives the operation clock signal from LCPLL to create 8 phases 14 GHz clock signal and produce a single-phase, adjustable clock based on interpolation input codes. The deskew circuit 510 also corrects the single-phase, adjustable clock to correct for skews and other distortions and subsequently transmits it to the second oscillator circuit 512. The second oscillator circuit 512 receive the operation clock signal from the PI 811 and create 4 phases 14 GHz clock and supply for the FFE circuit 502 / samplers 504.

[0113] In some implementations, the first AMS circuit 304 further includes: a first correction circuitry 514 and a second correction circuitry 516. The first correction circuitry 514 is coupled between the second oscillator circuit 512 and each of the plurality of thread circuits 503 in the FFE circuit 502 and configured to perform correction on the corresponding second clock signal. The first correction circuitry 514 can include a quadrature clock correction (QCC) circuit that corrects duty cycle distortion and phase error. The second correction circuitry 516 is coupled to an input of the first correction circuitry 514 and an output of the S2P interface 507 and configured to balance the second difference phases of the plurality of second clock signals. The second correction circuitry 516 can include one or more QCC circuits and / or one or more DCC circuits that improve clock signal quality and reduce duty cycle distortion. Each of the plurality of samplers 504 is coupled to the first correction circuitry 514 and configured to receive an output of the first correction circuitry 514 based on the corresponding second clock signal.

[0114] In some implementations, e.g., as illustrated in FIG. 5, the thread circuit 503 includes a pulse generator 503a, a track and hold (T&H) circuit 503b, a variable gain amplifier (VGA) Attorney Docket No. 07136-0126WO1

[0115] 503c, and a summer 503d. The pulse generator 503a is coupled to an output of the first correction circuitry 514 and configured to generate timing pulses based on the corresponding second clock signal. The track and hold (T&H) circuit 503b is coupled to the pulse generator 503a and configured to smooth the RX analog signal using the timing pulses. The variable gain amplifier (VGA) 503c is coupled to the T&H circuit 503b and configured to amplify the respective RX analog signal with a corresponding gain. The summer 503d is coupled to the VGA 503c and the pulse generator 503a and configured to perform weighted summing on the respective RX analog signal.

[0116] In some implementations, the first AMS circuit 304 further includes a clock data recovery (CDR) circuit 506 configured to receive the corresponding RX data signal and recover a clock signal associated with the corresponding RX data signal. The CDR circuit 506 is coupled to the deskew circuit 510 and configured to feed the recovered clock signal back to the deskew circuit 510. The plurality of second clock signals can be generated based on the recovered clock signal.

[0117] In some implementations, the first AMS circuit 304 further includes an FFE feedback circuit 508 coupled between an output of the S2P interface 507 and the FFE circuit 502 and configured to feed the corresponding RX data signal back to the FFE circuit 802. The FFE feedback circuit 508 can include an FFE Tap adaption configured for improving a quality of an optical eye diagram from a corresponding optical modulator.

[0118] With reference to FIG. 2, the FLIT circuitry 202 includes a FLIT generator 202a coupled to the interface circuitry 204 and configured to transmit a data signal, e.g., from a processing unit or a memory unit, to the interface circuitry 204. The interface circuitry 204 is coupled between the FLIT generator 202a and the AMS circuitry 160-1. The FLIT generator 202a can be configured to convert input data packets into segmented data in a FLIT format for data transfer.

[0119] The segmented data in the FLIT format can include control information for routing and error detection and correction. A flit is the smallest unit of data used in network-on-chip (NoC) and other high-performance computing interconnects, and is a part of a larger packet. Each packet can be divided into multiple flits for efficient data transfer. A structure of the Flits can include a header Flit that contains routing information and sets up the path for the subsequent flits, body Flits: carry the actual payload or data, and a tail Flit that marks the end of the packet and may include error-checking information. In some examples, for data with 256 bits, in the FLIT format, cyclic redundancy check (CRC) codes can be arranged in a middle of the 256 bits, Attorney Docket No. 07136-0126WO1 and error correction code (ECC) codes and / or other CRC codes can be arranged at the end of the 256 bits.

[0120] FIG. 6 is a diagram illustrating a clock correction circuit 120-1 for adjusting differential clock signals. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. The clock correction circuit 120-1 corresponds to the clock correction circuits 120 shown in FIGS 1-5.

[0121] As an example, clock correction circuit 120-1 includes three sections: the positive line 610, the crossover section 620, and the negative line 630. The positive line 610 begins at the positive input (Inp) and extends to the positive output (Outp). This line is responsible for processing the positive clock signal, which is part of the differential clock signal pair received by the circuit. The positive line includes a series of inverters, specifically a first positive inverter and a second positive inverter. Each inverter on the positive line introduces a specific, known delay to the positive clock signal as it propagates from the input to the output. Depending on the implementation, the number of inverters on the positive line varies. For example, the term “inverter” refers to a logic gate that flips the input signal's logic level. In other words, if the input is a logical “1” or high, the output will be a logical “0” or low, and vice versa. In the context of this circuit, each inverter not only flips the signal but also introduces a slight propagation delay. This delay is due to the time it takes for the signal to travel through the inverter's internal circuitry.

[0122] Each of these inverters is characterized by a delay, often measured in picoseconds (ps). The total delay introduced by the series of inverters in the positive line can be adjusted by varying the number of inverters, the specific design of each inverter, and the spacing between them. The delay introduced by each inverter is helpful in signal adjustment and correction, as it allows the circuit to time the processing of the negative clock signal in the negative line. The delayed positive signal serves as a reference for adjusting the negative clock signal at the corresponding node on the negative line. By accurately controlling the delay through these inverters, the circuit can ensure that the positive and negative clock signals remain synchronized, even as they undergo various corrections.

[0123] As the positive clock signal propagates through the positive line, it passes through multiple inverters. Each inverter adds a fixed delay to the signal, which is critical for timing Attorney Docket No. 07136-0126WO1 adjustments across the circuit. For example, inverter 612 introduces the first delay and inversion to the positive clock signal immediately after it enters the circuit. As the signal continues, inverter 614 introduces a second delay and further inverts the signal. This pattern continues with Inverters 616 and 618, each adding its own delay and inversion, progressively shaping the timing and phase of the positive clock signal as it approaches the output (Outp). In some implementations

[0124] The nodes where these inverters are connected play a significant role in the timing and characteristics of the correction signals introduced by the crossover section 620. Node 613, for example, is positioned after the first delay from inverter 612 and before the second delay from inverter 614. This node 613 provides a clock signal that has experienced one delay and one inversion. Node 617 represents a more delayed and further inverted version of the positive clock signal. The choice of which node to use for coupling in the crossover section directly impacts the effectiveness and timing of the corrections applied.

[0125] The negative line 630 runs parallel to the positive line, starting at the negative input (Inn) and ending at the negative output (Outn). This line handles the negative clock signal, which is the counterpart to the positive clock signal in the differential pair. Like the positive line, the negative line includes a first negative inverter and a second negative inverter. These inverters also introduce specific delays into the negative clock signal, similar to the delay characteristics found in the positive line. Like positive line 610, the negative line 630 includes a series of inverters 632, 634, 636, 638-each introducing specific delays and signal inversions. Inverter 632 provides the first delay and inversion, beginning the process of timing the negative clock signal. As the signal propagates, inverter 634 introduces a second delay and inversion. Inverters 636 and 638 continue this process, each adding their own delays and inversions. The nodes along the negative line help determine where the crossover inverters will introduce correction signals. For example, node 633 is positioned after the first delay from inverter 632 and before the second delay from inverter 634. A crossover inverter injecting a signal at this node would be correcting a signal that has been delayed and inverted once. Node 637 is positioned after several delays and inversions. The timing and characteristics of the signal at this node would be different from those at earlier nodes.

[0126] The adjustment or correction between the positive and negative clock signals is achieved by using the delayed positive signal as a timing reference. In various implementations circuit Attorney Docket No. 07136-0126WO1

[0127] 100 adjusts the negative clock signal at specific nodes along the negative line based on the known delays introduced by the inverters on the positive line. This adjustment ensures that the timing of the negative clock signal is precisely controlled to match the positive clock signal, thereby minimizing timing errors and ensuring signal integrity.

[0128] The crossover section 620 is configured to correct distortions that can occur in differential clock signals, such as differential duty cycle distortion and pre-cursor inter-symbol interference (ISI). As an example, inverter 621 generates a correctional signal by taking the positive clock signal from node 611 on the positive line, which is an un-delayed and un -inverted signal directly from the positive input (Inp). Inverter 621 inverts this signal, flipping its logical state, e.g., changing a logical “1” to a “0” and vice versa, and introduces a delay. This correctional signal is then injected into node 635 on the negative line, where it corrects the negative clock signal. The delay introduced by Inverter 621 comprises a propagation delay caused by the internal circuitry of the inverter. This delay is used to align the correctional signal with the negative clock signal at node 635. The negative clock signal at node 635 is delayed relative to the negative input clock signal at node 631 twice by inverters 632 and 634 on negative line 630, and has undergone two signal inversions.

[0129] In some implementations, the crossover section 620 is configured to perform dual correction functionality using a single inverter. Each crossover inverter, e.g., inverter 621, is configured to provide both a duty cycle correction (DCC) and an inter-symbol interference (ISI) equalization. This combined approach of dual correction reduces circuit complexity, improves the circuit’s use of power, reduces power consumption, and allows a single correction element to accomplish circuit tasks that typically are performed by multiple inverter designs. For instance, in traditional systems, a first inverter pair is used to maintain a 50% duty cycle by reinforcing the distinction between differential clock signals, while a second inverter pair is used to correct for ISI through delayed feedback. However, as shown in FIG. 6, the clock correction circuit 120-1 achieves both functions simultaneously using the same inverter.

[0130] Generally, the crossover section 620 operates as a pre-tap equalization function. In the pre-tap equalization function, a signal from an earlier stage of the positive line 610, e.g., node 611 or node 613, is used to correct distortions that are expected to appear in later stages of the negative line 630, e.g., at nodes 635 and 637, respectively. By preemptively compensation for potential signal distortion, the crossover section 620 performs pre-ISI correction, rather than post Attorney Docket No. 07136-0126WO1 correction. The pre-IST correction reduces distortions caused by ISI on the front end of the signal, which provides for a sharper pulse transition on the input signal and before distortion propagates downstream in the clock correction circuit 120-1, or elsewhere.

[0131] Each crossover inverter, e.g., inverter 621, 622, 623, and 624, may have a programmable driver strength. In some instances, each crossover inverter can include a digitally controlled driver with a two-bit weighting scheme. The two-bit weighting scheme of each crossover driver enables a coarse adjustment of the equalization or voltage level. For example, the coarse adjustment can be a 0% adjustment, a 12.5% adjustment, a 25% adjustment, a 50% adjustment, or other, of the maximum equalization level. In some examples, the inverter drive level or voltage level can be dynamically tuned according to an operation frequency or current load conditions, such as temperature conditions, on the clock correction circuit 120-1. This programmability allows the clock correction circuit 120-1 to be configured according to detected conditions, voltages, temperature, or current levels on the corresponding circuit.

[0132] At each of the nodes, e.g., nodes 615, 617, 635, and 637, a signal summation occurs. The signal summation occurs between the crossover inverter outputs and the local node signals for the corresponding line via a current summation. Each node include includes a particular capacitance or voltage, e.g., a parasitic capacitance, the summed current at the node translates into a corresponding voltage adjustment. The corresponding voltage adjustment at that node represents the instantaneous voltage at the node and enables a fine grain shaping of the differential waveforms that pass through the corresponding node without introducing further distortions.

[0133] Inverter 622 is connected to node 613 on positive line 610, which provides a positive clock signal that has been delayed by inverter 612. Inverter 622 further inverts this signal and introduces an additional delay. This correctional signal is injected at node 637 on the negative line 630. The delay introduced by Inverter 622 is the result of both the delay in the positive line from inverter 612 and the delay of crossover inverter 622.

[0134] Inverter 623 operates similarly to Inverter 621, but it takes its input from node 631 on negative line 630. Inverter 623 inverts the negative input clock signal, such as Inn at node 631, and introduces its delay, creating a correctional signal that is applied to node 615 on the positive line. By timing the correctional signal to align with the positive clock signal at node 615, inverter 623 helps provide a correction. Attorney Docket No. 07136-0126WO1

[0135] Inverter 624 is connected to node 633 on the negative line, which provides a negative clock signal that has been delayed once by Inverter 632. Inverter 624 further inverts this signal and introduces an additional delay before applying it as a correctional signal to node 617 on the positive line 610. The delay introduced by Inverter 624 is cumulative, including the delays from Inverters 632 and 634 on the negative line, as well as its own internal delay.

[0136] The crossover inverters 621, 622, 623, and 624 are useful for maintaining the integrity of the differential clock signals as they traverse the circuit. Depending on the implementation, connections of crossover inverters may be configured. For example, if a bigger correction, e.g., bigger timing window, is needed, the output of inverter 621 may be provided at node 637 or even at the negative output node Outn.

[0137] FIG. 7 is an example plot illustrating pre-cursor and post-cursor correction according to implementations of the disclosure. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications.

[0138] Pre-cursor ISI occurs, e.g., at 701, when the tail of a preceding pulse interferes with the leading edge of a current pulse. This type of interference can be corrected by through feedforward or pre-tap equalization paths that leverage delayed and inverted signals generated by the crossover inverters. For example, crossover inverters such as 621, 622, 623, and 624 generate correction signals based on the selected earlier stage nodes of the differential clock signals. By injecting these correction signals into specific nodes along the positive and negative lines, the circuit can preemptively adjust the timing and amplitude of the current pulse to counteract the anticipated or produced effects of pre-cursor ISI. For example, a delayed signal from Inverter 621 can be injected at node 637 to sharpen the negative clock signal transition and restore a proper pulse symmetry. This correction compensates for the spread of the pulse, reducing the interference from the previous pulse and sharpening the rise time of the current pulse.

[0139] Post-cursor ISI occurs, for example, at 703, when the current pulse affects with subsequent pulses. This interference can be mitigated by introducing feedback based correction from the differential outputs toward earlier stages in the signal processing chain. For example, a feedback switch or inverter path may be added from the output node to an upstream node to modify the succeeding pulse shape in real time. Together with the pre-tap correction network, the dual path architecture enabling both feed forward and feedback compensation allows the Attorney Docket No. 07136-0126WO1 circuit to dynamically adjust the timing and shape of the signal based on the actual output, thereby reducing the impact of post-cursor ISI and minimizing eye closure of the ISI across various data rates.

[0140] Now referring back to FIG. 6 the crossover section 620 may be implemented as a programmable matrix capable of dynamically reconfiguring crossover inverter connections. In some implementations, this programmable matrix allows the input of a given crossover inverter, e.g., inverter 621, to be switched from node 611 to a later node such as 617, or switch its output from node 625 to node 637, depending on the delay. Such reconfiguration enables adaptive selection of nodes along the positive or negative inputs based on measured timing delays or signal quality metrics, for example. The configuration of the crossover section 620 can be managed by a controller, which is illustrated in FIG. 8 and described below, which operates in a feedback loop utilizing the differential outputs to determine the correct switch position in the programmable matrix.

[0141] By default, inverter 621 receives the positive clock signal from node 611 and provides a correction signal to node 635 on the negative line. If timing analysis indicates that a greater delay alignment is required between the differential clock signal, then the controller may reroute the output of inverter 621 to node 637. This would apply the correction signal to a more delayed and inverted version of the negative clock signal, allowing for finer control over the signal's timing as it approaches the output. Alternatively, inverter 621 can be configured to inject its correction signal directly at the negative output node (Outn), ensuring that the final output transitions remain precisely aligned with the positive counterpart. These reconfigurable paths allow fine grained control of equalization strength and timing at multiple nodes in the clock correction circuit 120-1, which provides for an adjustable and programmable architecture.

[0142] FIG. 8 is an example block diagram illustrating clock correction circuit 120-1 for providing adjusting differential clock signals. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications.

[0143] Clock correction circuit 120-1 includes a positive line 810 for processing the positive differential clock signal, which is received at the input (Inp) and transmitted to the positive output (Outp). The positive line includes a series of inverters that propagate, amplify, and delay the positive clock signal, ensuring the signal is properly shaped in phase, is properly timed, and Attorney Docket No. 07136-0126WO1 includes the proper duty cycle. The corresponding negative line 830 operates in parallel, receiving the negative differential clock signal an input (Inn) and delivering it to output Outn. The negative line also includes a series of inverters that introduce corresponding delays and inversions, while maintaining synchronization with the positive clock signal.

[0144] Crossover section 820 provides adaptive correction to preserve the integrity and phase alignment of the differential clock signals. As previously mentioned, the crossover section includes crossover inverters 821-824, each of which are controlled by a controller 840 and can inject correctional signals between selected nodes on the positive and negative lines. These crossover inverters are connected through a switching or bus matrix, which is programmable, that allows for flexible routing of signals between the positive and negative lines. For instance, a switch might connect a crossover inverter to a specific node on the negative line to correct timing discrepancies between the positive and negative signals. Each inverter can be configured to preform dual correction functions, e.g., duty cycle correction and pre-cursor ISI equalization, by generating and injecting appropriately delayed and inverted versions of the clock signal to another node.

[0145] Controller 840 can monitor the differential outputs (Outp and Outn) of the positive and negative lines and generates control signals that determine both the connection topology of the crossover section 820 and the drive strength of the crossover inverters. Based on any detected timing discrepancies or waveform distortions, the controller 840 can configure the matrix switches 812-824 to select appropriate injection nodes on the positive and / or negative lines. The controller may further modulate the strength of the crossover inverters using programmable controlled bits, in order to scale the equalization applied at each of the nodes.

[0146] In some implementations, the controller 840 can be coupled to the crossover section 820 to dynamically monitor the slopes or other criteria of the differential outputs (Outp and Outn). For example, by observing the rate of voltage change, the controller 840 can determine whether the output pules are overly wide or slow to transition, which can indicate the presence of ISI. Then, the controller 840 can adjust the effective gain of the crossover inverters in the crossover section 820, by either modifying their bias conditions, altering their digital control bits, until the pulse width and edge sharpness meet a predefined swing, timing metric, or ther threshold.

[0147] In operation, the clock correction circuit 120-N in FIG. 8 receives differential clock signals (Inp, Inn) and processes them through the respective lines 810 and 830. As these signals Attorney Docket No. 07136-0126WO1 propagate, the inverter chains introduce controlled delays that align the positive and negative phases. The controller 840 continuously monitors the output signals and adjusts crossover section 820, e.g., the crossover inverter selections, in real time or substantial real time. By selectively activating crossover inverters and adjusting their drive strength, the controller 840 can ensure that both the equalization and the feedback corrections to improve synchronization and reduce jitter in the clock correction circuit 120-N.

[0148] In some embodiments, crossover section 820 incorporates a bus matrix network that interconnects a large number of crossover inverters. This matrix enabled fine grained configuration, allowing for multiple crossover inverters to be activated simultaneously or sequentially to achieve desired corrections. For example, one set of crossover inverters may apply pre-cursor ISI equalization while another set of crossover inverters may apply post-cursor ISI equalization. This allows the bus matrix configuration to provide the ability to select multiple crossover inverters simultaneously or in sequence, depending on the specific timing and phase correction needs.

[0149] In some embodiments, controller 840 is configured to execute an algorithm to dynamically adjust the selection of crossover inverters in a feedback path. The algorithm can include a closed-loop algorithm to dynamically update crossover configurations based on realtime feedback from the outputs. The algorithm can measure parameters such as edge slope, phase skew, or duty-cycle deviation, and compute corresponding adjustments for the crossover network. Control signals are then sent by the controller 840 to the matrix switches in the crossover section 820 to reassign inverter connections and adjust equalization strength. This adaptation ensures that stable synchronization is maintained across the differential clock signal under various conditions, e.g., temperature, voltage, and operating frequency.

[0150] In some implementations, controller 840 may be configured to execute a machine based algorithm or a rule based algorithm that can determine a crossover inverter selection or configuration based on multiple factors. These multiple factors can include, for example, the nature of the observed timing discrepancies, recent correction history, and operating frequency. The algorithm can be configured to select a specific crossover inverter configuration that provide the most effective phase and amplitude compensation, or activate multiple paths simultaneously to generate composite correction signals at critical nodes. The resulting output can correspond to a corrected differential clock signal with minimal distortions. This correction scheme can be Attorney Docket No. 07136-0126WO1 employed in both a transmitter and receiver domain, to ensure consistent clock correction throughout the communication link.

[0151] In some implementations, controller 840 may utilize a lookup table to streamline the selection process. For example, the lookup table can include different characterized correction profiles. Each profile can specify a particular crossover configuration for different operational scenarios, such as temperature conditions, frequency bands, or data rates being used. Upon detecting a known condition, the controller 840 can retrieve a corresponding profile to configure the matrix network of the crossover section 820 and create a system that produces repeatable and certain performance correction of the differential clock signals.

[0152] FIG. 9 is an example diagram illustrating a driver circuit with clock signal correction 120-N. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications.

[0153] As an example, the driver circuit in FIG. 9 integrates a high speed data transmission chain in which circuit 800 or circuit 600 provides corrections to the clock signals that feed into a 4: 1 multiplexer (MUX). The driver circuit in FIG. 9 includes an injection-locked oscillator (ILO), a quadrature clock conditioner (QCC) 904, a parallel-to-serial (P2S) converter 908, the 4: 1 MUX 906, and an electro-absorption modulator (EAM) driver 910. The clock signal correction 120-N can ensure that the differential clock signals feeding the 4: 1 MUX remain phase-aligned and distortion free.

[0154] In some implementations, the ILO 902 is configured to generate a stable reference clock signal, which has low jitter and suitable for high-speed operations. The output of the ILO 902 is provided to the QCC 904. The QCC 904 can processes the reference clock signal by dividing and phase-shifting the clock signal to produce multiple clock signals. For example, the QCC 904 may output four distinct phase-shifted clock signals, each offset by 90 degrees for example, that are used to control the timing of data transitions within the P2S 908 and MUX stages.

[0155] The P2S converter 908 receives parallel data inputs and converts them into serial data streams. The serialized data streams from the P2S converter 908 are then fed into the 4: 1 MUX for further processing. The 4: 1 MUX is configured to multiplex the four input data streams from the P2S converter 908 into a single high-speed data stream. The timing of this multiplexing operation is controlled and driven by the clock signals provided by the QCC, thus depends Attorney Docket No. 07136-0126WO1 critically on the precision and synchronization of those clock signals. The output of the 4: 1 MUX 906 is the amplified by the EAM driver 910, which conditions the signal for transmission in an optical communication system.

[0156] The clock correction circuit 120-N in FIG. 8 corresponds to the clock correction circuit 120 in FIGs. 6 and 8 and operates between the QCC 904 and the 4: 1 Mux 906. The clock correction circuit 120-N receives differential clock inputs (Inn, Inp) from the QCC 904 and processes them through the positive and negative lines, e.g., 810 and 830, which introduce controlled propagation delays and various duty cycle adjustments. The crossover section 820 dynamically applies pre-tap and feedback equalization corrections to mitigate phase skew, duty cycle distortions, and other distortions caused by inter-symbol interference. The controller 840 continuously monitors the outputs of the positive and negative lines (Outp and Outn) to ensure the clock signals are synchronized and to adaptively reconfigure the crossover inverters in the crossover section 820 to maintain synchronization and minimize jitter. The corrected clock signals are then fed into the 4: 1 MUX.

[0157] These corrected clock signals control the timing of the multiplexing operation, ensuring that each input data stream from the P2S converter 908 is accurately selected and combined into the output serial data stream. The high precision and low jitter of these clock signals, achieved through the corrections applied by circuit 800, are important for the correct operation of the MUX, as timing errors in the clock signals could lead to incorrect data being transmitted or received, resulting in data corruption or loss. In high-speed communication systems, such as those employing a 4: 1 MUX to combine multiple data streams, the integrity of the clock signals is important. Clock correction circuit 901 ensures that these clock signals are not only synchronized but also free from distortions and include reduce bit error rates that could otherwise impact the timing of data transitions.

[0158] FIG. 10 is an example diagram illustrating an electro-photonic network with clock signal correction. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications.

[0159] As an example, Figure 10 shows the configuration of an application-specific integrated circuit (ASIC) 1001 situated above a photonic integrated circuit (PIC) 1002. Various tiles 1004A, 1004B, 1004C, and 1004D within the ASIC are shown, along with the electro-optic (EO) Attorney Docket No. 07136-0126WO1 and optoelectronic (OE) interface components that facilitate communication between these tiles through optical links in the PIC. The optical signals in the PIC are coupled to external systems via an optical fiber 1033 connected to the fiber array unit (FAU) 1032. For example, the light is coupled into the PIC using a grating coupler 1020, which directs the light to the EAMs 1004A, 1004B, 1004C via waveguides.

[0160] The clock correction circuit 120-N is coupled to tiles 1004A-D to provide clock signals driving the optical modulation and detection processes are synchronized and free from distortions. In various implementations, corrected clock signals are generated using circuits similar to , which adjust the timing of the clock signals to correct any phase misalignments or jitter. The clock correction circuit ensures that the modulator drivers 1002A, 1002B, 1002C operate with precise timing, which is crucial for maintaining the integrity of the optical signals transmitted through the PIC.

[0161] In an implementation, the corrected clock signal is generated from a clock source located on a separate chip and is distributed to the various blocks 1004A-1004D. The corrected clock signals ensure that the timing of the optical modulation and detection processes in each block is synchronized and free from distortions, such as phase misalignments or jitter. For example, tiles 1004B and 1004C both receive the corrected clock signals to drive their respective modulator drivers, e.g., 1002B, 1002C, and transimpedance amplifiers 1006C, ensuring precise timing for data modulation and reception. The corrected clock signals are also provided to tiles 1004A and 1004D, allowing for consistent and synchronized operation across all blocks.

[0162] In an embodiment, the corrected clock signal is distributed from the separate clock source to each block 1004A-D in the ASIC. It feeds into both the modulator drivers, e.g., 1002A, 1002B, 1002C, and the receiver circuits, e.g., 1006B, 1006C, 1006D, in each tile. These corrected clock signals ensure that the drivers and transimpedance amplifiers (TIAs) operate with precise timing, which is crucial for maintaining the integrity of the optical signals transmitted and received through the PIC. For example, in tile 1004B, modulator driver 1002B uses the corrected clock signal to generate modulated optical signals that are transmitted via optical waveguide 1000BC to receiver 1006C in tile 1004C. The corrected clock signals ensure that the timing of the optical modulation in 1002B and the reception in 1006C is perfectly synchronized, avoiding data 10 errors due to timing mismatches. Attorney Docket No. 07136-0126WO1

[0163] The modulator drivers, e.g., 1002A, 1002B, 1002C, are electronic components situated within the ASIC 1001 in tiles 1004 A, 1004B, and 1004C. These drivers are responsible for generating the electrical signals that modulate light within the EAMs, e.g., 1004A, 1004B, 1004C, which are configured directly beneath the drivers in the PIC 1002. For example, the EAMs convert the electrical signals from the modulator drivers into modulated optical signals that can be transmitted through the optical waveguides, e.g., 1000AB, 1000BC, 1000CD, embedded in the PIC. As shown, the waveguides form the optical links between the tiles, enabling high-speed intrachip communication.

[0164] In FIG. 10, TIAs, e.g., 1006B, 1006C, 1006D, transimpedance amplifiers for converting small current signals generated by the photodetectors, e.g., PDs 1008B, 1008C, 1008D, into amplified voltage signals that can be further processed by the system. For example, the photodetectors first convert incoming optical signals into electrical current. For example, the PDs are located in the PIC directly beneath the TIAs, ensuring that the distance between the optical and electronic components is minimal.

[0165] As an example, the clock correction circuit 120-N can be implemented within the modulator driver 1002A and the EAM 1004A to ensure that the clock signals driving the modulation process are synchronized and free from distortions. In various embodiments, the clock correction circuit 120-N is integrated into the modulator driver 1002A to provide timing corrections to the clock signals that modulate the EAM 1004A. The positive and negative clock signals processed through the positive line 810 and negative line 830 of the clock correction circuit 120-N help ensure that the EAM is modulated at the correct times, thereby maintaining the integrity of the optical signals transmitted through the waveguides. For example, crossover section 820 in the clock correction circuit 120-N adjusts the timing of the clock signals to correct any phase mismatches or timing errors, ensuring that the modulated optical signals remain synchronized with the overall system timing.

[0166] For example, the driver circuit in FIG. 9 is implemented in the modulation process within 1002A and 1004A to combine multiple data streams and modulate them onto the optical carrier generated by the EAM. The clock signals driving the 4: 1 MUX are corrected by the clock correction circuit 120-N before being fed into the MUX. This ensures that the multiplexed data streams are accurately aligned with the modulated optical signal, preventing any data errors that could arise from timing mismatches. Attorney Docket No. 07136-0126WO1

[0167] It is to be appreciated that the close alignment between the electronic components, e.g., modulator drivers, TIAs, in the ASIC 1001 and the photonic components, e.g., EAMs, PDs, in the PIC 1002 is important for minimizing the distance over which electrical and optical signals must travel. This minimizes latency and reduces the power required for signal conversion. Additionally, the heat generated by the electronic components in the ASIC can help maintain the EAMs and PDs in the PIC at optimal operating temperatures, enhancing the overall thermal stability and performance of the system.

[0168] EMBODIMENTS

[0169] Although the present invention is defined in the claims, it should be understood that the present invention can also (alternatively) be defined in accordance with the following embodiments:

[0170] 1. A system for correcting differential clock signals, the system comprising: a first input configured to receive a first signal; a second input configured to receive a second signal; a first line coupled to the first input, wherein the first line comprises a plurality of first inverters; a second line coupled to the second input, wherein the second line comprises a plurality of second inverters; and a crossover circuit coupled to the first line at a first node and the second line at a second node, wherein the crossover circuit is configured to: generate a first correction signal with the first signal from the first node passing through a crossover inverter within the crossover circuit; and provide the first correction signal to the second node on the second line to correct the second signal.

[0171] 2. The system of embodiment 1, wherein the crossover circuit comprises: a plurality of switches configured to couple the crossover circuit to the first line at the first node and to the second line at the second node; and a matrix bus configured to set positions of the plurality of switches to select the first node and the second node.

[0172] 3. The system of any one of embodiments 1-2, wherein the circuit comprises: Attorney Docket No. 07136-0126WO1 a plurality of first nodes along the first line, wherein each first node of the plurality of first nodes is positioned as an input to a corresponding first inverter of the plurality of first inverters; and a plurality of second nodes along the second line, wherein each second node of the plurality of second nodes is positioned as an input to a corresponding second inverter of the plurality of second inverters.

[0173] 4. The system of any one of embodiments 1-3, wherein the circuit comprises: a first output connected to an output of the first line; and a second output connected to an output of the second line.

[0174] 5. The system of embodiment 4, wherein the circuit comprises: a controller coupled to the first output from the first line and the second output from the second line, wherein the controller is configured to: measure a difference between the first output and the second output; determine whether the difference between the first output and the second output satisfies a differential threshold; and in response to determining the difference between the first output and the second output does not satisfy the different threshold, determine a desired adjustment to at least one of the first output or the second output.

[0175] 6. The system of embodiment 5, wherein determining the desired adjustment to at least one of the first output or the second output, the circuit is configured to: determine a delay between the first output and the second output; select a configuration of the plurality of switches in the crossover circuit such that the correction signal generated from the first node and provided to the second node compensates for the determined delay, wherein the configuration of the plurality of switches is based on the crossover inverter and at least one of (i) a first inverter of the plurality of first inverters or (ii) a second inverter of the plurality of second inverters.

[0176] 7. The system of embodiment 5, wherein the controller is configured to dynamically adjust at least one of (i) a drive strength of the crossover inverter or (ii) a configuration of a plurality of switches in the crossover circuit. Attorney Docket No. 07136-0126WO1

[0177] 8. The system of embodiment 7, wherein the controller is configured to dynamically adjust at least one of (i) the drive strength of the crossover inverter or (ii) the configuration of a plurality of switches in the crossover circuit based on at least one of time, skew, or phase discrepancies between the first output and the second output.

[0178] 9. The system of embodiment 5, wherein determining the difference between the first output and the second output comprises the circuit is configured to determine a slope of a voltage change of the first output and the second output.

[0179] 10. The system of embodiment 5, wherein the controller is configured to monitor at least one of an edge slope, a deviation in duty cycle, or a phase skew of the first output and the second output.

[0180] 11. The system of embodiment 10, wherein the circuit is configured to assign a configuration of the crossover circuit in response to detecting at least one of the edge slope, the deviation in duty cycle, or the phase skew of the first output and the second output do not satisfy a threshold value.

[0181] 12. The system of any one of embodiments 1-11, wherein the crossover inverter in the crossover circuit is configured to perform duty cycle correction and inter-symbol inference (ISI) equalization.

[0182] 13. The system of any one of embodiments 1-12, wherein the crossover inverter is configured to provide pre-tap equalization by generating the first correction signal based on a delayed and inverted version of the first signal from the first node.

[0183] 14. The system of any one of embodiments 1-13, wherein the crossover inverter comprises a programmable driver that is controlled by a set of digital control bits, the set of digital control bits configures the crossover inverter for a drive level strength of the first correction signal.

[0184] 15. A method for correcting differential clock signals, the method comprising: receiving a first signal at a first input; receiving a second signal at a second input; propagating the first signal along a first line, the first line comprising a plurality of first inverters; propagating the second signal along a second line, the second line comprising a plurality of second inverters; Attorney Docket No. 07136-0126WO1 generating, at a crossover circuit coupled between the first line at a first node and the second line at a second node, a first correction signal by processing the first signal from the first node passing through a crossover circuit within the crossover circuit; and providing the first correction signal to the second node on the second line to correct the second signal.

[0185] 16. The method of embodiment 15, further comprising: coupling the crossover circuit to the first line at the first node and to the second line at the second node using a plurality of switches; and setting positions of the plurality of switches to select the first node and the second node using a matrix bus.

[0186] 17. The method of any one of embodiments 15-16, wherein the first line comprises a plurality of first nodes, each first node of the plurality of first nodes is positioned as an input to a corresponding first inverter of the plurality of first inverters.

[0187] 18. The method of any one of embodiments 15-17, wherein the second line comprises a plurality of second nodes along the second line, each second node of the plurality of second nodes is positioned as an input to a corresponding second inverter of the plurality of second inverters.

[0188] 19. The method of any one of embodiments 15-18, wherein the first line comprises a first output and the second line comprises a second output.

[0189] 20. The method of any one of embodiments 15-19, further comprising: measuring, using a controller that is coupled to the first output from the first line and the second output from the second line, a difference between the first output and the second output; determining whether the difference between the first output and the second output satisfies a differential threshold; and in response to determining the difference between the first output and the second output does not satisfy the different threshold, determining a desired adjustment to at least one of the first output or the second output.

[0190] This specification uses the term “configured to” in connection with systems, apparatus, and computer program components. That a system is configured to perform particular operations or actions means that the system has installed on it software, firmware, hardware, or a Attorney Docket No. 07136-0126WO1 combination of them that in operation cause the system to perform the operations or actions. That one or more computer programs is configured to perform particular operations or actions means that the one or more programs include instructions that, when executed, perform the operations or actions. That special -purpose circuitry is configured to perform particular operations or actions means that the circuitry circuit elements that, when put into operation, perform the operations or actions.

[0191] This specification uses the term “configured to” in connection with systems, apparatus, and computer program components. That a system is configured to perform particular operations or actions means that the system has installed on it software, firmware, hardware, or a combination of them that in operation cause the system to perform the operations or actions. That one or more computer programs is configured to perform particular operations or actions means that the one or more programs include instructions that, when executed, perform the operations or actions. That special-purpose circuitry is configured to perform particular operations or actions means that the circuitry circuit elements that, when put into operation, perform the operations or actions.

[0192] The articles “a,” “an,” and “the” are intended to mean that there are one or more of the elements in the preceding descriptions. The terms “comprising,” “including,” and “having” are intended to be inclusive and mean that there may be additional elements other than the listed elements. Additionally, it should be understood that references to “one example” or “an example” of the present disclosure are not intended to be interpreted as excluding the existence of additional examples that also incorporate the recited features. For example, any element described in relation to an example herein may be combinable with any element of any other example described herein. Numbers, percentages, ratios, or other values stated herein are intended to include that value, and also other values that are “about” or “approximately” the stated value, as would be appreciated by one of ordinary skill in the art encompassed by examples of the present disclosure. A stated value should therefore be interpreted broadly enough to encompass values that are at least close enough to the stated value to perform a desired function or achieve a desired result. The stated values include at least the variation to be expected in a suitable manufacturing or production process, and may include values that are within 5%, within 1%, within 0.1%, or within 0.01% of a stated value. Attorney Docket No. 07136-0126WO1

[0193] A person having ordinary skill in the art should realize in view of the present disclosure that equivalent constructions do not depart from the spirit and scope of the present disclosure, and that various changes, substitutions, and alterations may be made to examples disclosed herein without departing from the spirit and scope of the present disclosure. Equivalent constructions, including functional “means-plus-function” clauses are intended to cover the structures described herein as performing the recited function, including both structural equivalents that operate in the same manner, and equivalent structures that provide the same function. It is the express intention of the applicant not to invoke means-plus-function or other functional claiming for any claim except for those in which the words ‘means for’ appear together with an associated function. Each addition, deletion, and modification to the examples that falls within the meaning and scope of the claims is to be embraced by the claims.

[0194] The terms “approximately,” “about,” and “substantially” as used herein represent an amount close to the stated amount that still performs a desired function or achieves a desired result. For example, the terms “approximately,” “about,” and “substantially” may refer to an amount that is within less than 5% of, within less than 1% of, within less than 0.1% of, and within less than 0.01% of a stated amount. Further, it should be understood that any directions or reference frames in the preceding description are merely relative directions or movements. For example, any references to “up” and “down” or “above” or “below” are merely descriptive of the relative position or movement of the related elements.

[0195] While this specification contains many specific implementation details, these should not be construed as limitations on the scope of any invention or of what may be claimed, but rather as descriptions of features that may be specific to particular embodiments of particular inventions. Certain features that are described in this specification in the context of separate embodiments can also be implemented in combination in a single embodiment. Conversely, various features that are described in the context of a single embodiment can also be implemented in multiple embodiments separately or in any suitable subcombination. Moreover, although features may be described above as acting in certain combinations and even initially claimed as such, one or more features from a claimed combination can in some cases be excised from the combination, and the claimed combination may be directed to a subcombination or variation of a subcombination. Attorney Docket No. 07136-0126WO1

[0196] Similarly, while operations are depicted in the drawings in a particular order, this should not be understood as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desirable results. In certain circumstances, multitasking and parallel processing may be advantageous. Moreover, the separation of various system modules and components in the embodiments described above should not be understood as requiring such separation in all embodiments, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products.

[0197] Particular embodiments of the subject matter have been described. Other embodiments are within the scope of the following claims. For example, the actions recited in the claims can be performed in a different order and still achieve desirable results. As one example, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In certain implementations, multitasking and parallel processing may be advantageous. What is claimed is:

Claims

Attorney Docket No. 07136-0126WO1CLAIMS1. A circuit compri sin : a first input configured to receive a first signal; a second input configured to receive a second signal; a first line coupled to the first input, wherein the first line comprises a plurality of first inverters; a second line coupled to the second input, wherein the second line comprises a plurality of second inverters; and a crossover circuit coupled to the first line at a first node and the second line at a second node, wherein the crossover circuit is configured to: generate a first correction signal with the first signal from the first node passing through a crossover inverter within the crossover circuit; and provide the first correction signal to the second node on the second line to correct the second signal.

2. The circuit of claim 1, wherein the crossover circuit comprises: a plurality of switches configured to couple the crossover circuit to the first line at the first node and to the second line at the second node; and a matrix bus configured to set positions of the plurality of switches to select the first node and the second node.

3. The circuit of claim 1, wherein the circuit comprises: a plurality of first nodes along the first line, wherein each first node of the plurality of first nodes is positioned as an input to a corresponding first inverter of the plurality of first inverters; and a plurality of second nodes along the second line, wherein each second node of the plurality of second nodes is positioned as an input to a corresponding second inverter of the plurality of second inverters.

4. The circuit of claim 1, wherein the circuit comprises: a first output connected to an output of the first line; andAttorney Docket No. 07136-0126WO1 a second output connected to an output of the second line.

5. The circuit of claim 4, wherein the circuit comprises: a controller coupled to the first output from the first line and the second output from the second line, wherein the controller is configured to: measure a difference between the first output and the second output; determine whether the difference between the first output and the second output satisfies a differential threshold; and in response to determining the difference between the first output and the second output does not satisfy the different threshold, determine a desired adjustment to at least one of the first output or the second output.

6. The circuit of claim 5, wherein determining the desired adjustment to at least one of the first output or the second output, the circuit is configured to: determine a delay between the first output and the second output; select a configuration of the plurality of switches in the crossover circuit such that the correction signal generated from the first node and provided to the second node compensates for the determined delay, wherein the configuration of the plurality of switches is based on the crossover inverter and at least one of (i) a first inverter of the plurality of first inverters or (ii) a second inverter of the plurality of second inverters.

7. The circuit of claim 5, wherein the controller is configured to dynamically adjust at least one of (i) a drive strength of the crossover inverter or (ii) a configuration of a plurality of switches in the crossover circuit.

8. The circuit of claim 7, wherein the controller is configured to dynamically adjust at least one of (i) the drive strength of the crossover inverter or (ii) the configuration of a plurality of switches in the crossover circuit based on at least one of time, skew, or phase discrepancies between the first output and the second output.Attorney Docket No. 07136-0126WO19. The circuit of claim 5, wherein determining the difference between the first output and the second output comprises the circuit is configured to determine a slope of a voltage change of the first output and the second output.

10. The circuit of claim 5, wherein the controller is configured to monitor at least one of an edge slope, a deviation in duty cycle, or a phase skew of the first output and the second output.

11. The circuit of claim 10, wherein the circuit is configured to assign a configuration of the crossover circuit in response to detecting at least one of the edge slope, the deviation in duty cycle, or the phase skew of the first output and the second output do not satisfy a threshold value.

12. The circuit of claim 1, wherein the crossover inverter in the crossover circuit is configured to perform duty cycle correction and inter-symbol inference (ISI) equalization.

13. The circuit of claim 1, wherein the crossover inverter is configured to provide pre-tap equalization by generating the first correction signal based on a delayed and inverted version of the first signal from the first node.

14. The circuit of claim 1, wherein the crossover inverter comprises a programmable driver that is controlled by a set of digital control bits, the set of digital control bits configures the crossover inverter for a drive level strength of the first correction signal.

15. A method comprising: receiving a first signal at a first input; receiving a second signal at a second input; propagating the first signal along a first line, the first line comprising a plurality of first inverters; propagating the second signal along a second line, the second line comprising a plurality of second inverters;Attorney Docket No. 07136-0126WO1 generating, at a crossover circuit coupled between the first line at a first node and the second line at a second node, a first correction signal by processing the first signal from the first node passing through a crossover circuit within the crossover circuit; and providing the first correction signal to the second node on the second line to correct the second signal.

16. The method of claim 15, further comprising: coupling the crossover circuit to the first line at the first node and to the second line at the second node using a plurality of switches; and setting positions of the plurality of switches to select the first node and the second node using a matrix bus.

17. The method of claim 15, wherein the first line comprises a plurality of first nodes, each first node of the plurality of first nodes is positioned as an input to a corresponding first inverter of the plurality of first inverters.

18. The method of claim 15, wherein the second line comprises a plurality of second nodes along the second line, each second node of the plurality of second nodes is positioned as an input to a corresponding second inverter of the plurality of second inverters.

19. The method of claim 15, wherein the first line comprises a first output and the second line comprises a second output.

20. The method of claim 15, further comprising: measuring, using a controller that is coupled to the first output from the first line and the second output from the second line, a difference between the first output and the second output; determining whether the difference between the first output and the second output satisfies a differential threshold; and in response to determining the difference between the first output and the second output does not satisfy the different threshold, determining a desired adjustment to at least one of the first output or the second output.

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