Die, chip packaging structure, and electronic device

Abstract

The present application provides a die, a chip packaging structure, and an electronic device, which can meet the power supply requirements of multi-stage inverters in data channels without occupying external power supply resources. The die comprises at least one charge pump and at least one data channel. A power supply terminal of the charge pump is connected to a high-level power supply terminal and a low-level power supply terminal. The data channel comprises a first channel and a second channel, the first channel comprises multiple series-connected first inverters, and the second channel comprises multiple series-connected second inverters. A first power supply terminal of the multiple series-connected first inverters is connected to the high-level power supply terminal, a second power supply terminal of the multiple series-connected second inverters is connected to the low-level power supply terminal, an output terminal of the charge pump is connected to a second power supply terminal of the multiple series-connected first inverters and a first power supply terminal of the multiple series-connected second inverters and provides a first level, and the first level is an intermediate level between the high-level power supply terminal and the low-level power supply terminal.

Description

Bare die and chip packaging structure, electronic devices Technical Field

[0001] This application relates to the field of power supply technology, and in particular to a bare die and chip packaging structure and electronic equipment. Background Technology

[0002] In chips (especially network chips), long-distance traces can cover up to 50% of the chip area. The traditional trace method is full swing, with the trace voltage swing between 0 and VDD. Using this trace method will cause the trace power consumption to account for more than 17% of the total power consumption.

[0003] To reduce power consumption during wiring, as shown in Figure 1, a novel wiring method is provided in the prior art. This method uses a voltage stacking bus (VSB) to stack multiple inverters (INV stacking), enabling current sharing between the top and bottom channels, thereby reducing power consumption. This scheme requires an intermediate level Vmid to be introduced through a low dropout regulator (LDO), with a standard value of 0.5*VDD. The signal swing of both the top and bottom channels is 0.5*VDD; the top channel signal oscillates between 0.5*VDD and VDD, while the bottom channel signal oscillates between 0 and 0.5*VDD. When the currents of the top and bottom channels are perfectly matched, the intermediate level Vmid can naturally be stabilized at 0.5*VDD. However, due to the randomness of the signal pattern, a regulated power supply is required for the intermediate level Vmid.

[0004] Existing LDOs are divided into two types: on-chip low dropout power (OCLDC) and off-chip LDOs. On-chip LDOs are housed in a larger IP core (intellectual property core), requiring additional analog and digital power supplies, thus consuming chip solder bump resources. Off-chip LDOs, on the other hand, consume power resources from the printed circuit board (PCB) and package, and cannot meet the needs of the widely distributed voltage stacking buses (VSB) within the chip. Summary of the Invention

[0005] This application provides a bare die and chip packaging structure and an electronic device that can adapt to the power supply requirements of multi-stage inverters in the data channel without occupying external power supply resources.

[0006] This application provides a bare die (chip) including at least one charge pump, at least one data channel, a high-level power supply terminal VDD, and a low-level power supply terminal VSS. The charge pump includes an output terminal, and its power supply terminal is connected to both the high-level and low-level power supply terminals. Each data channel includes a first channel and a second channel. The first channel includes multiple series-connected first inverters, and the second channel includes multiple series-connected second inverters. The first power supply terminal of each series-connected first inverter is connected to the high-level power supply terminal, and its second power supply terminal is connected to the output terminal. The first power supply terminal of each series-connected second inverter is connected to the output terminal, and its second power supply terminal is connected to the low-level power supply terminal. The output terminal of the charge pump provides a first voltage level to both the second power supply terminal and the first power supply terminal of the series-connected first inverters. This first voltage level is an intermediate level between the high-level and low-level power supply terminals. This intermediate level is equal to or approximately equal to half the voltage of the high-level power supply terminal.

[0007] In other words, in the chip provided in this application, the data channel adopts a voltage stacking bus (VSB) routing method. Under this condition, the signal swing of the first and second channels in the data channel can be reduced, and current sharing can be achieved, thereby reducing power consumption. On this basis, the chip uses an on-chip charge pump to power the multi-stage inverters in the first and second channels. On the one hand, it does not occupy board-level power supply resources, that is, it does not occupy the power supply resources of the circuit board (PCB) and package. On the other hand, the charge pump does not require external power supply resources. The original power supply terminals (VDD, VSS) inside the chip can meet the requirements, and it does not occupy the chip's solder joint (bump, ball) resources. Furthermore, the charge pump itself has high efficiency and occupies a small area, which can be flexibly distributed inside the chip, and can better match the widely distributed data channels.

[0008] In some possible implementations, the die includes multiple data channels and multiple charge pumps. Each data channel is connected to a different charge pump. Because charge pumps themselves have a small area, multiple charge pumps can be flexibly distributed across the die as needed.

[0009] In some possible implementations, the die also includes control circuitry for generating a first clock signal and a second clock signal. The charge pump is configured to output a first level (i.e., an intermediate level) via its output terminal under the control of the first and second clock signals. Illustrated, the first and second clock signals can be a set of non-overlapping clock signals.

[0010] In some possible implementations, the charge pump includes a first transistor, a second transistor, a third transistor, a fourth transistor, and a first capacitor. The gate of the first transistor is connected to a first clock signal terminal, its first terminal is connected to a high-level power supply terminal, and its second terminal is connected to the first terminal of the first capacitor. The gate of the second transistor is connected to a second clock signal terminal, its first terminal is connected to an output terminal, and its second terminal is connected to the first terminal of the first capacitor. The gate of the third transistor is connected to the first clock signal terminal, its first terminal is connected to the output terminal, and its second terminal is connected to the second terminal of the first capacitor. The gate of the fourth transistor is connected to the second clock signal terminal, its first terminal is connected to a low-level power supply terminal, and its second terminal is connected to the second terminal of the first capacitor. Of the first, second, third, and fourth transistors, one of their first and second terminals is the source, and the other is the drain.

[0011] Under the control of the first and second clock signals, this charge pump operates in two phases. In the first phase, the first and third transistors are turned on, while the second and fourth transistors are turned off, resulting in an output level (intermediate level). In the second phase, the first and third transistors are turned off, while the second and fourth transistors are turned on, again outputting the first level (intermediate level). Compared to traditional charge pumps, this charge pump has a simpler circuit structure, uses fewer transistors, and has a smaller area advantage, making it easier to flexibly distribute within the chip and facilitating smaller chip designs. Furthermore, this charge pump offers better output voltage stability and energy efficiency.

[0012] In some possible implementations, the first, second, third, and fourth transistors are all N-type field-effect transistors. In this case, when the first clock signal input is high and the second clock signal input is low, the first and third transistors are turned on, the second and fourth transistors are turned off, and the output terminal outputs a first level (i.e., an intermediate level). When the first clock signal input is low and the second clock signal input is high, the first and third transistors are turned off, the second and fourth transistors are turned on, and the output terminal outputs a first level (i.e., an intermediate level).

[0013] In some possible implementations, the first, second, third, and fourth transistors are all P-type field-effect transistors. In this case, when the first clock signal input is high and the second clock signal input is low, the first and third transistors are off, while the second and fourth transistors are on, and the output terminal outputs a first level (i.e., an intermediate level). When the first clock signal input is low and the second clock signal input is high, the first and third transistors are on, while the second and fourth transistors are off, and the output terminal outputs a first level (i.e., an intermediate level).

[0014] In some possible implementations, the aforementioned die can be a network chip. Since network chips have long and dispersed traces, the novel power supply method of this application can significantly reduce trace power consumption by reducing the swing of the data signal.

[0015] This application also provides a chip packaging structure, which includes a substrate and a die as provided in any of the aforementioned possible implementations, the die being disposed on the substrate and electrically connected to the substrate.

[0016] In some possible implementations, the chip package structure also includes a filter circuit connected to the output terminal to filter the output level. This filter circuit reduces voltage noise fluctuations at the output terminal.

[0017] In some possible implementations, the filter circuit includes a second capacitor connected between the high-level power supply terminal and the output terminal. This second capacitor filters the output level, reducing voltage noise fluctuations at the output terminal.

[0018] In some possible implementations, the filter circuit includes a third capacitor connected between the low-level power supply terminal and the output terminal. This third capacitor filters the output level, reducing voltage noise fluctuations at the output terminal.

[0019] In some possible implementations, the filter circuit includes a fourth capacitor, multiple resistors, and multiple inductors. The fourth capacitor is connected between the low-level power supply and the output terminal, and the multiple resistors and multiple inductors are alternately connected in series between the fourth capacitor and the output terminal. In this case, the multiple resistors and multiple inductors alternately connected in series form a resistor-inductor circuit (RL circuit), and this RL circuit, connected in series with the fourth capacitor between the low-level power supply and the output terminal, can effectively reduce voltage noise fluctuations at the output terminal.

[0020] In some possible implementations, the outputs of multiple charge pumps are connected to the same filter circuit. In this case, multiple charge pumps can share the same filter circuit, thereby saving space and chip area resources.

[0021] In some possible implementations, the filter circuit is placed on the die, which is more conducive to highly integrated design.

[0022] In some possible implementations, some or all of the components in the filter circuit are mounted on the substrate independently of the die, which facilitates the placement of large-volume components and thus meets the wide range of needs of a wider range of devices.

[0023] In some possible implementations, the die also includes a first D flip-flop, a first buffer, and a second D flip-flop; wherein the output of the first D flip-flop is connected to the input of a multi-stage series-connected first inverter, the output of the multi-stage series-connected first inverter is connected to the input of the first buffer, and the output of the first buffer is connected to the input of the second D flip-flop. The die also includes a third D flip-flop, a second buffer, and a fourth D flip-flop; wherein the output of the third D flip-flop is connected to the input of a multi-stage series-connected second inverter, the output of the multi-stage series-connected second inverter is connected to the input of the second buffer, and the output of the second buffer is connected to the input of the fourth D flip-flop.

[0024] This application also provides an electronic device, which further includes a circuit board and a die as described in any of the aforementioned possible implementations, the die being electrically connected to the circuit board. Attached Figure Description

[0025] Figure 1 is a power supply diagram of a voltage stacking bus provided in the prior art;

[0026] Figure 2 is a schematic diagram of a circuit board and chip packaging structure in an electronic device provided in an embodiment of this application;

[0027] Figure 3 is a schematic diagram of the module connection inside a chip according to an embodiment of this application;

[0028] Figure 4 is a power supply schematic diagram of a voltage stacking bus provided in an embodiment of this application;

[0029] Figure 5 is a schematic diagram of the circuit structure of an inverter provided in an embodiment of this application;

[0030] Figure 6 is a power supply schematic diagram of a voltage stacking bus provided in an embodiment of this application;

[0031] Figure 7 is a schematic diagram of the relevant circuit of a charge pump provided in an embodiment of this application;

[0032] Figure 8 is a timing diagram of the clock signal control of a charge pump provided in an embodiment of this application;

[0033] Figure 9 is a schematic diagram of a charge pump circuit provided in an embodiment of this application;

[0034] Figure 10 is a schematic diagram of a charge pump circuit provided in an embodiment of this application;

[0035] Figure 11 is a circuit diagram of a charge pump provided in an embodiment of this application;

[0036] Figure 12 is a clock signal control timing diagram of a charge pump provided in an embodiment of this application;

[0037] Figure 13 is a schematic diagram of a charge pump circuit provided in an embodiment of this application;

[0038] Figure 14 shows a comparison curve of the output voltage of the charge pumps provided in Example 1 and Example 2;

[0039] Figure 15 shows the performance comparison curves of the charge pumps provided in Example 1 and Example 2. Detailed Implementation

[0040] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0041] The terms "first," "second," etc., used in the specification, embodiments, claims, and drawings of this application are for distinguishing purposes only and should not be construed as indicating or implying relative importance or order. "Connected," "linked," etc., should be interpreted broadly, for example, as an electrical connection or a mechanical connection; a direct connection or an indirect connection through an intermediate medium; or a connection within two elements. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion, such as including a series of steps or units. A method, product, or apparatus is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to these processes, methods, products, or apparatuses. "Upper," "lower," etc., are used only with respect to the orientation of components in the drawings. These directional terms are relative concepts used for relative description and clarification and may vary accordingly depending on the orientation of the components in the drawings.

[0042] This application provides an electronic device, as shown in FIG2. The electronic device includes a printed circuit board (PCB) and a chip package structure 01 disposed on the PCB. The chip package structure 01 uses a novel chip D (or die). The chip D supplies power to the voltage stacking bus (VSB) through an on-chip charge pump, without requiring external power supply resources. It has a small area and can be widely distributed in the chip to meet the power supply requirements of the VSB.

[0043] This application does not limit the form of the aforementioned electronic device. The electronic device can be any electronic product, such as consumer electronics, home electronics, automotive electronics, financial terminal products, communication electronic products, etc.

[0044] As illustrated, the aforementioned consumer electronics products can include mobile phones, tablet computers, laptops, personal computers (PCs), personal digital assistants (PDAs), smart wearable products (e.g., smartwatches, smart bracelets), virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, drones, etc. Home electronics products can include smart door locks, televisions, smart speakers, refrigerators, robot vacuum cleaners, etc. In-vehicle electronics products can include in-vehicle navigation systems, in-vehicle displays, etc. Financial terminal products can include automated teller machines (ATMs), self-service electronic devices, etc. Communication electronics products can include servers, storage devices, radar, base stations, and other communication equipment.

[0045] Depending on actual needs, the above-mentioned electronic device may also include other devices electrically connected to the chip, such as input / output devices, etc., and this application does not impose any restrictions on this.

[0046] This application does not limit the packaging type of the above-mentioned chip packaging structure 01, such as 2D or 3D packaging.

[0047] Of course, referring to Figure 2, in addition to chip D, the chip package structure 01 may also include substrate 1 and other peripheral devices (2, 3). In this case, chip D and peripheral devices (2, 3) can be disposed on substrate 1 and electrically connected to substrate 1.

[0048] The following describes the novel chip (bare die) and related settings in the chip packaging structure provided in the embodiments of this application.

[0049] As illustrated, this application provides a chip D, such as a network chip (but not limited thereto), referring to FIG3. The chip D includes a first module A1, a second module A2, and a voltage stacking bus VSB. The first module A1 is connected to the second module A2 through the voltage stacking bus VSB, thereby realizing data interaction between the first module A1 and the second module A2. That is, the voltage stacking bus VSB connects different modules to meet the data interaction between modules.

[0050] This application does not limit the types of the first module A1 and the second module A2 mentioned above, as long as they are modules in the chip that need to perform data interaction. For example, the first module A1 and the second module A2 can be storage modules, interface modules, power supply modules, data conversion modules, etc.

[0051] Based on this, as shown in Figure 2, the chip is also equipped with a charge pump OCCP (also known as an on-chip charge pump) connected to the voltage stacking bus VSB. The charge pump OCCP supplies power to the voltage stacking bus VSB to meet the power requirements of the voltage stacking bus VSB.

[0052] In existing technologies, either an off-chip LDO or an on-chip LDO is used to power the voltage stack bus (VSB). Powering an off-chip LDO will occupy the power supply resources of the printed circuit board (PCB) and the package, while an on-chip LDO will involve multiple additional analog and digital power supplies, which will occupy the chip's solder joint (bump, ball) resources. Both of these technologies have certain drawbacks.

[0053] In contrast, this application uses an on-chip charge pump OCCP to power the voltage stacking bus (VSB). On the one hand, it does not occupy the power supply resources of the circuit board (PCB) and package (i.e., it does not occupy board-level power supply resources); on the other hand, the charge pump OCCP does not require external power supply resources, and the original power supply terminals (VDD, VSS) inside the chip can meet the requirements. It does not occupy the chip's solder joint (bump, ball) resources. Furthermore, the charge pump OCCP itself occupies a small area and can be flexibly distributed inside the chip, which can better match the widely distributed voltage stacking bus (VSB).

[0054] Furthermore, compared to traditional on-chip LDOs, the on-chip charge pump in this application has the advantage of smaller area, enabling an area gain of over 20% within the chip. Additionally, using an on-chip charge pump for power supply offers higher energy efficiency and reduces chip power consumption; for example, a single charge pump can support a peak load current of 4mA with an energy efficiency exceeding 95%.

[0055] The following explains the settings for the charge pump OCCP in conjunction with the voltage stack bus VSB.

[0056] As illustrated in Figure 4, the Voltage Stacking Bus (VSB) includes at least one data channel 10. Each data channel 10 includes a first channel 100 (also known as the top channel) and a second channel 200 (also known as the bottom channel) stacked together. The first channel 100 and the second channel 200 can share current, thereby reducing power consumption. Figure 4 only illustrates one data channel 10 as an example.

[0057] Referring again to Figure 4, the first channel 100 includes multiple series-connected first inverters a1, and the second channel 200 includes multiple series-connected second inverters a2. The positive power supply terminals (also referred to as the first power supply terminals) of the multiple series-connected first inverters a1 are all connected to the high-level power supply terminal VDD. The negative power supply terminals (also referred to as the second power supply terminals) of the multiple series-connected first inverters a1 and the positive power supply terminals of the multiple series-connected second inverters a2 are respectively connected, and both the negative power supply terminals of the multiple series-connected first inverters a1 and the positive power supply terminals of the multiple series-connected second inverters a2 are connected to the output terminal VO of the charge pump OCCP. The negative power supply terminals of the multiple series-connected second inverters a2 are all connected to the low-level power supply terminal VSS. The low-level power supply terminal VSS can be grounded (gnd). It should be understood that the positive and negative power supply terminals serve as a set of power supply terminals for the inverters, with the voltage at the positive power supply terminal being greater than the voltage at the negative power supply terminal, thus meeting the power supply requirements of the inverters.

[0058] As illustrated, the inverters (a1, a2) involved in this application can be CMOS (complementary metal oxide semiconductor) inverters, but are not limited to this. As shown in Figure 5, the core components of a CMOS inverter consist of PMOS and NMOS, which are connected in a complementary and symmetrical manner. That is, the gates of the PMOS and NMOS are connected as the input terminal IN, and the drains are connected as the output terminal OUT. The source of the PMOS is connected to the positive power supply terminal, and the source of the NMOS is connected to the negative power supply terminal. When the input terminal IN is high, the NMOS is turned on, the PMOS is turned off, and the output terminal OUT outputs a low level; when the input terminal IN is low, the NMOS is turned off, the PMOS is turned on, and the output terminal OUT outputs a high level; that is, the inverter can reverse the phase of the input signal by 180° before outputting it.

[0059] Of course, Figure 5 is illustrated by connecting the positive and negative power supply terminals of the inverters (a1, a2) to the high-level power supply terminal VDD and the low-level power supply terminal VSS, respectively. In this application, the positive and negative power supply terminals of the inverters can be connected according to their functional requirements.

[0060] The output terminal VO of the charge pump OCCP provides an intermediate level Vmid (also called the first voltage) to the negative power supply terminal of the multi-stage series-connected first inverter a1 and the positive power supply terminal of the multi-stage series-connected second inverter a2. This intermediate level Vmid is the voltage between the high-level power supply terminal VDD and the low-level power supply terminal VSS, that is, the intermediate level Vmid is equal to or approximately equal to half of the voltage of the high-level power supply terminal VDD, that is, the intermediate level Vmid fluctuates around 0.5*VDD. If it can fluctuate within ±5% of 0.5*VDD, it can be expressed as Vmid≈0.5*VDD. In this case, the signal swing of the first channel 100 and the second channel 200 is both 0.5*VDD. The signal of the first channel 100 swings between 0.5*VDD and VDD, and the signal of the second channel 200 swings between 0 and 0.5*VDD.

[0061] As illustrated, in some possible implementations, the aforementioned chip is a network chip, which is equivalent to a microprocessor that transmits and receives data (including voice and video) in a communication network. The network chip has long, distributed traces and uses a voltage stacked bus (VSB) to significantly reduce trace power consumption by minimizing the swing of the data signal.

[0062] In addition, the chip also includes other devices such as triggers and buffers that are connected to the voltage stacking bus (VSB), which can be configured as needed in practice.

[0063] Schematic diagram, referring to Figure 4, shows that the chip also includes: a first D flip-flop DFF1, a first buffer BUFF1, and a second D flip-flop DFF2 connected to the first channel 100; and a third D flip-flop DFF3, a second buffer BUFF2, and a fourth D flip-flop DFF4 connected to the second channel 200. The output of the first D flip-flop DFF1 is connected to the input of a multi-stage cascaded first inverter a1; the output of the multi-stage cascaded first inverter a1 is connected to the input of the first buffer BUFF1; and the output of the first buffer BUFF1 is connected to the input of the second D flip-flop DFF2. The output of the third D flip-flop DFF3 is connected to the input of a multi-stage cascaded second inverter a2; the output of the multi-stage cascaded second inverter a2 is connected to the input of the second buffer BUFF2; and the output of the second buffer BUFF2 is connected to the input of the fourth D flip-flop DFF4. The inputs of the first D flip-flop DFF1 and the third D flip-flop DFF3 are used to connect to one module in the chip, and the outputs of the second buffer BUFF2 and the fourth D flip-flop DFF4 are used to connect to another module in the chip. In this way, data interaction between the two modules can be achieved through the voltage stacking bus VSB.

[0064] It should be noted that Figure 4 is illustrated using the example of two inverters in the first channel 100 and the second channel 200, but this application is not limited to this and may also have four, six, etc., as shown in Figure 6.

[0065] In addition, Figure 4 is illustrated using a voltage stacking bus (VSB) that includes a data channel (a first channel 100 and a second channel 200) as an example, but this application is not limited to this.

[0066] Schematic, referring to Figure 6, in some possible implementations, the voltage stacking bus (VSB) may include multiple data channels 10. In this case, a charge pump OCCP can be individually configured in the chip to power each data channel 10, meaning that multiple data channels 10 are connected to different charge pump OCCPs. Since the charge pump OCCP itself has the advantage of small area, multiple charge pump OCCPs can be flexibly distributed in the chip as needed. For example, multiple charge pump OCCPs can be staggered (see Figure 6), but this is not a limitation.

[0067] This application does not impose any restrictions on the specific circuit structure of the charge pump OCCP, as long as the charge pump can stably output the intermediate level Vmid (0.5*VDD) to the voltage stack bus VSB without occupying external power supply resources.

[0068] The following specific embodiments illustrate the charge pump OCCP and related settings.

[0069] Example 1

[0070] Schematic, referring to Figure 7, this embodiment provides a charge pump OCCP, which is connected to a first clock signal terminal S1, a second clock signal terminal S2, a high-level power supply terminal VDD, and a low-level power supply terminal VSS. Under the control of the clock signals of the first clock signal terminal S1 and the second clock signal terminal S2, the output terminal VO can output an intermediate level Vmid (0.5*VDD).

[0071] Of course, the chip is equipped with a control circuit that is connected to the first clock signal terminal S1 and the second clock signal terminal S2. The control circuit generates a clock signal and outputs it to the first clock signal terminal S1 and the second clock signal terminal S2 to satisfy the control of the charge pump OCCP.

[0072] As illustrated in Figure 8, in some possible implementations, the clock signals input to the first clock signal terminal S1 and the second clock signal terminal S2 can be a set of non-overlapping clock signals. The clock signals input to the two clock signal terminals are not simultaneously high, but there can be a brief overlap (e.g., tens of picoseconds / ps). Illustrated, when the clock signal input to the first clock signal terminal S1 is high, the clock signal input to the second clock signal terminal S2 is low; conversely, when the clock signal input to the first clock signal terminal S1 is low, the clock signal input to the second clock signal terminal S2 is high.

[0073] Referring again to Figure 7, the charge pump OCCP may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, and a first capacitor C1. The gate of the first transistor T1 is connected to the first clock signal terminal S1, the source of the first transistor T1 is connected to the high-level power supply terminal VDD, and the drain of the first transistor T1 is connected to the first terminal of the first capacitor C1. The gate of the second transistor T2 is connected to the second clock signal terminal S2, the source of the second transistor T2 is connected to the output terminal VO, and the drain of the second transistor T2 is connected to the first terminal of the first capacitor C1. The gate of the third transistor T3 is connected to the first clock signal terminal S1, the source of the third transistor T3 is connected to the output terminal VO, and the drain of the third transistor T3 is connected to the second terminal of the first capacitor C1. The gate of the fourth transistor T4 is connected to the second clock signal terminal S2, the source of the fourth transistor T4 is connected to the second terminal of the first capacitor C1, and the drain of the fourth transistor T4 is connected to the low-level power supply terminal VSS.

[0074] It should be noted that the source and drain of the transistors (such as T1, T2, T3, T4) involved in this embodiment do not need to be clearly distinguished. That is, of the two terminals of the transistor other than the gate, one is the source and the other is the drain.

[0075] In addition, it should be noted that this application does not limit the types of the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4. They can all be N-type field-effect transistors or P-type field-effect transistors. This embodiment is described using N-type field-effect transistors as an example.

[0076] The working principle of the above-mentioned charge pump OCCP is briefly explained below.

[0077] Schematic, referring to Figures 7 and 8, each control cycle of the charge pump OCCP may include a first phase P1 (phase 1) and a second phase P2 (phase 2).

[0078] In the first stage P1, the first clock signal terminal S1 is input with a high level, turning on the first transistor T1 and the third transistor T3. The second clock signal terminal S2 is input with a low level, turning off the second transistor T2 and the fourth transistor T4. At this time, the two ends of the first capacitor C1 are connected to the high-level power supply terminal VDD and the output terminal VO, respectively. By charging and discharging the first capacitor C1, the amount of charge stored in the first capacitor C1 is Q1 = (VDD - VO) * C1.

[0079] In the second stage P2, the first clock signal terminal S1 is input with a low level, turning off the first transistor T1 and the third transistor T3. The second clock signal terminal S2 is input with a high level, turning on the second transistor T2 and the fourth transistor T4. At this time, the two ends of the first capacitor C1 are connected to the output terminal VO and the low-level power supply terminal VSS, respectively. By charging and discharging the first capacitor C1, the amount of charge stored in the first capacitor C1 is Q2 = (VO - gnd) * C1 = VO * C1.

[0080] In this way, the charge transfer magnitude δQ=Q1-Q2=(VDD-VO)*C1-VO*C1=(VDD-2VO)*C1 is achieved in two stages (P1+P2) within one cycle.

[0081] When VO < 0.5 * VDD, (VDD - VO) * C1 > VO * C1, that is, δQ = Q1 - Q2 > 0, it is equivalent to continuously drawing charge from VDD - VO to VO - gnd, the voltage of VO - gnd gradually increases, the voltage of VDD - VO gradually decreases, and after several cycles, an equilibrium is reached, δQ ≈ 0, VO ≈ 0.5 * VDD.

[0082] When VO > 0.5*VDD, (VDD - VO)*C1 < VO*C1, that is, δQ = Q1 - Q2 < 0, which is equivalent to continuously drawing charge from VO - gnd to VDD - VO. The voltage of VDD - VO gradually rises, and the voltage of VO - gnd gradually drops. After multiple cycles, equilibrium is reached, δQ≈0, and VO≈0.5*VDD.

[0083] Illustratively, in some actual analog detections, in the first stage P1, the voltage difference across the first capacitor C1 is 0.367V, and the voltage of the output terminal VO is about 0.383V. In the second stage P2, the voltage difference across the first capacitor C1 is 0.381V, and the voltage of the output terminal VO is about 0.375V.

[0084] Of course, there may be a short overlapping stage between the first stage P1 and the second stage P2. Both the first clock signal terminal S1 and the second clock signal terminal S2 input low levels. In this case, the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 are all turned off, and at this time, the output terminal VO maintains the output intermediate level (0.5*VDD).

[0085] That is to say, the voltage across the first capacitor C1 can be controlled to be stable near 0.5*VDD through multiple consecutive cycles (P1, P2).

[0086] In addition, in order to assist in reducing the voltage noise fluctuation of the output terminal VO, in some possible implementation manners, a filter circuit can be provided at the output terminal VO to filter the level output from the output terminal VO through this filter circuit.

[0087] Illustratively, in some possible implementation manners, by setting the filter circuit, the fluctuation of the level (0.5*VDD) output from the output terminal VO can be controlled within ±5%.

[0088] This embodiment does not limit the circuit structure of the filter circuit, and it can be set according to needs in practice as long as it can meet the filtering requirements of the output terminal VO.

[0089] For example, as shown in FIG. 9, in some possible implementation manners, the filter circuit 20 may include a second capacitor C2 and a third capacitor C3. Among them, the second capacitor C2 is connected between the high - level power supply terminal VDD and the output terminal VO, and the third capacitor C3 is connected between the low - level power supply terminal VSS and the output terminal VO.

[0090] Of course, in some other possible implementation manners, the filter circuit 20 may also only include the second capacitor C2 or only include the third capacitor C3. This application does not limit this, and in this embodiment, it is illustrated by taking the filter circuit 20 including the second capacitor C2 and the third capacitor C3 as an example.

[0091] For example, referring to Figure 10, in some possible implementations, the filter circuit 20 may include a fourth capacitor C4, multiple resistors R, and multiple inductors L. The fourth capacitor C4 is connected between the low-level power supply terminal VSS and the output terminal VO, and the multiple resistors R and multiple inductors L are alternately connected in series between the fourth capacitor C4 and the output terminal VO. In this case, the multiple resistors R and multiple inductors L alternately connected in series form a resistor-inductor circuit (RL circuit), and this RL circuit, connected in series with the fourth capacitor C4 between the low-level power supply terminal VSS and the output terminal VO, can effectively reduce voltage noise fluctuations at the output terminal VO.

[0092] This application does not impose any restrictions on the placement of the components in the filter circuit 20; in practice, the design can be carried out as needed.

[0093] For example, in some possible implementations, all the components in the filter circuit 20 can be housed in a chip.

[0094] For example, in some possible implementations, the devices in the filter circuit 20 can be disposed independently of the chip on a substrate in the chip package structure.

[0095] For example, in some possible implementations, some components of the filter circuit 20 are located in the chip, while other components (such as inductors and capacitors) are set independently of the chip on the substrate in the package structure, as shown in devices 2 and 3 in Figure 2.

[0096] The illustration uses the filter capacitor in filter circuit 20 as an example. When the capacitance value of the filter capacitor is small, it can be integrated inside the chip, which is more conducive to high integration design. When the capacitance value of the filter capacitor is large, it can be set separately, either surface-mounted or back-mounted on the substrate in the package structure, thereby meeting the filtering needs of the device over a wider range.

[0097] In addition, to save space and area resources, referring to Figure 10, in some possible implementations, the output terminals of multiple charge pumps OCCP can be connected to the same filter circuit 20. In this case, multiple charge pumps OCCP can share the same filter circuit 20.

[0098] It should be noted that multiple charge pumps OCCP can share the entire filter circuit 20, or they can share some components of the filter circuit 20 (such as resistors, capacitors, etc.). This application does not impose any restrictions on this, and the design can be carried out as needed in practice.

[0099] Example 2

[0100] Schematic, referring to Figure 11, this embodiment provides a charge pump OCCP, which is connected to a first clock signal terminal S1, a second clock signal terminal S2, a high-level power supply terminal VDD, and a low-level power supply terminal VSS. Under the control of the clock signals of the first clock signal terminal S1 and the second clock signal terminal S2, the output terminal VO can output an intermediate level Vmid (0.5*VDD).

[0101] Correspondingly, the chip includes a control circuit that generates a clock signal and outputs it to the first clock signal terminal S1 and the second clock signal terminal S2. The clock signals input to the first clock signal terminal S1 and the second clock signal terminal S2 can be a set of non-overlapping clock signals. For relevant explanations, please refer to Embodiment 1, which will not be repeated here.

[0102] Referring again to Figure 11, the charge pump OCCP includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a first capacitor C1, and a second capacitor C2. The gate of the first transistor T1 is connected to the second clock signal terminal S2, the source of the first transistor T1 is connected to the high-level power supply terminal VDD, and the drain of the first transistor T1 is connected to the first terminal of the first capacitor C1. The gate of the second transistor T2 is connected to the first clock signal terminal S1, the source of the second transistor T2 is connected to the first terminal of the first capacitor C1, and the drain of the second transistor T2 is connected to the output terminal VO. The gate of the third transistor T3 is connected to the first clock signal terminal S1, the source of the third transistor T3 is connected to the second terminal of the first capacitor C1, and the drain of the third transistor T3 is connected to the low-level power supply terminal VSS. The gate of the fourth transistor T4 is connected to the second clock signal terminal S2, the source of the fourth transistor T4 is connected to the second terminal of the first capacitor C1, and the drain of the fourth transistor T4 is connected to the output terminal VO. The gate of the fifth transistor T5 is connected to the first clock signal terminal S1, the source of the fifth transistor T5 is connected to the output terminal VO, and the source of the fifth transistor T5 is connected to the first terminal of the second capacitor C2. The second terminal of the second capacitor C2 is connected to the low-level power supply terminal VSS.

[0103] It should be noted that the source and drain of the transistors (such as T1, T2, T3, T4, and T5) involved in this embodiment do not need to be explicitly distinguished; that is, of the two terminals of the transistor other than the gate, one is the source and the other is the drain. The first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, and the fifth transistor T5 can be either N-type or P-type field-effect transistors. This application does not impose any restrictions on this, and the configuration can be adjusted as needed in practice. This embodiment is illustrated using the example where the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, and the fifth transistor T5 are all N-type field-effect transistors, but it is not limited to this.

[0104] Referring to Figures 11 and 12, a control cycle of the charge pump OCCP may include a first stage P1 and a second stage P2.

[0105] In the first stage P1, when the first clock signal terminal S1 is low, the second transistor T2, the third transistor T3, and the fifth transistor T5 are turned off. When the second clock signal terminal S2 is high, the first transistor T1 and the fourth transistor T4 are turned on. The first capacitor C1 and the second capacitor C2 are charged.

[0106] In the second stage P2, in the first stage P1, when the first clock signal terminal S1 is low, the second transistor T2, the third transistor T3, and the fifth transistor T5 are switched on and off. When the second clock signal terminal S2 is low, the first transistor T1 and the fourth transistor T4 are switched off. The first capacitor C1 and the second capacitor C2 discharge.

[0107] In the first stage P1 and the second stage P2, the output voltage of the output terminal VO is maintained at around 0.5*VDD, that is, VO≈0.5*VDD.

[0108] In addition, to help reduce voltage noise fluctuations at the output terminal VO, a filter circuit can be set at the output terminal VO in some possible implementations to filter the output level of VO. The components in this filter circuit can be located within the chip, or they can be located independently of the chip on the substrate of the package structure. Alternatively, some components can be located within the chip, while others are located independently of the chip on the substrate of the package structure. For details, please refer to the aforementioned Embodiment 1, which will not be repeated here.

[0109] Schematic, referring to Figure 13, in some possible implementations, the filter circuit 20 may include a third capacitor C3 connected between the output terminal VO and the low-level power supply terminal VSS.

[0110] Schematic, referring to Figure 10, in some possible implementations, the filter circuit 20 may include a fourth capacitor C4, multiple resistors R, and multiple inductors L. The fourth capacitor C4 is connected between the low-level power supply terminal VSS and the output terminal VO, and the multiple resistors R and multiple inductors L are alternately connected in series between the fourth capacitor C4 and the output terminal VO.

[0111] Of course, in order to save space and chip area resources, referring to Figure 10, in some possible implementations, the output terminals of multiple charge pumps OCCP can be connected to the same filter circuit 20. In this case, multiple charge pumps OCCP can share the same filter circuit 20.

[0112] It should be noted that multiple charge pumps OCCP can share the entire filter circuit 20, or they can share some components of the filter circuit 20 (such as resistors, capacitors, etc.). This application does not impose any restrictions on this, and the design can be carried out as needed in practice.

[0113] The following is a simple comparison of the charge pumps OCCP provided in Embodiment 1 and Embodiment 2.

[0114] First, compared to the charge pump OCCP provided in Embodiment 2, which has five transistors and two capacitors (Figure 11), the charge pump OCCP provided in Embodiment 1 has four transistors and one capacitor (Figure 7). That is, the circuit structure of the charge pump OCCP provided in Embodiment 1 is simpler, contains fewer components, has a smaller area, and is easier to distribute flexibly within the chip, which is also beneficial for the miniaturization of the chip.

[0115] In addition, compared with the charge pump OCCP provided in Embodiment 2, the charge pump OCCP provided in Embodiment 1 has better output voltage stability and energy efficiency.

[0116] Figure 14 shows a comparison of the output voltage curves of the charge pump OCCP provided in Embodiment 1 and Embodiment 2. Wherein, m1 is the output voltage curve of the charge pump OCCP provided in Embodiment 1, and m2 is the output voltage curve of the charge pump OCCP provided in Embodiment 2.

[0117] As can be seen from curve m1, under different load currents, the output voltage of the charge pump OCCP provided in Example 2 is approximately in the range of 0.358V to 0.375V.

[0118] As can be seen from curve m2, under different load currents, the output voltage of the charge pump OCCP provided in Example 1 is approximately in the range of 0.340V to 0.371V.

[0119] It can be seen that the output voltage fluctuation of the charge pump OCCP provided in Example 2 is smaller and has higher stability.

[0120] Figure 15 shows the performance comparison curves of the charge pump OCCP provided in Embodiment 1 and Embodiment 2. Wherein, n1 is the performance curve of the charge pump OCCP provided in Embodiment 1, and n2 is the performance curve of the charge pump OCCP provided in Embodiment 2.

[0121] As can be seen from curve n1, under different load currents, the efficiency of the charge pump OCCP provided in Example 2 is approximately in the range of 0.958 to 0.992.

[0122] As can be seen from curve n2, under different load currents, the efficiency of the charge pump OCCP provided in Example 1 is approximately in the range of 0.917 to 0.998.

[0123] It can be seen that the charge pump OCCP provided in Example 2 has higher average efficiency.

[0124] It should be noted that this application does not limit the application scenarios of the charge pump OCCP provided in the foregoing embodiments in chips. In future chips, as power consumption becomes increasingly critical, scenarios involving charge sharing will become more frequent, with multiple standard cells or dies stacked together. In these scenarios, small-area, flexibly distributed charge pumps will inevitably have more applications. This invention can fundamentally solve the problem of powering the intermediate level Vmid of the voltage regulator in the voltage stacking bus VSB.

[0125] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A bare wafer, characterized in that, It includes at least one charge pump, at least one data channel, a high-level power supply terminal, and a low-level power supply terminal; the charge pump includes an output terminal, and the power supply terminal of the charge pump is connected to the high-level power supply terminal and the low-level power supply terminal; The data channel includes a first channel and a second channel. The first channel includes a first inverter connected in series with multiple stages, and the second channel includes a second inverter connected in series with multiple stages. The first power supply terminal of the multi-stage series-connected first inverter is connected to the high-level power supply terminal, and the second power supply terminal of the multi-stage series-connected first inverter is connected to the output terminal. The first power supply terminal of the multi-stage series-connected second inverter is connected to the output terminal, and the second power supply terminal of the multi-stage series-connected second inverter is connected to the low-level power supply terminal. The output terminal of the charge pump provides a first power level to the second power supply terminal of the multi-stage series-connected first inverter and the first power supply terminal of the multi-stage series-connected second inverter, wherein the first power level is the intermediate level between the high-level power supply terminal and the low-level power supply terminal.

2. The bare wafer according to claim 1, characterized in that, The die includes multiple data channels and multiple charge pumps, with each data channel connected to a different charge pump.

3. The bare wafer according to claim 1 or 2, characterized in that, The die also includes a control circuit, which is used to generate a first clock signal and a second clock signal. The charge pump is configured to output the first level through the output terminal under the control of the first clock signal and the second clock signal.

4. The bare die according to claim 3, characterized in that, The charge pump includes a first transistor, a second transistor, a third transistor, a fourth transistor, and a first capacitor; The gate of the first transistor is connected to the first clock signal terminal, the first terminal of the first transistor is connected to the high-level power supply terminal, and the second terminal of the first transistor is connected to the first terminal of the first capacitor. The gate of the second transistor is connected to the second clock signal terminal, the first terminal of the second transistor is connected to the output terminal, and the second terminal of the second transistor is connected to the first terminal of the first capacitor. The gate of the third transistor is connected to the first clock signal terminal, the first terminal of the third transistor is connected to the output terminal, and the second terminal of the third transistor is connected to the second terminal of the first capacitor. The gate of the fourth transistor is connected to the second clock signal terminal, the first terminal of the fourth transistor is connected to the low-level power supply terminal, and the second terminal of the fourth transistor is connected to the second terminal of the first capacitor. In the first transistor, the second transistor, the third transistor, and the fourth transistor, one of the first terminals and the other of the second terminal is the source and the other is the drain.

5. The bare die according to any one of claims 1-4, characterized in that, The die also includes a first D flip-flop, a first buffer, and a second D flip-flop; wherein the output of the first D flip-flop is connected to the input of the multi-stage series-connected first inverter, the output of the multi-stage series-connected first inverter is connected to the input of the first buffer, and the output of the first buffer is connected to the input of the second D flip-flop. The die also includes a third D flip-flop, a second buffer, and a fourth D flip-flop; wherein the output of the third D flip-flop is connected to the input of the multi-stage series-connected second inverter, the output of the multi-stage series-connected second inverter is connected to the input of the second buffer, and the output of the second buffer is connected to the input of the fourth D flip-flop.

6. The bare die according to any one of claims 1-5, characterized in that, The bare die is a network chip.

7. A chip packaging structure, characterized in that, It includes a substrate and a die as described in any one of claims 1-6; the die is disposed on the substrate and electrically connected to the substrate.

8. The chip packaging structure according to claim 7, characterized in that, The chip packaging structure also includes a filtering circuit, which is connected to the output terminal and is used to filter the level output by the output terminal.

9. The chip packaging structure according to claim 8, characterized in that, The filter circuit includes a second capacitor, which is connected between the high-level power supply terminal and the output terminal.

10. The chip packaging structure according to claim 8 or 9, characterized in that, The filter circuit includes a third capacitor, which is connected between the low-level power supply terminal and the output terminal.

11. The chip packaging structure according to any one of claims 8-10, characterized in that, The filter circuit includes a fourth capacitor, multiple resistors, and multiple inductors; The fourth capacitor is connected between the low-level power supply terminal and the output terminal, and multiple resistors and multiple inductors are alternately connected in series between the fourth capacitor and the output terminal.

12. The chip packaging structure according to any one of claims 8-11, characterized in that, The output terminals of the multiple charge pumps are connected to the same filter circuit.

13. The chip packaging structure according to any one of claims 8-12, characterized in that, The filtering circuit is disposed in the bare die; Alternatively, some or all of the components in the filter circuit may be disposed on the substrate independently of the die.

14. An electronic device, characterized in that, It includes a circuit board and a bare die as described in any one of claims 1-6, wherein the bare die is electrically connected to the circuit board.

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