Integrated gallium nitride and gallium oxide power chip and preparation method therefor, and electronic device
By integrating GaN and Ga2O3 power chips on the same substrate, the parasitic loss and delay problems of discrete chip integration are solved, achieving efficient chip integration and performance improvement.
Patent Information
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- XIAMEN CHANGELIGHT CO LTD
- Filing Date
- 2025-06-25
- Publication Date
- 2026-05-15
AI Technical Summary
When Ga2O3 and GaN power chips are integrated separately, parasitic losses, response delays, and noise are easily introduced. Furthermore, Ga2O3 materials are prone to failure at high temperatures, while GaN chips introduce parasitic losses, response delays, and noise into integrated circuits.
Integrating GaN and Ga2O3 power chips on the same substrate, by epitaxially layering Ga2O3 layers on GaN layers, reduces lattice mismatch, forms epitaxial structures, and forms functional components in different regions, reducing lead interconnection and bonding processes.
It reduces the size of wide-bandgap semiconductor power systems, avoids parasitic losses, response delays and noise problems caused by discrete chip integration, and improves chip performance and reliability.
Smart Images
Figure CN2025103352_15052026_PF_FP_ABST
Abstract
Description
Integrated gallium nitride and gallium oxide power chips and their fabrication methods, electronic devices
[0001] This application claims priority to Chinese Patent Application No. 202411589648.7, filed on November 8, 2024, entitled "Integrated Gallium Nitride and Gallium Oxide Power Chip and its Fabrication Method, Electronic Device", the entire contents of which are incorporated herein by reference. Technical Field
[0002] This application relates to the field of semiconductor technology, and in particular to an integrated gallium nitride and gallium oxide power chip, its fabrication method, and electronic devices. Background Technology
[0003] Ga2O3, with its ultra-wide bandgap (4.8 eV–5.1 eV), device quality factor (such as the low-loss Baliga quality factor for DC), and low defect density (at least three orders of magnitude lower than silicon carbide wafers), can effectively improve the breakdown voltage characteristics and reduce the on-resistance of power chips. Therefore, Ga2O3 power chips can significantly improve chip output current density and power density, and are expected to drive the rapid development of next-generation high-voltage, high-power electronic devices. However, Ga2O3 material has very low thermal conductivity, making it prone to failure under high junction temperature conditions. Furthermore, Ga2O3 power chips are mostly used in discrete device form, and the multiple interconnections between chips can easily increase contact resistance, further accelerating the rise in chip temperature.
[0004] Similarly, GaN, along with Ga2O3, is a hot research topic in power chip research. Its wide bandgap and the high electron mobility and electron surface density of the resulting heterojunction enable high gain, high power density, and high power stability. Furthermore, GaN power chips exhibit excellent temperature characteristics, significantly improving performance in variable-temperature environments, thus enabling high-performance power control. However, GaN power chips are currently mostly available in discrete form. Integrating GaN power chips into circuit systems via wire bonding inevitably introduces parasitic losses, response delays, and noise, making it difficult to fully realize the performance advantages of GaN chips in integrated circuits. Summary of the Invention
[0005] In view of the above problems, this application provides an integrated gallium nitride and gallium oxide power chip, its fabrication method, and an electronic device. By integrating the Ga2O3 power chip and the GaN power chip on the same substrate, the size of the wide bandgap semiconductor power system can be further reduced, avoiding the problems of parasitic losses, response delays, and noise introduced during discrete chip integration. The specific solution is as follows:
[0006] The first aspect of this application provides an integrated gallium nitride and gallium oxide power chip, the integrated gallium nitride and gallium oxide power chip comprising:
[0007] Substrate;
[0008] An epitaxial structure located on one side of the substrate; the epitaxial structure includes: a GaN channel layer, a barrier layer, a first Ga2O3 layer, and a second Ga2O3 layer sequentially located on one side of the substrate in a first direction, wherein the doping concentration of the first Ga2O3 layer is greater than the doping concentration of the second Ga2O3 layer; the first direction is perpendicular to the plane of the substrate and extends from the substrate to the GaN channel layer.
[0009] The epitaxial structure includes a first region and a second region. The surface of the first region is the surface of the barrier layer facing away from the substrate. The surface of the second region is partly the surface of the first Ga2O3 layer facing away from the substrate and partly the surface of the second Ga2O3 layer facing away from the substrate.
[0010] A first functional component is disposed on the first region, and a second functional component is disposed on the second region; wherein the first functional component and the epitaxial structure corresponding to the first region constitute a GaN power chip, and the second functional component and the epitaxial structure corresponding to the second region constitute a Ga2O3 power chip.
[0011] Preferably, in the above-mentioned integrated gallium nitride and gallium oxide power chip, the integrated gallium nitride and gallium oxide power chip further includes:
[0012] An isolation zone located between the first region and the second region.
[0013] Preferably, in the above-mentioned integrated gallium nitride and gallium oxide power chip, the first functional component includes:
[0014] The source, drain, and gate are located on the side of the barrier layer opposite to the substrate, with the source and drain located on opposite sides of the gate.
[0015] Preferably, in the above-mentioned integrated gallium nitride and gallium oxide power chip, the source, the drain and the barrier layer form an ohmic contact, and the gate and the barrier layer form a Schottky contact.
[0016] Preferably, in the above-mentioned integrated gallium nitride and gallium oxide power chip, the second functional component includes:
[0017] A cathode located on the side of the first Ga2O3 layer away from the substrate;
[0018] The anode is located on the side of the second Ga2O3 layer away from the substrate.
[0019] Preferably, in the above-mentioned integrated gallium nitride and gallium oxide power chip, the integrated gallium nitride and gallium oxide power chip further includes:
[0020] A passivation layer located on the side of the epitaxial structure opposite to the substrate.
[0021] Preferably, in the above-mentioned integrated gallium nitride and gallium oxide power chip, the integrated gallium nitride and gallium oxide power chip further includes:
[0022] The first pad, second pad, third pad, fourth pad, and fifth pad are located on the side of the passivation layer opposite to the substrate;
[0023] The first pad is connected to the source electrode through a via penetrating the passivation layer; the second pad is connected to the gate electrode through a via penetrating the passivation layer; the third pad is connected to the drain electrode through a via penetrating the passivation layer; the fourth pad is connected to the anode electrode through a via penetrating the passivation layer; and the fifth pad is connected to the cathode electrode through a via penetrating the passivation layer.
[0024] Preferably, in the above-mentioned integrated gallium nitride and gallium oxide power chip, the third pad and the fourth pad are integrally formed pad structures.
[0025] A second aspect of this application provides a method for fabricating an integrated gallium nitride and gallium oxide power chip, the method comprising:
[0026] Provide a substrate;
[0027] An epitaxial structure is formed on one side of the substrate; the epitaxial structure includes: a GaN channel layer, a barrier layer, a first Ga2O3 layer, and a second Ga2O3 layer, sequentially located on one side of the substrate in a first direction, wherein the doping concentration of the first Ga2O3 layer is greater than the doping concentration of the second Ga2O3 layer; the first direction is perpendicular to the plane of the substrate and extends from the substrate to the GaN channel layer; the epitaxial structure includes a first region and a second region, wherein the surface of the first region is the surface of the barrier layer facing away from the substrate, and the surface of the second region is partly the surface of the first Ga2O3 layer facing away from the substrate and partly the surface of the second Ga2O3 layer facing away from the substrate.
[0028] A first functional component is formed on the first region, and a second functional component is formed on the second region; wherein the first functional component and the epitaxial structure corresponding to the first region constitute a GaN power chip, and the second functional component and the epitaxial structure corresponding to the second region constitute a Ga2O3 power chip.
[0029] A third aspect of this application provides an electronic device comprising the integrated gallium nitride and gallium oxide power chip described in any of the preceding claims.
[0030] By employing the above technical solution, this application provides an integrated gallium nitride and gallium oxide power chip, its fabrication method, and an electronic device. In this integrated gallium nitride and gallium oxide power chip, the epitaxial structure integrates GaN and Ga2O3 layers epitaxially on the same substrate. The method of epitaxially layering Ga2O3 on the GaN layer reduces heteroepitaxial lattice mismatch and improves crystal quality. Based on the epitaxial structure, a first functional component is formed on a first region, and a second functional component is formed on a second region. The surface of the first region is the surface of the barrier layer facing away from the substrate, and the surface of the second region is the surface of the Ga2O3 layer facing away from the substrate. This achieves the purpose of integrating the Ga2O3 power chip and the GaN power chip on the same substrate, reducing interconnection and bonding processes, further reducing the size of wide-bandgap semiconductor power systems, and avoiding problems such as parasitic losses, response delays, and noise introduced during discrete chip integration. Attached Figure Description
[0031] The above and other features, advantages, and aspects of the embodiments of this disclosure will become more apparent from the accompanying drawings and the following detailed description. Throughout the drawings, the same or similar reference numerals denote the same or similar elements. It should be understood that the drawings are schematic, and the originals and elements are not necessarily drawn to scale.
[0032] Figure 1 is a schematic diagram of an integrated gallium nitride and gallium oxide power chip provided in an embodiment of the present invention;
[0033] Figure 2 is a schematic diagram of another integrated gallium nitride and gallium oxide power chip provided in an embodiment of the present invention;
[0034] Figure 3 is a schematic diagram of another integrated gallium nitride and gallium oxide power chip provided in an embodiment of the present invention;
[0035] Figure 4 is a schematic flowchart of a method for fabricating an integrated gallium nitride and gallium oxide power chip according to an embodiment of the present invention. Detailed Implementation
[0036] The embodiments of this application are described below with reference to the accompanying drawings. The terminology used in the implementation section of this application is only for explaining specific embodiments and is not intended to limit the application. Those skilled in the art will recognize that, with technological advancements and the emergence of new scenarios, the technical solutions provided in the embodiments of this application are also applicable to similar technical problems.
[0037] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.
[0038] It should be noted that the directional terms used in this invention are based on the relative positional relationships shown in the accompanying drawings and should not be taken as absolute limitations on this application.
[0039] Referring to Figure 1, Figure 1 is a schematic diagram of an integrated gallium nitride and gallium oxide power chip provided in an embodiment of the present invention. The integrated power device provided in this embodiment of the present invention includes: a substrate 11.
[0040] An epitaxial structure located on one side of the substrate 11; the epitaxial structure includes: a GaN channel layer 12, a barrier layer 13, a first Ga2O3 layer 14, and a second Ga2O3 layer 15, which are sequentially located on one side of the substrate 11 in a first direction, wherein the doping concentration of the first Ga2O3 layer 14 is greater than the doping concentration of the second Ga2O3 layer 15; the first direction is perpendicular to the plane of the substrate 11 and points from the substrate 11 to the GaN channel layer 12.
[0041] The epitaxial structure includes a first region AA and a second region BB. The surface of the first region AA is the surface of the barrier layer 13 facing away from the substrate 11. The surface of the second region BB is partly the surface of the first Ga2O3 layer 14 facing away from the substrate 11 and partly the surface of the second Ga2O3 layer 15 facing away from the substrate 11.
[0042] A first functional component is disposed on the first region AA, and a second functional component is disposed on the second region BB; wherein the epitaxial structure corresponding to the first functional component and the first region AA constitutes a GaN power chip, and the epitaxial structure corresponding to the second functional component and the second region BB constitutes a Ga2O3 power chip. The first functional component is a functional component required for fabricating the GaN power chip, and the second functional component is a functional component required for fabricating the Ga2O3 power chip.
[0043] The epitaxial structure corresponding to the first region AA includes a GaN channel layer 12 and a barrier layer 13; the epitaxial structure corresponding to the second region BB includes a GaN channel layer 12, a barrier layer 13, a first Ga2O3 layer 14, and a second Ga2O3 layer 15.
[0044] Specifically, in the embodiments of the present invention, the substrate 11 includes, but is not limited to, at least one of a silicon substrate, a sapphire substrate, a silicon carbide substrate, and a diamond substrate.
[0045] The thickness of the GaN channel layer 12 ranges from 0.5 μm to 15 μm. For example, the thickness of the GaN channel layer 12 can be 0.5 μm, 8 μm, or 15 μm, etc.
[0046] The barrier layer 13 includes, but is not limited to, at least one of a monolayer AlN layer, a monolayer AlGaN layer, a monolayer InAlGaN layer, a monolayer InAlN layer, and an AlN / GaN superlattice structure. The thickness of the barrier layer 13 ranges from 2 nm to 40 nm. For example, the thickness of the barrier layer 13 is 2 nm, 20.5 nm, 34.5 nm, or 40 nm.
[0047] The first Ga2O3 layer 14 and the second Ga2O3 layer 15 are doped with elements such as Si, Sn, or Ge. The source used in the fabrication of the first Ga2O3 layer 14 and the second Ga2O3 layer 15 is such as SiH4. The thickness of the first Ga2O3 layer 14 ranges from 0.1 μm to 5 μm. For example, the thickness of the first Ga2O3 layer 14 is 0.1 μm, 2.6 μm, or 5 μm. The thickness of the second Ga2O3 layer 15 ranges from 0.1 μm to 5 μm. For example, the thickness of the second Ga2O3 layer 15 is 0.1 μm, 3.7 μm, or 5 μm.
[0048] The doping concentration of the first Ga2O3 layer 14 is greater than or equal to 1×10⁻⁶. 18 / cm 3 The doping concentration of the second Ga2O3 layer 15 is greater than or equal to 1 × 10⁻⁶. 15 / cm 3 And less than 1×10 18 / cm 3 .
[0049] In the process of this invention, it was discovered that heteroepitaxial growth of Ga2O3 layers on a substrate with high thermal conductivity is limited by the substrate lattice mismatch, making it difficult to achieve high-quality Ga2O3 layers, which in turn affects chip performance.
[0050] Based on this, in this embodiment, a GaN layer 12 is first heteroepitaxially grown on a high thermal conductivity substrate 11, and then a Ga2O3 layer (including a first Ga2O3 layer 14 and a second Ga2O3 layer 15) is heteroepitaxially grown on the GaN layer 12, achieving the goal of integrating the GaN layer 12 and the Ga2O3 layer on the same substrate 11. Furthermore, the method of heteroepitaxially growing the Ga2O3 layer on the GaN layer 12 can reduce the lattice mismatch of the heteroepitaxial layer and improve the crystal quality. Specifically, the lattice mismatch between the GaN layer 12 and the Ga2O3 layer is only 2.6%, which is superior to that of high thermal conductivity substrates such as SiC, Si, and sapphire. This epitaxial structure integrates multiple wide bandgap semiconductor materials through epitaxy, simplifying the material fabrication process. The fabrication process of this epitaxial structure is simple and efficient, laying the foundation for monolithic integration of wide bandgap power semiconductor systems.
[0051] Furthermore, in this embodiment of the invention, a first functional component is formed on the first region AA and a second functional component is formed on the second region BB based on the epitaxial structure. The surface of the first region AA is the surface of the barrier layer 13 facing away from the substrate 11, and the surface of the second region BB is the surface of the Ga2O3 layer facing away from the substrate 11. This achieves the purpose of integrating the Ga2O3 power chip and the GaN power chip on the same substrate 11, reducing the need for interconnection and bonding processes, further reducing the size of the wide bandgap semiconductor power system, and avoiding problems such as parasitic losses, response delays and noise introduced during discrete chip integration.
[0052] In other words, in the prior art, the applicant found that circuit system integration requires the interconnection of multiple discrete chips, and the interconnection of discrete chips is mostly achieved through bonding, wire bonding, and other methods. At the bonding interface and wire bonding interface, contact resistance and parasitic capacitance are easily generated, leading to increased circuit system losses and delay effects. However, in the embodiments of this application, the monolithic integration fabrication of different wide bandgap semiconductor chips on the same substrate 11 can further reduce the size of the wide bandgap semiconductor power system and avoid problems such as parasitic losses, response delays, and noise introduced during discrete chip integration.
[0053] In an optional embodiment of the present invention, as shown in FIG1, the first functional component includes:
[0054] The source 16, drain 17 and gate 18 are located on the side of the barrier layer 13 away from the substrate 11, with the source 16 and the drain 17 located on both sides of the gate 18.
[0055] Specifically, in this embodiment of the invention, a GaN power chip is a high electron mobility transistor (HEMT) as an example.
[0056] The source 16, the drain 17 and the barrier layer 13 form an ohmic contact, and the gate 18 and the barrier layer 13 form a Schottky contact to achieve better electrical connection and improve the working performance of the GaN power chip.
[0057] In an optional embodiment of the present invention, as shown in FIG1, the second functional component includes:
[0058] The cathode 19 is located on the side of the first Ga2O3 layer 14 facing away from the substrate 11.
[0059] The anode 20 is located on the side of the second Ga2O3 layer 15 away from the substrate 11.
[0060] Specifically, in this embodiment of the invention, a Schottky barrier diode (SBD) is used as an example of a Ga2O3 power chip for illustration.
[0061] In an optional embodiment of the present invention, as shown in FIG1, the integrated gallium nitride and gallium oxide power chip further includes:
[0062] The passivation layer 21 is located on the side of the epitaxial structure opposite to the substrate 11.
[0063] Specifically, in this embodiment of the invention, the passivation layer 21 covers the source 16, drain 17, gate 18, cathode 19, and anode 20, thereby achieving passivation protection for the integrated power chip and isolation between components. For example, the passivation layer 21 is covered between the source 16 and gate 18, and between the drain 17 and gate 18.
[0064] It should be noted that the material of the passivation layer 21 can be SiO2 or SiNx or other materials with passivation effect, and is not limited in the embodiments of the present invention.
[0065] In an optional embodiment of the present invention, as shown in FIG1, the integrated gallium nitride and gallium oxide power chip further includes:
[0066] The first pad 22, the second pad 23, the third pad 24, the fourth pad 25, and the fifth pad 26 are located on the side of the passivation layer 21 opposite to the substrate 11.
[0067] The first pad 22 is connected to the source 16 through a through-hole penetrating the passivation layer 21; the second pad 23 is connected to the gate 18 through a through-hole penetrating the passivation layer 21; the third pad 24 is connected to the drain 17 through a through-hole penetrating the passivation layer 21; the fourth pad 25 is connected to the anode 20 through a through-hole penetrating the passivation layer 21; and the fifth pad 26 is connected to the cathode 19 through a through-hole penetrating the passivation layer 21.
[0068] Specifically, in this embodiment of the invention, by setting pads on the surface of the passivation layer 21 away from the substrate 11, the source 16, drain 17, gate 18, cathode 19 and anode 20 are brought out to achieve electrical connection between the integrated power chip and other chips.
[0069] Referring to Figure 2, which is a schematic diagram of another integrated gallium nitride and gallium oxide power chip provided in an embodiment of the present invention, the third pad 24 and the fourth pad 25 in the integrated gallium nitride and gallium oxide power chip provided in this embodiment of the present invention are integrally formed pad structure 27.
[0070] In other words, in the integrated gallium nitride and gallium oxide power chip provided in this embodiment of the invention, the GaN power chip and the Ga2O3 power chip are electrically connected through an integrally formed pad structure 27. By integrating the Ga2O3 power chip and the GaN power chip onto the same substrate 11, the required interconnection and bonding processes for discrete chips are reduced, further minimizing the size of the wide-bandgap semiconductor power system and avoiding problems such as parasitic losses, response delays, and noise introduced during discrete chip integration.
[0071] In an optional embodiment of the present invention, referring to FIG3, FIG3 is a schematic diagram of another integrated gallium nitride and gallium oxide power chip provided by an embodiment of the present invention.
[0072] A nucleation layer 28 and a buffer layer 29 are disposed sequentially between the substrate 11 and the GaN channel layer 12 and in the first direction.
[0073] Specifically, in this embodiment of the invention, the nucleation layer 28 includes, but is not limited to, at least one of an AlN layer, a GaN layer, and an AlGaN layer. The thickness of the nucleation layer 28 ranges from 5 nm to 500 nm. For example, the thickness of the nucleation layer 28 is 5 nm, 20.5 nm, 30 nm, 200 nm, 316 nm, or 500 nm, etc.
[0074] The buffer layer 29 includes, but is not limited to, a single AlN layer, a single GaN layer, a single InGaN layer, a single AlGaN layer, an AlN / GaN superlattice structure, an AlN / AlGaN superlattice structure, or multiple AlGaN layers with different Al compositions, as well as different combinations of various nitride layers. The thickness of the buffer layer 29 ranges from 0.02 μm to 3 μm. For example, the thickness of the buffer layer 29 may be 0.02 μm, 1.5 μm, or 3 μm, etc.
[0075] Furthermore, as shown in Figures 1-3, the integrated gallium nitride and gallium oxide power chip provided in this embodiment of the invention further includes an isolation region CC located between the first region AA and the second region BB, thereby isolating the GaN power chip and the Ga2O3 power chip. This isolation region can be achieved through ion implantation.
[0076] Based on the above embodiments of the present invention, another embodiment of the present invention also provides a method for fabricating an integrated gallium nitride and gallium oxide power chip. Referring to FIG4, FIG4 is a schematic flowchart of a method for fabricating an integrated gallium nitride and gallium oxide power chip provided by an embodiment of the present invention. The method for fabricating an integrated gallium nitride and gallium oxide power chip provided by an embodiment of the present invention includes:
[0077] S101: Provide a substrate 11.
[0078] Specifically, the substrate 11 includes, but is not limited to, at least one substrate selected from silicon substrate, sapphire substrate, silicon carbide substrate, and diamond substrate. It should be noted that the substrate 11 can also be other substrates with high thermal conductivity, and this is not limited in the embodiments of the present invention.
[0079] S102: An epitaxial structure is formed on one side of the substrate 11; the epitaxial structure includes: a GaN channel layer 12, a barrier layer 13, a first Ga2O3 layer 14, and a second Ga2O3 layer 15, which are sequentially located on one side of the substrate in a first direction, wherein the doping concentration of the first Ga2O3 layer 14 is greater than the doping concentration of the second Ga2O3 layer 15; the first direction is perpendicular to the plane of the substrate 11 and points from the substrate 11 to the GaN channel layer 12; the epitaxial structure includes a first region AA and a second region BB, wherein the surface of the first region AA is the surface of the barrier layer 13 facing away from the substrate 11, and the surface of the second region BB is partly the surface of the first Ga2O3 layer 14 facing away from the substrate 11 and partly the surface of the second Ga2O3 layer 15 facing away from the substrate 11.
[0080] S103: A first functional component is formed on the first region AA, and a second functional component is formed on the second region BB; wherein the epitaxial structure corresponding to the first functional component and the first region AA constitutes a GaN power chip, and the epitaxial structure corresponding to the second functional component and the second region BB constitutes a Ga2O3 power chip.
[0081] Specifically, this includes, but is not limited to, sequentially growing a nucleation layer 28, a buffer layer 29, a GaN channel layer 12, a barrier layer 13, a first Ga2O3 layer 14, and a second Ga2O3 layer 15 on substrate 11 using MOCVD. For example, a 200 nm thick AlN nucleation layer, a 3 μm thick GaN buffer layer, a 200 nm thick GaN channel layer 12, a 20 nm thick AlGaN barrier layer, a 1 μm thick first Ga2O3 layer 13, and a 1 μm thick second Ga2O3 layer 14 are sequentially grown on substrate 11 using MOCVD.
[0082] In an optional embodiment of the present invention, trimethylgallium is used as the gallium source, trimethylaluminum as the aluminum source, high-purity oxygen as the oxygen source, high-purity argon as the carrier gas for the MO source, silane as the silicon doping source during the thin film growth process, and ammonia as the nitrogen source. An AlN nucleation layer with a thickness of 0.02 μm is grown on a silicon carbide substrate under a growth environment of 50 torr chamber pressure, 1100°C growth temperature, and 100 sccm aluminum source flow rate; a GaN buffer layer with a thickness of 1.5 μm is grown under a growth environment of 200 torr chamber pressure, 1080°C growth temperature, and 650 sccm gallium source flow rate; a GaN channel layer 12 with a thickness of 0.15 μm is grown under a growth environment of 150 torr chamber pressure, 1060°C growth temperature, and 650 sccm gallium source flow rate; and a GaN channel layer 12 with a thickness of 50 torr chamber pressure is grown under a growth environment of 150 torr chamber pressure, 1060°C growth temperature, and 650 sccm gallium source flow rate. An AlN barrier layer with a thickness of 0.005 μm was grown at a growth temperature of 1100℃ and an aluminum source flow rate of 100 sccm. A first Ga2O3 layer with a thickness of 0.5 μm was grown at an oxygen flow rate of 2800 sccm, a growth temperature of 750℃, and a SiH4 flow rate of 150 sccm. A second Ga2O3 layer with a thickness of 1 μm was grown at an oxygen flow rate of 2800 sccm, a growth temperature of 850℃, and a SiH4 flow rate of 90 sccm. After growth, the temperature was lowered to room temperature to complete the preparation of the epitaxial structure.
[0083] After cleaning the epitaxial structure, a first region AA and a second region BB are defined, including but not limited to using photolithography, wherein the first region AA is the region where the GaN power chip is located, and the second region BB is the region where the Ga2O3 power chip is located. Based on the second region BB, the second Ga2O3 layer 15 is subjected to RIE etching using a mixed gas of BCl3 and Ar until a portion of the surface of the first Ga2O3 layer 14 is exposed.
[0084] A cathode 19 is formed on the side of the first Ga2O3 layer 14 facing away from the substrate 11, and an anode 20 is formed on the side of the second Ga2O3 layer 15 facing away from the substrate 11. The anode 20 can be a stacked structure of Ti and Au layers, and the cathode 19 can also be a stacked structure of Ti and Au layers. In an optional embodiment of the present invention, the thickness of the Ti layer can be 20 nm, and the thickness of the Au layer can be 120 nm.
[0085] Hard mask deposition is performed, including but not limited to etching the first Ga2O3 layer 14 and the second Ga2O3 layer 15 of the first region AA pair by dry etching until the surface of the barrier layer 13 is exposed.
[0086] After removing the hard mask, an isolation region CC is formed, including but not limited to photolithography and ion implantation, to achieve isolation between the GaN power chip and the Ga2O3 power chip. The depth of this isolation region CC can be 3.5 μm.
[0087] A passivation layer 21 is deposited, which can be a SiNx layer with a thickness of 0.5 μm.
[0088] The passivation layer 21 is etched to form a first through hole and a second through hole, which expose a portion of the surface of the barrier layer 13.
[0089] A source electrode 16 is formed on the surface of the barrier layer 13 via a first via; a drain electrode 17 is formed on the surface of the barrier layer 13 via a second via. The source electrode 16 and drain electrode 17 are in ohmic contact with the barrier layer 13. In an optional embodiment of the invention, the source electrode 16 and drain electrode 17 are formed by electron beam evaporation deposition of ohmic metal, followed by lift-off and laser annealing. The source electrode 16 can be a stacked structure of Ti, Al, Ni, and Au layers. The drain electrode 17 can also be a stacked structure of Ti, Al, Ni, and Au layers. The thickness of the Ti layer can be 20 nm, the thickness of the Al layer can be 120 nm, the thickness of the Ni layer can be 40 nm, and the thickness of the Au layer can be 50 nm.
[0090] This includes, but is not limited to, using chemical etching to remove the passivation layer 21 to form a third via, the third via exposing a portion of the surface of the barrier layer 13.
[0091] A gate 18 is formed on the surface of the barrier layer 13 via a third via. The gate 18 forms a Schottky contact with the barrier layer 13. The gate 18 can be a stacked structure of Ni and Au layers, with the Ni layer having a thickness of 60 nm and the Au layer having a thickness of 100 nm.
[0092] On the basis of passivation layer 21, a passivation layer 21 of a certain thickness is deposited. Then, including but not limited to, the electrodes are opened by photolithography and etching processes to prepare the pad structure, so as to realize the external lead-out of source 16, drain 17, gate 18, cathode 19 and anode 20, so as to realize the electrical connection between the integrated power chip and other chips.
[0093] The method for fabricating integrated gallium nitride and gallium oxide power chips is applicable to traditional integrated circuit device fabrication processes without increasing additional device fabrication costs. It lays the foundation for monolithic integration of wide-bandgap power semiconductor systems. The fabricated integrated gallium nitride and gallium oxide power chips can be widely used in various high-power demand system modules such as industrial power grids, new energy power conversion, and data center power conversion.
[0094] Based on the above embodiments of the present invention, another embodiment of the present invention provides an electronic device, which includes the integrated gallium nitride and gallium oxide power chip described in the above embodiments.
[0095] In summary, the technical solution of this application solves the problems of increased loss and delay effect that may be caused by the integration of Ga2O3 discrete chips and GaN discrete chips by epitaxially growing GaN layer 12 and Ga2O3 layer on the same substrate 11 and fabricating the corresponding power chip.
[0096] The above provides a detailed description of an integrated gallium nitride and gallium oxide power chip, its fabrication method, and electronic device provided by the present invention. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.
[0097] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. Regarding the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to in the method section.
[0098] It should also be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that elements inherent to a process, method, article, or apparatus that comprises a list of elements, or elements inherent to such processes, methods, articles, or apparatus, are also included. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.
[0099] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims
1. A power chip integrating gallium nitride and gallium oxide, characterized in that, The integrated gallium nitride and gallium oxide power chip includes: Substrate; An epitaxial structure located on one side of the substrate; the epitaxial structure includes: a GaN channel layer, a barrier layer, a first Ga2O3 layer, and a second Ga2O3 layer sequentially located on one side of the substrate in a first direction, wherein the doping concentration of the first Ga2O3 layer is greater than the doping concentration of the second Ga2O3 layer; the first direction is perpendicular to the plane of the substrate and extends from the substrate to the GaN channel layer. The epitaxial structure includes a first region and a second region. The surface of the first region is the surface of the barrier layer facing away from the substrate. The surface of the second region is partly the surface of the first Ga2O3 layer facing away from the substrate and partly the surface of the second Ga2O3 layer facing away from the substrate. A first functional component is disposed on the first region, and a second functional component is disposed on the second region; wherein the first functional component and the epitaxial structure corresponding to the first region constitute a GaN power chip, and the second functional component and the epitaxial structure corresponding to the second region constitute a Ga2O3 power chip.
2. The integrated gallium nitride and gallium oxide power chip according to claim 1, characterized in that, The integrated gallium nitride and gallium oxide power chip also includes: An isolation zone located between the first region and the second region.
3. The integrated gallium nitride and gallium oxide power chip according to claim 1, characterized in that, The first functional component includes: The source, drain, and gate are located on the side of the barrier layer opposite to the substrate, with the source and drain located on opposite sides of the gate.
4. The integrated gallium nitride and gallium oxide power chip according to claim 3, characterized in that, The source, the drain, and the barrier layer form an ohmic contact, and the gate and the barrier layer form a Schottky contact.
5. The integrated gallium nitride and gallium oxide power chip according to claim 3 or 4, characterized in that, The second functional component includes: A cathode located on the side of the first Ga2O3 layer away from the substrate; The anode is located on the side of the second Ga2O3 layer away from the substrate.
6. The integrated gallium nitride and gallium oxide power chip according to claim 5, characterized in that, The integrated gallium nitride and gallium oxide power chip also includes: A passivation layer located on the side of the epitaxial structure opposite to the substrate.
7. The integrated gallium nitride and gallium oxide power chip according to claim 6, characterized in that, The integrated gallium nitride and gallium oxide power chip also includes: The first pad, second pad, third pad, fourth pad, and fifth pad are located on the side of the passivation layer opposite to the substrate; The first pad is connected to the source electrode through a via penetrating the passivation layer; the second pad is connected to the gate electrode through a via penetrating the passivation layer; the third pad is connected to the drain electrode through a via penetrating the passivation layer; the fourth pad is connected to the anode electrode through a via penetrating the passivation layer; and the fifth pad is connected to the cathode electrode through a via penetrating the passivation layer.
8. The integrated gallium nitride and gallium oxide power chip according to claim 7, characterized in that, The third pad and the fourth pad are integrally formed pad structures.
9. A method for fabricating an integrated gallium nitride and gallium oxide power chip, characterized in that, The method for fabricating the integrated gallium nitride and gallium oxide power chip includes: Provide a substrate; An epitaxial structure is formed on one side of the substrate; the epitaxial structure includes: a GaN channel layer, a barrier layer, a first Ga2O3 layer, and a second Ga2O3 layer, sequentially located on one side of the substrate in a first direction, wherein the doping concentration of the first Ga2O3 layer is greater than the doping concentration of the second Ga2O3 layer; the first direction is perpendicular to the plane of the substrate and extends from the substrate to the GaN channel layer; the epitaxial structure includes a first region and a second region, wherein the surface of the first region is the surface of the barrier layer facing away from the substrate, and the surface of the second region is partly the surface of the first Ga2O3 layer facing away from the substrate and partly the surface of the second Ga2O3 layer facing away from the substrate. A first functional component is formed on the first region, and a second functional component is formed on the second region; wherein the first functional component and the epitaxial structure corresponding to the first region constitute a GaN power chip, and the second functional component and the epitaxial structure corresponding to the second region constitute a Ga2O3 power chip.
10. An electronic device, characterized in that, The electronic device includes the integrated gallium nitride and gallium oxide power chip as described in any one of claims 1-8.