Semiconductor component

Abstract

The invention relates to a semiconductor component, preferably a MISFET, in particular a PowerMISFET, preferably based on a wide-bandgap semiconductor material, in particular silicon carbide (SiC), having at least one active half-cell (30) defining an active region, wherein the active half-cell (30) has a p-doped pBody region (8) and a n-doped Source region (9).

Description

[0001] R.415316

[0002] - 1 -

[0003] Description

[0004] Semiconductor device

[0005] Technical field

[0006] The invention relates to a semiconductor device, preferably a MISFET, in particular a PowerMISFET, preferably based on a wide-bandgap semiconductor material, in particular silicon carbide (SiC).

[0007] State of the art

[0008] One challenge with semiconductor devices such as MISFETs (Metal-Insulator-Semiconductor Field Effect Transistor), especially PowerMISFETs, particularly those based on silicon carbide (SiC), is to achieve good conductivity, especially a low area-specific RDSon*A, with good short-circuit strength.

[0009] An active region of a power MISFET typically consists of a multitude of parallel-connected active cells, in which a forward current flow can be controlled via a gate. The following explanation uses the example of an n-channel trench MISFET. In the forward-biased state, a positive voltage above a threshold voltage is applied to a gate electrode, which may, for example, be made of n-doped polysilicon with a high (n+) doping content. At this threshold voltage, a noticeable current flow begins from a drain metal, operating at a low drain voltage (typically on the order of < 10 V), to a source metal. In this case, electrons are attracted to a trench-side interface of p-doped p-body regions by an induction effect of the gate electrode, forming an inversion channel or conductive channel. The p-body regions exhibit the following characteristics at R.415316

[0010] - 2 -

[0011] The interface to the gate dielectric typically exhibits a corresponding doping concentration of approximately 1 × 10⁶ cm⁻³ to 1 × 18 cm⁻³ in an interface normal direction, extending at least 100 nm from this interface. In the conduction state, a current path extends from the drain metal through an n-doped substrate, an optional n-doped buffer region, an n-doped drift region, an n-doped spreading region, and then through the respective inversion channel and a respective n-doped source region to the source metal. A specific on-resistance Ron*A is derived from an applied drain-source voltage VDS and a current density of one cell j = l / A as Ron*A = VDS / j = VDS / l*A, where A is determined by the pitch, the width of the cell, and its extent z as A = pitch*z.The source regions can exhibit resistance or, through appropriate selection of their location-dependent doping and the doping of the adjacent p-body regions, can be configured as a JFET. Current feedback reduces the current flow, leading to an increased specific on-resistance Ron*A. This is unfavorable for Ron*A in the forward conduction case, but advantageous in a short-circuit case described below.

[0012] In a short circuit, the gate electrode is subjected to a voltage above the threshold voltage, and the drain metal is subjected to a high voltage, for example, several hundred volts. A very high current flows, causing the MISFET to heat up to 1000 °C or more in picoseconds. The design goal here is to limit power dissipation by limiting the short-circuit current. In a short circuit, the source regions provide strong current feedback and thus contribute to limiting the short-circuit current.

[0013] The state of the art, for example in silicon-based components such as IGBTs (Insulated Gate Bipolar Transistors), is to separate a portion of the active cells as a so-called sense component (here, sense IGBT) from the rest of the active cells, the main component (here, main IGBT). A portion of the current flowing through its source and body regions is not directly connected, but rather via a sense resistor to a reference potential (see Monolithic integration of the vertical IGBT and intelligent protection circuits, ZJ Shen, P. Robb, pp. 295 ff., ISPSD 1996 Proceedings; specifically Fig. 3). The resulting voltage drop across the sense resistor is then used to bypass a component connected to an R.415316 by means of a circuit integrated on the IGBT.

[0014] - 3 -

[0015] The gate terminal of the applied control signal is opened relative to the reference potential, thereby reducing the effective control voltage at the gate electrode of the sense IGBT and main IGBT, especially in the case of a short circuit, i.e., high currents. Thus, negative feedback reduces the drive signal and limits the short-circuit current. Comparable arrangements are also common for MISFETs.

[0016] To generate the voltage drop required to control the limiting circuit, which is a more or less accurate representation of the current in the main component, an additional resistor, for example made of polysilicon, is necessary. Furthermore, the voltage drop across the sense resistor is usually too small, typically a few tens to hundreds of millivolts, to ensure sufficient accuracy by keeping the operating points VDS and VGS of the sense component from being too far removed from those of the main component.

[0017] Disclosure of the invention

[0018] The invention relates to a semiconductor device, preferably a MISFET, in particular a PowerMISFET, preferably based on a wide-bandgap semiconductor material, in particular silicon carbide (SiC), comprising at least one active half-cell defining an active region, wherein the active half-cell has a p-doped p-body region and an n-doped source region, wherein the semiconductor device has at least one sense half-cell connected in parallel to the active half-cell, which is configured to detect a voltage drop at least across an inversion channel formable in the p-body region and the source region when a control voltage is greater than a threshold voltage.

[0019] The design according to the invention enables the detection of a voltage drop in a part of a drift region of the semiconductor device itself, preferably provided at least below the p-body region, which is located near the inversion channel or MIS channel, by utilizing the voltage drop across the inversion channel or MIS channel that can be formed in the p-body region and the source region of the active half-cell adjacent to the sense half-cell, which is preferably provided at least partially above the p-body region, in the case where the R.415316 is located at at least one gate electrode.

[0020] - 4 -

[0021] The control voltage applied to the semiconductor device is greater than the threshold voltage Vth, i.e., in both forward and short-circuit conditions. The voltage drop, which is higher in the short-circuit case than in the forward case, can be easily evaluated by a circuit formed monolithically with the semiconductor device or separately from it, since it can be greater than the voltage drop generated across the sense resistor according to the prior art. The circuit can provide negative feedback to a gate drive signal, thus reducing the drain current in the short-circuit case. The source region contacts the p-body region. Preferably, the p-body region is p-doped, particularly depending on its location, with a medium (p) or heavy (p+) doping. Preferably, the source region is n-doped, particularly depending on its location, with a medium (n) or heavy (n+) doping.The active half-cell can be part of a first cell of the semiconductor device, while the sense half-cell can be part of a second cell of the semiconductor device connected in parallel to the first cell.

[0022] In a preferred embodiment, the semiconductor device has a source metal that contacts at least the source region, wherein the sense half-cell comprises a p-doped sense p-body region, an n-doped sense source region, and a sense metal that contacts the sense source region. The voltage drop can then be detected as a voltage applied between the source metal and the sense metal. The sense metal does not contact the source metal. Furthermore, the sense metal does not contact the sense p-body region. The sense source region, preferably located at least partially above the sense p-body region, does contact the sense p-body region. If the control voltage is greater than the threshold voltage, an inversion channel can also be formed in the sense p-body region. Preferably, the sense-pBody region is p-doped, particularly depending on location, with a medium (p) or strong (p+) doping.The sense-pbody region can have the same or a different doping concentration and / or depth as the pbody region. Preferably, the sense-source region is doped with a medium (n) or high (n+) doping concentration, particularly depending on location. The sense-source region can have the same or a different doping concentration and / or depth as the source region. R.415316.

[0023] - 5 - In a preferred embodiment, the sense pBody region is connected to a reference potential, preferably via a strongly p-doped sense pPlus region of the sense half-cell. The pBody region can be connected to the reference potential, preferably via a strongly p-doped pPIus region of the active half-cell. Preferably, the reference potential is ground (GND). Preferably, the source metal is connected to the reference potential, wherein the source metal further contacts the pPIus region, and the sense pPIus region contacts the sense pBody region and the pPIus region such that the sense pBody region is connected to the reference potential via the sense pPlus region, the pPIus region, and the source metal. The pPIus region can further contact the pBody region. The pBody area can thus be connected to the reference potential via the pPIus area and the source metal.The source region or sense-source region may or may not contact the pPIus region or sense-pPlus region. The pPIus region or sense-pPlus region may be shallow, deep, or extend in a third dimension. The pPIus region is, particularly depending on its location, heavily p-doped (p+). The sense-pPlus region is, particularly depending on its location, heavily p-doped (p+). The sense-pPlus region may have the same or a different doping concentration and / or depth as the pPIus region.

[0024] In a preferred embodiment, the sense metal is provided for connection to the reference potential or the source metal via a resistor, preferably of high resistance. A potential at the sense metal then corresponds approximately to a potential in the part of the drift region near the inversion channel formable in the sense pBody region or pBody region, or in an n-doped sense-nSpreading region of the sense half-cell or nSpreading region of the active half-cell, preferably provided above the drift region, and is thus a measure of the voltage drop across the inversion channel or MIS channel formable in the pBody region and the source region of the active half-cell adjacent to the sense half-cell. In other words, by means of the sense half-cell, a potential can be developed behind the inversion channel that can be formed in the sense-pBody area, or in the area that is formed in the sense-pBody area.pBody area formable inversion channel near part of the drift area or Sense-nSpreading area or R.415316.

[0025] - 6 - The spreading region can be detected if the control voltage is greater than the threshold voltage. Contrary to the prior art, a separate sense resistor is not required. The voltage drop can be detected as a voltage drop across the resistor. The high-impedance resistor can be infinitely large. The resistance can be determined by an intrinsic input resistance of the circuit.

[0026] In a preferred embodiment, the semiconductor device, in particular the sense half-cell, is designed to interact with a circuit, either monolithically integrated with the semiconductor device or separate from it. This circuit is configured to detect a short circuit based on the magnitude of the voltage drop and, in the event of a short circuit, to reduce the control voltage to decrease the drain current or short-circuit current. The circuit can be connected to the sense metal and the source metal. The circuit can include a resistor, particularly as an input resistor.

[0027] In a preferred embodiment, the sense half-cell is integrated into the active half-cell or another such active half-cell of the semiconductor device. Preferably, the sense half-cell is arranged on a central section of the trench finger extending between two end sections of a trench finger, or on one of the end sections. Without limiting the generality of the embodiment, it is particularly advantageous to use it in cell cross-sections that have a deep pPIus region or sense pPlus region that is significantly deeper than the pBody region or sense pBody region. The sense source region does not contact the source region of the active half-cell or a source region of the other active half-cell.

[0028] If the sense half-cell is located on the mid-section of the trench finger, a first pBody region of the active half-cell or other active half-cells can extend between the sense-source region and a first source region of the active half-cell or other active half-cells, and a second pBody region of the active half-cell or other active half-cells can extend between the sense-source region and a second source region of the active half-cell or other active half-cells. R.415316

[0029] - 7 - In a preferred embodiment, the sense half-cell has at least one strongly p-doped sense-shield pPlus region extending between the sense-source region and at least one source region of the active half-cell or the other active half-cell. The sense-shield pPlus region can prevent the formation of an inversion channel that would otherwise extend laterally between the source region and the sense-source region. This suppression of shunts leads to higher voltages on the sense metal, which is advantageous for the downstream circuitry. The sense-shield pPlus region can extend perpendicular to the trench finger. Furthermore, the sense-shield pPlus region can contact the pBody region or the sense-pBody region. Furthermore, the Sense-Shield-pPlus area can contact the Source area or Sense-Source area. Additionally, the Sense-Shield-pPlus area can contact the Sense-pPIus area.If the sense half-cell is located on the central section of the trench finger, it can have two sense-shield pPlus regions. A first sense-shield pPlus region can extend between the sense-source region and a first source region of the active half-cell or other active half-cells, and a second sense-shield pPlus region can extend between the sense-source region and a second source region of the active half-cell or other active half-cells. The sense-shield pPlus region is p-doped, particularly depending on its location. The Sense-Shield-pPlus area can have the same or a different doping concentration and / or depth as the pPIus area and / or the Sense-pPlus area and / or the pBody area and / or the Sense-pBody area.

[0030] In a preferred embodiment, the active half-cell has an n-doped nSpreading region, and the sense half-cell has an n-doped sense-nSpreading region. The pBody region or sense-pBody region, preferably located above the nSpreading region or sense-nSpreading region, can contact the nSpreading region or sense-nSpreading region. Preferably, the nSpreading region or sense-nSpreading region is located above the drift region. Preferably, the nSpreading region is n-doped with an average doping concentration (n). Preferably, the sense-nSpreading region is n-doped with an average doping concentration (n). The sense nSpreading area may have the same or a different doping concentration and / or depth as the nSpreading area. R.415316

[0031] - 8 - In a preferred embodiment, the semiconductor device comprises a drain metal, at least one gate electrode to which the control voltage can be applied, an n-doped substrate, preferably located above the drain metal, preferably an n-doped n-buffer region, preferably located between the substrate and the drift region, and an n-doped drift region, preferably located above the substrate or the n-buffer region. Preferably, the substrate is made of silicon carbide. The drain metal and / or the substrate and / or the n-buffer region and / or the drift region can extend into a region of the active half-cell and the sense half-cell and thus be a partial component of the active half-cell and the sense half-cell.The semiconductor device can have a first gate electrode extending at least within the region of the active half-cell and a second gate electrode extending at least within the region of the sense half-cell. The first gate electrode and the second gate electrode can then be part of the active half-cell and the sense half-cell, respectively, in sections, preferably halfway. The nSpreading region and the sense nSpreading region can contact the drift region. The substrate can contact the drain metal. The nBuffer region can contact the substrate. If no nBuffer region is provided, the drift region can contact the substrate; if an nBuffer region is provided, it can contact the nBuffer region. Preferably, the gate electrode is made of polysilicon heavily doped with (n+) n-types. Preferably, the substrate is also heavily doped with (n+) n-types.Preferably, the optional n-buffer region is heavily (n+) n-doped. Preferably, the drift region is moderately (n) n-doped. The n-spreading region and / or the sense n-spreading region can be doped to the same or a higher degree than the drift region. The active half-cell and / or the sense half-cell can have a p-doped p-bubble region. Preferably, the p-bubble region is heavily (p+) p-doped. The p-bubble region can be connected to the reference potential or a source potential.

[0032] All the aforementioned areas and metals can preferably be arranged in a layered structure, especially one above the other.

[0033] The semiconductor device can be configured as an n-channel trench MISFET or as a planar n-channel MISFET. R.415316

[0034] - 9 -

[0035] The application of the invention and the scope of protection are not limited to n-channel MISFETs, but can also be applied to p-channel MISFETs by changing the doping type from n to p. Application to other devices with MIS control heads, such as IGBTs, is also conceivable. The application of the invention is not limited to wide-bandgap semiconductor materials, such as silicon carbide (SiC) or gallium nitride (GaN), but can also be applied to other semiconductor materials such as silicon (Si).

[0036] Further advantages, features and details of the invention will become apparent from the following description of preferred embodiments of the invention and from the drawings.

[0037] Brief description of the drawings

[0038] Fig. 1a shows a section through a layer structure of a semiconductor device designed as an n-channel trench MISFET according to the prior art with an optional pBubble region and a deep pPIus region as an active cell of the semiconductor device consisting of two active half-cells;

[0039] Fig. 1b shows a section through a layer structure of a semiconductor device designed as an n-channel trench MISFET according to the prior art with a pBubble region and a flat pPIus region as an active cell of the semiconductor device consisting of two active half-cells;

[0040] Fig. 1c shows a section through a layer structure of a semiconductor device designed as a planar n-channel MISFET according to the prior art as an active cell of the semiconductor device consisting of two active half-cells;

[0041] Fig. 2 shows a partial view of a section through a layer structure of a semiconductor device designed as an n-channel trench MISFET according to a first embodiment of the invention as an R.415316 designed in the manner of one of the active half-cells shown in Fig. 1b.

[0042] - 10 - active half-cell and one sense half-cell of the semiconductor device;

[0043] Fig. 3a shows a top view of a semiconductor device designed as an n-channel trench MISFET according to a second embodiment of the invention with a sense half-cell;

[0044] Fig. 3b shows a top view of a semiconductor device configured as an n-channel trench MISFET according to a third embodiment of the invention with a sense half-cell; and

[0045] Fig. 4 shows a partial view of a section through a layer structure of the semiconductor device according to the third embodiment of the invention along a line BB' shown in Fig. 3b.

[0046] Embodiments of the invention

[0047] Identical elements, or elements with the same function, are marked with the same reference symbols in the figures. The following description focuses particularly on a cell or half-cell.

[0048] An active region of a semiconductor device configured as a MISFET, particularly a PowerMISFET, typically consists of a plurality of parallel-connected active cells, in which current flow in a forward direction can be controlled via a gate. Examples of an active cell of a MISFET are shown in Figures 1a to c for the case of an n-channel MISFET. Figures 1a to c represent prior art examples. In each example shown, the active cell consists of two active half-cells 30, and the plurality of parallel-connected active cells in the active region is obtained by mirroring or repetitively laterally joining the depicted active cells at their outer boundaries.

[0049] Figures 1a to c show the basic structure of such a MISFET, or such an active cell or half-cell. This, or its active cell or half-cells 30, each has a drain metal 3, an n-doped substrate 13 arranged above and contacting the drain metal 3, and an optional substrate 13 arranged above the substrate 13. The substrate R.415316

[0050] - 11 -

[0051] 13 contacting n-doped n buffer region 14, an n-doped drift region 15 arranged above the substrate 13 or the n buffer region 14 and contacting the substrate 13 or the n buffer region 14, an n-doped n spreading region 11 arranged above the drift region 15 and contacting the drift region 15, a p-doped p body region 8 arranged above the n spreading region 11 and contacting the n spreading region 11, an n-doped source region 9 arranged at least partially above the p body region 8 and contacting the p body region 8, a p P U region 10 heavily doped with p, and an n P U region arranged at least above the source region 9 and contacting the source region 9, as well as the pPIus region 10 contacts source metal 2. pPIus region 10 contacts at least pBody region 8.The drain metal 3, the substrate 13, the optional nBuffer region 14, the drift region 15, and the source metal 2 each extend section by section, in this case half, within a region of one of the active half-cells 30. A control voltage can be applied to a gate electrode 4 of the MISFET or its active half-cells 30. The gate electrode 4 extends section by section, in this case half, within the region of one of the active half-cells 30. An inversion channel can be formed at an interface with a gate dielectric 6, which can be, for example, an oxide, in particular silicon dioxide (SiO2), a high-k dielectric, or a layered dielectric made of the aforementioned materials. Furthermore, an intermediate dielectric 7 is provided to insulate the source metal 2 from the gate electrode 4.The gate dielectric 6 and the intermediate dielectric 7 each extend section by section, in this case each half, in the area of ​​one of the active half-cells 30.

[0052] Fig. 1a shows such an active cell of an n-channel trench MISFET with a trench 5, an optional p-doped pBubble region 20 located at a reference potential or source potential and a deep pPIus region 10.

[0053] Fig. 1b shows such an active cell of an n-channel trench MISFET with a trench 5, a p-doped p-bubble region 20 lying at a reference potential or source potential and a flat pPIus region 10.

[0054] Figure 1c shows such an active cell of a planar n-channel MISFET. R.415316

[0055] - 12 -

[0056] In a conduction state, a positive voltage above a threshold voltage is applied to the gate electrode 4, at which a noticeable current flows from the drain metal 3, which is at a low drain voltage (typically on the order of < 10 V), to the source metal 2. In this case, electrons are attracted to the trench-side interface of the p-body regions 8 by an induction effect of the gate electrode 4, so that an inversion channel or conductive channel is formed there. For this purpose, the p-body regions 8 at the interface with the gate dielectric 6 typically exhibit a corresponding doping concentration of approximately 1 × 10⁻⁶ cm⁻³ to 1 × 10⁻⁸ cm⁻³ up to at least approximately 100 nm in an interface normal direction from this interface.In the conduction case, a current path exists from the drain metal 3 through the substrate 13, the optional n buffer region 14, the drift region 15, the n spreading region 11, and then through the respective inversion channel and the respective source region 9 to the source metal 2. A specific on-resistance Ron*A results from an applied drain-source voltage VDS and a current density of the cell j = l / A as Ron*A = VDS / j = VDS / l*A, where A results from a pitch (width of the cell) and its extent z into the plane of the drawing as A = pitch*z. The source regions 9 can have a resistance or, by appropriate choice of their location-dependent doping and the doping of the adjacent pBody regions 8, be designed as a JFET and cause a reduction of the current flow through current feedback, which leads to an increased specific on-resistance Ron*A.This is unfavorable for Ron*A in the pass-through case, but advantageous in a short-circuit case described below.

[0057] In the event of a short circuit, the gate electrode 4 is subjected to a voltage above the threshold voltage, and the drain metal 3 is subjected to a high voltage, for example, several hundred volts. A very high current flows, causing the MISFET to heat up to 1000 °C or more in ps. The design goal here is to limit power dissipation by limiting the short-circuit current. In the event of a short circuit, the source regions 9 provide strong current feedback and thus contribute to limiting the short-circuit current.

[0058] To obtain a semiconductor device according to the invention, at least one active half-cell of a semiconductor device known from the prior art, in particular one of those shown in Figs. 1a to c, can be used.

[0059] - 13 - active half-cells 30, replaced by a sense half-cell or combined with the sense half-cell.

[0060] Figure 2 shows a semiconductor device configured as an n-channel trench MISFET in a preferred embodiment, showing only one active half-cell 30, configured in the manner of one of the active half-cells shown in Figure 1b, and a sense half-cell 40 connected in parallel to the active half-cell 30. The active half-cell 30 and the sense half-cell 40 belong to two different parallel-connected cells of the semiconductor device. Only the upper part, which is in focus, is shown here. For the sake of simplicity, the intermediate dielectrics and cover layers are not shown.

[0061] The sense half-cell 40 is similar in structure to the active half-cell 30. It features an n-doped sense-nSpreading region 11b, a p-doped sense-pBody region 8b arranged above and contacting the sense-nSpreading region 11b, an n-doped sense-Source region 9b arranged above and contacting the sense-pBody region 8b, a p-doped sense-pPIus region 10b with a strong doping and contacting the sense-pBody region 8b and the pPIus region 10, and a sense-metal 2b arranged above and contacting the sense-Source region 9b. The addition of "Sense-" to the aforementioned areas and the aforementioned metal indicates that the respective area or metal is part of the Sense half-cell 40.Furthermore, the semiconductor device has a gate electrode 4 extending section by section, in this case half, within a region of the sense half-cell 40, to which the control voltage can also be applied, and a gate dielectric 6 extending section by section, in this case half, within the region of the sense half-cell 40. The source metal 2 is connected to a reference potential, so that, on the one hand, the sense pBody region 8b is connected to the reference potential via the sense pPlus region 10b, the pPIus region 10 and the source metal 2, and on the other hand, the pBody region 8 is connected to the reference potential via the pPIus region 10 and the source metal 2. The drain metal 3, the substrate 13, and the optional buffer region 14, which each extend within the area of ​​the active half-cell 30 and the sense half-cell 40, are not shown. R.415316.

[0062] - 14 -

[0063] If the gate electrode 4 in the region of the active half-cell 30 or the sense half-cell 40 is at a potential greater than the respective threshold voltage Vth, an inversion channel or conductive channel forms at the gate-dielectric-side interface of the sense p-body region 8b and the p-body region 8, respectively. If the drain metal 3 is at a positive potential, a current flows in the active half-cell 30 to the source metal 2 as described above, and in the case of forward or short circuit, a voltage drop is generated across the inversion channel then formed in the p-body region 8 and the source region 9. If the sense metal 2b is connected to the reference potential or source metal 2 via a resistor 50, preferably of high resistance, as shown, then a potential at the sense metal 2b corresponds approximately to a potential in the pBody region 8 or .The inversion channel formed in the sense-pBody region 8b is located near the drift region 15, nSpreading region 11, or sense-nSpreading region 11b, and is thus a measure of the voltage drop across the inversion channel or MIS channel formed in the pBody region 8 and the source region 9 of the active half-cell 30 adjacent to the sense half-cell 40. This voltage drop is higher in the short-circuit case than in the forward-biased case and can be easily evaluated by a suitable circuit (not shown here) that is monolithically integrated with the MISFET and / or separate from the MISFET, as it can be greater than the voltage drop generated across the sense resistor in the prior art. This circuit can then, similarly to the prior art, provide negative feedback to the gate drive signal, thus reducing the drain current in the short-circuit case. Contrary to the prior art, a separate sense resistor is not required. The one shown in the figure...The resistance 50 shown in Figure 2 refers to an intrinsic input resistance of the circuit.

[0064] Another preferred embodiment of a semiconductor device configured as an n-channel trench MISFET is shown in Fig. 3a. The sense half-cell is shown together with active cell regions. A section along a line AA' shown in Fig. 3a corresponds to the upper part of the arrangement of the embodiment shown in Fig. 2. The embodiment shown in Fig. 3a results from replacing a portion of at least one active half-cell in a longitudinal direction of the trench 5 by a sense half-cell 40 in a semiconductor device known from the prior art. Therefore, the sense half-cell 40 is located next to the active half-cell.

[0065] - 15 -

[0066] Half-cell 30 integrates a further active half-cell 31 as shown. The sense half-cell 40 can, as shown, be arranged in a central section of the trench finger extending between two end sections and / or at at least one of the end sections. The basic operating principle is analogous to that already described above. Without limiting the generality, this embodiment is particularly advantageous in cell cross-sections that have deep (sense)pPlus regions 10, 10b, which are significantly deeper than the (sense)pBody regions 8, 8b.

[0067] Another preferred embodiment of a semiconductor device configured as an n-channel trench MISFET is shown in Fig. 3b. The sense half-cell is shown together with active cell regions. A section along a line BB' shown in Fig. 3b for the upper part of the arrangement is shown in Fig. 4. The embodiment shown in Fig. 3b results from replacing a portion of at least one active half-cell in a longitudinal direction of the trench 5 in a semiconductor device known from the prior art with a sense half-cell 40. Therefore, the sense half-cell 40 is integrated into another active half-cell 31 shown next to the active half-cell 30. As shown, the sense half-cell 40 can be arranged in a central section of the trench finger extending between two end sections and / or at at least one of the end sections.The basic operating principle is analogous to that already described above. Without limiting the generality of this embodiment, it is particularly advantageous for use in cell cross-sections that have deep (sense)pPlus regions 10, 10b, which are significantly deeper than the (sense)pBody regions 8, 8b. In contrast to the embodiment shown in Fig. 3a, the strongly p-doped sense-shield pPlus regions 10c present here can suppress the inversion channels that form laterally between the source regions 9 of the further active half-cell 31 and the sense-source region 9b in the embodiment shown in Fig. 3a. This suppression of shunts leads to higher voltages at the sense metal 2b, which is advantageous for the downstream circuitry.

[0068] For the description relating to Figures 2 to 4, reference is made to the description of Figures 1a to c. R.415316

[0069] - 16 -

[0070] The application of the invention is not limited to the strip-shaped cell topologies shown. Furthermore, the half-cells mentioned do not have to have the same width or can have different widths.

Claims

R.415316 - 17 - Claims 1. Semiconductor device, preferably MISFET, in particular PowerMISFET, preferably based on a wide-bandgap semiconductor material, in particular silicon carbide (SiC), comprising at least one active half-cell (30) defining an active region, wherein the active half-cell (30) comprises a p-doped p-body region (8) and an n-doped source region (9), characterized in that the semiconductor device comprises at least one sense half-cell (40) connected in parallel to the active half-cell (30), which is configured to detect a voltage drop at least across an inversion channel formable in the p-body region (8) and the source region (9) when a control voltage is greater than a threshold voltage.

2. Semiconductor device according to claim 1, characterized in that the semiconductor device has a source metal (2) contacting at least the source region (9), wherein the sense half-cell (40) has a p-doped sense p-body region (8b), an n-doped sense source region (9b) and a sense metal (2b) contacting the sense source region (9b).

3. Semiconductor device according to claim 2, characterized in that the sense-pBody region (8b) is connected to a reference potential, preferably via a strongly doped p-doped sense-pPlus region (10b) of the sense half-cell (40).

4. Semiconductor device according to claim 3, characterized in that the sense metal (2b) is provided to be connected to the reference potential via a, preferably high-resistance, resistor (50) or is connected to the reference potential via a, preferably high-resistance, resistor (50).

5. Semiconductor device according to one of the preceding claims, characterized in that the semiconductor device is provided for R.415316 - 18 - is to cooperate with a circuit formed monolithically with the semiconductor device or separately from the semiconductor device, which is designed to detect a short circuit based on the magnitude of the voltage drop and to reduce the control voltage in the event of a short circuit in order to reduce a drain current.

6. Semiconductor device according to one of the preceding claims, characterized in that the sense half-cell (40) is integrated into the active half-cell (30) or another such active half-cell (31) of the semiconductor device, wherein the sense half-cell (40) is arranged on a central section of the trench finger extending between two end sections of a trench finger or on one of the end sections.

7. Semiconductor device according to claim 6, characterized in that the sense half-cell (40) has at least one strongly doped p-doped sense shield pPlus region (10c) extending between the sense source region (9b) and at least one source region (9) of the active half-cell (30) or the further active half-cell (31).

8. Semiconductor device according to one of the preceding claims, characterized in that the active half-cell (30) has an n-doped nSpreading region (11), wherein the sense half-cell (40) has an n-doped sense nSpreading region (11b).

9. Semiconductor device according to one of the preceding claims, characterized in that the semiconductor device comprises a drain metal (3), at least one gate electrode (4) to which the control voltage can be applied, an n-doped substrate (13), preferably an n-doped n buffer region (14), and an n-doped drift region (15).

10. Semiconductor device according to one of the preceding claims, characterized in that the semiconductor device is configured as an n-channel trench MISFET or as a planar n-channel MISFET.

Images