Gate drive device

Abstract

This gate drive device supplies a gate voltage to a power semiconductor element. The gate drive device comprises: a parallel circuit that is provided in a current path for charging and discharging the gate capacitance of the power semiconductor element and has a diode, the forward direction of which is a direction in which a charge / discharge current flows, and a switching element connected in parallel with the diode; and a control unit that controls the switching element to be in an off state at the start of a turn-on operation or a turn-off operation of the power semiconductor element and controls the switching element to be in an on state after the start of the turn-on operation or the turn-off operation.

Description

Gate driving device

[0001] The present invention relates to a gate driving device.

[0002] In recent years, the electrification of vehicles, including vehicle drive systems, has been progressing. In order to miniaturize and increase the output power density of power converters in vehicle drive systems, reducing the loss of power semiconductors is important. For example, Patent Document 1 discloses a multi-stage gate drive circuit capable of adjusting the switching speed by switching the gate voltage, enabling a rapid rise and fall of the gate drive voltage.

[0003] Japanese Patent Application Laid-Open No. 2019-110665

[0004] However, the technique of Patent Document 1 has drawbacks such as an increase in the number of components and difficulty in control and fine adjustment.

[0005] The gate driving device according to an aspect of the present invention is a gate driving device that supplies a gate voltage to a power semiconductor element, and includes a parallel circuit provided on a current path for charging and discharging the gate capacitance of the power semiconductor element, the parallel circuit having a diode whose forward direction is the direction in which the charging and discharging current flows and a switching element connected in parallel to the diode, and a control unit that controls the switching element to be in an off state at the start of the turn-on operation or turn-off operation of the power semiconductor element and controls the switching element to be in an on state after the start of the turn-on operation or the turn-off operation.

[0006] According to the present invention, it is possible to reduce switching losses while simplifying the circuit.

[0007] Figure 1 shows an example of a power conversion device. Figure 2 shows the circuit configuration of the gate drive device in the first embodiment. Figure 3 shows an example of the waveforms of each signal when the device is turned on. Figure 4 shows an example of the waveforms of each signal when the device is turned off. Figure 5 shows a modification 1. Figure 6 shows a modification 2. Figure 7 shows a modification 3. Figure 8 is a diagram illustrating a second embodiment of the present invention. Figure 9 shows an example of the signal waveform when the device is turned on in a comparative example. Figure 10 shows an example of the signal waveform when the device is turned on in the second embodiment. Figure 11 shows an example of the signal waveform when the device is turned off in a comparative example. Figure 12 shows an example of the signal waveform when the device is turned off in the second embodiment.

[0008] The embodiments for carrying out the present invention will be described below with reference to the figures. The following description and drawings are illustrative examples for explaining the present invention, and have been omitted and simplified as appropriate for clarity of explanation. In addition, in the following description, the same or similar elements and processes are denoted by the same reference numerals, and redundant explanations may be omitted. It should be noted that the contents described below are merely examples of embodiments of the present invention, and the present invention is not limited to the embodiments described below, and can be carried out in various other forms.

[0009] (First Embodiment) Figure 1 shows an example of a power conversion device. In the first embodiment, a power conversion device 200 mounted on a vehicle 1000 will be described as an example. The power conversion device 200 drives an electric motor 300 mounted on the vehicle 1000. The vehicle 1000 is equipped with a power storage device 100. The power conversion device 200 converts the DC power supplied from the power storage device 100 into AC power and drives the electric motor 300.

[0010] The electric motor 300 is, for example, a motor for driving the wheels. The electric motor 300 has three-phase coils connected in a predetermined pattern. The connection pattern is not limited to the Y-shaped pattern shown in Figure 1, but may also be other connection patterns such as a delta pattern. The electric motor 300 is driven to rotate by applying a predetermined energizing pattern to the three-phase coils from the power conversion device 200.

[0011] The energy storage device 100 has a positive terminal 100a and a negative terminal 100b. The power converter 200 has a positive bus line 201p, a negative bus line 201n, a smoothing capacitor 110, and a three-phase switching arm 500 (U, V, W). The positive bus line 201p is connected to the positive terminal 100a of the energy storage device 100. The negative bus line 201n is connected to the negative terminal 100b of the energy storage device 100. Both ends of the smoothing capacitor 110 and the three-phase switching arm 500 (U, V, W) are connected to the positive bus line 201p and the negative bus line 201n.

[0012] Each of the three-phase switching arms 500 (U, V, W) is provided with a semiconductor switching element 101 for the upper arm and a semiconductor switching element 101 for the lower arm. The semiconductor switching element 101 is, for example, a power semiconductor element, such as an IGBT (Insulated Gate Bipolar Transistor) or a MOSFET (Metal Oxide Semiconductor Field Effect Transistor). Each semiconductor switching element 101 has a parallel-connected freewheeling diode (or body diode) 102. The semiconductor switching element 101 of the upper arm and the semiconductor switching element 101 of the lower arm are connected in series. The connection point between the semiconductor switching element 101 of the upper arm and the semiconductor switching element 101 of the lower arm is connected to one end of the coil of the corresponding phase of the electric motor 300. In the example shown in Figure 1, one semiconductor switching element 101 is provided on each upper and lower arm, but a configuration in which multiple semiconductor switching elements 101 are used in parallel is also possible.

[0013] The power converter 200 includes a conversion control device 400 that controls the gate drive device 600. The conversion control device 400 outputs a control signal P for each gate drive device 600, and controls each semiconductor switching element 101 individually. The control signal P is a pulse signal having a predetermined pulse width, and the conversion control device 400 performs PWM control on the semiconductor switching elements 101. This control signal P causes the semiconductor switching elements 101 of the same phase to be alternately turned on / off within a range where they are not turned on simultaneously. As a result, the DC power from the energy storage device 100 is converted to AC power, and the electric motor 300 is driven to rotate.

[0014] In this embodiment, a power conversion device 200 constituting an inverter as shown in Figure 1 is described as an example, but the present invention is not limited to this and can also be applied to DC / DC converters, AC / AC converters, AC / DC inverters, etc.

[0015] Figure 2 shows the circuit configuration of the semiconductor switching element 101 related to the lower arm of the U phase shown in Figure 1, and the gate drive device 600 provided for the semiconductor switching element 101. Although not shown in the figure, the upper arm of the U phase and the upper and lower arms of the other phases (V and W phases) have similar configurations. In the following explanation, the case in which the semiconductor switching element 101 used is a MOSFET will be used as an example.

[0016] The output side of the gate drive device 600 is connected to the gate terminal of the semiconductor switching element 101, and the input side is connected to the conversion control device 400. The gate drive device 600 includes a driver circuit 700 and control signal generation units 800H and 800L that control the driver circuit 700. The control signal P from the conversion control device 400 is input to the gate driver IC 710 and the control signal generation units 800H and 800L, respectively, which are provided in the driver circuit 700. The conversion control device 400 and the control signal generation units 800H and 800L have, for example, a CPU, RAM, ROM, etc., internally. Alternatively, the conversion control device 400 and the control signal generation units 800H and 800L may be configured as a single control device.

[0017] The primary side of the gate driver IC 710 is provided with a VCC1 terminal, a PWM terminal, and a GND1 terminal. The VCC1 terminal is connected to the primary power supply, and the GND1 terminal is connected to the primary ground. A control signal P is input to the PWM terminal from the conversion control device 400. On the other hand, the secondary side of the gate driver IC 710 is provided with a VCC2 terminal, an OUTH terminal, an OUTL terminal, and a VEE2 terminal. The VCC2 terminal is connected to the secondary power supply, and the VEE2 terminal is connected to the source potential of the semiconductor switching element 101.

[0018] (Gate Charging Path) The OUTH terminal is connected to a path that charges the gate capacitance of the semiconductor switching element 101, i.e., a path with a resistor RH, and is ultimately connected to the gate terminal of the semiconductor switching element 101. When the gate capacitance is being charged, current flows from the OUTH terminal toward the gate of the semiconductor switching element 101. The resistor RH is a resistor that determines the magnitude of the gate current when the gate capacitance is being charged. A diode DH is provided on the gate charging path, and a switching element SH is connected in parallel to the diode DH. The diode DH is positioned so that the direction in which the charging current flows is forward. The switching element SH is controlled by a switch control signal CH from the control signal generation unit 800H. The control signal generation unit 800H receives a state signal J from a terminal (condition monitor sensor) that senses the state of the semiconductor switching element 101. The state signal J includes information such as the main voltage (Vds), main current (Ids), and temperature of the semiconductor switching element 101. The control signal generation unit 800H generates a switch control signal CH based solely on the control signal P output from the conversion control device 400, or based on both the control signal P and the status signal J.

[0019] The OUTL terminal is connected to a path for discharging the gate capacitance of the semiconductor switching element 101, i.e., a path with a resistor RL, and ultimately to the gate terminal of the semiconductor switching element 101. During gate capacitance discharge, current flows from the gate of the semiconductor switching element 101 towards the OUTL terminal. The resistor RL is a resistor that determines the magnitude of the gate current during gate capacitance discharge. A diode DL is provided on the gate discharge path, and a switching element SL is connected in parallel to the diode DL. The resistance value of the resistor RL is set to a smaller value than in the conventional case where a parallel circuit between the diode DL and the switching element SL is not provided.

[0020] The diode DL is positioned so that the discharge current flows in the forward direction. The switching element SL is controlled by a switch control signal CL from the control signal generation unit 800L. The control signal generation unit 800L receives a state signal J from a terminal (condition monitor sensor) that senses the state of the semiconductor switching element 101. The control signal generation unit 800L generates the switch control signal CL based only on the control signal P output from the conversion control device 400, or based on both the control signal P and the state signal J.

[0021] As will be described in detail later, in the first embodiment, the loss of the semiconductor switching element 101 is reduced by controlling the opening and closing of the switching elements SH and SL when the semiconductor switching element 101 is operating.

[0022] <Explanation of Operation During Turn-On> First, the operation of the semiconductor switching element 101 during turn-on will be explained. Here, let Vsw be the voltage on the left side of the diode DH in the diagram during the turn-on operation of the semiconductor switching element 101. When the switching element SH is in the open state (off state), current flows in the forward direction (to the right in the diagram) of the diode DH. When current flows in the forward direction, a voltage drop Vf occurs in the diode DH. As a result, the voltage on the right side of the diode DH, that is, the voltage at the gate terminal, becomes Vsw - Vf. On the other hand, when the switching element SH is in the closed state (on state), both ends of the diode DH are short-circuited by the switching element SH. Therefore, the voltage drop Vf across both ends of the diode DH disappears. As a result, the voltage on the right side of the diode DH, that is, the voltage at the gate terminal, becomes Vsw. In this way, the voltage at the gate terminal during turn-on can be adjusted to Vsw or Vsw - Vf by switching the switching element SH on / off.

[0023] Figure 3 shows an example of the waveforms of each signal when the semiconductor switching element 101 is turned on. Waveform (A) shows the control signal P from the conversion control device 400. Waveform (B) shows the switch control signal CH from the control signal generation unit 800H. Waveform (C) shows the gate voltage Vgs of the semiconductor switching element 101. In waveform (C), the solid line L10 shows the gate voltage Vgs in the first embodiment, and the dashed line L11 shows the gate voltage Vgs in the conventional case where a parallel circuit between the diode DH and the switching element SH is not provided. Waveform (D) shows the drain current Ids and the drain-source main voltage (hereinafter referred to as drain-source voltage) Vds of the semiconductor switching element 101. The solid line L20 shows the drain current Ids, the solid line L21 shows the drain-source voltage Vds, and the dashed line L22 shows the drain-source voltage Vds in the conventional case. Waveform (E) shows the waveform of the power loss (= Vds × Ids) of the semiconductor switching element 101. The solid line L30 shows the case of the first embodiment, and the dashed line L31 shows the case of the conventional example.

[0024] As shown in waveform (A), at time t0, the control signal P switches from off to on, initiating the gate turn-on operation, and as shown in waveform (C), the gate voltage Vgs begins to rise. Subsequently, when the gate voltage Vgs rises and exceeds the gate threshold voltage Vth, the drain-source voltage Vds begins to decrease, as shown in waveform (D). Then, along with the decrease in the drain-source voltage Vds, the drain current Ids increases. Subsequently, when the condition monitor sensor provided on the semiconductor switching element 101 detects that the drain current Ids has reached its peak value Ipeak, the control signal generation unit 800H switches the switch control signal CH from off to on. Alternatively, the switch control signal CH may be switched from off to on by adding a delay to the turn-on timing (time t0) of the control signal P.

[0025] At time t1, after the drain current Ids, which is the main current, has reached its peak value Ipeak, the control signal generation unit 800H switches the switch control signal CH from off to on, as shown in waveform (B), to close the switching element SH. When the switching element SH is closed, the ends of the diode DH are short-circuited, and the gate voltage Vgs becomes larger than in the conventional case (dashed line L11), as shown by the solid line L10 in waveform (C). As a result, as shown in waveform (D), the rate of decrease of the drain-source voltage Vds becomes faster than in the conventional case (dashed line L22). Subsequently, at any timing (time t2) when the gate voltage Vgs reaches a steady value, the control signal generation unit 800H switches the switch control signal CH from on to off, as shown in waveform (B). If the on state of the control signal P is short, the switch control signal CH may be switched from on to off at the same time as the control signal P switches from on to off.

[0026] As shown in waveform (D), the drain-source voltage Vds (solid line L21) in this embodiment is lower than in the conventional case (dashed line L22) during the period from time t1 to time t2. Therefore, as shown in waveform (E), the power loss (solid line L30), which is the product of the drain-source voltage Vds and the drain current Ids, is also smaller than in the conventional case (dashed line L31). As a result, the amount of loss, which is the time integral of the power loss, is also smaller than in the conventional example. In other words, in this embodiment, by increasing the slew rate of the drain-source voltage Vds in the latter half while avoiding the disadvantage of increased Ids surge during turn-on, the loss during the turn-on operation of the semiconductor switching element 101 can be reduced compared to the conventional example. In particular, the loss reduction effect can be made even greater when a large current output is required, such as when starting vehicle operation.

[0027] <Explanation of operation during turn-off> Returning to Figure 2, let Vsw be the voltage on the left side of the diode DL when the semiconductor switching element 101 is turned off. When the switching element SL is in the open state (off state), current flows in the forward direction (leftward direction in the diagram) of the diode DL. When current flows in the forward direction, a voltage drop Vf occurs in the diode DL. As a result, the voltage on the right side of the diode DL, that is, the voltage at the gate terminal, becomes Vsw + Vf.

[0028] On the other hand, when the switching element SL is in the closed state (on state), the ends of the diode DL are short-circuited by the switching element SL. As a result, the voltage drop Vf across the ends of the diode DL disappears. Consequently, the voltage to the right of the diode DL, i.e., the gate terminal voltage, becomes Vsw. In this way, by switching the switching element SL on or off, the gate terminal voltage during turn-off can be adjusted to Vsw or Vsw + Vf.

[0029] Figure 4 shows examples of waveforms of each signal when the semiconductor switching element 101 is turned off. Waveform (A) shows the control signal P from the conversion control device 400. Waveform (B) shows the switch control signal CL from the control signal generation unit 800L. Waveform (C) shows the gate voltage Vgs of the semiconductor switching element 101. In waveform (C), the solid line L40 shows the gate voltage Vgs in the first embodiment, and the dashed line L41 shows the gate voltage Vgs in the conventional case where a parallel circuit between the diode DL and the switching element SL is not provided. Waveform (D) shows the drain current Ids (solid line L50 and dashed line L51) and drain-source voltage Vds (solid line L60 and dashed line L61) of the semiconductor switching element 101. The solid lines L50 and L60 show the case of the first embodiment, and the dashed lines L51 and L61 show the conventional case. Waveform (E) shows the waveform of the power loss (= Vds × Ids) of the semiconductor switching element 101. Note that the solid line L70 shows the case of the first embodiment, and the dashed line L71 shows the conventional case.

[0030] As shown in waveform (A), at time t0, the control signal P switches from on to off, the gate turn-off operation begins at time t0, and the gate voltage Vgs begins to decrease as shown in waveform (C). After a short time has elapsed since the gate voltage Vgs began to decrease, the drain-source voltage Vds begins to rise and the drain current Ids begins to decrease as shown in waveform (D). In the first embodiment, as shown in waveform (B), the control signal generation unit 800L switches the switch control signal CL from off to on with a delay of Δt = t1 - t0 from the gate turn-off time t0. The timing for turning on the switch control signal CL (time t1) is set before the start of the rise in the drain-source voltage Vds.

[0031] When the switch control signal CL is turned on and the switching element SL is closed, the ends of the diode DL are short-circuited by the switching element SL. As a result, the gate capacitance discharge current flows to the OUTL terminal through only the resistor RL on the gate discharge path, as in the conventional case. However, since the value of resistor RL is set smaller than in the conventional case, the gate voltage Vgs (solid line L40) in the first embodiment (as shown in waveform (C)) is smaller than in the conventional case (dashed line L41). Therefore, the gate discharge speed becomes faster than in the conventional case, and as shown in waveform (D), the slew rates of the drain current Ids and the drain-source voltage Vds increase compared to the conventional case (dashed lines L51, L61).

[0032] Subsequently, as shown in waveform (B), the control signal generation unit 800L switches the switch control signal CL from on to off at time t2. For example, the detection threshold voltage is set to a value obtained by subtracting a predetermined value stored in memory or the like from the Vds peak value of the solid line L60. Then, the condition monitor sensor provided on the semiconductor switching element 101 detects the timing (time t2) when the drain-source voltage Vds exceeds the detection threshold voltage, and switches the switch control signal CL from on to off at that timing.

[0033] When the switch control signal CL is turned off, the short circuit of the diode DL by the switching element SL is released, causing the gate voltage Vgs to rise compared to the conventional state, as shown in waveform (C). In accordance with this rise in gate voltage Vgs, the slew rates of the drain current Ids and the drain-source voltage Vds also decrease, and the voltage peak of the drain-source voltage Vds is suppressed. For example, the value of resistor RL is set so that the peak value of the solid line L60 and the peak value of the dashed line L61 are approximately the same.

[0034] As shown in waveform (D), in the first embodiment, the slew rates of the drain current Ids and the drain-source voltage Vds are larger than in the conventional design. Therefore, as can be seen from the power loss waveform shown in waveform (E), the power loss is reduced, and the amount of loss, which is the time integral of the power loss, is also smaller than in the conventional example. Furthermore, since it is only necessary to provide a parallel circuit of a switching element and a diode in the gate charging path or gate discharging path compared to the conventional configuration, loss reduction can be achieved with a simpler additional configuration compared to the configuration described in Patent Document 1 mentioned above.

[0035] In the first embodiment described above, parallel circuits of diodes and switching elements were provided in both the gate charging path and the gate discharge path, but they may be placed in only one of the paths. When placed in the gate charging path, the operation shown in Figure 3 reduces losses during turn-on, and when placed in the gate discharge path, the operation shown in Figure 4 reduces losses during turn-off. Note that the types of diodes DH and DL are not limited, and Schottky barrier diodes, PiN diodes, etc., can be used.

[0036] (Modification 1) In the example shown in Figure 2 above, the gate driver IC 710 was configured to have an OUTH terminal and an OUTL terminal. However, if these terminals are combined into a single OUT terminal, the driver circuit 700 shown in Figure 2 can be replaced with the driver circuit 700 shown in Figure 5. The control operation of the switching elements SH and SL is the same as in the first embodiment described above.

[0037] (Modification 2) Figure 6 shows Modification 2 of the above-described embodiment. In Modification 2, a plurality (n) of diodes DH1, DH2, ..., DHn are connected in series, and a switching element SH is connected in parallel to the plurality of diodes DH1 to DHn connected in series. In Modification 2, by changing the number of diodes connected in series, the forward voltage drop of the diodes, that is, the gate voltage of the semiconductor switching element 101, can be finely adjusted. The operation is the same as in the first embodiment described above, so the explanation will be omitted.

[0038] In Figure 6, a parallel circuit of a switching element and a diode is placed only in the gate charging path. However, as in the configuration of Figure 2, the parallel circuit may be placed in both the gate charging path and the gate discharge path, or it may be placed only in the gate discharge path.

[0039] (Modification 3) Figure 7 shows Modification 3 of the above-described embodiment. In Modification 3, a MOSFET 720 is provided in the gate charging path or gate discharging path as an element having the same function as the parallel circuit of the switching element and diode described above. In Figure 7, the MOSFET 720 is provided in the gate charging path. A body diode BD is formed between the source and drain of the MOSFET 720. The source S of the MOSFET 720 is connected to a resistor RH and the drain D is connected to the gate terminal of the semiconductor switching element 101, such that the diode forward direction of the body diode BD is the same as the direction in which the charging current flows.

[0040] MOSFET 720 is controlled on / off by a switch control signal CH from the control signal generation unit 800H. When MOSFET 720 is turned on, the ends of the body diode BD are shorted, and when MOSFET 720 is turned off, the body diode BD becomes conductive. By using a configuration like that of Modification 3, the same functions as in the first embodiment can be achieved with a simpler configuration.

[0041] In the example shown in Figure 7, the MOSFET 720 is placed only in the gate charging path, but it may also be placed in both the gate charging path and the gate discharge path, as in the case of Figure 2, or it may be placed only in the gate discharge path. When the MOSFET 720 is placed in the gate discharge path, it should be positioned so that the forward direction of the body diode BD is the same as the direction in which the discharge current flows. Furthermore, when the MOSFET 720 is applied to the modified example 2, multiple MOSFETs 720 are connected in series, and each MOSFET 720 is controlled to be turned on / off simultaneously.

[0042] In the above description, the case of using an external diode as the diode for the parallel circuit (the first embodiment) and the case of using the body diode BD of the MOSFET 720 (Modification 3) have been separately described. However, a configuration in which the body diode BD and the external diode are mixed may also be used. Further, in a configuration in which a plurality of diodes are provided, when it is desired to adjust the gate voltage, a series arrangement as shown in FIG. 6 is preferable, and when it is desired to pass a larger gate current (when adjusting the rated value of the current), a parallel arrangement is preferable. When the gate current can be increased, faster switching is possible and the loss can be further reduced.

[0043] (Second Embodiment) FIG. 8 is a diagram for explaining the second embodiment of the present invention. FIG. 8 is a diagram showing the configuration of a single-phase circuit, and shows, for example, a driver circuit 700 for a pair of semiconductor switching elements 101a and 101b constituting the upper arm of the U phase. The semiconductor switching elements 101a and 101b connected in parallel are driven by the same driver circuit 700. The OUTH terminal of the driver circuit 700 is connected to the gate terminal of the semiconductor switching element 101a via the resistor RHa and to the gate terminal of the semiconductor switching element 101b via the resistor RHb. Similarly, the OUTL terminal of the driver circuit 700 is connected to the gate terminal of the semiconductor switching element 101a via the resistor RLa and to the gate terminal of the semiconductor switching element 101b via the resistor RLb.

[0044] A parallel circuit of a diode DHa and a switching element SHa is provided on the gate charging path provided with the resistor RHa, and a parallel circuit of a diode DHb and a switching element SHb is provided on the gate charging path provided with the resistor RHb. Similarly, a parallel circuit of a diode DLa and a switching element SLa is provided on the gate discharging path provided with the resistor RLa, and a parallel circuit of a diode DLb and a switching element SLb is provided on the gate discharging path provided with the resistor RLb.

[0045] Here, the switching elements SHA and SHb provided on the gate charging path are controlled by the control signal CH from the control signal generation unit 800H, and these control signals may be the same signal or different signals. The same applies to the control signals of the switching elements SLa and SLb provided on the gate discharging path. Note that in the second embodiment, a configuration using a plurality of diodes connected in series as shown in FIG. 6 or a configuration using the MOSFET 720 as shown in FIG. 7 may also be applied.

[0046] By the way, due to aging deterioration, thermal non-uniformity, etc., an imbalance in the drain current Ids may occur between the semiconductor switching elements 101a and 101b connected in parallel. When such an imbalance occurs, there is a concern that the thermal losses of the semiconductor switching elements 101a and 101b become imbalanced and the element with the larger loss may deteriorate prematurely. Hereinafter, a method for correcting such an imbalance will be described.

[0047] Although the description is omitted, in the configuration shown in FIG. 8 of the second embodiment, by controlling the switching elements provided in each parallel circuit in the same manner as in the case of the first embodiment described above, it is possible to reduce the losses during turn-on and turn-off.

[0048] <Explanation of the operation during turn-on> First, referring to FIGS. 9 and 10, the operation of the semiconductor switching elements 101a and 101b during turn-on will be described. FIG. 9 shows, as a comparative example, the signal waveforms in the case of a conventional configuration, that is, the signal waveforms when a parallel circuit of a diode and a switching element is not provided in the gate charging path and the gate discharging path.

[0049] In Figure 9, waveform (A) shows the control signal P from the conversion control device 400. In waveform (C), the solid line L80 shows the gate voltage Vgs of the semiconductor switching element 101a, and the dashed line L81 shows the gate voltage Vgs of the semiconductor switching element 101b. Here, it is assumed that the gate threshold voltage Vth1 of the semiconductor switching element 101a and the gate threshold voltage Vth2 of the semiconductor switching element 101b have different values, and that Vth2 > Vth1. Waveform (D) is a figure showing the drain current Ids and the drain-source voltage Vds, where the solid line L90 shows the drain current Ids of the semiconductor switching element 101a, and the dashed line L91 shows the drain current Ids of the semiconductor switching element 101b. The solid line L100 shows the drain-source voltage Vds of the parallel-connected semiconductor switching elements 101a and 101b.

[0050] As shown in waveform (A), when the control signal P switches from off to on at time t0, the gate voltages Vgs of semiconductor switching elements 101a and 101b rise as shown in waveform (C). However, as mentioned above, since Vth1 < Vth2, semiconductor switching element 101a reaches its gate threshold voltage earlier than semiconductor switching element 101b. Therefore, as shown in waveform (D), the drain current Ids rises first in semiconductor switching element 101a, and the drain current Ids during the switching period is larger in semiconductor switching element 101a. In other words, an imbalance in drain current Ids occurs between semiconductor switching elements 101a and 101b during this period.

[0051] On the other hand, Figure 10 shows an example of a signal waveform at turn-on in the second embodiment. Waveform (A) shows the control signal P from the conversion control device 400, which switches from off to on at time t0, similar to the case in Figure 9. Waveform (B) shows the switch control signal CH input to the switching elements Sha and SHb. The solid line CHa is the switch control signal of the switching element Sha, and the dashed line CHb is the switch control signal of the switching element SHb. Waveform (C) shows the gate voltage Vgs of each semiconductor switching element 101a and 101b. The solid line L80 shows the gate voltage Vgs of the semiconductor switching element 101a, and the dashed line L181 shows the gate voltage Vgs of the semiconductor switching element 101b. Waveform (D) shows the drain current Ids and drain-source voltage Vds of each semiconductor switching element 101a and 101b. The solid line L90 represents the drain current Ids of semiconductor switching element 101a, and the dashed line L191 represents the drain current Ids of semiconductor switching element 101b. The solid line L110 represents the drain-source voltage Vds of semiconductor switching elements 101a and 101b.

[0052] In the second embodiment, as shown in waveform (B), the switch control signal CHb of the switching element SHb switches from off to on at time t11, before (for example, immediately before) the gate voltage Vgs of the semiconductor switching element 101a becomes the gate threshold voltage Vth1, and then switches from on to off at time t12. On the other hand, the switch control signal CHa of the switching element Sha remains in the off state.

[0053] When the switch control signal CHb switches from off to on at time t11, the ends of the diode DHb are short-circuited by the switching element SHb. This accelerates the rise in the gate voltage of the semiconductor switching element 101b. As a result, the rise in the drain current Ids of the semiconductor switching element 101b is also accelerated and becomes similar to that of the semiconductor switching element 101a. In other words, the imbalance in the drain current Ids between the semiconductor switching elements 101a and 101b is corrected. Here, it is preferable to set the forward voltage drop of the diode DHb to be approximately the same as the difference between the gate threshold voltage Vth2 of the semiconductor switching element 101b and the gate threshold voltage Vth1 of the semiconductor switching element 101a (= Vth2 - Vth1).

[0054] In the above explanation, the imbalance in the drain current Ids between semiconductor switching elements 101a and 101b was corrected by turning on only the switching element SHb among the switching elements Sha and SHb. However, the imbalance can also be corrected by controlling both switching elements Sha and SHb to be turned on at the same timing. In the case of simultaneous turning control, it is preferable to make the difference between the forward voltage drop of diode DHb connected in parallel with switching element SHb and the forward voltage drop of diode DHa connected in parallel with switching element Sha approximately equal to the difference between the gate threshold voltage Vth2 and the gate threshold voltage Vth1 (= Vth2 - Vth1).

[0055] <Explanation of operation during turn-off> Next, the operation of the semiconductor switching elements 101a and 101b during turn-off will be explained with reference to Figures 11 and 12. During turn-off, the gate capacitance of each semiconductor switching element 101a and 101b is discharged through the gate discharge path provided with resistors RLa and RLb in Figure 8. Figure 11 shows an example of a signal waveform during turn-off in a comparative example (conventional configuration), and Figure 12 shows an example of a signal waveform during turn-off in the second embodiment.

[0056] In Figure 11, waveform (A) shows the control signal P from the conversion control device 400. Waveform (C) shows the gate voltage Vgs, where the solid line L120 shows the gate voltage Vgs of semiconductor switching element 101a and the dashed line L121 shows the gate voltage Vgs of semiconductor switching element 101b. Waveform (D) shows the drain current Ids and drain-source voltage Vds, where the solid line L130 shows the drain current Ids of semiconductor switching element 101a and the dashed line L131 shows the drain current Ids of semiconductor switching element 101b. Also, the solid line L140 shows the drain-source voltage Vds of semiconductor switching element 101a and the dashed line L141 shows the drain-source voltage Vds of semiconductor switching element 101b.

[0057] When the control signal P switches from on to off at time t0, the gate voltages Vgs of the semiconductor switching elements 101a and 101b begin to decrease, as shown in waveform (C). As described above, the gate threshold voltage Vth1 of semiconductor switching element 101a is assumed to be lower than the gate threshold voltage Vth2 of semiconductor switching element 101b. Therefore, semiconductor switching element 101b reaches the gate threshold voltage Vth2 before semiconductor switching element 101a, the drain-source voltage Vds of semiconductor switching element 101b begins to rise first, and the drain current Ids begins to decrease first. During the switching period, the drain-source voltage Vds of semiconductor switching element 101b is greater than that of semiconductor switching element 101a, and the drain current Ids is smaller than that of semiconductor switching element 101a. Thus, an imbalance occurs between semiconductor switching elements 101a and 101b.

[0058] Figure 12, on the other hand, shows an example of a signal waveform during turn-off in the second embodiment. Waveform (A) shows the control signal P from the conversion control device 400. Waveform (B) shows the switch control signal CL input to the switching elements SLa and SLb on the gate discharge path. The solid line CLa is the switch control signal of the switching element SLa, and the dashed line CLb is the switch control signal of the switching element SLb. Waveform (C) shows the gate voltage Vgs of each semiconductor switching element 101a and 101b. The solid line L150 shows the gate voltage Vgs of the semiconductor switching element 101a, and the dashed line L121 shows the gate voltage Vgs of the semiconductor switching element 101b. Waveform (D) shows the drain current Ids and the drain-source voltage Vds. The solid line L160 shows the drain current Ids of the semiconductor switching element 101a, and the dashed line L161 shows the drain current Ids of the semiconductor switching element 101b. Furthermore, the solid line L170 represents the drain-source voltage Vds of the semiconductor switching element 101a, and the dashed line L171 represents the drain-source voltage Vds of the semiconductor switching element 101b.

[0059] In the second embodiment, as shown in waveform (B), only the switch control signal CLa among the switch control signals CLa and CLb switches from off to on at time t13, and then switches from on to off at time t14. Meanwhile, the switch control signal CLb remains in the off state. The timing at time t13 is before the gate voltage Vgs of the semiconductor switching elements 101a and 101b reach the gate threshold voltages Vth1 and Vth2. The timing at time t14 is before the gate voltage Vgs of the semiconductor switching elements 101a and 101b reaches its peak.

[0060] By controlling the switching elements SLa and SLb as shown in waveform (B), the switching element SLa is turned on during the period from time t13 to time t14, accelerating the decrease in the gate voltage Vgs of the semiconductor switching element 101a. As a result, the decrease in the drain current Ids and the increase in the drain-source voltage Vds of the semiconductor switching element 101a are accelerated, becoming similar to that of the semiconductor switching element 101b. Consequently, the imbalance in the drain current Ids between the semiconductor switching elements 101a and 101b is corrected. Here, it is preferable that the forward voltage drop of the diode DLa connected in parallel with the switching element SLa be approximately equal to the difference between the gate threshold voltage Vth2 and the gate threshold voltage Vth1 (= Vth2 - Vth1).

[0061] In the control of waveform (B) shown in Figure 12, the imbalance in the drain current Ids of the semiconductor switching elements 101a and 101b was corrected by turning on only the switching element SLa among the switching elements SLa and SLb. However, the imbalance can also be corrected by controlling both switching elements SLa and SLb to be turned on at the same timing. In that case, it is preferable to make the difference between the forward voltage drop of diode DLa and the forward voltage drop of diode DLb approximately the same as the difference between the gate threshold voltage Vth2 and the gate threshold voltage Vth1 (= Vth2 - Vth1).

[0062] Furthermore, when correcting an imbalance, it is preferable to do so in a way that reduces losses. In other words, when correcting an imbalance, there are two options: to align to the side with the smaller loss, or to align to the side with the larger loss. Here, the priority is to correct the imbalance, and if possible, align to the side with the smaller loss.

[0063] In the above explanation, we described the case in which two semiconductor switching elements 101a and 101b are connected in parallel, as shown in Figure 8. However, the present invention can also be applied to a configuration in which three or more semiconductor switching elements 101 are connected in parallel.

[0064] The embodiments and modifications of the present invention described above provide the following effects.

[0065] (1) As shown in Figures 2 to 4, the gate drive device 600 supplies a gate voltage Vgs to a semiconductor switching element (power semiconductor element) 101, and comprises a parallel circuit having diodes DH and DL provided on a current path for charging and discharging the gate capacitance of the semiconductor switching element 101, with the direction of charge and discharge current flow being forward, and switching elements SH and SL connected in parallel to the diodes DH and DL, and control signal generation units (control units) 800H and 800L that control the switching elements SH and SL to the off state at the start of the turn-on or turn-off operation of the semiconductor switching element 101, and control the switching elements SH and SL to the on state after the start of the turn-on or turn-off operation.

[0066] By providing the parallel circuit described above on the charge / discharge path and controlling the switching element as described above, the slew rate of the drain current Ids and drain-source voltage Vds during turn-on or turn-off operation can be increased compared to conventional configurations without a parallel circuit on the charge / discharge path, thereby reducing losses. Furthermore, the circuit can be simplified compared to the configuration described in Patent Document 1.

[0067] (2) In (1) above, as shown in Figure 6, the diode in the parallel circuit includes a plurality of diodes (diode elements) DH1 to DHn connected in series. By changing the number of diodes DH1 to DHn connected in series, the forward voltage drop of the diode, that is, the gate voltage of the semiconductor switching element 101, can be finely adjusted.

[0068] (3) In (1) above, as shown in Figure 7, the diode in the parallel circuit is the body diode of the MOSFET 720. By using this configuration, a simpler configuration can be achieved.

[0069] (4) In (1) above, as shown in Figure 3, the control signal generation unit 800H controls the switching element SH to the ON state at time t1 after the surge timing of the drain current (main current) Ids when the semiconductor switching element 101 is turned on. By controlling in this way, it is possible to reduce losses while avoiding an increase in the surge of the drain current Ids when the element is turned on.

[0070] (5) In (1) above, as shown in Figures 8 to 12, the power semiconductor element includes a semiconductor switching element 101a having a gate threshold voltage Vth1, and a semiconductor switching element 101b connected in parallel to the semiconductor switching element 101a and having a gate threshold voltage Vth2 different from the gate threshold voltage Vth1. The parallel circuit of the diode and the switching element has a first parallel circuit and a second parallel circuit. The first parallel circuit is provided on a current path that charges and discharges the gate capacitance of the semiconductor switching element 101a and has diodes DHa and DLa with the direction of charge / discharge current flow being forward, and switching elements Sha and SLa connected in parallel to the diodes DHa and DLa. The second parallel circuit is provided on a current path that charges and discharges the gate capacitance of the semiconductor switching element 101b and has diodes DHb and DLb with the direction of charge / discharge current flow being forward, and switching elements SHb and SLb connected in parallel to the diodes DHb and DLb. Furthermore, the forward voltage drop of diodes DHb and DLb is different from the forward voltage drop of diodes DHa and DLa.

[0071] By using the above configuration, even if an imbalance occurs in the parallel-connected semiconductor switching elements 101a and 101b, the imbalance can be corrected by controlling the switching elements (Sha, SLa) and (SHb, SLb). Furthermore, by performing the same control as in case (1) above, losses during turn-off or turn-on operation can be reduced.

[0072] (6) In (5) above, as shown in Figures 8 to 12, when the gate threshold voltage Vth2 is greater than the gate threshold voltage Vth1, the forward voltage drop of diode DHb provided on the charging path during turn-on operation is set to be greater than the forward voltage drop of diode DHa, and the forward voltage drop of diode DHb provided on the discharge path during turn-off operation is set to be less than the forward voltage drop of diode DHa. By setting in this way, the imbalance of semiconductor switching elements 101a and 101b during turn-on and turn-off operation can be corrected.

[0073] (7) In (5) above, as shown in Figures 8, 10, 12, etc., the control signal generation units 800H and 800L control only one of the switching elements Sha, SLa and SHb, SLb to the ON state during the turn-on operation or turn-off operation of the semiconductor switching elements 101a and 101b.

[0074] For example, in the turn-on operation shown in Figure 10, the switching element SHb among the switching elements SHa and SHb is controlled to the ON state, and in the turn-off operation shown in Figure 12, the switching element SLa among the switching elements SLa and SLb is controlled to the ON state. By controlling in this way, the imbalance of the semiconductor switching elements 101a and 101b is corrected.

[0075] The embodiments and various modifications described above are merely examples, and the present invention is not limited to these, as long as the features of the invention are not impaired. Other embodiments conceivable within the scope of the technical idea of ​​the present invention are also included within the scope of the present invention.

[0076] 100...Energy storage device, 101, 101a, 110b...Semiconductor switching element, 102...Freewheeling diode, 200...Power converter, 300...Electric motor, 400...Conversion control device, 600...Gate drive device, 700...Driver circuit, 710...Gate driver IC, 720...MOSFET, 800H, 800L...Control signal generation unit, BD...Body diode, CH, CHa, CHb, CL, CLa, CLb...Switch control signal, DH, DHa, DHb, DL, DLa, DLb...Diode, P...Control signal, RH, RHa, RHb, RL, RLa, RLb...Resistor, SH, Sha, SHb, SL, SLa, SLb...Switching element, Vth, Vth1, Vth2...Gate threshold voltage

Claims

1. A gate drive device for supplying a gate voltage to a power semiconductor element, comprising: a parallel circuit provided on a current path for charging and discharging the gate capacitance of the power semiconductor element, having a diode whose direction of charge and discharge current is forward and a switching element connected in parallel to the diode; and a control unit that controls the switching element to an off state at the start of the turn-on or turn-off operation of the power semiconductor element, and controls the switching element to an on state after the start of the turn-on or turn-off operation.

2. A gate drive device according to claim 1, wherein the diode includes a plurality of diode elements connected in series.

3. A gate drive device according to claim 1, wherein the diode is a body diode of a MOSFET (Metal Oxide Semiconductor Field Effect Transistor).

4. A gate drive device according to claim 1, wherein the control unit controls the switching element to an ON state after the surge timing of the main current during the turn-on operation of the power semiconductor element.

5. A gate drive device according to claim 1, wherein the power semiconductor element includes a first power semiconductor element having a first gate threshold voltage and a second power semiconductor element connected in parallel to the first power semiconductor element and having a second gate threshold voltage different from the first gate threshold voltage, the parallel circuit includes a first parallel circuit provided on a current path for charging and discharging the gate capacitance of the first power semiconductor element and having a first diode with the direction of charge / discharge current flow in the forward direction and a first switching element connected in parallel to the first diode, and a second parallel circuit provided on a current path for charging and discharging the gate capacitance of the second power semiconductor element and having a second diode with the direction of charge / discharge current flow in the forward direction and a second switching element connected in parallel to the second diode, the forward voltage drop of the second diode and the forward voltage drop of the first diode are different.

6. A gate drive device according to claim 5, wherein when the second gate threshold voltage is greater than the first gate threshold voltage, the forward voltage drop of the second diode provided on the charging path is set to be greater than the forward voltage drop of the first diode, and the forward voltage drop of the second diode provided on the discharge path is set to be less than the forward voltage drop of the first diode.

7. A gate drive device according to claim 5, wherein the control unit controls only one of the first switching element and the second switching element to be in the ON state during the turn-on operation or turn-off operation of the first power semiconductor element and the second power semiconductor element.

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