Semiconductor storage device and multiply–accumulate operation device

Abstract

Each of n memory cells (150 etc.) provided in a semiconductor storage device (130a) has: a first resistance element (61p) and a first switch element (71p), which is controlled by a first word line (WL), connected in series between a bit line (BL) and a first source line (SL); a second resistance element (62n) and a second switch element (72n), which is controlled by the first word line (WL), connected in series between the bit line (BL) and a second source line (SLB); a third switch element (73p), which is controlled by a second word line (WLB), connected in series with the second resistance element (62n) between the bit line (BL) and the first source line (SL); and a fourth switch element (74n), which is controlled by the second word line (WLB), connected in series with the first resistance element (61p) between the bit line (BL) and the second source line (SLB).

Description

Semiconductor memory device and multiply-accumulate unit

[0001] This disclosure relates to a semiconductor memory device and a multiply-accumulate device used in multiply-accumulate operations.

[0002] As one method for efficiently performing the sum-of-products operation, a major operation in AI, Compute in Memory (CiM) has been proposed, which, based on Kirchhoff's laws, performs the sum of the products of the input and the current corresponding to the weight coefficient (in this case, the resistance value) using a memory array and its peripheral circuitry (see, for example, Patent Documents 1 and 2).

[0003] Patent Document 1 discloses a configuration for realizing highly efficient, small-area AI hardware using CiM technology, in which the calculation result is extracted based on the difference between the current representing the sum-of-accumulate operation and an additional bias current.

[0004] Furthermore, Patent Document 2 discloses a configuration that extracts calculation results based on the difference between the current representing the sum-of-accumulate operation and an additional bias current, in order to provide hardware that realizes a small-area artificial neural network model using CiM technology.

[0005] International Publication No. 2019 / 182730, Japanese Patent Publication No. 2017-174425

[0006] However, both the techniques described in Patent Documents 1 and 2 involve applying a bias current, which has the problem of increasing power consumption. Furthermore, there is the problem that the bias current needs to be increased in accordance with the increase in the number of simultaneous readouts (i.e., the number of products (parallel operations) subject to the sum-of-products operation). In other words, there is also the problem that the dynamic range narrows as the number of simultaneous readouts increases, limiting the number of simultaneous readouts. Here, dynamic range is the ratio of the maximum and minimum values ​​of the readable sum-of-products.

[0007] Therefore, the purpose of this disclosure is to provide a semiconductor memory device and a multiply-accumulate device used for multiply-accumulate operations that can solve the problems of dynamic range and power consumption that limit the upper limit of the number of parallel operations when performing multiply-accumulate operations in the prior art.

[0008] To achieve the above objective, a semiconductor memory device according to one embodiment of the present disclosure is a semiconductor memory device used for a sum-of-accumulate operation in which n products of corresponding input values ​​and weight coefficients are added together for n (≧2) input values ​​and n weight coefficients, comprising: a bit line, a first source line, and a second source line; a constant current source connected to the bit line; n sets of word lines, each consisting of a first word line and a second word line that transmit signals representing the input values; and an array of n memory cells provided corresponding to each set of the n sets of word lines, which, according to the signal state of the first word line and the second word line of the set, causes current to flow through the bit line to flow through the first source line and the second source line, wherein the n memory cells Each includes a first resistor element having a first resistance value corresponding to the weight coefficient and a first switch element controlled by the first word line, connected in series between the bit line and the first source line; a second resistor element having a second resistance value and a second switch element controlled by the first word line, connected in series between the bit line and the second source line; a third switch element connected in series with the second resistor element and controlled by the second word line, connected between the bit line and the first source line; and a fourth switch element connected in series with the first resistor element and controlled by the second word line, connected between the bit line and the second source line.

[0009] To achieve the above objective, a sum-of-accumulate device according to one embodiment of the present disclosure comprises a semiconductor memory device and a calculation unit that generates the result of the sum-of-accumulate operation based on the difference between a first current, which is the total current flowing through the first source line by the n memory cells, and a second current, which is the total current flowing through the second source line by the n memory cells, or the difference in the time integral amounts of the first current and the second current, respectively.

[0010] This disclosure provides a semiconductor memory device and a multiply-accumulate (MLP) unit that can solve the problems of dynamic range and power consumption that limit the upper limit of the number of parallel operations when performing MLP operations. In other words, a semiconductor memory device and a multiply-accumulate unit used for MLP operations can be realized that can increase the number of parallel operations when performing MLP operations compared to conventional methods, without narrowing the dynamic range or increasing power consumption.

[0011] Figure 1 illustrates the essential problems in a conventional current-readout mode CiM configuration multiply-accumulate unit. Figure 2 is a circuit diagram showing the configuration of a multiply-accumulate unit according to a reference example. Figure 3 is a timing chart showing an example of operation of a multiply-accumulate unit according to a reference example. Figure 4 illustrates the power consumption and calculation efficiency of a multiply-accumulate unit according to a reference example when calculating the sum of 16 products. Figure 5 illustrates the power consumption and calculation efficiency of a multiply-accumulate unit according to a reference example when calculating the sum of 2048 products. Figure 6 illustrates the power consumption and calculation efficiency of a multiply-accumulate unit according to a reference example when calculating the sum of 8192 products. Figure 7 illustrates the power consumption and calculation efficiency of a multiply-accumulate unit according to conventional technology without a constant current source when calculating the sum of 16 products. Figure 8 illustrates the power consumption and calculation efficiency of a multiply-accumulate unit according to conventional technology when calculating the sum of 2048 products. Figure 9 is a circuit diagram showing the configuration of a semiconductor memory device according to an embodiment. Figure 10A is a diagram illustrating the operation of a semiconductor memory device according to an embodiment (operation when the first word line is High). Figure 10B is a diagram illustrating the operation of a semiconductor memory device according to an embodiment (operation when the second word line is High). Figure 11 is a diagram showing a simulation circuit for evaluating the difference between the positive output current and the negative output current when the number n of memory cells in the semiconductor memory device according to an embodiment is changed. Figure 12 is a diagram showing the simulation results showing the fluctuations of the potential of the first capacitance and the potential of the second capacitance under the conditions shown in Figure 11. Figure 13 is a diagram showing an example of a simulation circuit when there is a resistance matching error in a multiply-accumulate unit according to a reference example. Figure 14 is a diagram showing the simulation results showing the difference between a multiply-accumulate unit according to a reference example when there is no resistance matching error and when there is a resistance matching error as shown in Figure 13. Figure 15 is a circuit diagram showing the configuration of a multiply-accumulate unit including a semiconductor memory device according to an embodiment. Figure 16 is a diagram showing a neural network model corresponding to Figure 15. Figure 17A is a diagram illustrating a modified example of the calculation unit included in the sum-of-accumulate arithmetic device according to the embodiment shown in Figure 15.Figure 17B is a timing chart showing an example of the operation of the calculation unit according to the modified example shown in Figure 17A. Figure 18 is a diagram illustrating the equivalent circuit of a semiconductor memory device according to the embodiment. Figure 19 is a diagram illustrating a modified example of a memory cell provided in the semiconductor memory device according to the embodiment.

[0012] (Challenges in the Conventional Technology) First, we will explain the challenges in the conventional technology, namely, the challenges of the dynamic range narrowing and power consumption increasing as the number of simultaneous readouts increases, and the challenge of limiting the number of simultaneous readouts. This challenge is an essential issue in the conventional current readout mode CiM configuration.

[0013] Figure 1 illustrates the essential problems in a conventional current-read mode CiM configuration multiply-accumulate unit 10. More specifically, Figure 1(a) shows an example of an array of memory cells 12 composed of one transistor-one resistor (i.e., 1T-1R) and peripheral circuits 14 for reading the multiply-accumulate result. Figure 1(b) shows an example of the change in the voltage Vx of the readout capacitor 16 in Figure 1(a) during pre-charging and reading. Figure 1(c) shows the equivalent circuit of the column during reading.

[0014] As shown in Figure 1(a), in a conventional current-read mode CiM configuration multiply-accumulate unit 10, multiple 1T-1R memory cells 12 are connected in parallel between the bit line 20 and the source line 22 for each column. In each column, the capacitor 16 is precharged via the transistor 11a, and then, in response to the signal on the word line 24 indicating the input value, the transistor 12b of the corresponding memory cell 12 is turned on / off, thereby allowing / cutting current to flow through the resistor element 12a that stores a resistance value corresponding to the weight coefficient (more precisely, the reciprocal of the weight coefficient). As a result, a current equivalent to the sum of the products of the input value and the weight coefficient is discharged from the precharged capacitor 16 to ground via the bit line 20, the on memory cell 12, the source line 22, and the transistor 11b (see Figure 1(c)).

[0015] Therefore, when the number of word lines 24 to be read is increased (i.e., when the number of products (parallel operations) subject to the sum-of-accumulate operation is increased), the value of the parallel resistance decreases accordingly (see Figure 1(c)), and as shown in Figure 1(b), the voltage Vx of the pre-charged capacitor 16 corresponding to the result of the sum-of-accumulate operation shows a rapid change.

[0016] As a result, for example, when reading hundreds of rows simultaneously, it is necessary to implement measures to increase the response speed in order to keep up with rapid changes, or to apply a bias current corresponding to the number of rows being read in order to slow down the changes (see Patent Documents 1 and 2), or to perform repeated readings in time division multiplexing. These measures have the problem of increasing power consumption and processing time.

[0017] (Reference example of a multiply-accumulate arithmetic device) As a result of diligent study, the present inventors have created a multiply-accumulate arithmetic device according to the reference example, that is, a multiply-accumulate arithmetic device with a CiM configuration employing a current-limited differential readout method. More specifically, the multiply-accumulate arithmetic device is a multiply-accumulate arithmetic device that performs a multiply-accumulate operation on n (≧2) input values ​​and n weight coefficients, by adding n products of the corresponding input values ​​and weight coefficients, and comprises a common connection point, a first bit line, a second bit line and a source line, a first current mirror circuit connected between the common connection point and one end of the first bit line, which outputs a first current obtained by multiplying the current flowing between the common connection point and one end of the first bit line by a predetermined multiplier, and a connection between the common connection point and one end of the second bit line The circuit includes a second current mirror circuit that outputs a second current obtained by multiplying the current flowing between the common connection point and one end of the second bit line by a predetermined multiplier, n sets of word lines, each consisting of a first word line and a second word line that transmit a signal representing the input value, and a collection of memory cells provided corresponding to each set of the n sets of word lines, which, according to the signal state of the first word line and the second word line of that set, cause the current flowing through the first bit line to flow to the source line, and the current flowing through the second bit line to flow to the source line. The memory cell comprises an array, a constant current source that supplies current to the common connection point or the source line so as to maintain a constant sum of the current flowing from the common connection point through the first current mirror circuit, the first bit line, and the source line, and the current flowing from the common connection point through the second current mirror circuit, the second bit line, and the source line, and an arithmetic unit that generates the result of the sum-of-products operation based on the difference between the first current and the second current, or the difference in the time integral amounts of the first current and the second current, respectively, wherein the memory cell comprises a first resistor element having a first resistance value corresponding to the weight coefficient (strictly speaking, the reciprocal of the weight coefficient) and a first switch element controlled by the first word line, connected in series between the first bit line and the source line,It comprises a third resistor element having the second resistance value and a third switch element controlled by the second word line, connected in series between the second bit line and the source line, and a fourth resistor element having the first resistance value and a fourth switch element controlled by the second word line.

[0018] This enables the realization of a multiply-accumulate (MLI) unit that can solve the problems of dynamic range and power consumption that limit the upper limit of the number of parallel operations when performing MILK operations in conventional technology. In other words, it is possible to realize an MILK unit that can increase the number of parallel operations when performing MILK operations compared to conventional methods without narrowing the dynamic range or increasing power consumption.

[0019] Figure 2 is a circuit diagram showing the configuration of a sum-of-accumulate unit 30 according to a reference example. In this figure, the main components constituting the sum-of-accumulate unit 30 are shown, and peripheral circuits that are not shown will be described later.

[0020] The multiply-accumulate unit 30 is a multiply-accumulate unit with a CiM configuration employing a current-limited differential readout method, and is a circuit that performs a multiply-accumulate operation by adding n products of corresponding input values ​​and weight coefficients for n (≧2) input values ​​and n weight coefficients, and is connected to a common connection point 34, a first bit line 31, a second bit line 32 and a source line 33, and between the common connection point 34 and one end of the first bit line 31, and is a predetermined multiplier for the current flowing between the common connection point 34 and one end of the first bit line 31. A first current mirror circuit 41p that outputs a first current Ip obtained by multiplying by a rate, a second current mirror circuit 41n connected between a common connection point 34 and one end of a second bit line 32 that outputs a second current In obtained by multiplying the current flowing between the common connection point 34 and one end of the second bit line 32 by a predetermined multiplier, n sets of word lines WL, each consisting of a first word line WL and a second word line WLB that transmit a signal representing the input value, and each set of n sets of word lines WL An array 80 is provided in correspondence with the first word line WL and the second word line WLB of the pair, and in accordance with the signal state of the first word line WL and the second word line WLB of the pair, the array 80 is a collection of memory cells (hereinafter also called "nodes") (0th memory cell 50, 1st memory cell 51, 2nd memory cell 52) that cause current flowing through the 1st bit line 31 to flow to the source line 33, and current flowing through the 2nd bit line 32 to flow to the source line 33, and from the common connection point 34, the first current mirror circuit 41p, the 1st bit line 31, and the array 80 The system includes a constant current source 40 that supplies current to the common connection point 34 or the source line 33 so as to maintain a constant sum between the current flowing to the source line 33 via the common connection point 34 and the current flowing to the source line 33 from the common connection point 34 via the second current mirror circuit 41n, the second bit line 32, and the array 80, and an arithmetic unit 44 that generates the result of a sum-of-products operation based on the difference between the first current Ip and the second current In (Ip - In), or the difference in the time integral amounts of the first current Ip and the second current In, respectively.

[0021] Each of the 0th to 2nd memory cells 50 to 52 consists of four 1T-1R memory cells and is an multiplication unit that performs one product calculation. More specifically, it comprises a first resistor element 61p having a first resistance value corresponding to a weight coefficient (more precisely, the reciprocal of the weight coefficient) connected in series between the first bit line 31 and the source line 33, and a first switch element 71p controlled by the first word line WL, and a second resistor having a second resistance value connected in series between the second bit line 32 and the source line 33. The device includes an element 62n, a second switch element 72n controlled by the first word line WL, a third resistor 63p having a second resistance value and a third switch element 73p controlled by the second word line WLB, connected in series between the first bit line 31 and the source line 33, and a fourth resistor 64n having a first resistance value and a fourth switch element 74n controlled by the second word line WLB, connected in series between the second bit line 32 and the source line 33.

[0022] The first switch element 71p, the second switch element 72n, the third switch element 73p, and the fourth switch element 74n are composed of, for example, nMOSFETs.

[0023] Here, the calculation unit 44 calculates the difference between the first current Ip and the second current In (Ip - In), or the difference in the time integral amounts of the first current Ip and the second current In. In this reference example, more specifically, it has a first capacitor 42p charged by the first current Ip and a second capacitor 42n charged by the second current In, and is a circuit that generates the result of a sum-of-products operation based on the difference between the potential at the first capacitor 42p and the potential at the second capacitor 42n. However, the calculation unit 44 is not limited to a configuration using such two capacitors. Details of the calculation unit 44 and its modified forms will be described later.

[0024] Also, as described above, both the first resistor element 61p and the fourth resistor element 64n have a first resistance value that corresponds to the weight coefficient (strictly speaking, the reciprocal of the weight coefficient) assigned to the switch group to which they belong. On the other hand, as described above, both the second resistor element 62n and the third resistor element 63p have a second resistance value. Typically, there is a relationship of second resistance value ≥ first resistance value between these first resistance value and second resistance value. Therefore, the current I Ｌ，ｉ (i = 0, 1, 2) flowing through the first resistor element 61p and the fourth resistor element 64n is the current I Ｈ，ｉ (i = 0, 1, 2) flowing through the second resistor element 62n and the third resistor element 63p or less.

[0025] However, the relationship of second resistance value ≥ first resistance value is not limited, and the reverse relationship may hold. Also, the first resistor element 61p, the second resistor element 62n, the third resistor element 63p, and the fourth resistor element 64n may be resistor elements having variable resistance values (that is, non-volatile resistance change elements), or may be resistor elements having fixed resistance values. When these resistor elements are resistance change elements, the product-sum operation device 30 is also used as a learning AI machine learning model. On the other hand, when these resistor elements are resistor elements having fixed resistance values, the product-sum operation device 30 can be used as an inference (that is, learned) AI machine learning model.

[0026] Note that, in FIG. 2, among the components of the product-sum operation device 30, the components arranged on the left side in FIG. 2 (the first current mirror circuit 41p, the first capacitor 42p, the first resistance elements 61p of the 0th to 2nd memory cells 50 to 52, the first switch element 71p, the third resistance element 63p, and the third switch element 73p) are elements that determine the first current Ip in the calculation of the difference (Ip - In) in the arithmetic unit 44, so they are denoted as "POSI." (also called "positive side"). On the other hand, the components arranged on the right side in FIG. 2 (the second current mirror circuit 41n, the second capacitor 42n, the second resistance elements 62n of the 0th to 2nd memory cells 50 to 52, the second switch element 72n, the fourth resistance element 64n, and the fourth switch element 74n) are elements that determine the second current In in the calculation of the difference (Ip - In) in the arithmetic unit 44, so they are denoted as "NEG." (also called "negative side").

[0027] Also, in this reference example, the array 80 is composed of three memory cells (the 0th to 2nd memory cells 50 to 52), but it is not limited to this number. For example, it may be composed of four or more memory cells.

[0028] Also, in this reference example, the constant current source 40 is connected to a voltage source with a constant power supply voltage Vcc and is composed of a pMOS transistor that outputs a constant current according to the input signal Vi, but it is not limited to such a circuit. For example, it may be composed of a bipolar transistor inserted between the source line 33 and the ground and outputting a constant current.

[0029] Also, in this reference example, the predetermined magnification (that is, the ratio of the output current to the input current) in the first current mirror circuit 41p and the second current mirror circuit 41n is 1, but it is not limited to this and may be other values such as 2.

[0030] Also, the product-sum operation device 30 may include a word line driving circuit that outputs a signal to the word line WL.

[0031] The feature of the product-sum operation device 30 shown in this figure is that it realizes a current-limited differential reading method, and specifically, it is as follows.

[0032] (1) The constant current source 40 ensures that the sum of the current flowing through the first bit line 31 and the current flowing through the second bit line 32 remains constant.

[0033] (2) The first capacitor 42p is charged by a current copied from the current flowing through the first bit line 31, and the second capacitor 42n is charged by a current copied from the current flowing through the second bit line 32. The difference between the voltage of the first capacitor 42p and the voltage of the second capacitor 42n is output as the sum-of-products calculation result.

[0034] (3) In each of the 0th to 2nd memory cells 50 to 52, the resistive elements belonging to different rows and columns (the first resistive element 61p and the fourth resistive element 64n, the second resistive element 62n and the third resistive element 63p) have the same resistance value (that is, the resistive elements located diagonally opposite each other have the same resistance value).

[0035] Figure 3 is a timing chart showing an example of the operation of the sum-of-accumulate unit 30 according to the reference example shown in Figure 2. Here, examples of signals for the first word lines WL<0> to WL<2> and the second word lines WLB<0> to WLB<2> of the 0th to 2nd memory cells 50 to 52 are shown.

[0036] As shown in this figure, for each of the three sets of word lines WL, the signal transmitted by the first word line WL is a first pulse-width modulated signal having a pulse width corresponding to the input value, and the signal transmitted by the second word line WLB is a second pulse-width modulated signal representing the negative logic of the first pulse-width modulated signal.

[0037] In the example shown in this figure, with respect to the period Tmax, the first word line WL<0> is a pulse-width modulated (PWM) signal with approximately 50% duty cycle, and the second word line WLB<0> is a pulse-width modulated (PWM) signal representing negative logic, which is the inverse of the first word line WL<0>. Furthermore, the first word line WL<1> is a pulse-width modulated (PWM) signal with approximately 75% duty cycle, and the second word line WLB<1> is a pulse-width modulated (PWM) signal representing negative logic, which is the inverse of the first word line WL<1>. In addition, the first word line WL<2> is a pulse-width modulated (PWM) signal with approximately 85% duty cycle, and the second word line WLB<2> is a pulse-width modulated (PWM) signal representing negative logic, which is the inverse of the first word line WL<2>.

[0038] The pulse widths indicated by the first word lines WL<0> to WL<2>, X0 to X2, correspond to negative input values ​​when less than Tmax / 2, to zero input values ​​when equal to Tmax / 2, and to positive input values ​​when greater than Tmax / 2.

[0039] The principle of the sum-of-products operation performed by the sum-of-products unit 30 on such input values ​​is as follows:

[0040] The voltage Vp of the positive first capacitance 42p is expressed by the following equation 1.

[0041]

[0042] Here, I Ｌ，ｉ This is the current flowing through the low-resistance elements of the i-th memory cell (i.e., the first resistive element 61p and the fourth resistive element 64n), as shown in Figure 2. Ｈ，ｉ This is the current flowing through the high-resistance elements of the i-th memory cell (i.e., the second resistive element 62n and the third resistive element 63p), as shown in Figure 2. ｉ As shown in Figure 3, is the pulse width indicated by the first word line WL of the i-th memory cell. Tmax is the maximum value (i.e., period) of the pulse width modulated signal indicated by the first word line WL, as shown in Figure 3. C is the capacitance value of the first capacitance 42p, and is also the capacitance value of the second capacitance 42n.

[0043] On the other hand, the voltage Vn of the negative second capacitance 42n is expressed by the following equation 2.

[0044]

[0045] Therefore, the difference between the voltage Vp and the voltage Vn calculated by the calculation unit 44 is expressed in the following equation 3 by subtracting the left and right sides of equation 2 from the left and right sides of equation 1, respectively.

[0046]

[0047] Here, in the right-hand side of equation 3 above, (2X ｉ -Tmax) corresponds to the pulse width (i.e., input value) indicated by the first word line WL of the i-th memory cell, and (I) on the right side of equation 3 above.Ｌ，ｉ -I Ｈ，ｉ corresponds to the current (i.e., weight coefficient) flowing from the first bit line 31 and the second bit line 32 to the source line 33 in the i-th memory cell. Therefore, the right side of the above formula 3 is in the form of a product-sum operation that calculates the sum of the products of the input value and the weight coefficient.

[0048] Also, as can be seen from (2X ｉ -Tmax) on the right side of the above formula 3, when the relationship X ｉ < Tmax / 2 holds, the input value corresponds to a negative value. Furthermore, as can be seen from (I Ｌ，ｉ -I Ｈ，ｉ ), when I Ｌ，ｉ < I Ｈ，ｉ is satisfied, the weight coefficient corresponds to a negative value. That is, the product-sum operation device 30 according to this reference example can calculate not only the product-sum operation of a positive input value and a positive weight coefficient but also the sum of the products of an input value that can take a negative value and a weight coefficient that can take a negative value.

[0049] As described above, according to the product-sum operation device 30 according to the reference example, the current output from the constant current source 40 connected to a constant power supply voltage Vcc flows to the ground through the array 80 and the source line 33, and the product-sum operation is executed. Therefore, except for the power for driving the word line WL, the power required for the product-sum operation becomes constant regardless of the number of word lines WL. As a result, the problems of the dynamic range and power consumption that limit the upper limit of the parallel operation count when performing the product-sum operation are solved.

[0050] Next, the power consumption and operation efficiency of the product-sum operation device 30 according to the reference example will be described in comparison with the prior art.

[0051] FIG. 4 is a diagram for explaining the power consumption and operation efficiency of the product-sum operation device 30 when the product-sum operation device 30 according to the reference example calculates the sum of 16 products (the number of products M = 16, that is, the array 80 is composed of 16 memory cells). Here, the results confirmed by simulation calculations are shown.

[0052] More specifically, Figure 4(a) shows the voltage and current conditions for calculating power consumption and computational efficiency. Specifically, as shown in Figure 4(a), the power supply voltage Vcc is set to 0.8V, the output current of the constant current source 40 is set to 100μA, the capacitances of the first capacitor 42p and the second capacitor 42n are both set to 20pF, the resistance values ​​of the first resistor element 61p and the fourth resistor element 64n are set to 1kΩ, and the resistance values ​​of the second resistor element 62n and the third resistor element 63p are set to 1GΩ.

[0053] Figure 4(b) shows examples of input waveforms representing the input values ​​transmitted by the first word line WL<0:7> (i.e., WL<0> to WL<7>), input waveforms representing the input values ​​transmitted by the first word line WL<8:15> (i.e., WL<8> to WL<15>), changes in the voltages Vx,p of the first capacitor 42p, and changes in the voltages Vx,n of the second capacitor 42n, under the conditions shown in Figure 4(a). Here, waveform examples are shown for time from 0 to 100 ns (horizontal axis). The voltage (V) on the vertical axis is the voltage scale for voltages Vx,p and Vx,n.

[0054] When the input values ​​of the input waveform shown in Figure 4(b) were input, as shown in Figure 4(b), the voltage Vx,n at 100ns became 172mV, and the voltage Vx,p at 100ns became 74.0mV, resulting in a differential voltage of -98.0mV.

[0055] In this example, the power consumption (energy) of the multiply-accumulate unit 30 is 100 μA × 0.8 V × 100 ns = 8 pWs, and the calculation efficiency is 2 (operations) × 16 (number of multiply operations) / 8 pWs = 4 TOPS (Tera Operation Per Second) / W.

[0056] Figure 5 illustrates the power consumption and computational efficiency of the sum-of-accumulate (SUM) unit 30 in the reference example when it calculates the sum of 2048 products (number of products M = 2048, i.e., the array 80 is composed of 2048 memory cells). Here, four waveforms corresponding to Figure 4(b) in the case where M = 2048 are shown. Note that the voltage, current, and other conditions are the same as in Figure 4(a).

[0057] As shown in this figure, in the case of M = 2048, the input waveforms showing the input values ​​transmitted by the first word line WL<0:1023> (i.e., WL<0> to WL<1023>) and the input waveforms showing the input values ​​transmitted by the first word line WL<1024:2047> (i.e., WL<1024> to WL<2047>) are the same as in the case of M = 16 (Figure 4(b)). However, the changes in the voltage Vx,p of the first capacitor 42p and the changes in the voltage Vx,n of the second capacitor 42n obtained in the simulation yielded the same results as in the case of M = 16 (Figure 4(b)). In other words, as shown in this figure, the voltage Vx,n at 100ns was 172mV, and the voltage Vx,p at 100ns was 74.0mV, resulting in a differential voltage of -98.0mV.

[0058] In the case where M = 2048, the power consumption (energy) of the multiply-accumulate unit 30 is 100 μA × 0.8 V × 100 ns = 8 pWs, and the calculation efficiency is 2 (calculations) × 2048 (number of multiply-accumulate operations) / 8 pWs = 512 TOPS / W. In other words, compared to the case where M = 16, the power consumption is the same, but the calculation efficiency is improved.

[0059] Figure 6 illustrates the power consumption and computational efficiency of the sum-of-accumulate (SUM) arithmetic unit 30 in the reference example when it calculates the sum of 8192 products (number of products M = 8192, i.e., the array 80 is composed of 8192 memory cells). Here, four waveforms corresponding to Figure 4(b) in the case where M = 8192 are shown. Note that the voltage, current, and other conditions are the same as in Figure 4(a).

[0060] As shown in this figure, in the case of M = 8192, the input waveforms showing the input values ​​transmitted by the first word line WL<0:4095> (i.e., WL<0> to WL<4095>) and the input waveforms showing the input values ​​transmitted by the first word line WL<4096:8191> (i.e., WL<4096> to WL<8191>) are the same as in the case of M = 16 (Figure 4(b)). However, the changes in the voltage Vx,p of the first capacitor 42p and the changes in the voltage Vx,n of the second capacitor 42n obtained in the simulation were almost the same as in the case of M = 16 (Figure 4(b)). In other words, as shown in this figure, the voltage Vx,n at 100ns was 169mV, and the voltage Vx,p at 100ns was 76.7mV, resulting in a differential voltage of -92.3mV.

[0061] In the case where M = 8192, the power consumption (energy) of the multiply-accumulate unit 30 is 100 μA × 0.8 V × 100 ns = 8 pWs, and the calculation efficiency is 2 (calculations) × 8192 (number of multiply-accumulate operations) / 8 pWs = 2048 TOPS / W. In other words, compared to the case where M = 8, the power consumption is the same, but the calculation efficiency is further improved.

[0062] As can be seen from Figures 4 to 6, in the example sum-of-accumulate unit 30, the operating range (i.e., power consumption) hardly changes even when the number of driven word lines is increased, while the proportional relationship between the size of the array 80 and the computational efficiency can be maintained.

[0063] Figure 7 illustrates the power consumption and computational efficiency of a conventional multiply-accumulate (SPL) device 10a without a constant current source when it calculates the sum of 16 products (number of products M = 16, i.e., the array consists of 16 memory cells). The results shown here are those confirmed by simulation calculations.

[0064] More specifically, Figure 7(a) shows the conditions for voltage, current, etc., used to calculate power consumption and computational efficiency. The power supply voltage Vcc, the capacitances of the first capacitor 42p and the second capacitor 42n, and the resistance values ​​of each resistive element are the same as in Figure 4(a).

[0065] Figure 7(b) shows examples of input waveforms indicating the input value transmitted by the first word line WL<0:7>, the input waveform indicating the input value transmitted by the first word line WL<8:15>, the change in voltage Vx,p of the first capacitor 42p, and the change in voltage Vx,n of the second capacitor 42n, under the conditions shown in Figure 7(a). Here, waveform examples are shown for time from 0 to 100 ns (horizontal axis). The voltage (V) on the vertical axis is the voltage scale for voltage Vx,p and voltage Vx,n.

[0066] When the input values ​​of the input waveform shown in Figure 7(b) were input, as shown in Figure 7(b), the voltage Vx,n at 100ns was 19.9mV, and the voltage Vx,p at 100ns was 0.00mV, resulting in a differential voltage of -19.9mV.

[0067] Focusing on the voltages Vx and p, we can see that after approximately 10 ns out of 100 ns, the voltage reaches a point where it changes linearly (i.e., 0.4 (= 0.8 - 0.4) V).

[0068] Figure 8 illustrates the power consumption and computational efficiency of a conventional multiply-accumulate (MLP) unit 10a when it calculates the sum of 2048 products (number of products M = 2048, i.e., the array 80 is composed of 2048 memory cells). Here, four waveforms corresponding to Figure 4(b) when M = 2048 are shown. Note that the voltage and other conditions are the same as in Figure 7(a).

[0069] In the case of M = 2048, the voltages Vx,n at 100ns are 0.00mV, and the voltages Vx,p at 100ns are 0.00mV, resulting in a differential voltage of 0.00mV. Both voltages Vx,p and Vx,n exhibit waveforms that drop to 0V immediately, indicating that there is no time domain in which the voltage changes linearly.

[0070] As can be seen from Figures 7 and 8, in the conventional multiply-accumulate unit 10a, unlike the reference example, when the number of driven word lines is increased, the read waveform shows a rapid change, dropping sharply to zero. Therefore, as explained using Figure 1, in the conventional multiply-accumulate unit 10, for example, when reading hundreds of rows simultaneously, it is necessary to take measures to increase the response speed, or to add a bias current corresponding to the number of rows to be read in order to keep up with the rapid changes (see Patent Documents 1 and 2), or to perform repeated reading in time division multiplexing. These measures have the problem of increasing power consumption and processing time.

[0071] As can be seen from Figures 4 to 8 above, the sum-of-accumulate arithmetic device 30 in the reference example is a device that can solve the problems of dynamic range and power consumption that limit the upper limit of the number of parallel operations when performing sum-of-accumulate operations in the conventional technology.

[0072] (Problems with the multiply-accumulate arithmetic device in the reference example) However, in the multiply-accumulate arithmetic device 30 in the reference example, four resistive elements 61p, 62n, 63p, and 64n are required for each of the memory cells 50 to 52, and the resistance values ​​of two resistive elements located diagonally opposite each other (the resistance values ​​of the first resistive element 61p and the fourth resistive element 64n, and the resistance values ​​of the second resistive element 62n and the third resistive element 63p) must be the same.

[0073] Therefore, after diligent study, the present inventors have created an improved multiply-accumulate arithmetic device (multiply-accumulate)

[0074] One form of the improved semiconductor memory device is a semiconductor memory device used for a sum-of-accumulate operation in which n products of corresponding input values ​​and weight coefficients are added together for n (≧2) input values ​​and n weight coefficients, comprising: a bit line, a first source line, and a second source line; a constant current source connected to the bit line; n sets of word lines, each consisting of a first word line and a second word line that transmit signals representing the input values; and an array of n memory cells provided corresponding to each set of the n sets of word lines, which, according to the signal state of the first word line and the second word line of the set, causes current to flow through the bit line to flow through the first source line and the second source line, wherein each of the n memory cells is The system includes a first resistor element having a first resistance value corresponding to the weight coefficient, connected in series between the bit line and the first source line, and a first switch element controlled by the first word line; a second resistor element having a second resistance value, connected in series between the bit line and the second source line, and a second switch element controlled by the first word line; a third switch element connected in series with the second resistor element and controlled by the second word line between the bit line and the first source line; and a fourth switch element connected in series with the first resistor element and controlled by the second word line between the bit line and the second source line.

[0075] Furthermore, one form of the improved sum-of-accumulate device comprises the semiconductor memory device and an arithmetic unit that generates the result of the sum-of-accumulate operation based on the difference between a first current, which is the total current flowing through the first source line by the n memory cells, and a second current, which is the total current flowing through the second source line by the n memory cells, or the difference in the time integral amounts of the first current and the second current, respectively.

[0076] This solves the problems of the multiply-accumulate device in the reference example, and realizes a semiconductor memory device and multiply-accumulate device used for multiply-accumulate operations that also solve the problems of the prior art.

[0077] (Embodiments) Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. Note that each embodiment described below is a specific example of the present disclosure. The numerical values, input values, weighting coefficients, signal waveforms, components, arrangement and connection configurations of components, signal processing order, signal timing, etc. shown in the following embodiments are examples and are not intended to limit the present disclosure. In addition, each figure is not necessarily a strict illustration. In each figure, substantially identical components are denoted by the same reference numerals, and redundant explanations are omitted or simplified. Furthermore, "connection" means an electrical connection and may include not only cases where two circuit elements are directly connected, but also cases where two circuit elements are indirectly connected with another circuit element inserted between them.

[0078] Figure 9 is a circuit diagram showing the configuration of a semiconductor memory device 130a according to an embodiment. The semiconductor memory device 130a is a semiconductor memory device used for multiply-accumulate operations and has the same function (i.e., current-limited differential readout method) as the multiply-accumulate unit 30 according to the reference example shown in Figure 2. However, it differs from the multiply-accumulate unit 30 according to the reference example in that each memory cell (i.e., multiplier) is composed of only two resistive elements, meaning that the constraint of matching the resistance values ​​of the two resistive elements is unnecessary. The following explanation will focus on the differences from the multiply-accumulate unit 30 according to the reference example.

[0079] The semiconductor memory device 130a is a semiconductor memory used for a sum-of-accumulate operation in which n products of corresponding input values ​​and weight coefficients are added together for n (≧2) input values ​​and n weight coefficients, and comprises a bit line BL, a first source line SL, a second source line SLB, a constant current source 40 connected between the power supply voltage Vcc and the bit line BL, n sets of word lines, each consisting of a first word line WL and a second word line WLB that transmit signals representing input values, and an array 180 which is a collection of n memory cells (first memory cell 150 and second memory cell 151) provided corresponding to each set of n sets of word lines, and which causes current to flow through the bit line BL to flow through the first source line SL and the second source line SLB according to the signal state of the first word line WL and the second word line WLB of the set, and n memory cells (first memory cell 150 Each of the first and second memory cells (151) has a first resistive element 61p having a first resistance value corresponding to a weighting coefficient, connected in series between the bit line BL and the first source line SL, and a first switch element 71p controlled by the first word line WL; a second resistive element 62n having a second resistance value, connected in series between the bit line BL and the second source line SLB, and a second switch element 72n controlled by the first word line WL; a third switch element 73p connected in series with the second resistive element 62n between the bit line BL and the first source line SL, and controlled by the second word line WLB; and a fourth switch element 74n connected in series with the first resistive element 61p between the bit line BL and the second source line SLB, and controlled by the second word line WLB. In other words, each memory cell is composed of 4T2R (four transistors and two resistive elements).

[0080] Furthermore, in Figure 9, a first current mirror circuit 141p is provided connected to the first source line SL to output a first current Ioleft (i.e., positive output current), which is the total current flowing through the first source line SL by n memory cells (first memory cell 150 and second memory cell 151). On the other hand, a second current mirror circuit 141n is provided connected to the second source line SLB to output a second current Ioright (i.e., negative output current), which is the total current flowing through the second source line SLB by n memory cells (first memory cell 150 and second memory cell 151).

[0081] In Figure 9, two memory cells (first memory cell 150 and second memory cell 151) are shown as the n memory cells constituting the array 180, but this is for illustrative purposes only, and n can be any integer such as 256 or 1024.

[0082] The difference between this multiply-accumulate unit 30 and the reference example lies in the configuration of the individual memory cells (first memory cell 150 and second memory cell 151). Each memory cell (first memory cell 150 and second memory cell 151) is the same as the multiply-accumulate unit 30 in that it is composed of four switch elements (first switch element 71p, second switch element 72n, third switch element 73p, and fourth switch element 74n), but it differs from the multiply-accumulate unit 30 in that it is composed of only two resistive elements (first resistive element 61p and second resistive element 62n). In other words, because there are no resistive elements located diagonally opposite each other, the constraint in the multiply-accumulate unit 30 in the reference example, namely the constraint that the resistance values ​​of two resistive elements located diagonally opposite each other in the memory cell must be the same, is unnecessary.

[0083] To achieve this, in the semiconductor memory device 130a according to the embodiment, the current path flowing through the four switch elements constituting the memory cell is different from that of the multiply-accumulate arithmetic unit 30 according to the reference example. That is, the constant current supplied from the constant current source 40 under the input signal Vi flows through the bit line BL and then splits to the first resistive element 61p and the second resistive element 62n, and the resulting current flows to the first switch element 71p and the fourth switch element 74n, and to the second switch element 72n and the third switch element 73p, respectively.

[0084] Figure 10A is a diagram illustrating the operation of the semiconductor memory device 130a according to the embodiment (operation when the first word line WL is High). As shown in this figure, when the first word line WL is High, the current supplied from the bit line BL is divided between the first resistive element 61p and the second resistive element 62n, and the divided current flows to the first switch element 71p and the second switch element 72n, respectively.

[0085] Figure 10B is a diagram illustrating the operation of the semiconductor memory device 130a according to the embodiment (operation when the second word line WLB is High). As shown in this figure, when the second word line WLB is High, the current supplied from the bit line BL is divided between the first resistive element 61p and the second resistive element 62n, and the divided current flows to the fourth switch element 74n and the third switch element 73p, respectively.

[0086] As can be seen from Figures 10A and 10B, when the first word line WL is High, a current dependent on the resistance value of the first resistive element 61p (i.e., the first resistance value) flows on the positive side (here, the first source line SL), and a current dependent on the resistance value of the second resistive element 62n (i.e., the second resistance value) flows on the negative side (here, the second source line SLB). On the other hand, when the second word line WLB is High, a current dependent on the resistance value of the second resistive element 62n (i.e., the second resistance value) flows on the positive side (here, the first source line SL), and a current dependent on the resistance value of the first resistive element 61p (i.e., the first resistance value) flows on the negative side (here, the second source line SLB).

[0087] The relationship between the input from the word line and the current output from the semiconductor memory device 130a according to this embodiment is the same as that of the sum-of-accumulate device 30 according to the reference example. In other words, in the sum-of-accumulate device 30 according to the reference example, the third resistive element 63p has a second resistance value (that is, the second resistive element 62n located diagonally opposite and the third resistive element 63p have the same resistance value), and the fourth resistive element 64n has a first resistance value (that is, the first resistive element 61p located diagonally opposite and the fourth resistive element 64n have the same resistance value).

[0088] From this, the semiconductor memory device 130a according to the embodiment can, in the same principle as the sum-of-products device 30 according to the reference example (see the explanation using equations 1 to 3 above), calculate not only the sum-of-products of a positive input value and a positive weight coefficient, but also the sum of the products of an input value that can take negative values ​​and a weight coefficient that can take negative values.

[0089] Next, we will explain the advantages of the semiconductor memory device 130a according to this embodiment compared with the multiply-accumulate arithmetic unit 30 according to the reference example.

[0090] Figure 11 shows a simulation circuit for evaluating the difference between the positive output current and the negative output current when the number n of memory cells in the semiconductor memory device 130a according to the embodiment is changed.

[0091] Here, as additions to the circuit of the semiconductor memory device 130a shown in Figure 9, (1) a constant current source 40 is configured as a current mirror circuit that outputs a current of 10 μA, (2) a 3 pF first capacitor 142p is added to convert the positive output current (first current Ioleft) into a voltage, and a switch element 148p is added to preset the first capacitor 142p to an initial potential (power supply voltage Vcc; 0.8 V), and (3) a 3 pF second capacitor 142n is added to convert the negative output current (second current Ioright) into a voltage, and a switch element 148n is added to preset the second capacitor 142n to an initial potential (power supply voltage Vcc; 0.8 V). Instead of the difference between the positive output current (first current Ioleft) and the negative output current (second current Ioright) of the semiconductor memory device 130a, the difference (potential difference) between the potential VXL of the first capacitor 142p and the potential VXR of the second capacitor 142n was evaluated.

[0092] Furthermore, as shown in Figure 11, the power supply voltage Vcc is set to 0.8V, the resistance value of the first resistive element 61p is set to 100kΩ, and the resistance value of the second resistive element 62n is set to 1GΩ.

[0093] Figure 12 shows the simulation results of the fluctuations in the potential VXL of the first capacitance 142p and the potential VXR of the second capacitance 142n when the number of memory cells n is changed (n = 256, 1024) under the conditions shown in Figure 11. Here, the input waveform ("WL<0>") shows the input value transmitted by the first word line WL<0> in half of the n memory cells, the input waveform ("WL<1>") shows the input value transmitted by the first word line WL<1> in the remaining half of the n memory cells, the change in the voltage VXL of the first capacitance 142p (two solid lines), and the change in the voltage VXR of the second capacitance 142n (two solid lines) are shown. The vertical axis represents voltage (V), and the horizontal axis represents time (1 period; 0 to 200 ns).

[0094] As shown in Figure 12, in the semiconductor memory device 130a according to the embodiment, even when the number of simultaneous readouts (i.e., the number of memory cells n) was increased fourfold (i.e., from 256 to 1024), the change in potential difference was less than 5% (i.e., (303mV - 289mV) / 303mV = 4.6%).

[0095] Figure 13 shows an example of a simulation circuit in the reference example of a sum-of-accumulate device 30 when there is a resistance value matching error. As shown in this figure, in the reference example of a sum-of-accumulate device 30, the resistance value of the fourth resistor element 64n is 150 kΩ, not 100 kΩ, which is the resistance value of the first resistor element 61p located diagonally opposite it, and is therefore misaligned.

[0096] Figure 14 shows the simulation results for a multiply-accumulate arithmetic unit 30 according to a reference example, illustrating the difference between a case with no resistance matching error and a case with a resistance matching error as shown in Figure 13. Here, the input waveform ("WL<0>") shows the input value transmitted by the first word line WL<0> in half of the n memory cells, the input waveform ("WL<1>") shows the input value transmitted by the first word line WL<1> in the remaining half of the n memory cells, the change in voltage Vx,p of the first capacitor 42p (of the two lines, the solid line is when there is a resistance matching error, and the dashed line is when there is no resistance matching error), and the change in voltage Vx,p of the second capacitor 42n (of the two lines, the solid line is when there is a resistance matching error, and the dashed line is when there is no resistance matching error). The vertical axis represents voltage (V), and the horizontal axis represents time (1 period; 0 to 100 ns).

[0097] As shown in the figure, there is a 31.9% difference in potential difference (voltage Vx,p - voltage Vx,n) between the case where there is no resistance matching error (i.e., both the first resistor element 61p and the fourth resistor element 64n have a resistance value of 100kΩ) and the case where there is a resistance matching error (i.e., the resistance values ​​of the first resistor element 61p and the fourth resistor element 64n are 100kΩ and 150kΩ, respectively).

[0098] Thus, according to the semiconductor memory device 130a of this embodiment, the constraint of matching the resistance values ​​of two diagonally positioned resistive elements is unnecessary, and since identical resistive elements are used, the output potential difference error due to the resistance value matching error that occurs in the sum-of-accumulate arithmetic device 30 of the reference example does not occur.

[0099] As described above, the semiconductor memory device 130a according to this embodiment, like the multiply-accumulate unit 30 according to the reference example, uses a current-limited differential readout method. This not only solves the problems of dynamic range and power consumption that limit the upper limit of the number of parallel operations when performing multiply-accumulate operations, but also, unlike the multiply-accumulate unit 30 according to the reference example, it does not require the constraint of matching the resistance values ​​of two diagonally opposite resistors in the memory cell, and thus has the advantage of not causing errors in the output potential difference due to this constraint.

[0100] Next, we will describe application examples and modifications utilizing the semiconductor memory device 130a according to the embodiment.

[0101] Figure 15 is a circuit diagram showing the configuration of a multiply-accumulate unit 120a including a semiconductor memory device 130a according to an embodiment. Figure 16 is a diagram showing a neural network model 90 corresponding to Figure 15.

[0102] Figure 15 shows a configuration in which a calculation unit 144a for generating the result of a sum-of-accumulate operation, an arithmetic operation unit (f(.)) 82, and a pulse width modulation circuit (PWM Conv.) 83 are added to the semiconductor memory device 130a shown in Figure 9.

[0103] The calculation unit 144a includes a first capacitor 142p that discharges from its initial potential by a first current Ioleft, a second capacitor 142n that discharges from its initial potential by a second current Ioright, and a difference calculation unit 145 that generates the result of a sum-of-products calculation based on the difference between the potential VXL at the first capacitor 142p and the potential VXR at the second capacitor 42n. The difference calculation unit 145 includes analog-to-digital converters 145p and 145n that convert the potentials at the first capacitor 42p and the second capacitor 42n into numerical data, and a voltage difference circuit 145d that calculates the difference using the numerical data obtained by the conversion by the analog-to-digital converters 145p and 145n, and generates the result of a sum-of-products calculation based on the difference obtained by the voltage difference circuit 145d.

[0104] In Figure 16, the arithmetic unit (f(.)) 82 is an arithmetic unit that performs predetermined arithmetic operations corresponding to the activation function of the neuron 92. The pulse width modulation circuit (PWM Conv.) 83 is a circuit that converts the numerical data obtained by the arithmetic unit 82 into a pulse width modulation (PWM) signal.

[0105] In the neural network model 90 shown in Figure 16, neurons 92 that receive input values ​​represented by PWM signals via synapses 91 corresponding to array 180 generate output values ​​using analog-to-digital converters 145p and 145n, a voltage difference circuit 145d, and an arithmetic unit 82 shown in Figure 15, and output these values ​​as PWM signals to other neurons via a pulse width modulation circuit 83. In other words, the input and output are PWM signals, and multiple neurons 92 with such configurations are arranged to form layers, and further, such layers are arranged in multiple layers to form a neural network.

[0106] Figure 17A illustrates a modified example (i.e., a modified calculation unit 144b) of the calculation unit 144a of the sum-of-accumulate calculation device 120a according to the embodiment shown in Figure 15. Here, a sum-of-accumulate calculation device 120b is shown in which the calculation unit 144a of the sum-of-accumulate calculation device 120a according to the embodiment shown in Figure 15 is replaced with the modified calculation unit 144b.

[0107] The modified calculation unit 144b includes a third current mirror circuit 147 that outputs a third current Ioright obtained by multiplying the second current Ioright by a predetermined multiplier (here, 1), and a third capacitor 143 that divides the third current Ioright from the first current Ioleft at the connection point 149 and charges with the remaining fourth current (Ioleft - Ioright), and generates the result of a sum-of-products calculation based on the voltage Vxc in the third capacitor 143. In this modified example, the calculation unit 144b sets the third capacitor 143 to an initial voltage V ＭＩＤ It also includes a switch element 148 for initialization.

[0108] Figure 17B is a timing chart showing an example of operation of the arithmetic unit 144b according to the modified example shown in Figure 17A. More specifically, Figure 17B(a) shows an example of signals (input waveforms) for the first word line WL<0> of the first memory cell 150, the first word line WL<1> of the second memory cell 151, the second word line WLB<0> of the first memory cell 150, and the second word line WLB<1> of the second memory cell 151. Figure 17B(b) shows the change in the voltage Vxc of the third capacitor 143 (initial voltage V) when the signal shown in Figure 17B(a) is input. ＭＩＤThis shows the change from the previous version.

[0109] As can be seen from Figure 17B, when the positive current (i.e., the first current Ioleft) is greater than the negative current (i.e., the second current Ioright), the slope of the voltage Vxc is positive, and conversely, when the opposite is true, the slope of the voltage Vxc is negative. Also, the sum-of-products calculation result is the initial voltage V before charging and discharging. ＭＩＤ This serves as the baseline, and the difference from this baseline is used to express the result.

[0110] Next, we will explain how to set the specific weighting coefficients (the weighting coefficients determined by the resistance values ​​of the first resistive element 61p and the second resistive element 62n).

[0111] Figure 18 is a diagram illustrating the equivalent circuit of a semiconductor memory device 130a according to an embodiment. That is, the equivalent circuit of the semiconductor memory device 130a shown in Figure 18(a) becomes the circuit shown in Figure 18(b). Here, an example is shown in which the semiconductor memory device 130a is equipped with k memory cells 150 to 152.

[0112] In the semiconductor memory device 130a according to the embodiment, in order to achieve an ideal sum-of-products operation under current limiting conditions in which the sum of the first current Ioleft flowing through the first source line SL and the second current Ioright flowing through the second source line SLB is limited to a constant value, it is necessary to set the equivalent resistance of each of the memory cells composed of 4T2R to the same value, as shown in Figure 18. Since the equivalent resistances of the positive and negative sides appear to be connected in parallel from the perspective of the constant current source 40 which defines the total amount of current, the equivalent resistance Ri is expressed by the following equation 4.

[0113]

[0114] R ｐ，ｉ , is the resistance value of the first resistive element 61p (i.e., the first resistance value), R ｎ，ｉ This is the resistance value of the second resistive element 62n (i.e., the second resistance value), and R ｃｏｎｓ This is an arbitrary fixed resistance value.

[0115] The combined resistance of each memory cell is R ｃｏｎｓBy doing so, the sum of the currents flowing into the positive and negative sides of each memory cell from the perspective of the constant current source 40 becomes a constant value, that is, (I ｂｉａｓ / k) becomes. Here, I ｂｉａｓ k is the value of the current output by the constant current source 40, and k is the number of input memory cells.

[0116] The weighting coefficient is expressed by the current difference between the positive and negative sides, therefore the weighting coefficient W of the i-th memory cell ｉ This is expressed by the following equation 5.

[0117]

[0118] Here, I ｐ，ｉ This is the current flowing on the positive side in the i-th memory cell, and I ｐ，ｉ > 0, I Ｎ，ｉ This is the current flowing on the negative side in the i-th memory cell, and I Ｎ，ｉ > 0.

[0119] Here, the condition that the current used to extract a single memory cell (the i-th memory cell) satisfies is the condition described above (I ｂｉａｓ From / k), it can be expressed as follows in equation 6.

[0120]

[0121] Furthermore, given the condition that the voltage across the resistive elements is the same, the following equation 7 holds true.

[0122]

[0123] From equations 6 and 7 above, I Ｐ，ｉ and I Ｎ，ｉ Solving for this, we derive equations 8 and 9 below.

[0124]

[0125]

[0126] By substituting equations 8 and 9 into equation 5 above, the weight coefficient W ｉ Thus, the following equation 10 is derived.

[0127]

[0128] Thus, the weight coefficient W ｉ The resistance value R of the first resistive element 61p is ｐ，ｉ and the resistance value R of the second resistor element 62n ｎ，ｉ Using these, it can be expressed as shown in equation 10.

[0129] Furthermore, as can be seen from the presence of 1 / k on the right-hand side of equation 10 above, it indicates that the current is automatically scaled according to the number of memory cells.

[0130] Incidentally, in order to achieve a weight coefficient of zero, as can be seen from equation 10 above, R ｐ，ｉ and R ｎ，ｉ The same as (R ｐ，ｉ = R ｎ，ｉ ) is sufficient. Substituting this condition into equation 4 above, we get the following equation 11.

[0131]

[0132] Figure 19 illustrates a modified example of the memory cell provided in the semiconductor memory device 130a according to the embodiment. More specifically, Figure 19(a) is a circuit diagram of the memory cell provided in the semiconductor memory device 130a according to the embodiment, Figure 19(b) is a circuit diagram of the memory cell provided in the semiconductor memory device 130b according to the first modified example of the embodiment, and Figure 19(c) is a circuit diagram of the memory cell provided in the semiconductor memory device 130c according to the second modified example of the embodiment.

[0133] As shown in Figure 19(b), in the semiconductor memory device 130b according to the first modified embodiment, the bit line is composed of two bit lines (first bit line BL and second bit line BLB). The first bit line BL and the second bit line BLB are connected to a constant current source 40 (not shown), and current is supplied from the constant current source 40 so that the sum of the current flowing through the first bit line BL and the current flowing through the second bit line BLB is constant.

[0134] More specifically, the semiconductor memory device 130b according to the first modified embodiment is a semiconductor memory used for sum-of-accumulate operations, which involves adding n products of corresponding input values ​​and weight coefficients for n (≧2) input values ​​and n weight coefficients, and comprises a first bit line BL, a second bit line BLB, a first source line SL, and a second source line SLB, and connected to the first bit line BL and the second bit line BLB, and the sum of the current flowing through the first bit line BL and the current flowing through the second bit line BLB The system includes a constant current source 40 (not shown) that supplies current to the first bit line BL and the second bit line BLB so that the current remains constant, n sets of word lines, each consisting of a first word line WL and a second word line WLB that transmit a signal representing an input value, and an array of n memory cells provided corresponding to each set of n word lines, which, according to the signal state of the first word line WL and the second word line WLB of that set, cause current to flow through the first bit line BL and the second bit line BLB to flow through the first source line SL and the second source line SLB, each of the n memory cells comprising: a first resistive element 61p having a first resistance value corresponding to a weighting coefficient, connected in series between the first bit line BL and the first source line SL; a first switch element 71p controlled by the first word line WL; and a second resistive element having a second resistance value, connected in series between the second bit line BLB and the second source line SLB. The device includes a child 62n, a second switch element 72n controlled by the first word line WL, a third switch element 73p connected in series with the second resistor 62n between the second bit line BLB and the first source line SL and controlled by the second word line WLB, and a fourth switch element 74n connected in series with the first resistor 61p between the first bit line BL and the second source line SLB and controlled by the second word line WLB.

[0135] Furthermore, as shown in Figure 19(c), in the semiconductor memory device 130c according to the second modified embodiment, each memory cell is composed of a first resistive element 61p, a first switch element 71p that directs the current flowing through the first resistive element 61p to the first source line SL, and a fourth switch element 74n that directs the current flowing through the first resistive element 61p to the second source line SLB, that is, it is composed of 2T1R. In other words, this memory cell holds only the positive weighting coefficient (strictly speaking, the positive side resistive element (i.e., the first resistive element 61p)).

[0136] More specifically, the semiconductor memory device 130c according to the second modified embodiment is a semiconductor memory used for a sum-of-accumulate operation in which n products of corresponding input values ​​and weight coefficients are added together for n (≧2) input values ​​and n weight coefficients, and comprises a bit line BL, a first source line SL, and a second source line SLB, a constant current source (not shown) connected to the bit line BL, n sets of word lines, each consisting of a first word line WL and a second word line WLB that transmit signals representing input values, and provided corresponding to each set of n sets of word lines, the first word line WL and the second word line WLB<i The system comprises an array of n memory cells that, depending on the signal state, cause current to flow through the bit line BL to flow through the first source line SL and the second source line SLB, each of the n memory cells having a first resistive element 61p having a first resistance value corresponding to a weight coefficient, connected in series between the bit line BL and the first source line SL, and a first switch element 71p controlled by the first word line WL, and a fourth switch element 74n connected in series with the first resistive element 61p between the bit line BL and the second source line SLB, and controlled by the second word line WLB.

[0137] In addition, similar to the semiconductor memory device 130a according to the embodiment, a sum-of-accumulate device that performs sum-of-accumulate calculations based on voltage differences may be realized by adding the calculation unit 144a shown in Figure 15 to the semiconductor memory device 130b according to the first modification or the semiconductor memory device 130c according to the second modification, or a sum-of-accumulate device that performs sum-of-accumulate calculations based on current differences may be realized by adding the calculation unit 144b shown in Figure 17A to the semiconductor memory device 130b according to the first modification or the semiconductor memory device 130c according to the second modification.

[0138] As described above, the semiconductor memory device 130a according to the embodiment is a semiconductor memory used for a sum-of-accumulate operation in which n products of corresponding input values ​​and weight coefficients are added together for n (≧2) input values ​​and n weight coefficients, and comprises a bit line BL, a first source line SL, and a second source line SLB, a constant current source 40 connected to the bit line BL, n sets of word lines, each consisting of a first word line WL and a second word line WLB that transmit signals representing input values, and an array 180 which is a collection of n memory cells (first memory cell 150 and second memory cell 151) provided corresponding to each set of n sets of word lines, and which causes current to flow through the bit line BL to flow through the first source line SL and the second source line SLB according to the signal state of the first word line WL and the second word line WLB of the set, and n memory cells (first memory cell 150 Each of the memory cells 150 and 151) includes a first resistive element 61p having a first resistance value corresponding to a weighting coefficient, connected in series between the bit line BL and the first source line SL, and a first switch element 71p controlled by the first word line WL, a second resistive element 62n having a second resistance value, connected in series between the bit line BL and the second source line SLB, and a second switch element 72n controlled by the first word line WL, a third switch element 73p connected in series with the second resistive element 62n between the bit line BL and the first source line SL and controlled by the second word line WLB, and a fourth switch element 74n connected in series with the first resistive element 61p between the bit line BL and the second source line SLB and controlled by the second word line WLB.

[0139] As a result, the sum of products (i.e., the result of the multiply-accumulate operation) from the multiplier units (i.e., memory cells) connected in parallel using a current-limited differential readout method is read out, thus solving the issues of dynamic range and power consumption that limit the upper limit of the number of parallel operations when performing multiply-accumulate operations in conventional technology. In other words, it is possible to realize a semiconductor memory device used for multiply-accumulate operations that can increase the number of parallel operations compared to conventional methods without narrowing the dynamic range or increasing power consumption.

[0140] Furthermore, unlike the sum-of-accumulate device 30 in the reference example, the semiconductor memory device 130a in this embodiment does not require the constraint of matching the resistance values ​​of two diagonally positioned resistive elements, and since identical resistive elements are used, it has the advantage of not causing an error in the output potential difference due to this constraint.

[0141] Furthermore, the semiconductor memory device 130b according to the first modified embodiment is a semiconductor memory used for sum-of-accumulate operations, which involves adding n products of corresponding input values ​​and weight coefficients for n (≧2) input values ​​and n weight coefficients, and comprises a first bit line BL, a second bit line BLB, a first source line SL, and a second source line SLB, and connected to the first bit line BL and the second bit line BLB, such that the sum of the current flowing through the first bit line BL and the current flowing through the second bit line BLB is constant. A constant current source 40 that supplies current to the bit line BL and the second bit line BLB, n sets of word lines, each consisting of a first word line WL and a second word line WLB that transmit a signal representing an input value, and n memory cells (first memory cell) provided corresponding to each set of n word lines, which, according to the signal state of the first word line WL and the second word line WLB of that set, cause the current flowing through the first bit line BL and the second bit line BLB to flow through the first source line SL and the second source line SLB. The system comprises an array 180 which is a collection of n memory cells (first memory cell 150 and second memory cell 151), each of which has a first resistor element 61p having a first resistance value corresponding to a weight coefficient, connected in series between the first bit line BL and the first source line SL, and a first switch element 71p controlled by the first word line WL, and a second resistor element connected in series between the second bit line BLB and the second source line SLB. The system includes a second resistor 62n having a value, a second switch element 72n controlled by the first word line WL, a third switch element 73p connected in series with the second resistor 62n between the second bit line BLB and the first source line SL and controlled by the second word line WLB, and a fourth switch element 74n connected in series with the first resistor 61p between the first bit line BL and the second source line SLB and controlled by the second word line WLB.

[0142] As a result, the same features as the semiconductor memory device 130a according to the embodiment are achieved, and the same effects as the semiconductor memory device 130a according to the embodiment are obtained.

[0143] Furthermore, the semiconductor memory device 130c according to the modified embodiment 2 is a semiconductor memory used for sum-of-accumulate operations, which involves adding n products of corresponding input values ​​and weight coefficients for n (≧2) input values ​​and n weight coefficients, and comprises a bit line BL, a first source line SL, a second source line SLB, a constant current source 40 connected to the bit line BL, n sets of word lines, each consisting of a first word line WL and a second word line WLB that transmit signals representing input values, and a current source 40 provided corresponding to each set of n sets of word lines, which controls the current flowing through the bit line BL according to the signal state of the first word line WL and second word line WLB of the set. The system includes an array 180 which is a collection of n memory cells (first memory cell 150 and second memory cell 151) that flow through SL and a second source line SLB, and each of the n memory cells (first memory cell 150 and second memory cell 151) has a first resistive element 61p having a first resistance value corresponding to a weight coefficient, connected in series between the bit line BL and the first source line SL, and a first switch element 71p controlled by the first word line WL, and a fourth switch element 74n connected in series with the first resistive element 61p between the bit line BL and the second source line SLB, and controlled by the second word line WLB.

[0144] This limits the sum-of-accumulate operation to using only positive weighting coefficients (more precisely, positive-side resistive elements (i.e., the first resistive element 61p)), but in this respect, it has the same characteristics as the semiconductor memory device 130a according to the embodiment, and achieves the same effects as the semiconductor memory device 130a according to the embodiment.

[0145] Furthermore, the sum-of-accumulate devices 120a and 120b according to the embodiment include one of the semiconductor memory devices 130a to 130c and an arithmetic unit 144a or 144b that generates the result of a sum-of-accumulate operation based on the difference between a first current Ioleft, which is the total current flowing through the first source line SL by n memory cells (first memory cell 150 and second memory cell 151), and a second current Ioright, which is the total current flowing through the second source line SLB by n memory cells (first memory cell 150 and second memory cell 151), or the difference in the time integral amounts of the first current Ioleft and the second current Ioright. This realizes a sum-of-accumulate device that generates the result of a sum-of-accumulate operation using one of the semiconductor memory devices 130a to 130c.

[0146] Here, the calculation unit 144a includes a first capacitor 142p that is charged or discharged by a first current Ioleft, a second capacitor 142n that is charged or discharged by a second current Ioright, and a voltage difference circuit 145d that generates the result of a sum-of-products calculation based on the difference between the potential at the first capacitor 142p and the potential at the second capacitor 142n. In this way, the result of the sum-of-products calculation is generated by converting the first current Ioleft and the second current Ioright into voltages and then calculating the difference.

[0147] On the other hand, the calculation unit 144b includes a third current mirror circuit 147 as a current difference circuit that calculates the difference between the first current Ioleft and the second current Ioright, and a third capacitor 143 that charges or discharges based on the difference calculated by the current difference circuit, and generates the result of a sum-of-products calculation based on the voltage of the third capacitor 143. In this way, the result of a sum-of-products calculation is generated by converting the difference between the first current Ioleft and the second current Ioright into a voltage.

[0148] The semiconductor memory device and multiply-accumulate unit relating to this disclosure have been described above based on embodiments and modifications, but this disclosure is not limited to these embodiments and modifications. Within the scope of this disclosure, various modifications conceivable by those skilled in the art, as well as other forms constructed by combining some of the components of the embodiments and modifications, are also included, as long as they do not depart from the spirit of this disclosure.

[0149] For example, the semiconductor memory device 130a, etc., according to the embodiment shown in Figure 9, does not have a word line driving circuit, but it may be provided. In that case, the word line driving circuit may be a circuit that outputs the pulse width modulated signal shown in Figure 12 to the word line WL, or it may be a circuit that outputs the pulse width modulated signal with a shifted rising edge timing (phase) on different word lines WL to the word line WL without changing the duty cycle.

[0150] Furthermore, in the embodiments and modified examples, the constant current source, current mirror circuit, and switching element are composed of MOSFETs, but the circuit elements are not limited to such components and may be composed of circuits including bipolar transistors or diodes.

[0151] Furthermore, the arithmetic circuits and control circuits such as the arithmetic units 144a and 144b and the arithmetic operation unit 82 in the embodiment and modified examples may be implemented in hardware using logic circuits, or they may be implemented in software by a processor that executes a program. The program may be recorded on a computer-readable non-temporary recording medium such as a DVD.

[0152] Furthermore, the semiconductor memory device 130a and the multiply-accumulate unit 120a according to the embodiment may be composed of a single semiconductor integrated circuit, or multiple semiconductor integrated circuits may be mounted on a circuit board.

[0153] This disclosure can be used as a semiconductor memory device and a multiply-accumulate device used for multiply-accumulate operations, for example, as a CiM and a multiply-accumulate device used to implement a neural network model in hardware.

[0154] 30, 120a, 120b Multiply-accumulate unit 31 First bit line 32 Second bit line 33 Source line 34 Common connection point 40 Constant current source 41p, 141p First current mirror circuit 41n, 141n Second current mirror circuit 42p, 142p First capacitor 42n, 142n Second capacitor 44, 144a, 144b Arithmetic unit 50-52, 150-152 Memory cell 61p First resistive element 62n Second resistive element 63p Third resistive element 64n Fourth resistive element 71p First switch element 72n Second switch element 73p Third switch element 74n Fourth switch element 80, 180 Array 82 Arithmetic unit 83 Pulse width modulation circuit 90 Neural network model 91 Synapse 92 Neuron 130a, 130b, 130c Semiconductor memory device 143 Third capacity 145 Difference calculation unit 145p, 145n Analog-to-digital converter 145d Voltage difference circuit 147 Third current mirror circuit 148, 148p, 148n Switch element 149 Connection point Vi Input signal line (input signal) WL First word line of the i-th memory cell WLB Second word line of the i-th memory cell SL First source line SLB Second source line BL Bit line, first bit line BLB Second bit line

Claims

1. A semiconductor memory device used for a sum-of-accumulate operation in which n products of corresponding input values ​​and weight coefficients are added together for n (≧2) input values ​​and n weight coefficients, comprising: a bit line, a first source line, and a second source line; a constant current source connected to the bit line; n sets of word lines, each consisting of a first word line and a second word line that transmit signals representing the input values; and an array of n memory cells provided corresponding to each set of the n sets of word lines, which, according to the signal state of the first word line and the second word line of the set, causes current to flow through the bit line to flow through the first source line and the second source line, wherein each of the n memory cells comprises: a first resistor element having a first resistance value corresponding to the weight coefficient, connected in series between the bit line and the first source line, and a first switch element controlled by the first word line; and a second resistor element having a second resistance value, connected in series between the bit line and the second source line, and a second switch element controlled by the first word line. A semiconductor memory device comprising: a third switch element connected in series with the second resistive element between the bit line and the first source line and controlled by the second word line; and a fourth switch element connected in series with the first resistive element between the bit line and the second source line and controlled by the second word line.

2. A semiconductor memory device used for a sum-of-accumulate operation in which n products of corresponding input values ​​and weight coefficients are added together for n (≧2) input values ​​and n weight coefficients, comprising: a first bit line, a second bit line, a first source line, and a second source line; a constant current source connected to the first bit line and the second bit line, which supplies current to the first bit line and the second bit line such that the sum of the current flowing through the first bit line and the current flowing through the second bit line is constant; n sets of word lines, each consisting of a first word line and a second word line that transmit signals representing the input values; an array of n memory cells provided corresponding to each set of the n sets of word lines, which, according to the signal state of the first word line and the second word line of that set, causes current to flow through the first bit line and the second bit line to flow through the first source line and the second source line; and each of the n memory cells is A semiconductor memory device comprising: a first resistor element having a first resistance value corresponding to the weight coefficient, connected in series between the first bit line and the first source line, and a first switch element controlled by the first word line; a second resistor element having a second resistance value, connected in series between the second bit line and the second source line, and a second switch element controlled by the first word line; a third switch element connected in series with the second resistor element and controlled by the second word line between the second bit line and the first source line; and a fourth switch element connected in series with the first resistor element and controlled by the second word line between the first bit line and the second source line.

3. A semiconductor memory device used for a sum-of-accumulate operation in which n products of corresponding input values ​​and weight coefficients are added together for n (≧2) input values ​​and n weight coefficients, comprising: a bit line, a first source line, and a second source line; a constant current source connected to the bit line; n sets of word lines, each consisting of a first word line and a second word line that transmit signals representing the input values; and an array of n memory cells provided corresponding to each set of the n sets of word lines, which cause current to flow through the bit line to flow through the first source line and the second source line according to the signal state of the first word line and the second word line of that set, wherein each of the n memory cells comprises: a first resistor element having a first resistance value corresponding to the weight coefficient, connected in series between the bit line and the first source line, and a first switch element controlled by the first word line; and a fourth switch element connected in series with the first resistor element between the bit line and the second source line and controlled by the second word line.

4. A multiply-accumulate device comprising: a semiconductor memory device according to any one of claims 1 to 3; and an arithmetic unit that generates the result of the multiply-accumulate operation based on the difference between a first current, which is the total current flowing through the first source line by the n memory cells, and a second current, which is the total current flowing through the second source line by the n memory cells, or the difference in the time integral amounts of the first current and the second current, respectively.

5. The sum-of-products calculation device according to claim 4, wherein the calculation unit comprises a first capacitor that is charged or discharged by the first current, a second capacitor that is charged or discharged by the second current, and a voltage difference circuit that generates the result of the sum-of-products calculation based on the difference between the potential at the first capacitor and the potential at the second capacitor.

6. The sum-of-products calculation device according to claim 4, wherein the calculation unit includes a current difference circuit that calculates the difference between the first current and the second current, and a third capacitor that charges or discharges based on the difference calculated by the current difference circuit, and generates the result of the sum-of-products calculation based on the voltage of the third capacitor.

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