Power amplifier having stack structure and communication circuit thereof

Abstract

This power amplifier may comprise: an amplifier circuit including a first transistor, a second transistor, and a third transistor connected in a cascode structure stacked between a power supply voltage and a ground; and a bias circuit including a first operational amplifier configured to provide a first bias voltage to the first transistor, and a first operational amplifier and a second operational amplifier configured to provide a second bias voltage to the second transistor. The first operational amplifier may include: a positive input terminal connected to a first reference voltage divided from the power supply voltage; a negative input terminal connected to a source node of the first transistor; an output terminal configured to provide the first bias voltage to a gate node of the first transistor; a positive power supply terminal connected to the power supply voltage; and a negative power supply terminal.

Description

Power amplifier with stack structure and its communication circuit

[0001] One or more embodiments relate to a power amplifier with a stack structure and its communication circuit.

[0002] To meet the increasing demand for wireless data traffic following the 4G system (i.e., the LTE (long-term evolution) system), 5G systems have been developed and commercialized. 5G systems can be implemented in the millimeter wave (mmWave) band. To mitigate path loss and increase the transmission distance of radio waves in the millimeter wave band, beamforming, massive array multiple input / output (massive MIMO), full-dimensional multiple input / output (Full Dimensional MIMO: FD-MIMO), array antenna, analog beamforming, and large-scale antenna technologies are being discussed for 5G systems.

[0003] In a base station of a MIMO-based 5G system using the mmWave band, a single beam or multiple beams can be formed through an array antenna and used for communication with user equipment (UE). The base station can improve communication quality by focusing signals from each direction of one or more terminals through beamforming.

[0004] With the advancement of technologies such as the Internet of Things (IoT), cloud computing, and big data, and the increasing public data consumption, the demand for high-capacity wireless communication technology is surging. Frequency bands have already reached saturation with various communication services, and limited bandwidth makes it difficult to provide higher data transmission speeds. Therefore, implementing high-capacity wireless communication technology requires signal processing in higher frequency bands.

[0005] High frequency bands, such as mmWave (millimeter wave) bands higher than 10 GHz, can significantly improve data transmission speeds based on wide bandwidth and avoid congestion in low frequency bands, thereby enabling the provision of high-quality communication services. However, mmWave bands have the problem of high signal loss and can be easily blocked by obstacles.

[0006] To overcome the aforementioned problems, research is being conducted on beamforming, increasing cell density, and high-power amplifiers. High-power amplifiers amplify the strength of output signals to extend communication distance and provide a stable connection. CMOS (complementary MOSFET (metal-oxide-semiconductor field-effect transistor))-based power amplifiers are inexpensive and have very high integration density, making it easy to implement beamforming technology at high frequencies. However, compared to other compound semiconductors (e.g., GaAs (gallium arsenide) or GaN (gallium nitride)), the usable power is low, and it may be difficult to provide high output power.

[0007] The information described above may be provided as background information for the purpose of aiding understanding of the present disclosure. No claim or determination is made as to whether any of the foregoing may be applied as prior art related to the present disclosure.

[0008] One or more embodiments may provide a power amplifier with a stack structure and a communication circuit thereof.

[0009] One or more embodiments may also provide a communication circuit including a bias circuit for a stacked cascode power amplifier.

[0010] The technical problems to be solved in this disclosure are not limited to those mentioned above, and other unmentioned technical problems will be clearly understood by those skilled in the art from the description below.

[0011] According to embodiments of the present disclosure, a power amplifier may include an amplifier circuit comprising a first transistor, a second transistor, and a third transistor connected in a stacked cascode structure between a power supply voltage and ground, and a bias circuit comprising a first operational amplifier configured to provide a first bias voltage to the first transistor and a second operational amplifier configured to provide a second bias voltage to the second transistor. The first operational amplifier may include a positive input terminal connected to a first reference voltage distributed from the power supply voltage, a negative input terminal connected to a source node of the first transistor, an output terminal configured to provide the first bias voltage to a gate node of the first transistor, a positive power supply terminal connected to the power supply voltage, and a negative power supply terminal. The second operational amplifier may include a positive input terminal connected to a second reference voltage distributed from the power supply voltage, a negative input terminal connected to the source node of the second transistor, an output terminal configured to provide the second bias voltage to the gate node of the second transistor, a positive power supply terminal connected to the negative power supply terminal of the first operational amplifier, and a negative power supply terminal connected to ground.

[0012] The power amplifier may further include a resistor ladder comprising a first resistor, a second resistor, and a third resistor connected in series between the power supply voltage and the ground. The positive input terminal of the first operational amplifier may be connected to the resistor ladder between the first resistor and the second resistor, and the positive input terminal of the second operational amplifier may be connected to the resistor ladder between the second resistor and the third resistor.

[0013] At least one of the first resistor, the second resistor, or the third resistor may be a variable resistor.

[0014] An input RF (radio frequency) signal can be received through the gate node of the third transistor. An amplified output RF signal corresponding to the input RF signal can be output through the drain node of the first transistor.

[0015] The power amplifier may further include an inductor coil connected between the power supply voltage and the drain node of the first transistor.

[0016] The amplifier circuit may further include a fourth transistor connected in a cascode structure stacked on the first transistor, and the bias circuit may further include a third operational amplifier configured to provide a bias voltage to the fourth transistor.

[0017] The power amplifier may further include a voltage regulator configured to generate source voltages to be provided to the first operational amplifier and the second operational amplifier based on the power supply voltage.

[0018] The power amplifier may further include an analog bias circuit comprising a mirror transistor corresponding to the third transistor and a third operational amplifier configured to provide a third bias voltage to the mirror transistor. The third operational amplifier may include a positive input terminal connected to an analog power supply voltage, a negative input terminal connected to the positive input terminal of the second operational amplifier, a positive power supply terminal connected to the analog power supply voltage, and a negative power supply terminal connected to ground. The mirror transistor may include a gate node connected to the gate node of the third transistor, a drain node connected to the analog power supply voltage through a reference current source, and a source node connected to ground.

[0019] The first transistor, the second transistor, and the third transistor may be CMOS (complementary MOS (metal-oxide-semiconductor)) transistors.

[0020] The above amplifier circuit can be configured to be used in the transmission path of an RF communication circuit configured to support a mmWave (millimeter wave) frequency band.

[0021] According to embodiments of the present disclosure, a communication circuit may include a transmission path, and the transmission path may include one or more power amplifiers, and at least one of the one or more power amplifiers may include an amplifier circuit comprising a first transistor, a second transistor, and a third transistor connected in a stacked cascode structure between a power supply voltage and ground, and a bias circuit comprising a first operational amplifier configured to provide a first bias voltage to the first transistor and a second operational amplifier configured to provide a second bias voltage to the second transistor. The first operational amplifier may include a positive input terminal connected to a first reference voltage distributed from the power supply voltage, a negative input terminal connected to a source node of the first transistor, an output terminal configured to provide the first bias voltage to a gate node of the first transistor, a positive power supply terminal connected to the power supply voltage, and a negative power supply terminal. The second operational amplifier may include a positive input terminal connected to a second reference voltage distributed from the power supply voltage, a negative input terminal connected to the source node of the second transistor, an output terminal configured to provide the second bias voltage to the gate node of the second transistor, a positive power supply terminal connected to the negative power supply terminal of the first operational amplifier, and a negative power supply terminal connected to ground.

[0022] The at least one power amplifier may further include a resistor ladder comprising a first resistor, a second resistor, and a third resistor connected in series between the power supply voltage and the ground. The positive input terminal of the first operational amplifier may be connected to the resistor ladder between the first resistor and the second resistor, and the positive input terminal of the second operational amplifier may be connected to the resistor ladder between the second resistor and the third resistor.

[0023] At least one of the first resistor, the second resistor, or the third resistor may be a variable resistor.

[0024] An input RF (radio frequency) signal is received through the gate node of the third transistor, and an amplified output RF signal corresponding to the input RF signal can be output through the drain node of the first transistor.

[0025] The above at least one power amplifier may further include an inductor coil connected between the power supply voltage and the drain node of the first transistor.

[0026] The above and other aspects, features, and advantages of specific embodiments of the present disclosure will become more apparent from the following description in conjunction with the accompanying drawings.

[0027] FIG. 1 is a block diagram of an electronic device in a network environment according to various embodiments.

[0028] FIG. 2a shows the structure of a power amplifier according to one embodiment.

[0029] FIG. 2b shows a stack structure of a power amplifier according to one embodiment.

[0030] FIG. 3 shows an operational amplifier-based bias circuit for a power amplifier with a two-stack structure according to one embodiment.

[0031] FIG. 4 shows an operational amplifier-based bias circuit for a 3-stack power amplifier according to one embodiment.

[0032] FIG. 5 shows a bias circuit including stacked operational amplifiers according to one embodiment.

[0033] FIG. 6 shows a power amplifier circuit including a bias circuit of a stacked operational amplifier structure according to one embodiment.

[0034] FIG. 7 shows a power amplifier circuit including a bias circuit of a multi-stacked operational amplifier structure according to one embodiment.

[0035] Embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. In describing the embodiments of the present disclosure, specific descriptions of related functions or configurations are omitted if it is determined that such detailed descriptions would unnecessarily obscure the essence of the present disclosure. Furthermore, terms used below are defined considering their functions in the embodiments of the present disclosure, and these may vary depending on the intent or convention of the user or operator. Therefore, such definitions should be based on the content throughout the present disclosure.

[0036] It should be noted that technical terms used in this disclosure are used merely to describe one embodiment and are not intended to limit this disclosure. Alternatively, unless specifically defined otherwise in this disclosure, technical terms used in this disclosure shall be interpreted in the sense generally understood by those skilled in the art to which this disclosure pertains, and shall not be interpreted in an overly broad or overly narrow sense. Alternatively, technical terms used in this disclosure may be understood as being replaced by other technical terms understood by those skilled in the art. General terms used in the embodiments of this disclosure shall be interpreted according to their prior definitions or according to the context, and shall not be interpreted in an overly narrow sense.

[0037] Singular expressions used in this disclosure may include plural expressions unless the context clearly indicates otherwise. In this disclosure, terms such as “composed” or “comprising” should not be interpreted as necessarily including all of the various components or operations described in the specification, and should be interpreted as some of the components or operations may not be included, or additional components or operations may be included.

[0038] Terms such as "first" or "second" used in this disclosure may be used to describe corresponding components regardless of importance or order, but said components should not be limited by said terms. Such terms may be used solely for the purpose of distinguishing one component from another. For example, without departing from the scope of this disclosure, the first component may be named the second component, and similarly, the second component may be named the first component. The terms "first" or "first" and "second" or "second" used in this specification may be used to refer to corresponding components regardless of importance or order and may be used to distinguish one component from another without limiting the components.

[0039] When it is stated that one component is "connected" or "connected" to another component, it may be directly connected or connected to that other component, or there may be other components in between. On the other hand, when it is stated that one component is "directly connected" or "directly connected" to another component, it should be understood that there are no other components in between.

[0040] Hereinafter, embodiments according to the present disclosure will be described with reference to the attached drawings. Identical or similar components regardless of drawing symbols are given the same reference numeral, and redundant descriptions thereof will be omitted. In describing the embodiments of the present disclosure, detailed descriptions of related prior art are omitted if it is determined that such detailed descriptions may obscure the essence of the present disclosure. It should be noted that the attached drawings are intended only to facilitate understanding of the embodiments of the present disclosure and should not be interpreted as limiting the present disclosure. The present disclosure should be interpreted as extending to all modifications, equivalents, and substitutions in addition to the attached drawings.

[0041] In this disclosure, embodiments will be described using an electronic device as an example, but the electronic device may be referred to as a terminal, mobile station, mobile equipment (ME), user equipment (UE), user terminal (UT), subscriber station (SS), wireless device, handheld device, or access terminal (AT). In the embodiments of this disclosure, the electronic device may be a device equipped with communication functions, such as a mobile phone, personal digital assistant (PDA), smartphone, wireless modem, or laptop.

[0042] FIG. 1 is a block diagram of an electronic device (101) in a network environment (100) according to various embodiments.

[0043] Referring to FIG. 1, in a network environment (100), an electronic device (101) may communicate with an electronic device (102) through a first network (198) (e.g., a short-range wireless communication network) or with an electronic device (104) or a server (108) through a second network (199) (e.g., a long-range wireless communication network). According to one embodiment, the electronic device (101) may communicate with the electronic device (104) through a server (108). According to one embodiment, the electronic device (101) may include a processor (120), memory (130), input module (150), sound output module (155), display module (160), audio module (170), sensor module (176), interface (177), connection terminal (178), haptic module (179), camera module (180), power management module (188), battery (189), communication module (190), subscriber identification module (196), or antenna module (197). In some embodiments, at least one of these components (e.g., connection terminal (178)) may be omitted from the electronic device (101), or one or more other components may be added. In some embodiments, some of these components (e.g., sensor module (176), camera module (180), or antenna module (197)) may be integrated into a single component (e.g., display module (160)).

[0044] The processor (120) can control at least one other component (e.g., hardware or software component) of the electronic device (101) connected to the processor (120) by executing software (e.g., program (140)), and can perform various data processing or operations. According to one embodiment, as at least part of the data processing or operations, the processor (120) can store commands or data received from other components (e.g., sensor module (176) or communication module (190)) in volatile memory (132), process the commands or data stored in volatile memory (132), and store the resulting data in non-volatile memory (134). According to one embodiment, the processor (120) may include a main processor (121) (e.g., central processing unit or application processor) or an auxiliary processor (123) that can operate independently or together with it (e.g., graphics processing unit, neural processing unit (NPU), image signal processor, sensor hub processor, or communication processor). For example, if the electronic device (101) includes a main processor (121) and an auxiliary processor (123), the auxiliary processor (123) may be configured to use lower power than the main processor (121) or to be specialized for a designated function. The auxiliary processor (123) may be implemented separately from the main processor (121) or as part thereof.

[0045] The auxiliary processor (123) may control at least some of the functions or states associated with at least one component of the electronic device (101) (e.g., display module (160), sensor module (176), or communication module (190)) on behalf of the main processor (121) while the main processor (121) is in an inactive (e.g., sleep) state, or together with the main processor (121) while the main processor (121) is in an active (e.g., application execution) state. According to one embodiment, the auxiliary processor (123) (e.g., image signal processor or communication processor) may be implemented as part of another functionally related component (e.g., camera module (180) or communication module (190)). According to one embodiment, the auxiliary processor (123) (e.g., neural network processing unit) may include a hardware structure specialized for processing an artificial intelligence model. The artificial intelligence model may be generated through machine learning. Such learning may be performed, for example, on the electronic device (101) itself where the artificial intelligence is performed, or through a separate server (e.g., server (108)). The learning algorithm may include, for example, supervised learning, unsupervised learning, semi-supervised learning, or reinforcement learning, but is not limited to the examples described above. The artificial intelligence model may include a plurality of artificial neural network layers.An artificial neural network may be a deep neural network (DNN), a convolutional neural network (CNN), a recurrent neural network (RNN), a restricted Boltzmann machine (RBM), a deep belief network (DBN), a bidirectional recurrent deep neural network (BRDNN), a deep Q-network, or a combination of two or more of the above, but is not limited to the examples described above. In addition to the hardware structure, the artificial intelligence model may include a software structure, either additionally or substantially.

[0046] The memory (130) can store various data used by at least one component of the electronic device (101) (e.g., processor (120) or sensor module (176)). The data may include, for example, input data or output data for software (e.g., program (140)) and related commands. The memory (130) may include volatile memory (132) or non-volatile memory (134).

[0047] The program (140) may be stored as software in memory (130) and may include, for example, an operating system (142), middleware (144), or an application (146).

[0048] The input module (150) can receive commands or data to be used for a component of the electronic device (101) (e.g., processor (120)) from outside the electronic device (101) (e.g., user). The input module (150) may include, for example, a microphone, a mouse, a keyboard, a key (e.g., a button), or a digital pen (e.g., a stylus pen).

[0049] The sound output module (155) can output a sound signal to the outside of the electronic device (101). The sound output module (155) may include, for example, a speaker or a receiver. The speaker may be used for general purposes, such as multimedia playback or recording playback. The receiver may be used to receive incoming calls. According to one embodiment, the receiver may be implemented separately from the speaker or as part thereof.

[0050] The display module (160) can visually provide information to an external (e.g., user) of the electronic device (101). The display module (160) may include, for example, a display, a holographic device, or a projector and a control circuit for controlling said device. According to one embodiment, the display module (160) may include a touch sensor configured to detect a touch, or a pressure sensor configured to measure the intensity of the force generated by said touch.

[0051] The audio module (170) can convert sound into an electrical signal or, conversely, convert an electrical signal into sound. According to one embodiment, the audio module (170) can acquire sound through the input module (150) or output sound through the sound output module (155) or an external electronic device (e.g., electronic device (102)) (e.g., speaker or headphones) connected directly or wirelessly to the electronic device (101).

[0052] The sensor module (176) can detect the operating state of the electronic device (101) (e.g., power or temperature) or the external environmental state (e.g., user state) and generate an electrical signal or data value corresponding to the detected state. According to one embodiment, the sensor module (176) may include, for example, a gesture sensor, a gyroscope sensor, a barometric pressure sensor, a magnetic sensor, an accelerometer sensor, a grip sensor, a proximity sensor, a color sensor, an IR (infrared) sensor, a biosensor, a temperature sensor, a humidity sensor, or an illuminance sensor.

[0053] The interface (177) may support one or more specified protocols that can be used for the electronic device (101) to be connected directly or wirelessly to an external electronic device (e.g., electronic device (102)). According to one embodiment, the interface (177) may include, for example, a high definition multimedia interface (HDMI), a universal serial bus (USB) interface, an SD card interface, or an audio interface.

[0054] The connection terminal (178) may include a connector through which the electronic device (101) can be physically connected to an external electronic device (e.g., electronic device (102)). According to one embodiment, the connection terminal (178) may include, for example, an HDMI connector, a USB connector, an SD card connector, or an audio connector (e.g., a headphone connector).

[0055] The haptic module (179) can convert an electrical signal into a mechanical stimulus (e.g., vibration or movement) or an electrical stimulus that the user can perceive through tactile or kinesthetic senses. According to one embodiment, the haptic module (179) may include, for example, a motor, a piezoelectric element, or an electric stimulation device.

[0056] The camera module (180) can capture still images and video. According to one embodiment, the camera module (180) may include one or more lenses, image sensors, image signal processors, or flashes.

[0057] The power management module (188) can manage the power supplied to the electronic device (101). According to one embodiment, the power management module (188) can be implemented, for example, as at least part of a power management integrated circuit (PMIC).

[0058] The battery (189) can supply power to at least one component of the electronic device (101). According to one embodiment, the battery (189) may include, for example, a non-rechargeable primary battery, a rechargeable secondary battery, or a fuel cell.

[0059] The communication module (190) can support the establishment of a direct (e.g., wired) communication channel or a wireless communication channel between an electronic device (101) and an external electronic device (e.g., electronic device (102), electronic device (104), or server (108)), and the performance of communication through the established communication channel. The communication module (190) may include one or more communication processors that operate independently of the processor (120) (e.g., application processor) and support direct (e.g., wired) communication or wireless communication. According to one embodiment, the communication module (190) may include a wireless communication module (192) (e.g., cellular communication module, short-range wireless communication module, or GNSS (global navigation satellite system) communication module) or a wired communication module (194) (e.g., LAN (local area network) communication module, or power line communication module). The corresponding communication module among these communication modules can communicate with an external electronic device (104) through a first network (198) (e.g., a short-range communication network such as Bluetooth, WiFi (wireless fidelity) direct, or IrDA (infrared data association)) or a second network (199) (e.g., a legacy cellular network, a 5G network, a next-generation communication network, the Internet, or a computer network (e.g., a LAN or WAN)). These various types of communication modules may be integrated into a single component (e.g., a single chip) or implemented as multiple separate components (e.g., multiple chips). The wireless communication module (192) can identify or authenticate the electronic device (101) within a communication network such as the first network (198) or the second network (199) using subscriber information (e.g., International Mobile Subscriber Identifier (IMSI)) stored in the subscriber identification module (196).

[0060] The wireless communication module (192) can support 5G networks and next-generation communication technologies following 4G networks, for example, new radio access technology. NR access technology can support high-speed transmission of high-capacity data (enhanced mobile broadband (eMBB)), minimization of terminal power and connection of multiple terminals (massive machine type communications (mMTC)), or high reliability and low latency (ultra-reliable and low-latency communications (URLLC)). The wireless communication module (192) can support a high-frequency band (e.g., mmWave band) to achieve a high data transmission rate, for example. The wireless communication module (192) can support various technologies for securing performance in the high-frequency band, such as beamforming, massive MIMO (multiple-input and multiple-output), full-dimensional MIMO (FD-MIMO), array antenna, analog beam-forming, or large-scale antenna. The wireless communication module (192) can support various requirements specified in the electronic device (101), external electronic device (e.g., electronic device (104)), or network system (e.g., second network (199)). According to one embodiment, the wireless communication module (192) can support a Peak data rate (e.g., 20 Gbps or more) for realizing eMBB, loss coverage (e.g., 164 dB or less) for realizing mMTC, or U-plane latency (e.g., downlink (DL) and uplink (UL) each 0.5 ms or less, or round trip 1 ms or less) for realizing URLLC.

[0061] An antenna module (197) can transmit a signal or power to or from an external source (e.g., an external electronic device). According to one embodiment, the antenna module (197) may include an antenna comprising a radiator made of a conductor or a conductive pattern formed on a substrate (e.g., a PCB). According to one embodiment, the antenna module (197) may include a plurality of antennas (e.g., an array antenna). In this case, at least one antenna suitable for a communication method used in a communication network, such as a first network (198) or a second network (199), may be selected from the plurality of antennas, for example, by a communication module (190). A signal or power may be transmitted or received between the communication module (190) and an external electronic device through the selected at least one antenna. According to some embodiments, in addition to the radiator, other components (e.g., a radio frequency integrated circuit (RFIC)) may be additionally formed as part of the antenna module (197).

[0062] According to various embodiments, the antenna module (197) may form a mmWave antenna module. According to one embodiment, the mmWave antenna module may include a printed circuit board, an RFIC disposed on or adjacent to a first surface (e.g., bottom surface) of the printed circuit board and capable of supporting a specified high frequency band (e.g., mmWave band), and a plurality of antennas (e.g., array antennas) disposed on or adjacent to a second surface (e.g., top surface or side surface) of the printed circuit board and capable of transmitting or receiving a signal of the specified high frequency band.

[0063] At least some of the above components can be connected to each other via a communication method between peripheral devices (e.g., bus, GPIO (general purpose input and output), SPI (serial peripheral interface), or MIPI (mobile industry processor interface)) and exchange signals (e.g., commands or data) with each other.

[0064] According to one embodiment, commands or data may be transmitted or received between the electronic device (101) and an external electronic device (104) through a server (108) connected to a second network (199). Each of the external electronic devices (102, or 104) may be the same or a different type of device as the electronic device (101). According to one embodiment, all or part of the operations performed on the electronic device (101) may be performed on one or more of the external electronic devices (102, 104, or 108). For example, if the electronic device (101) needs to perform a function or service automatically or in response to a request from a user or another device, the electronic device (101) may request one or more external electronic devices to perform at least part of the function or service instead of performing the function or service itself or additionally. One or more external electronic devices that receive the above request may execute at least part of the requested function or service, or additional function or service related to the request, and transmit the result of the execution to the electronic device (101). The electronic device (101) may provide the result as is or additionally processed as at least part of the response to the request. For this purpose, for example, cloud computing, distributed computing, mobile edge computing (MEC), or client-server computing technology may be used. The electronic device (101) may provide ultra-low latency services using, for example, distributed computing or mobile edge computing. In another embodiment, the external electronic device (104) may include an Internet of Things (IoT) device. The server (108) may be an intelligent server using machine learning and / or neural networks. According to one embodiment, the external electronic device (104) or the server (108) may be included within a second network (199).The electronic device (101) can be applied to intelligent services (e.g., smart home, smart city, smart car, or healthcare) based on 5G communication technology and IoT-related technology.

[0065] In wireless communication technology, RF (radio frequency) signals on a designated frequency band may be filtered and amplified through a transmission path of a communication circuit (e.g., wireless communication module (192) of FIG. 1) and then radiated into the air through an antenna (e.g., antenna module (197) of FIG. 1), or received by an antenna (e.g., antenna module (197) of FIG. 1) and then filtered and amplified through a reception path of a communication circuit (e.g., wireless communication module (192) of FIG. 1). The transmission path may include one or more power amplifiers to amplify the transmitted RF signal to a desired power level.

[0066] Embodiments of the present disclosure may provide circuit structures for implementing a CMOS (complementary MOSFET (metal-oxide-semiconductor field-effect transistor))-based high-power amplifier to implement beamforming technology in frequency bands such as mmWave higher than 10 GHz. The CMOS device has a low supply voltage (V DD It is difficult to produce high output due to ). To improve this, multiple transistors can be stacked to increase the power supply voltage and the magnitude of the maximum output signal.

[0067] FIG. 2a shows the structure of a power amplifier according to one embodiment.

[0068] Referring to FIG. 2a, the power amplifier (202) may include a single transistor (210) composed of a gate node, a drain node, and a source node. The gate node receives the input signal RF IN (e.g., V IN(212)) can be connected to, and the drain node is an output signal RF OUT (e.g., V OUT (214)) can be connected, and the source node can be connected to ground (GND). The drain node is connected to the supply voltage V through the inductor coil (216). DD (218) (e.g., 1.2V) can be provided. The transistor (210) receives the input signal RF provided to the gate node. IN (e.g., V IN (212)) amplifies the amplified signal corresponding to the input signal through the drain node, i.e., the output signal RF OUT (e.g., V OUT (214)) can be printed.

[0069] FIG. 2b shows a stack structure of a power amplifier according to one embodiment.

[0070] Referring to FIG. 2b, a stacked power amplifier (204) comprises one or more transistors, each consisting of a gate node, a drain node, and a source node (e.g., power supply voltage V DD It may include a first transistor (220a), a second transistor (220b), and a third transistor (220c) connected in a stacked cascode structure between (228) and ground (GND).

[0071] In one embodiment, the source node of the first transistor (220a) is connected to the drain node of the second transistor (220b), and the source node of the second transistor (220b) is connected to the drain node of the third transistor (220c). Thus, the first transistor (220a), the second transistor (220b), and the third transistor (220c) can form a stacked cascode structure. The drain node of the first transistor (220a) is connected to the power supply voltage V through the inductor coil (226). DD(228) (e.g., 3.6V) can be provided, and the source node of the third transistor (220c) can be connected to ground.

[0072] In one embodiment, the drain node of the first transistor (220a) is the output signal RF OUT (e.g., V OUT (224)) can be connected, and the gate node of the third transistor (220c) is the input signal RF IN (e.g., V IN It can be connected to (222). Input signal RF provided to the gate node of the third transistor (220c). IN (e.g., V IN (222)) is amplified by the third transistor (220c), the second transistor (220b), and the first transistor (220a), and through the drain node of the first transistor (220c), the amplified signal corresponding to the input signal, i.e., the output signal RF OUT (e.g., V OUT (224)) can be output.

[0073] In one embodiment, a power amplifier (204) comprising three stacked transistors (220a, 220b, 220c) is a power amplifier (202) comprising one transistor (210) (e.g., V DD Compared to (218) = 1.2V), a power supply voltage three times higher (e.g., V DD (228) = 3.6V) can be used, and therefore the same input voltage (e.g., V IN (222)) for a higher output voltage (e.g., V OUT (224)) can be provided.

[0074] The embodiments may generate one or more additional bias voltages to power a plurality of transistors constituting a stacked power amplifier. The embodiments may use at least one operational amplifier (OP AMP) to supply bias voltages to the transistors of the stacked power amplifier.

[0075] FIG. 3 shows an operational amplifier-based bias circuit for a power amplifier with a two-stack structure according to one embodiment.

[0076] Referring to FIG. 3, a 2-stack power amplifier (300) comprises one or more transistors each configured as a gate node, a drain node, and a source node (e.g., power supply voltage V DD It may include a first transistor (302) and a second transistor (304) connected between (310) and ground (GND), and an operational amplifier (OP AMP) (306) for providing a bias voltage to the first transistor (302).

[0077] In one embodiment, the source node of the first transistor (302) may be connected to the drain node of the second transistor (304). The drain node of the first transistor (302) is connected to the power supply voltage V through the inductor coil (308). DD (310) (e.g., 3.6V) can be provided, and the source node of the second transistor (304) can be connected to ground.

[0078] In one embodiment, the drain node of the first transistor (302) is the output signal RF OUT (e.g., V OUT It can be connected to ), and the gate node of the second transistor (304) is the input signal RF IN (e.g., V INIt can be connected to ). Input signal RF provided to the gate node of the second transistor (304). IN The signal is amplified by the second transistor (304) and the first transistor (302), and through the drain node of the first transistor (302), the amplified signal corresponding to the input signal, i.e., the output signal RF OUT This can be output.

[0079] In one embodiment, the operational amplifier (306) is at power supply voltage V DD 3 divided power voltage V generated from (310) DD It may include a positive input terminal (i.e., non-inverting input terminal) connected to / 3 (312) (e.g., 1.2V), a negative input terminal (i.e., inverting input terminal) connected to the source node of the first transistor (302) and the drain node of the second transistor (304), and an output terminal connected to the gate node of the first transistor (302). The operational amplifier (306) may have a three-divided power supply voltage V DD A bias voltage for the first transistor (302) can be generated based on / 3 (312) and output to the gate node of the first transistor (302). The operational amplifier (306) can generate a supply voltage for an analog circuit (e.g., an analog supply voltage V). DD_ANA (314) (e.g., 1.8V)) can be driven by receiving it as a power supply terminal.

[0080] In one embodiment, the power amplifier (300) may further include a mirror transistor (320) corresponding to the second transistor (304). The mirror transistor (320) has a gate node connected to the gate node of the second transistor (304), an analog power supply voltage V DD_ANAIt may include a drain node connected to (314) (e.g., 1.8V) and a source node connected to ground. An operational amplifier (318) that provides a bias voltage for the mirror transistor (320) may be connected to the gate node of the mirror transistor (320).

[0081] In one embodiment, the operational amplifier (318) is a three-divided power supply voltage V DD It may include a positive input terminal connected to / 3 (312) (e.g., 1.2V), a negative input terminal connected to the drain node of the mirror transistor (320), and an output terminal connected to the gate node of the mirror transistor (320). The operational amplifier (318) is connected to a 3-divided power supply voltage V DD A bias voltage for the mirror transistor (320) can be generated based on / 3 (312) and output to the gate node of the mirror transistor (320). The operational amplifier (318) is analog power supply voltage V DD_ANA (314) (e.g., 1.8V) can be input to the power supply terminal and driven by the analog power supply voltage.

[0082] FIG. 4 shows an operational amplifier-based bias circuit for a 3-stack power amplifier according to one embodiment.

[0083] Referring to FIG. 4, a 3-stack power amplifier (400) comprises one or more transistors each configured as a gate node, a drain node, and a source node (e.g., power supply voltage V DD It may include a third transistor (402), a first transistor (302), and a second transistor (304) connected between (310) and ground (GND), and one or more operational amplifiers (e.g., operational amplifier (306) and operational amplifier (404)) for providing bias voltages to the first transistor (302) and the third transistor (402).

[0084] In one embodiment, the source node of the third transistor (402) is connected to the drain node of the first transistor (302), and the source node of the first transistor (302) may be connected to the drain node of the second transistor (304). The drain node of the third transistor (402) is connected to the power supply voltage V through the inductor coil (308). DD (310) (e.g., 3.6V) can be provided, and the source node of the second transistor (304) can be connected to ground.

[0085] In one embodiment, the drain node of the third transistor (402) is the output signal RF OUT (e.g., V OUT It can be connected to ), and the gate node of the second transistor (304) is the input signal RF IN (e.g., V IN It can be connected to ). Input signal RF provided to the gate node of the second transistor (304). IN The signal is amplified by the second transistor (304), the first transistor (302), and the third transistor (402), and through the drain node of the third transistor (402), the amplified signal corresponding to the input signal, i.e., the output signal RF OUT This can be output.

[0086] In one embodiment, the positive input terminal of the operational amplifier (306) is the power supply voltage V DD 3 divided power voltage V generated from (310) DD It can be connected to / 3 (312) (e.g., 1.2V), the negative input terminal of the operational amplifier (306) can be connected to the source node of the first transistor (302) and the drain node of the second transistor (304), and the output terminal of the operational amplifier (306) can be connected to the gate node of the first transistor (302). The operational amplifier (306) is connected to a 3-divided power supply voltage V DDA bias voltage for the first transistor (302) can be generated based on / 3 (312) and output to the gate node of the first transistor (302). The operational amplifier (306) is analog power supply voltage V DD_ANA (314) (e.g., 1.8V) can be input to the power supply terminal and driven by the analog power supply voltage.

[0087] In one embodiment, the power amplifier (400) may further include a mirror transistor (320) corresponding to the second transistor (304). The mirror transistor (320) has a gate node connected to the gate node of the second transistor (304), an analog power supply voltage V DD_ANA It may include a drain node connected to (314) (e.g., 1.8V) and a source node connected to ground. An operational amplifier (318) that provides a bias voltage for the mirror transistor (320) may be connected to the gate node of the mirror transistor (320).

[0088] In one embodiment, the positive input terminal of the operational amplifier (318) is a 3-divided power supply voltage V DD It can be connected to / 3 (312) (e.g., 1.2V), the negative input terminal of the operational amplifier (318) can be connected to the drain node of the mirror transistor (320), and the output terminal of the operational amplifier (318) can be connected to the gate node of the mirror transistor (320). The operational amplifier (318) is connected to a 3-divided power supply voltage V DD A bias voltage for the mirror transistor (320) can be generated based on / 3 (312) and output to the gate node of the mirror transistor (320). The operational amplifier (318) is analog power supply voltage V DD_ANA (314) (e.g., 1.8V) can be driven by receiving it as a power supply terminal.

[0089] In one embodiment, the power amplifier (400) may further include an operational amplifier (404) for providing a bias voltage for a third transistor (402). The operational amplifier (404) may be configured to provide a bias voltage for the third transistor (402) that is higher than the bias voltage for the first transistor (302).

[0090] In one embodiment, a power amplifier (400) comprising three transistors (e.g., a third transistor (402), a first transistor (302), and a second transistor (304)) compared to a power amplifier (300) comprising two transistors (e.g., a first transistor (302) and a second transistor (304)), voltages (e.g., V) for upper stack transistors (e.g., the third transistor (402) and the first transistor (302)) G1 , V S1 , V G2 , and V S2 ) must be appropriately provided. In one embodiment, the source voltage V of the first transistor (302) S1 =1.2V, and the source voltage V of the third transistor (402) S2 Since is 2.4V, the third transistor (402) has a bias voltage V higher than 2.4V. G2 It may be necessary. The above high bias voltage V G2 For this purpose, the operational amplifier (404) uses a reference power supply voltage VDD (310) (e.g., 3.6V) or an analog power supply voltage V DD_ANA (314) In addition, a higher additional power supply voltage may be required.

[0091] The use of additional components (e.g., operational amplifier (404)) for biasing power amplifier transistors (e.g., third transistor (402) and first transistor (302)) places a significant burden on the configuration of the entire system. In particular, in communication circuits of phase array structures for utilizing beamforming, the burden of using additional components (e.g., operational amplifier) ​​for each power amplifier is further increased because a large number of power amplifiers (e.g., power amplifier (400)) are integrated within a single chip.

[0092] In one embodiment, a power amplifier (300) with a two-stack structure includes one stacked transistor (e.g., a first transistor (302)) excluding a second transistor (304) for signal input, and since the bias voltage required for the first transistor (302) is 1.2V, the power amplifier (300) has a power supply voltage V for an analog circuit. DD_ANA The bias voltage can be provided to the first transistor (302) through an operational amplifier (306) driven by (314) (e.g., 1.8V). As the number of stacked transistors increases, the transistors in the higher stack (e.g., the third transistor (402) in FIG. 4) may require a higher bias voltage than the transistors in the lower stack (e.g., the first transistor (302) in FIG. 3).

[0093] In one embodiment, a 3-stack power amplifier (400) comprises two stacked transistors (e.g., a first transistor (302) and a third transistor (402)), excluding a second transistor (304) for signal input, and the third transistor (402) of the highest stack has a source voltage V of 2.4V. S2 and gate voltage V higher than 2.4V G2 ...is required. The above source voltage V S2 and the gate voltage V G2 For the analog circuit voltage VDD_ANA A bias circuit may be further designed to include an operational amplifier (e.g., operational amplifier (404)) operating at a supply voltage higher than (e.g., 1.8 V) (e.g., higher than 3.0 V). The bias circuit operating at the higher supply voltage may require high-voltage transistors such as LDMOS (lateral double diffused MOS), and the use of such high-voltage transistors may increase the production cost of the communication circuit.

[0094] The embodiments include a reference power supply voltage (e.g., power supply voltage V). DD Bias voltages for transistors (e.g., transistors (502, 504) of FIG. 5) constituting a stacked power amplifier can be generated without using an additional power supply voltage other than (e.g., analog power supply voltage (314)). Embodiments can efficiently provide higher bias voltages to transistors included in the stacked power amplifier by configuring the operational amplifiers (e.g., operational amplifiers (512, 514) of FIG. 5) included in the bias circuit for the stacked power amplifier in a stacked structure.

[0095] FIG. 5 shows a bias circuit including stacked operational amplifiers according to one embodiment.

[0096] Referring to FIG. 5, the power amplifier (500) may include an amplifier circuit (522) and a bias circuit (524). The amplifier circuit (522) is a power supply voltage V DDIt may include a first transistor (502), a second transistor (504), and a third transistor (506) connected in a stacked cascode structure between (516) (e.g., 3.6V) and ground (GND). The bias circuit (524) may include a first operational amplifier (512) and a second operational amplifier (514) that provide a first bias voltage and a second bias voltage, respectively, to the first transistor (502) and the second transistor (504).

[0097] In one embodiment, each of the first transistor (502), the second transistor (504), and the third transistor (506) may be a field effect transistor (FET) comprising a gate node, a source node, and a drain node. The source node of the first transistor (502) is connected to the drain node of the second transistor (504), and the source node of the second transistor (504) is connected to the drain node of the third transistor (506), so that the first transistor (502), the second transistor (504), and the third transistor (506) can form a stacked cascode structure. The drain node of the first transistor (502) is connected to the power supply voltage V through an inductor coil (508). DD (516) can be provided, and the source node of the third transistor (506) can be connected to ground (e.g., AC (alternating current) ground).

[0098] In one embodiment, an input signal RF for a power amplifier (500) IN (e.g., input voltage V IN (510)) is provided as the gate node of the third transistor (506) and can be amplified by the amplifier circuit (522) (e.g., the third transistor (506), the second transistor (504), and the first transistor (502)). Input voltage V IN Output signal RF corresponding to (510) OUT(e.g., output voltage V OUT (518)) can be provided at the drain node of the first transistor (502).

[0099] In one embodiment, the first operational amplifier (512) is at a power supply voltage V DD Reference voltage distributed from (516) (e.g., V DD A positive input terminal connected to ×2 / 3), a negative input terminal connected to the source node of the first transistor (502) and the drain node of the second transistor (504), an output terminal connected to the gate node of the first transistor (502) to provide the first bias voltage, and a power supply voltage V DD It may include a power supply terminal (e.g., a positive power supply terminal) and a ground terminal (e.g., a negative power supply terminal) connected to (516). In one embodiment, the first operational amplifier (512) has a power supply voltage V to the positive input terminal of the first operational amplifier (512). DD It receives a distributed power voltage (e.g., 2.4V) from (516), and the ground terminal of the first operational amplifier (512) provides a voltage of 1.8V and can be connected to the power supply terminal of the second operational amplifier (514).

[0100] In one embodiment, the second operational amplifier (514) is at power supply voltage V DD (516) second reference voltage distributed from (e.g., V DD It may include a positive input terminal connected to ×1 / 3), a negative input terminal connected to the source node of the second transistor (504) and the drain node of the third transistor (506), an output terminal connected to the gate node of the second transistor (504) to provide the second bias voltage, a power supply terminal connected to the ground terminal of the first operational amplifier (512), and a ground terminal. In one embodiment, the second operational amplifier (514) may have a power supply voltage V connected to the positive input terminal of the second operational amplifier (514). DDThe power supply voltage distributed from (516) (e.g., 1.2V) is provided, and the ground terminal of the second operational amplifier (514) can be grounded.

[0101] In one embodiment, the power supply voltage V DD (516) is divided by a resistor ladder (520) (e.g., a resistive voltage divider) composed of resistors connected in series (e.g., a first resistor (520a), a second resistor (520b), and a third resistor (520c)), and the divided voltages can be provided to the positive input terminals of a first operational amplifier (512) and a second operational amplifier (514). In one embodiment, the first resistor (520a), the second resistor (520b), and the third resistor (520c) are connected to a power supply voltage V DD It can be connected in series between (516) and ground. In one embodiment, the positive input terminal of the first operational amplifier (512) can be connected between the first resistor (520a) and the second resistor (520b). In one embodiment, the positive input terminal of the second operational amplifier (512) can be connected between the second resistor (520b) and the third resistor (520c). In one embodiment, the gate node of the third transistor (506) can be connected between the third resistor (520c) and the ground terminal.

[0102] In one embodiment, the resistance values ​​of the first resistor (520a), the second resistor (520b), and the third resistor (520c) can be set to the same value. Accordingly, the first transistor (502), the second transistor (504), and the third transistor (506) have uniform drain-source voltages (V DSIt may have ). In one embodiment, at least one of the first resistor (520a), the second resistor (520b), or the third resistor (520c) may be configured as a configurable resistor (i.e., variable resistor). The resistance value of at least one of the first resistor (520a), the second resistor (520b), or the third resistor (520c) may be set to a different value depending on the required gate voltage of at least one of the first transistor (502), the second transistor (504), or the third transistor (506).

[0103] In one embodiment, the first resistor (520a), the second resistor (520b), and the third resistor (520c) can be set to the same values, and the power supply voltage V DD (516) may be 3.6V. Accordingly, a voltage of 2.4V may be provided to the positive input terminal of the first operational amplifier (512), and a voltage of 1.2V may be provided to the positive input terminal of the second operational amplifier (514). By utilizing the virtual short and high input impedance of the first operational amplifier (512) and the second operational amplifier (514), the negative input terminal of the first operational amplifier (512) is connected to the junction between the source node of the first transistor (502) and the drain node of the second transistor (504), V S2 It can supply V, and the negative input terminal of the second operational amplifier (514) is connected to the junction between the source node of the second transistor (504) and the drain node of the third transistor (506). S1 It can supply.

[0104] In one embodiment, the first transistor (502), the second transistor (504), and the third transistor (506) have the same drain-source voltage and drain-source current, so the gate-source voltages of the first transistor (502), the second transistor (504), and the third transistor (506) are also the same, and the first transistor (502), the second transistor (504), and the third transistor (506) can use the same gate voltages.

[0105] In one embodiment, the power amplifier (500) connects the first operational amplifier (512) and the second operational amplifier (514) in a stack structure, thereby providing a single power supply voltage (e.g., V DD By using (516)) to drive both the first operational amplifier (512) and the second operational amplifier (514), it is possible to avoid using additional high power supply voltages or operational amplifier elements that operate at high power supply voltages. In one embodiment, the first operational amplifier (512) and the second operational amplifier (514) may be composed of operational amplifiers of the same type, thereby reducing the design complexity of the power amplifier (500).

[0106] FIG. 6 shows a power amplifier circuit including a bias circuit of a stacked operational amplifier structure according to one embodiment.

[0107] Referring to FIG. 6, the power amplifier (600) may include an amplifier circuit (522) and a bias circuit (524). The amplifier circuit (522) may include a first transistor (502), a second transistor (504), and a third transistor (506) connected in a cascode structure stacked between a power supply voltage VDD (516) (e.g., 3.6 V) and ground (GND). The bias circuit (524) may include a first operational amplifier (512) and a second operational amplifier (514) that provide a first bias voltage and a second bias voltage, respectively, to the first transistor (502) and the second transistor (504). In one embodiment, the power amplifier (600) may further include a resistor ladder (520) composed of resistors (e.g., a first resistor (520a), a second resistor (520b), and a third resistor (520c)) connected in series between the power supply voltage VDD (516) and ground. The amplifier circuit (522), the bias circuit (524), and the resistor ladder (520) may be substantially similar to the description provided above with reference to FIG. 5.

[0108] In one embodiment, the power amplifier (600) may further include a mirror transistor (602) corresponding to the third transistor (506). The mirror transistor (602) has a gate node connected to the gate node of the third transistor (506), an analog power supply voltage V DD_ANA It may include a drain node connected to a reference current source supplied with (608) (e.g., 1.8 V), and a source node connected to ground. An operational amplifier (604) providing a bias voltage for the mirror transistor (602) may be connected to the gate node of the mirror transistor (602). In this regard, 1.2 V may be provided to the drain node of the mirror transistor (602).

[0109] In one embodiment, the operational amplifier (604) may include a positive input terminal connected between the second resistor (520b) and the third resistor (520c) of the resistor ladder (520), a negative input terminal connected to the drain node of the mirror transistor (602), and an output terminal connected to the gate node of the mirror transistor (602). The operational amplifier (604) provides a three-divided power supply voltage V at the junction between the second resistor (520b) and the third resistor (520c). DD A bias voltage for the mirror transistor (602) can be generated based on / 3 (e.g., 1.2V) and output to the gate node of the mirror transistor (602). The operational amplifier (604) is based on the analog power supply voltage V DD_ANA (608) (e.g., 1.8V) can be input to the power supply terminal and driven by the analog power voltage.

[0110] FIG. 7 shows a power amplifier circuit including a bias circuit of a multi-stacked operational amplifier structure according to one embodiment.

[0111] Referring to FIG. 7, the power amplifier (700) may include an amplifier circuit (522) and a bias circuit (524). The amplifier circuit (522) may include a first transistor (502), a second transistor (504), and a third transistor (506), as well as at least one additional stacked transistor (e.g., a fourth transistor (702)) connected in a cascode structure stacked between the power supply voltage VDD (516) (e.g., 3.6 V) and ground (GND). The bias circuit (524) may include at least one additional operational amplifier (e.g., a third operational amplifier (704)), a first operational amplifier (512), and a second operational amplifier (514) that provide a third bias voltage, a first bias voltage, and a second bias voltage, respectively, to the fourth transistor (702), the first transistor (502), and the second transistor (504). In one embodiment, the amplifier circuit (522) is configured with N stacked power amplifiers, and the bias circuit (524) may include (N-1) stacked operational amplifiers.

[0112] In one embodiment, the power amplifier (700) may further include a resistor ladder (520) composed of N resistors (e.g., a fourth resistor (706), a first resistor (520a), a second resistor (520b), and a third resistor (520c)) connected in series between the power supply voltage VDD (516) and ground. The first transistor (502), the second transistor (504), and the third transistor (506) may be substantially similar to the description provided above with reference to FIG. 5. The first operational amplifier (512), the second operational amplifier (514), the first resistor (520a), the second resistor (520b), and the third resistor (520c) may be substantially similar to the description provided above with reference to FIG. 5.

[0113] In one embodiment, the drain node of the fourth transistor (702) can receive a power supply voltage (516) through an inductor coil (508), and the source node of the fourth transistor (702) is connected to the drain node of the first transistor (502), so that the fourth transistor (702), the first transistor (502), the second transistor (504), and the third transistor (506) can form a stacked cascode structure.

[0114] In one embodiment, an input signal RF for a power amplifier (700) IN (e.g., input voltage V IN (510)) is provided as the gate node of the third transistor (506) and can be amplified by an amplifier circuit (522) (e.g., the third transistor (506), the second transistor (504), the first transistor (502), and the fourth transistor (702)). Input voltage V IN Output signal RF corresponding to (510) OUT (e.g., output voltage V OUT (518)) can be provided at the drain node of the fourth transistor (702).

[0115] In one embodiment, the third operational amplifier (704) is at power supply voltage V DD Reference voltage distributed from (516) (e.g., V DD A positive input terminal connected to *((N-1) / N)), a negative input terminal connected to the source node of the fourth transistor (702) and the drain node of the first transistor (502), an output terminal connected to the gate node of the fourth transistor (702) to provide the third bias voltage, and a power supply voltage V DD It may include a power supply terminal connected to (516) and a ground terminal. In one embodiment, the third operational amplifier (704) has a power supply voltage V at a positive input terminal. DD Power supply voltage distributed from (516) (e.g., V DD*((N-1) / N)) is provided, and the ground terminal of the third operational amplifier (704) can be connected to the power supply terminal of the first operational amplifier (512).

[0116] In one embodiment, the power supply voltage V DD (516) can be distributed by a resistor ladder (520) composed of resistors connected in series (e.g., a fourth resistor (706), a first resistor (520a), a second resistor (520b), and a third resistor (520c)) and provided to the positive input terminals of a third operational amplifier (704), a first operational amplifier (512), and a second operational amplifier (514). In one embodiment, the positive input terminal of the third operational amplifier (704) can be connected between the fourth resistor (706) and the first resistor (520a).

[0117] In one embodiment, the power amplifier (700) may further include a mirror transistor (602) corresponding to the third transistor (506). The mirror transistor (602) has a gate node connected to the gate node of the third transistor (506), an analog power supply voltage V DD_ANA It may include a drain node connected to a reference current source supplied with (608) (e.g., 1.8 V), and a source node connected to ground. An operational amplifier (604) providing a bias voltage for the mirror transistor (602) may be connected to the gate node of the mirror transistor (602). In this regard, 1.2 V may be provided to the drain node of the mirror transistor (602).

[0118] In one embodiment, the positive input terminal of the operational amplifier (604) may be connected between the second resistor (520b) and the third resistor (520c) of the resistor ladder (520), the negative input terminal of the operational amplifier (604) may be connected to the drain node of the mirror transistor (602), and the output terminal of the operational amplifier (604) may be connected to the gate node of the mirror transistor (602). The operational amplifier (604) is provided with an N-divided power supply voltage V at the junction between the second resistor (520b) and the third resistor (520c). DD A bias voltage for the mirror transistor (602) can be generated based on / N (e.g., 1.2V) and output to the gate node of the mirror transistor (602). The operational amplifier (604) can generate an analog power supply voltage V DD_ANA (608) (e.g., 1.8V) can be input to the power supply terminal and driven by the analog power voltage.

[0119] In one embodiment, the power amplifier (700) is provided with source voltages (e.g., V) to be supplied as a supply power for the remaining operational amplifiers (e.g., first operational amplifier (512) and second operational amplifier (514)) excluding the third operational amplifier (704) (e.g., the top-stacked operational amplifier). SS_N-1 , V SS_2 , and V SS_1 It may further include a voltage regulator (708) that generates a power supply voltage V. The voltage regulator (708) generates a power supply voltage V DD The above source voltages can be generated based on (516). By using a voltage regulator (708), the power amplifier (700) can generate the power supply voltage V DD (516) and analog power supply voltage V DD_ANA(608) In addition, operational amplifiers (e.g., third operational amplifier (704), first operational amplifier (512) and second operational amplifier (514)) can be operated without using additional power supply voltage for the bias circuit (524).

[0120] A power amplifier (500) according to one embodiment may include an amplifier circuit (522) comprising a first transistor (502), a second transistor (504), and a third transistor (506) connected in a stacked cascode structure between a power supply voltage (516) and ground, and a bias circuit (524) comprising a first operational amplifier (512) configured to provide a first bias voltage to the first transistor and a second operational amplifier (514) configured to provide a second bias voltage to the second transistor. The first operational amplifier may include a positive input terminal connected to a first reference voltage distributed from the power supply voltage, a negative input terminal connected to a source node of the first transistor, an output terminal configured to provide the first bias voltage to a gate node of the first transistor, a positive power supply terminal connected to the power supply voltage, and a negative power supply terminal. The second operational amplifier may include a positive input terminal connected to a second reference voltage distributed from the power supply voltage, a negative input terminal connected to the source node of the second transistor, an output terminal configured to provide the second bias voltage to the gate node of the second transistor, a positive power supply terminal connected to the negative power supply terminal of the first operational amplifier, and a negative power supply terminal connected to ground.

[0121] In one embodiment, the power amplifier circuit may further include a resistor ladder comprising a first resistor (520a), a second resistor (520b), and a third resistor (520c) connected in series between the power supply voltage and the ground. The positive input terminal of the first operational amplifier may be connected to the resistor ladder between the first resistor and the second resistor, and the positive input terminal of the second operational amplifier may be connected to the resistor ladder between the second resistor and the third resistor.

[0122] In one embodiment, at least one of the first resistor, the second resistor, or the third resistor may be a variable resistor.

[0123] In one embodiment, an input RF (radio frequency) signal is received through the gate node of the third transistor, and an amplified output RF signal corresponding to the input RF signal can be output through the drain node of the first transistor.

[0124] In one embodiment, the power amplifier may further include an inductor coil connected between the power supply voltage and the drain node of the first transistor.

[0125] In one embodiment, the amplifier circuit may further include a fourth transistor (702) connected in a cascode structure stacked on the first transistor. The bias circuit may further include a third operational amplifier (704) configured to provide a bias voltage to the fourth transistor.

[0126] In one embodiment, the power amplifier may further include a voltage regulator (708) configured to generate source voltages to be provided to the first operational amplifier and the second operational amplifier based on the power supply voltage.

[0127] In one embodiment, the amplifier circuit may further include an analog bias circuit comprising a mirror transistor (602) corresponding to the third transistor and a third operational amplifier (604) configured to provide a third bias voltage to the mirror transistor. The third operational amplifier may include a positive input terminal connected to an analog power supply voltage, a negative input terminal connected to the positive input terminal of the second operational amplifier, a positive power supply terminal connected to the analog power supply voltage, and a negative power supply terminal connected to ground. The mirror transistor may include a gate node connected to the gate node of the third transistor, a drain node connected to the analog power supply voltage through a reference current source, and a source node connected to ground.

[0128] In one embodiment, the first transistor, the second transistor, and the third transistor may be CMOS (complementary MOS (metal-oxide-semiconductor)) transistors.

[0129] In one embodiment, the amplifier circuit may be configured to be used in the transmission path of an RF communication circuit configured to support a mmWave (millimeter wave) frequency band.

[0130] In a communication circuit including a transmission path according to one embodiment, the transmission path may include one or more power amplifiers. At least one power amplifier (500) among the one or more power amplifiers may include an amplifier circuit (522) including a first transistor (502), a second transistor (504), and a third transistor (506) connected in a stacked cascode structure between a power supply voltage (516) and ground, and a bias circuit (524) including a first operational amplifier (512) configured to provide a first bias voltage to the first transistor and a second operational amplifier (514) configured to provide a second bias voltage to the second transistor. The first operational amplifier may include a positive input terminal connected to a first reference voltage distributed from the power supply voltage, a negative input terminal connected to the source node of the first transistor, an output terminal configured to provide the first bias voltage to the gate node of the first transistor, a positive power supply terminal connected to the power supply voltage, and a negative power supply terminal. The second operational amplifier may include a positive input terminal connected to a second reference voltage distributed from the power supply voltage, a negative input terminal connected to the source node of the second transistor, an output terminal configured to provide the second bias voltage to the gate node of the second transistor, a positive power supply terminal connected to the negative power supply terminal of the first operational amplifier, and a negative power supply terminal connected to ground.

[0131] In one embodiment, the at least one power amplifier may further include a resistor ladder comprising a first resistor (520a), a second resistor (520b), and a third resistor (520c) connected in series between the power supply voltage and the ground. The positive input terminal of the first operational amplifier may be connected to the resistor ladder between the first resistor and the second resistor, and the positive input terminal of the second operational amplifier may be connected to the resistor ladder between the second resistor and the third resistor.

[0132] In one embodiment, at least one of the first resistor, the second resistor, or the third resistor may be a variable resistor.

[0133] In one embodiment, an input RF (radio frequency) signal is received through the gate node of the third transistor, and an amplified output RF signal corresponding to the input RF signal can be output through the drain node of the first transistor.

[0134] In one embodiment, the at least one power amplifier may further include an inductor coil connected between the power supply voltage and the drain node of the first transistor.

[0135] In one embodiment, the amplifier circuit may further include a fourth transistor (702) connected in a cascode structure stacked on the first transistor. The bias circuit may further include a third operational amplifier (704) configured to provide a bias voltage to the fourth transistor.

[0136] In one embodiment, the at least one power amplifier may further include a voltage regulator (708) configured to generate source voltages to be provided to the first operational amplifier and the second operational amplifier based on the power supply voltage.

[0137] In one embodiment, the at least one power amplifier may further include an analog bias circuit comprising a mirror transistor (602) corresponding to the third transistor and a third operational amplifier (604) configured to provide a third bias voltage to the mirror transistor. The third operational amplifier may include a positive input terminal connected to an analog power supply voltage, a negative input terminal connected to the positive input terminal of the second operational amplifier, a positive power supply terminal connected to the analog power supply voltage, and a negative power supply terminal connected to ground. The mirror transistor may include a gate node connected to the gate node of the third transistor, a drain node connected to the analog power supply voltage through a reference current source, and a source node connected to ground.

[0138] In one embodiment, the first transistor, the second transistor, and the third transistor may be CMOS (complementary MOS (metal-oxide-semiconductor)) transistors.

[0139] In one embodiment, the transmission path may be configured to support a mmWave (millimeter wave) frequency band.

[0140] According to embodiments of the present disclosure, a power amplifier comprises a first transistor, a second transistor, and a third transistor connected in series between a power supply voltage and ground, wherein the drain of the first transistor is configured to provide a voltage amplified based on an input voltage at the gate of the third transistor, a first operational amplifier configured to provide a first bias voltage to the first transistor, a second operational amplifier configured to provide a second bias voltage to the second transistor, and a first resistor, a second resistor, and a third resistor connected in series between a power supply voltage and ground.

[0141] The positive power supply terminal of the first operational amplifier can be connected to a power supply voltage, and the positive power supply terminal of the second operational amplifier can be connected to the negative power supply terminal of the first operational amplifier.

[0142] The negative power supply terminal of the second operational amplifier can be connected to ground.

[0143] The node between the first resistor and the second resistor can be connected to the non-inverting input of the first operational amplifier, and the node between the second resistor and the third resistor can be connected to the non-inverting input of the second operational amplifier.

[0144] The inverting input of the first operational amplifier can be connected to the source of the first transistor and the drain of the second transistor.

[0145] The inverting input of the second operational amplifier can be connected to the source of the second transistor and the drain of the third transistor.

[0146] The power amplifier may further include a third operational amplifier. The output terminal of the third operational amplifier may be connected to the gate of the third transistor.

[0147] The power amplifier may further include a mirror transistor. The output terminal of the third operational amplifier may be connected between the gate of the mirror transistor and the gate of the third transistor.

[0148] The electronic device according to the various embodiments disclosed in this document may be of various forms. The electronic device may include, for example, a portable communication device (e.g., a smartphone), a computer device, a portable multimedia device, a portable medical device, a camera, a wearable device, or a consumer electronics device. The electronic device according to the embodiments of this document is not limited to the devices described above.

[0149] The various embodiments of this document and the terms used therein are not intended to limit the technical features described in this document to specific embodiments, and should be understood to include various modifications, equivalents, or substitutions of said embodiments. In connection with the description of the drawings, similar reference numerals may be used for similar or related components. The singular form of a noun corresponding to an item may include one or more of said items unless the relevant context clearly indicates otherwise. In this document, phrases such as "A or B," "at least one of A and B," "at least one of A or B," "A, B or C," "at least one of A, B and C," and "at least one of A, B, or C" may each include any one of the items listed together in the corresponding phrase, or all possible combinations thereof. Terms such as "first," "second," or "first" or "second" may be used simply to distinguish said components from other said components and do not limit said components in any other aspect (e.g., importance or order). Where any (e.g., 1st) component is referred to as “coupled” or “connected” to another (e.g., 2nd) component, with or without the terms “functionally” or “communicationly,” it means that said any component may be connected to said other component directly (e.g., via a wire), wirelessly, or through a third component.

[0150] The term “module” as used in the various embodiments of this document may include a unit implemented in hardware, software, or firmware, and may be used interchangeably with terms such as logic, logic block, component, or circuit, for example. A module may be a component formed integrally, or a minimum unit of said component or a part thereof that performs one or more functions. For example, according to one embodiment, a module may be implemented in the form of an application-specific integrated circuit (ASIC).

[0151] Various embodiments of the present document may be implemented as software (e.g., program (140)) comprising one or more instructions stored in a storage medium (e.g., internal memory (136) or external memory (138)) readable by a machine (e.g., electronic device (101)). For example, a processor (e.g., processor (120)) of the machine (e.g., electronic device (101)) may call at least one of the one or more instructions stored in the storage medium and execute it. This enables the machine to be operated to perform at least one function according to the at least one called instruction. The one or more instructions may include code generated by a compiler or code that can be executed by an interpreter. The storage medium readable by the machine may be provided in the form of a non-transitory storage medium. Here, 'non-temporary' simply means that the storage medium is a tangible device and does not contain a signal (e.g., electromagnetic waves), and the term does not distinguish between cases where data is stored semi-permanently and cases where it is stored temporarily.

[0152] According to one embodiment, the method according to the various embodiments disclosed herein may be provided by being included in a computer program product. The computer program product may be traded between a seller and a buyer as a product. The computer program product may be distributed in the form of a device-readable storage medium (e.g., compact disc read-only memory (CD-ROM)) or an application store (e.g., Play Store). TM It can be distributed online (e.g., downloaded or uploaded) through ) or directly between two user devices (e.g., smartphones). In the case of online distribution, at least a portion of the computer program product may be temporarily stored or temporarily created on a device-readable storage medium, such as the memory of a manufacturer's server, an application store's server, or a relay server.

[0153] According to various embodiments, each component (e.g., module or program) of the components described above may include a singular or multiple entities, and some of the multiple entities may be separated and placed in other components. According to various embodiments, one or more of the components or operations of the aforementioned components may be omitted, or one or more other components or operations may be added. Generally or additionally, multiple components (e.g., module or program) may be integrated into a single component. In this case, the integrated component may perform one or more functions of each of the multiple components in the same or similar manner as those performed by the corresponding component among the multiple components prior to integration. According to various embodiments, operations performed by the module, program, or other components may be executed sequentially, in parallel, iteratively, or heuristically, or one or more of the operations may be executed in a different order, omitted, or one or more other operations may be added.

Claims

1. In a power amplifier (500), An amplifier circuit (522) comprising a first transistor (502), a second transistor (504), and a third transistor (506) connected in a stacked cascode structure between a power supply voltage (516) and ground; and A bias circuit (524) comprising a first operational amplifier (512) configured to provide a first bias voltage to the first transistor and a second operational amplifier (514) configured to provide a second bias voltage to the second transistor, and The first operational amplifier comprises a positive input terminal connected to a first reference voltage distributed from the power supply voltage, a negative input terminal connected to the source node of the first transistor, an output terminal configured to provide the first bias voltage to the gate node of the first transistor, a positive power supply terminal connected to the power supply voltage, and a negative power supply terminal. The second operational amplifier is a power amplifier comprising a positive input terminal connected to a second reference voltage distributed from the power supply voltage, a negative input terminal connected to the source node of the second transistor, an output terminal configured to provide the second bias voltage to the gate node of the second transistor, a positive power supply terminal connected to the negative power supply terminal of the first operational amplifier, and a negative power supply terminal connected to ground.

2. In Paragraph 1, It further includes a resistor ladder comprising a first resistor (520a), a second resistor (520b), and a third resistor (520c) connected in series between the power supply voltage and the ground, and A power amplifier in which the positive input terminal of the first operational amplifier is connected to the resistance ladder between the first resistor and the second resistor, and the positive input terminal of the second operational amplifier is connected to the resistance ladder between the second resistor and the third resistor.

3. A power amplifier according to claim 2, wherein at least one of the first resistor, the second resistor, or the third resistor is a variable resistor.

4. In any one of paragraphs 1 to 3, An input RF (radio frequency) signal is received through the gate node of the third transistor, and A power amplifier that outputs an amplified output RF signal corresponding to the input RF signal through the drain node of the first transistor.

5. A power amplifier according to any one of claims 1 to 4, further comprising an inductor coil connected between the power supply voltage and the drain node of the first transistor.

6. In any one of paragraphs 1 to 5, The amplifier circuit further includes a fourth transistor (702) connected in a cascode structure stacked on the first transistor, and The above bias circuit is a power amplifier further comprising a third operational amplifier (704) configured to provide a bias voltage to the fourth transistor.

7. In Paragraph 6, A power amplifier further comprising a voltage regulator (708) configured to generate source voltages to be provided to the first operational amplifier and the second operational amplifier based on the above power supply voltage.

8. In any one of paragraphs 1 through 7, The analog bias circuit further includes a mirror transistor (602) corresponding to the third transistor and a third operational amplifier (604) configured to provide a third bias voltage to the mirror transistor. The third operational amplifier includes a positive input terminal connected to an analog power supply voltage, a negative input terminal connected to the positive input terminal of the second operational amplifier, a positive power supply terminal connected to the analog power supply voltage, and a negative power supply terminal connected to ground. The mirror transistor is a power amplifier comprising a gate node connected to the gate node of the third transistor, a drain node connected to the analog power supply voltage through a reference current source, and a source node connected to ground.

9. In any one of paragraphs 1 through 8, A power amplifier in which the first transistor, the second transistor, and the third transistor are CMOS (complementary MOS (metal-oxide-semiconductor)) transistors.

10. In any one of paragraphs 1 through 9, The above amplifier circuit is a power amplifier configured to be used in the transmission path of an RF communication circuit configured to support a mmWave (millimeter wave) frequency band.

11. In a communication circuit including a transmission path, The above transmission path includes one or more power amplifiers, and at least one power amplifier (500) among the one or more power amplifiers is, An amplifier circuit (522) comprising a first transistor (502), a second transistor (504), and a third transistor (506) connected in a stacked cascode structure between a power supply voltage (516) and ground; and A bias circuit (524) comprising a first operational amplifier (512) configured to provide a first bias voltage to the first transistor and a second operational amplifier (514) configured to provide a second bias voltage to the second transistor, and The first operational amplifier comprises a positive input terminal connected to a first reference voltage distributed from the power supply voltage, a negative input terminal connected to the source node of the first transistor, an output terminal configured to provide the first bias voltage to the gate node of the first transistor, a positive power supply terminal connected to the power supply voltage, and a negative power supply terminal. The communication circuit comprising: a second operational amplifier connected to a second reference voltage distributed from the power supply voltage; a negative input terminal connected to the source node of the second transistor; an output terminal configured to provide the second bias voltage to the gate node of the second transistor; a positive power supply terminal connected to the negative power supply terminal of the first operational amplifier; and a negative power supply terminal connected to ground.

12. In claim 11, the at least one power amplifier is, It further includes a resistor ladder comprising a first resistor (520a), a second resistor (520b), and a third resistor (520c) connected in series between the power supply voltage and the ground, and A communication circuit in which the positive input terminal of the first operational amplifier is connected to the resistor ladder between the first resistor and the second resistor, and the positive input terminal of the second operational amplifier is connected to the resistor ladder between the second resistor and the third resistor.

13. A communication circuit according to claim 12, wherein at least one of the first resistor, the second resistor, or the third resistor is a variable resistor.

14. In any one of paragraphs 11 through 13, An input RF (radio frequency) signal is received through the gate node of the third transistor, and A communication circuit in which an amplified output RF signal corresponding to the input RF signal is output through the drain node of the first transistor.

15. A communication circuit according to any one of claims 11 to 14, wherein the at least one power amplifier further comprises an inductor coil connected between the power supply voltage and the drain node of the first transistor.

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