Electronic device comprising output voltage switching circuit, and method therefor

Abstract

The present disclosure relates to a 5G or 6G communication system for supporting data a transmission rate higher than that of a 4G communication system such as LTE. The electronic device comprises: a first transistor connected to a first control input node to which a first delay circuit is connected, a first voltage node and an output voltage node; a second transistor connected to a second control input node to which a first pulse-width increasing circuit is connected, a second voltage node and a third transistor; a third transistor connected to a third control input node to which a second delay circuit is connected, the output voltage node and the second transistor; a fourth transistor connected to a fourth control input node to which a third delay circuit is connected, a third voltage node and the output voltage node; and a first OR gate for connecting the first delay circuit, the second delay circuit and the first pulse-width increasing circuit.

Description

Electronic device and method including an output voltage switching circuit

[0001] The present disclosure relates to an output voltage switching circuit, and more specifically, to an electronic device and method comprising a circuit for multi-level output voltage switching.

[0002] Looking back at the evolution of wireless communication through successive generations, technologies have been developed primarily for human-oriented services, such as voice, multimedia, and data. Following the commercialization of 5G (5th-generation) communication systems, connected devices, which have been increasing explosively, are expected to be connected to communication networks. Examples of networked objects include vehicles, robots, drones, home appliances, displays, smart sensors installed in various infrastructures, construction machinery, and factory equipment. Mobile devices are expected to evolve into various form factors, such as augmented reality glasses, virtual reality headsets, and holographic devices. In the 6G (6th-generation) era, efforts are underway to develop improved 6G communication systems to connect hundreds of billions of devices and objects to provide diverse services. For this reason, 6G communication systems are being referred to as "beyond 5G" systems.

[0003] In the 6G communication system predicted to be realized around 2030, the maximum transmission speed is tera (i.e., 1,000 gigabit) bps, and the wireless latency is 100 microseconds (μsec). In other words, compared to the 5G communication system, the transmission speed in the 6G communication system is 50 times faster, and the wireless latency is reduced to one-tenth.

[0004] To achieve such high data transmission speeds and ultra-low latency, 6G communication systems are being considered for implementation in the terahertz band (e.g., the 95 GHz to 3 terahertz (3 THz) band). In the terahertz band, due to more severe path loss and atmospheric absorption compared to the millimeter wave (mmWave) band introduced in 5G, the importance of technology capable of guaranteeing signal reach, or coverage, is expected to increase. As key technologies to ensure coverage, radio frequency (RF) devices, antennas, new waveforms that offer better coverage than orthogonal frequency division multiplexing (OFDM), beamforming, and multi-antenna transmission technologies such as massive multiple-input and multiple-output (massive MIMO), full-dimensional MIMO (FD-MIMO), array antennas, and large-scale antennas must be developed. In addition, new technologies such as metamaterial-based lenses and antennas, high-dimensional spatial multiplexing technology using orbital angular momentum (OAM), and reconfigurable intelligent surface (RIS) are being discussed to improve coverage of terahertz band signals.

[0005] In addition, to improve frequency efficiency and system network, development is underway in 6G communication systems for full duplex technology, in which uplink and downlink simultaneously utilize the same frequency resources at the same time; network technology that integrates satellites and HAPS (high-altitude platform stations); network structure innovation technology that supports mobile base stations and enables network operation optimization and automation; dynamic spectrum sharing technology through collision avoidance based on spectrum usage prediction; AI-based communication technology that utilizes AI (artificial intelligence) from the design stage and internalizes end-to-end AI support functions to realize system optimization; and next-generation distributed computing technology that realizes services of complexity exceeding the limits of terminal computing capabilities by utilizing ultra-high performance communication and computing resources (mobile edge computing (MEC), cloud, etc.). In addition, attempts are continuing to further strengthen connectivity between devices, further optimize networks, promote the softwareization of network entities, and increase the openness of wireless communication through the design of new protocols to be used in 6G communication systems, the implementation of hardware-based security environments, the development of mechanisms for the safe utilization of data, and the development of technologies regarding privacy maintenance methods.

[0006] Due to the research and development of such 6G communication systems, it is expected that a new dimension of hyper-connected experience will become possible through the hyper-connectivity of 6G communication systems, which encompasses not only connections between objects but also connections between people and objects. Specifically, it is projected that 6G communication systems will enable the provision of services such as truly immersive extended reality (truly immersive XR), high-fidelity mobile holograms, and digital replicas. Furthermore, services such as remote surgery, industrial automation, and emergency response, which are provided through 6G communication systems with enhanced security and reliability, will be applied in various fields including industry, healthcare, automotive, and home appliances.

[0007] In one embodiment of the present disclosure, an electronic device comprising an output voltage switching circuit may be provided. The electronic device may include a first control input node connected to a first delay circuit and a first transistor connected to a first voltage node and an output voltage node. The electronic device may include a second control input node connected to a first pulse width increase circuit and a second transistor connected to a second voltage node and a third transistor. The electronic device may include a third control input node connected to a second delay circuit and the third transistor connected to the output voltage node and the second transistor. In the electronic device, the source node of the third transistor may be connected to the source node of the second transistor, or the drain node of the third transistor may be connected to the drain node of the second transistor. The electronic device may include a fourth control input node connected to a third delay circuit and a fourth transistor connected to a third voltage node and the output voltage node. The electronic device may include a first OR gate connecting the first delay circuit, the second delay circuit, and the first pulse width increase circuit.

[0008] In one embodiment of the present disclosure, a method performed by an electronic device may be provided. The electronic device may include a first transistor associated with a first voltage, a second transistor and a third transistor associated with a second voltage, and a fourth transistor associated with a third voltage. The method may include the step of inputting a first signal to the gate node of the first transistor connected to a first delay circuit. The method may include the step of inputting a second signal to the gate node of the first transistor connected to the first delay circuit, the gate node of the third transistor connected to a second delay circuit, and the gate node of the fourth transistor connected to a third delay circuit, and inputting the first signal to the gate node of the second transistor connected to a first pulse width increase circuit. In the method, the first pulse width increase circuit may be connected to a first OR gate connected to the first delay circuit and the second delay circuit. The method may include the step of inputting the first signal to the gate node of the third transistor connected to the second delay circuit. In the above method, the source node of the third transistor may be connected to the source node of the second transistor, or the drain node of the third transistor may be connected to the drain node of the second transistor.

[0009] FIG. 1 illustrates the configuration of a multi-level output voltage switching circuit according to one embodiment of the present disclosure.

[0010] FIGS. 2a and 2b illustrate a back-to-back switch according to one embodiment of the present disclosure.

[0011] FIG. 3a illustrates a transistor operating as a switch according to one embodiment of the present disclosure.

[0012] FIG. 3b illustrates a multi-level output voltage switching circuit according to one embodiment of the present disclosure.

[0013] FIG. 4 illustrates the switching of an output voltage according to one embodiment of the present disclosure.

[0014] FIG. 5 illustrates an output voltage waveform in a switch operation according to one embodiment of the present disclosure.

[0015] FIG. 6 illustrates a multi-level output voltage switching circuit including a phase inversion circuit according to one embodiment of the present disclosure.

[0016] FIG. 7 illustrates the switching of an output voltage according to one embodiment of the present disclosure.

[0017] FIG. 8 illustrates an output voltage waveform in a switch operation according to one embodiment of the present disclosure.

[0018] FIG. 9 illustrates the operation of a multi-level output voltage switching circuit according to one embodiment of the present disclosure.

[0019] FIGS. 10a and FIGS. 10b illustrate a multi-level output voltage waveform according to one embodiment of the present disclosure in comparison with an ideal situation.

[0020] FIGS. 11a and FIGS. 11b illustrate a power amplifier gain supplied with an output voltage according to one embodiment of the present disclosure, compared with an ideal situation.

[0021] FIG. 12 illustrates a multi-level output voltage switching circuit including an inverter according to one embodiment of the present disclosure.

[0022] FIGS. 13a and FIGS. 13b illustrate a multi-level output voltage switching circuit including a logic operation circuit according to one embodiment of the present disclosure.

[0023] FIG. 14 illustrates a multi-level output voltage switching circuit with an extended output voltage level according to one embodiment of the present disclosure.

[0024] FIGS. 15a and 15b illustrate a multi-level output voltage waveform according to one embodiment of the present disclosure in comparison to an ideal situation.

[0025] FIGS. 16a and 16b illustrate a multi-level output voltage switching circuit including a deadtime detection circuit and a multiplexer according to one embodiment of the present disclosure.

[0026] FIGS. 17a and FIGS. 17b illustrate a multi-level output voltage switching circuit including a current sense unit according to one embodiment of the present disclosure.

[0027] FIG. 18 illustrates an operation for controlling a transistor of an output voltage switching circuit according to one embodiment of the present disclosure.

[0028] FIG. 19a illustrates a multi-level output voltage switching circuit comprising a delay circuit, an OR gate, and a pulse width increasing circuit according to one embodiment of the present disclosure.

[0029] FIG. 19b illustrates a delay circuit and a pulse width increasing circuit according to one embodiment of the present disclosure.

[0030] FIG. 20 illustrates a multi-level output voltage switching circuit comprising a delay circuit, an OR gate, and a pulse width increasing circuit according to one embodiment of the present disclosure.

[0031] FIG. 21 illustrates a multi-level output voltage switching circuit with an extended output voltage level according to one embodiment of the present disclosure.

[0032] FIG. 22 illustrates a Supply Modulator Integrated Circuit (SMIC) according to one embodiment of the present disclosure.

[0033] FIG. 23 illustrates a Switched-Capacitor Voltage Divider (SCVD) according to one embodiment of the present disclosure.

[0034] FIG. 24a illustrates a 4-level LSSW (Level Selection Switch) according to one embodiment of the present disclosure.

[0035] FIG. 24b illustrates a bootstrap circuit for an LSSW according to one embodiment of the present disclosure.

[0036] FIGS. 25a and FIGS. 25b illustrate simulation results of an SMIC according to one embodiment of the present disclosure.

[0037] FIG. 26 illustrates an operation for controlling a transistor of an output voltage switching circuit according to one embodiment of the present disclosure.

[0038] In describing the present disclosure, technical details that are well known in the technical field to which the present disclosure belongs and are not directly related to the present disclosure are omitted. This is intended to convey the essence of the present disclosure more clearly without obscuring it by omitting unnecessary explanations. The terms used in this specification will be briefly explained, and the present disclosure will be described in detail.

[0039] The terms used in this disclosure have been selected to be as widely used and general as possible, taking into account their functions within this disclosure; however, these terms may vary depending on the intent of those skilled in the art, case law, the emergence of new technologies, etc. Additionally, in specific cases, terms have been selected at the applicant's discretion, and in such cases, their meanings will be described in detail in the relevant explanatory sections. Therefore, terms used in this disclosure should be defined not merely by their names, but based on their meanings and the overall content of this disclosure.

[0040] Singular expressions may include plural expressions unless the context clearly indicates otherwise. Terms used herein, including technical or scientific terms, may have the same meaning as generally understood by those skilled in the art as described in this specification. Additionally, terms including ordinal numbers, such as "first" or "second," used in this specification may be used to describe various components, but said components should not be limited by said terms. Such terms are used solely for the purpose of distinguishing one component from another.

[0041] When a part of a specification is described as "comprising" a certain component, this means that, unless specifically stated otherwise, it does not exclude other components but may include additional components. Furthermore, terms such as "part" or "module" as used in the specification refer to a unit that processes at least one function or operation, and this may be implemented in hardware or software, or as a combination of hardware and software.

[0042] Embodiments of the present disclosure are described below with reference to the attached drawings so that those skilled in the art can easily implement the invention. However, the present disclosure may be embodied in various different forms and is not limited to the embodiments described herein. Furthermore, in order to clearly explain the present disclosure in the drawings, parts unrelated to the explanation have been omitted, and similar parts throughout the specification are denoted by similar reference numerals.

[0043] The present disclosure will be described below with reference to the attached drawings.

[0044] FIG. 1 illustrates the configuration of a multi-level output voltage switching circuit according to one embodiment of the present disclosure.

[0045] Referring to FIG. 1, the multi-level output voltage switching circuit (100) may include transistors (120, 142, 144, 160). In this disclosure, "output voltage switching circuit" may be used interchangeably with "LSSW (Level Selection Switch)". As described with reference to FIG. 2a and 2b, the transistors (142, 144) may be connected back-to-back. For example, the transistors (120, 142, 144, 160) may include Metal Oxide Semiconductor Field Effect Transistors (MOSFETs). For example, the MOSFETs may include N-channel MOSFETs, P-channel MOSFETs, or Complementary Metal Oxide Semiconductor (CMOS) transistors. Although the embodiments of the present disclosure are described assuming an N-channel MOSFET, the embodiments of the present disclosure are not limited to N-channel MOSFETs and can be applied in the same or similar manner even when using similar transistors known in the art, such as P-channel MOSFETs, CMOS, etc.

[0046] In one embodiment, a transistor (120, 142, 144, 160) (e.g., MOSFET) may include a body diode (162). The body diode (162) may refer to a parasitic diode that naturally exists within the transistor (e.g., MOSFET). For example, in an N-channel MOSFET, the body diode (162) may be formed from the anode to the cathode direction by the PN junction, which is a fundamental characteristic. For example, in the case of a P-channel MOSFET, the body diode may be formed from the anode to the cathode direction. In this disclosure, "transistor" may mean a MOSFET including a body diode.

[0047] In one embodiment, the transistors (120, 142, 144, 160) are controlled one by one, and the output voltage (V out ) can be changed to a first voltage (V1), a second voltage (V2), or a third voltage (V3). In the present disclosure, voltage may mean a voltage applied to a transistor (120, 142, 160), and output voltage may mean a voltage output from a transistor (120, 140, 160). The first voltage (V1) may be greater than the second voltage (V2), the second voltage (V2) may be greater than the third voltage (V3), and the first voltage (V1) may be greater than the third voltage (V3).

[0048] In one embodiment, when the output voltage changes to a first voltage (V1), a second voltage (V2), or a third voltage (V3), the drain node of the first transistor (120) is connected to the first voltage (V1) node, and the source node of the first transistor (120) is connected to the output voltage (V out It can be connected to the ) node. Since the first voltage (V1) is always greater than or equal to the output voltage, unwanted power loss may not occur through the body diode of the first transistor (120). The drain node of the fourth transistor (160) is connected to the output voltage (V out It is connected to the ) node, and the source node of the fourth transistor (160) can be connected to the first voltage (V1) node. Since the third voltage (V3) is always less than or equal to the output voltage, unwanted power loss may not occur through the body diode (162) of the fourth transistor (160). On the other hand, the second voltage (V2) node and the output voltage (V out If the nodes are connected by a single transistor, unwanted power loss may occur through the body diode of the single transistor because the output voltage may be greater or smaller than the second voltage (V2). The second voltage (V2) node and the output voltage (V out ) node By connecting the second transistor (142) and the third transistor (144) in a back-to-back configuration, the design can be made so that no power loss occurs through the body diode. The back-to-back switch (140) in which the second transistor (142) and the third transistor (144) are connected in a back-to-back configuration will be described in more detail through the drawings (Figs. 2a and 2b) and the description thereof described below.

[0049] FIGS. 2a and 2b illustrate a back-to-back switch according to one embodiment of the present disclosure. The back-to-back switch of FIGS. 2a and 2b may correspond to the back-to-back switch (140) of FIG. 1.

[0050] A back-to-back switch can refer to two transistors configured to function as switches by being connected in opposite directions. For example, connecting MOSFETs back-to-back can mean connecting the source nodes of the two MOSFETs to each other or connecting the drain nodes to each other.

[0051] In one embodiment, two transistors of a back-to-back switch may be turned on or turned off simultaneously by a single control signal. For example, if the control signal turns on two transistors simultaneously, the back-to-back switch may be in a turned-on state. For example, if the control signal turns off two transistors simultaneously, the back-to-back switch may be in a turned-off state.

[0052] Referring to FIG. 2a, when the back-to-back switch is turned on (200a), a current path is created so that current can flow through two back-to-back connected transistors. In the example of FIG. 2a, a current path is created so that current can flow through two N-channel MOSFETs connected back-to-back to a source node.

[0053] Referring to FIG. 2b, when the back-to-back switch is turned off (200b), there is no current path, so current cannot flow through the two back-to-back connected transistors. In the example of FIG. 2b, since the source node and the body diodes of the two N-channel MOSFETs connected back-to-back are connected in opposite directions, there is no current path, so current cannot flow.

[0054] FIG. 3a illustrates a transistor operating as a switch according to one embodiment of the present disclosure.

[0055] Referring to FIG. 3a, the MOSFET switch block (300a) is illustrated as an N-channel MOSFET including a body diode, but a P-channel MOSFET or CMOS may be used. In this disclosure, "transistor" may be used interchangeably with "switch," "MOSFET switch," etc.

[0056] FIG. 3b illustrates a multi-level output voltage switching circuit according to one embodiment of the present disclosure.

[0057] Referring to FIG. 3b, in one embodiment, the multi-level output voltage switching circuit (300b) may be a 3-level output voltage switching circuit. The 3-level output voltage may mean outputting three voltage levels: a first voltage (V1), a second voltage (V2), and a third voltage (V3). The first voltage (V1) may be input through the first voltage (V1) node (310). The second voltage (V2) may be input through the second voltage (V2) node (312). The third voltage (V3) may be input through the third voltage (V3) node (314).

[0058] In one embodiment, the multi-level output voltage switching circuit (300b) may include a switch control unit (320), a first transistor (340), a second transistor (342), a third transistor (344), and a fourth transistor (346). The switch control unit (320) may supply a first control signal (S1), a second control signal (S2), and a third control signal (S3). In the present disclosure, a control signal may refer to a signal input to a transistor gate to turn on or turn off the transistor. For example, in the case of an N-channel MOSFET operating at 1 volt (V), the control signal may be a 1-volt signal or a 0-volt signal. For example, in the case of an N-channel MOSFET operating at 5 volts, the control signal may be a 5-volt signal or a 0-volt signal.

[0059] In one embodiment, a first control signal (S1) may be input through a first control input node (350). A second control signal (S2) may be input through a second control input node (352) and a third control input node (354). For example, the same second control signal (S2) may be input to a second transistor (342) and a third transistor (344). As a result, the second transistor (342) and the third transistor (344) may be turned on or turned off simultaneously under the control of the second control signal (S2). A third control signal (S3) may be input through a fourth control input node (356).

[0060] In one embodiment, the first transistor (340) may be connected to the first voltage (V1) node (310), the output voltage node (330), and the first control input node (350). The second transistor (342) may be connected to the second voltage (V2) node (312), the third transistor (344), and the second control input node (352). The third transistor (344) may be connected to the third control input node (354), the output voltage node (330), and the second transistor (342). For example, the second transistor (342) and the third transistor (344) may be connected back-to-back. For example, the source node of the third transistor (344) may be connected to the source node of the second transistor (342). For example, the drain node of the third transistor (344) may be connected to the drain node of the second transistor (342). The fourth transistor (346) can be connected to the third voltage (V3) node (314), the output voltage node (330), and the fourth control input node (356).

[0061] FIG. 4 illustrates the switching of an output voltage according to one embodiment of the present disclosure.

[0062] With reference to FIG. 4, the operation of the multi-level output voltage switching circuit (300b) of FIG. 3b is described below. In FIG. 4, the same configurations as in FIG. 3b are illustrated using the same reference numerals. Therefore, in describing the configurations of FIG. 4, descriptions that overlap with the descriptions above are omitted. FIG. 4 may be an example of switching from a first voltage (V1) to a second voltage (V2). In this disclosure, the power amplifier is merely an example for illustrative purposes and does not limit the disclosure.

[0063] In one embodiment, in the first operation (400a), the first transistor (340) connected to the first voltage (V1) node may be in a turned-on state. At this time, the first voltage (V1) may be supplied through the first transistor (340) to a power amplifier (420) connected to an output voltage switching circuit.

[0064] A dead time may be required to change from the first voltage (V1) to the second voltage (V2). Dead time refers to the time during which all transistors are in the turned-off state. When controlling switches that perform complementary operations (e.g., a switch applying the first voltage (V1) or the second voltage (V2)), to prevent a short circuit caused by both switches turning on simultaneously, one switch may be turned off and the other switch turned on after a time delay. This time difference can be referred to as dead time. By setting the dead time to an appropriate value, power conversion efficiency and switching losses can be optimized. For example, if the dead time is too long, distortion may occur in the output waveform. For example, if the dead time is too short, a short circuit may occur, resulting in power loss. Since dead time changes sensitively with process and temperature variations, a circuit capable of real-time tracking and optimization may be required.

[0065] In order to change from the first voltage (V1) to the second voltage (V2), all transistors are turned off during the dead time, so the voltage supplied to the power amplifier (420) may decrease. When the voltage decreases, the first transistor (340) associated with the first voltage (V1), the second transistor (342) and the third transistor (344) associated with the second voltage (V2), and their body diodes cannot supply power, so the voltage may continue to decrease.

[0066] In one embodiment, the second operation (400b) may indicate a state in which the voltage supplied to the power amplifier (420) continues to decrease until it drops below the third voltage (V3). In this state, the body diode of the fourth transistor (346) connected to the third voltage (V3) node may be turned on. At this time, the third voltage (V3) may be supplied to the power amplifier (420) connected to the output voltage switching circuit through the body diode of the fourth transistor (346). For example, the third voltage (V3) may be supplied to the power amplifier (420) during dead time.

[0067] In one embodiment, the third operation (400c) may represent a switching process to the second voltage (V2) after a dead time. The second transistor (342) and the third transistor (344) associated with the second voltage (V2) after the dead time may be turned on. At this time, the second voltage (V2) may be supplied to a power amplifier (420) connected to an output voltage switching circuit through the back-to-back connected second transistor (342) and third transistor (344).

[0068] FIG. 5 illustrates an output voltage waveform in a switch operation according to one embodiment of the present disclosure.

[0069] With reference to FIG. 5, the operation (500a) of the switch (V1Switch) associated with the first voltage (V1) and the switch (V2Switch) associated with the second voltage (V2), and the corresponding output voltage waveform (500b) are described below. The switch associated with the first voltage (V1) may correspond to the first transistor (340) of FIG. 4. The switch associated with the second voltage (V2) may correspond to the second transistor (342) and the third transistor (344) of FIG. 4.

[0070] In one embodiment, after the first deadtime (502) of the switch operation (500a) and before the second deadtime (504), the switch associated with the first voltage (V1) may be in a turned-on state, and the switch associated with the second voltage (V2) may be in a turned-off state. For example, the first transistor (440) may be in a turned-on state, and the second transistor (442) and the third transistor (444) may be in a turned-off state. At this time, the output voltage waveform (500b) may represent the first voltage (V1). For example, the first voltage (V1) may be output through the first transistor (340). This may correspond to the first operation (400a) of FIG. 4.

[0071] In one embodiment, during the second dead time (504) of the switch operation (500a), the switch associated with the first voltage (V1) and the switch associated with the second voltage (V2) may be in a turned-off state. For example, the first transistor (340), the second transistor (342), and the third transistor (344) may be in a turned-off state. At this time, the output voltage waveform (500b) may represent the third voltage (V3). For example, the third voltage (V3) may be output through the body diode of the fourth transistor (346). This may correspond to the second operation (400b) of FIG. 4.

[0072] In one embodiment, after the second dead time (504) of the switch operation (500a) and before the third dead time (506), the switch associated with the first voltage (V1) may be in a turned-off state, and the switch associated with the second voltage (V2) may be in a turned-on state. For example, the first transistor (340) may be in a turned-off state, and the second transistor (342) and the third transistor (344) may be in a turned-on state. In this case, the output voltage waveform (500b) may represent the second voltage (V2). For example, the second voltage (V2) may be output through the back-to-back connected second transistor (342) and third transistor (344). This may correspond to the third operation (400c) of FIG. 4.

[0073] In one embodiment, according to the first operation (400a), the second operation (400b), and the third operation (400c), the output voltage waveform (500b) may appear in the order of the first voltage (V1), the third voltage (V3) (dead time), and the second voltage (V2).

[0074] To prevent the phenomenon where multiple voltages are applied simultaneously through the transistor, when operating including the dead time during which all switches are turned off, the ideal output voltage waveform should only have the first voltage (V1) and the second voltage (V2). However, in the output voltage switching circuit (300b) of FIG. 3b and the example of FIG. 4, an unwanted third voltage (V3) is produced during the dead time, and the linearity of circuits such as power amplifiers that operate by receiving the output voltage may be degraded.

[0075] Accordingly, the present disclosure proposes a circuit in which, during operation including dead time, the phase of a transistor control signal associated with a voltage lower than the switching voltage is inverted, or a transistor control signal associated with a voltage equal to or higher than the switching voltage is processed to separately control two back-to-back connected transistors, thereby producing an output voltage waveform similar to an ideal output voltage waveform.

[0076] FIG. 6 illustrates a multi-level output voltage switching circuit including a phase inversion circuit according to one embodiment of the present disclosure.

[0077] Referring to FIG. 6, in one embodiment, the multi-level output voltage switching circuit (600) may be a 3-level output voltage switching circuit. The 3-level may refer to three voltage levels: a first voltage (V1), a second voltage (V2), and a third voltage (V3). The first voltage (V1) may be input through the first voltage (V1) node (610). The second voltage (V2) may be input through the second voltage (V2) node (612). The third voltage (V3) may be input through the third voltage (V3) node (614).

[0078] In one embodiment, the multi-level output voltage switching circuit (600) may include a switch control unit (620), a first transistor (640), a second transistor (642), a third transistor (644), a fourth transistor (646), and a phase inversion circuit (660). The switch control unit (620) may supply a first control signal (S1), a second control signal (S2), and a third control signal (S3). A control signal may refer to a signal input to a transistor gate to turn the transistor on or off. For example, in the case of an N-channel MOSFET operating at 1 volt (V), the control signal may be a 1-volt signal or a 0-volt signal. For example, in the case of an N-channel MOSFET operating at 5 volts, the control signal may be a 5-volt signal or a 0-volt signal.

[0079] In one embodiment, a first control signal (S1) may be input through a first control input node (650). A second control signal (S2) may be input through a third control input node (654). A third control signal (S3) may be input through a fourth control input node (656). Additionally, the third control signal (S3) may be input through a second control input node (652) after its phase is inverted through a phase inversion circuit (660). For example, different control signals may be input to back-to-back connected second transistor (642) and third transistor (644), respectively. For example, the first transistor (640) may be controlled by the first control signal (S1). For example, the third transistor (644) may be controlled by the second control signal (S2). For example, the fourth transistor (646) can be controlled by the third control signal (S3), and the second transistor (642) can be controlled by the opposite phase signal of the third control signal (S3). As a result, the second transistor (642) and the fourth transistor (646) can perform a complementary operation in which one turns off when the other turns on.

[0080] In one embodiment, the first transistor (640) may be connected to the first voltage (V1) node (610), the output voltage node (630), and the first control input node (650). The second transistor (642) may be connected to the second voltage (V2) node (612), the third transistor (644), and the second control input node (652). The third transistor (644) may be connected to the third control input node (654), the output voltage node (630), and the second transistor (642). For example, the second transistor (642) and the third transistor (644) may be connected back-to-back. For example, the source node of the third transistor (644) may be connected to the source node of the second transistor (642). For example, the drain node of the third transistor (644) may be connected to the drain node of the second transistor (642). The fourth transistor (646) can be connected to the third voltage (V3) node (614), the output voltage node (630), and the fourth control input node (656).

[0081] In one embodiment, the phase inversion circuit (660) may be connected to the second control input node (652) and the fourth control input node (656). The phase inversion circuit (660) may invert the phase of an input signal to output an opposite phase signal. For example, it may receive a signal from the fourth control input node (656), invert the phase, and output an opposite phase signal to the second control input node (652). For example, the phase inversion circuit (660) may include a NOT gate. However, the present disclosure is not limited to a NOT gate and may include any circuit capable of inverting the phase.

[0082] FIG. 7 illustrates the switching of an output voltage according to one embodiment of the present disclosure.

[0083] With reference to FIG. 7, the operation of the multi-level output voltage switching circuit (600) of FIG. 6 is described below. In FIG. 7, the same configurations as in FIG. 6 are illustrated using the same reference numerals. Therefore, in describing the configurations of FIG. 7, descriptions that overlap with the descriptions above are omitted. FIG. 7 illustrates an operation (700a, 700b, 700c) of switching from a first voltage (V1) to a second voltage (V2). In this disclosure, the power amplifier is merely an example for illustrative purposes and does not limit the disclosure.

[0084] In one embodiment, in the first operation (700a), the first transistor (640) connected to the first voltage (V1) node may be in a turned-on state. Additionally, the second transistor (642) connected to the second voltage (V2) node may be in a turned-on state. For example, a first signal may be input to the gate node of the first transistor (640). For example, the first signal input to the gate node of the first transistor (640) may be a signal to turn on the transistor. For example, the first signal input to the gate node of the second transistor (642) may be a signal to turn on the transistor. For example, the second signal input to the gate node of the fourth transistor (646) may be a signal to turn off the transistor. For example, the first signal may be a signal with the opposite phase of the second signal. At this time, the first voltage (V1) can be supplied to a power amplifier (720) connected to an output voltage switching circuit through the first transistor (640). For example, the first voltage (V1) can be output through the first transistor (640). The output voltage switching circuit can supply the output first voltage (V1) to the power amplifier (720).

[0085] In order to change from the first voltage (V1) to the second voltage (V2), all transistors except the second transistor (642) may be turned off during the dead time. At this time, the voltage supplied to the power amplifier (720) may be lowered. For example, a second signal may be input to the gate node of the first transistor (640), the gate node of the third transistor (644), and the gate node of the fourth transistor (646). For example, the second signal input to the gate node of the fourth transistor (646) may be inverted through a phase inversion circuit, and the first signal may be input to the gate node of the second transistor (642). For example, the second signal input to the gate node of the first transistor (640), the gate node of the third transistor (644), and the gate node of the fourth transistor (646) may be a signal to turn off the transistors. For example, the first signal input to the gate node of the second transistor (642) may be a signal that turns on the transistor. For example, the first signal may be a signal with the opposite phase of the second signal. When the voltage is lowered, power cannot be supplied through the first transistor (640) associated with the first voltage (V1), the second transistor (642) and the third transistor (644) associated with the second voltage (V2), and their body diodes, so the voltage may continue to drop.

[0086] In one embodiment, the second operation (700b) may indicate a state in which the voltage supplied to the power amplifier continues to decrease until it drops below the second voltage (V2). In the second operation (700b), when the voltage drops below a certain value (e.g., the forward voltage of the body diode of the third transistor (644)) lower than the second voltage (V2), the body diode of the third transistor (644) may be turned on. Since the second transistor (642) is turned on by receiving the first signal through the phase inversion circuit (660), the second voltage (V2) may be supplied to the power amplifier (720) connected to the output voltage switching circuit through the body diodes of the second transistor (642) and the third transistor (644). For example, the second voltage (V2) may be supplied to the power amplifier (720) during dead time. A voltage lower than a certain value (e.g., the forward voltage of the body diode of the third transistor (644)) can be output from the second voltage (V2) through the body diodes of the second transistor (642) and the third transistor (644). The output voltage switching circuit can supply the output second voltage (V2) to the power amplifier (720).

[0087] In one embodiment, the third operation (700c) may represent a switching process to the second voltage (V2) after a dead time. The second transistor (642) and the third transistor (644) associated with the second voltage (V2) may be turned on. A first signal may be input to the gate node of the third transistor (644). For example, the first signal input to the gate node of the third transistor (644) may be a signal to turn on the transistor. At this time, the second voltage (V2) may be supplied to a power amplifier (720) connected to an output voltage switching circuit through the back-to-back connected second transistor (642) and third transistor (644). The source node of the third transistor (644) may be connected to the source node of the second transistor (642). The drain node of the third transistor (644) may be connected to the drain node of the second transistor (642). A second voltage (V2) can be output through the second transistor (642) and the third transistor (644). The output voltage switching circuit can supply the output second voltage (V2) to the power amplifier (720).

[0088] FIG. 8 illustrates an output voltage waveform in a switch operation according to one embodiment of the present disclosure.

[0089] Referring to FIG. 8, the operation (800a) of the switch (V1Switch) associated with the first voltage (V1) and the switch (V2Switch) associated with the second voltage (V2), and the corresponding output voltage waveform (800b) are described below. The switch associated with the first voltage (V1) may correspond to the first transistor (640) of FIG. 7. The switch associated with the second voltage (V2) may correspond to the second transistor (642) and the third transistor (644) of FIG. 7. For example, the turn-on state of the switch associated with the second voltage (V2) may mean a state where both the second transistor (642) and the third transistor (644) are turned on. For example, the turn-off state of the switch associated with the second voltage (V2) may mean a state where the second transistor (642) is turned on and the third transistor (644) is turned off.

[0090] In one embodiment, after the first deadtime (802) of the switch operation (800a) and before the second deadtime (804), the switch associated with the first voltage (V1) may be in a turned-on state, and the switch associated with the second voltage (V2) may be in a turned-off state. For example, the first transistor (640) may be in a turned-on state, the second transistor (642) may be in a turned-on state, and the third transistor (644) may be in a turned-off state. At this time, the output voltage waveform (800b) may represent the first voltage (V1). For example, the first voltage (V1) may be output through the first transistor (640). This may correspond to the first operation (700a) of FIG. 7.

[0091] In one embodiment, during the second dead time (804) of the switch operation (800a), the switch associated with the first voltage (V1) and the switch associated with the second voltage (V2) may be in a turned-off state. For example, the first transistor (640) may be in a turned-off state, the second transistor (642) may be in a turned-on state, and the third transistor (644) may be in a turned-off state. At this time, the output voltage waveform (800b) may represent the second voltage (V2). For example, the second voltage (V2) may be output through the body diodes of the second transistor (642) and the third transistor (644). This may correspond to the second operation (700b) of FIG. 7.

[0092] In one embodiment, after the second dead time (804) of the switch operation (800a) and before the third dead time (806), the switch associated with the first voltage (V1) may be in a turned-off state, and the switch associated with the second voltage (V2) may be in a turned-on state. For example, the first transistor (640) may be in a turned-off state, and the second transistor (642) and the third transistor (644) may be in a turned-on state. In this case, the output voltage waveform (800b) may represent the second voltage (V2). For example, the second voltage (V2) may be output through the back-to-back connected second transistor (642) and third transistor (644). This may correspond to the third operation (700c) of FIG. 7.

[0093] In one embodiment, according to the first operation (700a), the second operation (700b), and the third operation (700c), the output voltage waveform (800b) may appear in the order of the first voltage (V1), the second voltage (V2) (dead time), and the second voltage (V2). When operating including the dead time, the ideal output voltage waveform should only have the first voltage (V1) and the second voltage (V2). When operating with the output voltage switching circuit (600) of FIG. 6, the second voltage (V2) is produced during the dead time, which can prevent the third voltage (V3), which is an unwanted voltage, from being produced. The output voltage waveform (800b) may be a waveform similar to the ideal output voltage waveform.

[0094] FIG. 9 illustrates the operation of a multi-level output voltage switching circuit according to one embodiment of the present disclosure.

[0095] With reference to FIG. 9, the operation of the multi-level output voltage switching circuit (600) of FIG. 6 is described below. The operation sequence of FIG. 9 is merely an example, and the operation sequence may be changed, added, or omitted. The first transistor (640) of FIG. 6 may correspond to M1 of FIG. 9, the second transistor (642) of FIG. 6 may correspond to M2 of FIG. 9, the third transistor (644) of FIG. 6 may correspond to M3 of FIG. 9, and the fourth transistor (646) of FIG. 6 may correspond to M4 of FIG. 9.

[0096] A switch control signal can be input through a switch control unit (620) (920). The switch control signal may include a first control signal (S1), a second control signal (S2), and a third control signal (S3). In one embodiment, the switch control signal may be High or Low. For example, if the switch control signal is High, the transistor may be in a turned-on state. For example, if the switch control signal is Low, the transistor may be in a turned-off state. If any one of the switch control signals is High, the other signals may be Low. The switch control signal may be input to a plurality of transistors simultaneously.

[0097] In one embodiment, the first control signal (S1) may be input to the gate node of the first transistor (640) to control the transistor turn-on / off. The second control signal (S2) may be input to the gate node of the third transistor (644) to control the transistor turn-on / off. The phase-inverted signal of the third control signal (S3) may be input to the gate node of the second transistor (642) to control the transistor turn-on / off. For example, the back-to-back connected second transistor (642) and third transistor (644) may each be controlled by different control signals. The third control signal (S3) may be input to the gate node of the fourth transistor (646) to control the transistor turn-on / off.

[0098] In one embodiment, the electronic device can identify whether the third control signal (S3) is high (940). In the present disclosure, the electronic device may be any device including an output voltage switching circuit, and may be a terminal (user equipment, UE), a base station (BS), or a device performing communication, but this is merely an example and may include a device performing an output voltage switching function. When the third control signal (S3) is high, the fourth transistor (646) may be in a turned-on state, and the first transistor (640), the second transistor (642), and the third transistor (644) may be in a turned-off state (942). The third voltage (V3) through the fourth transistor (646) outputs the voltage (V out It can be output as ) (944).

[0099] In one embodiment, if the third control signal (S3) is not high (940), it can be identified whether the second control signal (S2) is high (960). If the second control signal (S2) is high (960), the second transistor (642) and the third transistor (644) may be in a turned-on state, and the first transistor (640) and the fourth transistor (646) may be in a turned-off state (962). The second voltage (V2) is output voltage (V) through the second transistor (642) and the third transistor (644). out It can be output as ) (964).

[0100] In one embodiment, if the second control signal (S2) is not high (960), it can be identified whether the first control signal (S1) is high (980). If the first control signal (S1) is high (980), the first transistor (640) and the second transistor (642) may be in a turned-on state, and the third transistor (644) and the fourth transistor (646) may be in a turned-off state (982). The first voltage (V1) is output voltage (V) through the first transistor (640). outIt can be output as (984). At this time, the second transistor (642) is turned on, but the third transistor (644) connected back-to-back with the second transistor (642) is turned off, and the body diode of the third transistor (644) has a reverse voltage applied, so that current does not flow from the second voltage (V2) node (612) toward the output voltage node (630).

[0101] In one embodiment, when the first control signal (S1) is not high (980), all control signals may be low. The second transistor (642) may be in a turned-on state, and the first transistor (640), the third transistor (644), and the fourth transistor (646) may be in a turned-off state (986). The second voltage (V2) is output voltage (V) through the body diodes of the second transistor (642) and the third transistor (644). out It can be output as ) (988).

[0102] [Table 1] shows the switch state, switch control signals (S1, S2, S3), multiple transistors (M1, M2, M3, M4), and output voltage (V) in the operation of the output voltage switching circuit exemplified in FIG. 9. out ), and current path are examples.

[0103]

[0104] FIGS. 10a and FIGS. 10b illustrate a multi-level output voltage waveform according to one embodiment of the present disclosure in comparison with an ideal situation.

[0105] With reference to FIGS. 10a and FIGS. 10b, the simulation results of the multi-level output voltage switching circuit (600) of FIG. 6 are described below.

[0106] Referring to FIG. 10a, an output voltage graph (1000) over time is shown, and for a more detailed explanation, an output voltage graph (1020) at a specific time is described below with reference to FIG. 10b. The values ​​listed in the graphs are merely examples to aid in understanding the present disclosure and do not limit the present disclosure.

[0107] Referring to FIG. 10b, an output voltage graph (1022) of an ideal circuit, an output voltage graph (1024) of a multi-level output voltage switching circuit (300b) of FIG. 3b, and an output voltage graph (1026) of a multi-level output voltage switching circuit (600) of FIG. 6 are shown. For example, the dead time of the ideal circuit may be 0 seconds. For example, the dead time of the multi-level output voltage switching circuit (300b, 600) may be 10ns. However, this is merely an example, and the dead time may be any specific value greater than 0 seconds.

[0108] In one embodiment, referring to the output voltage graph (1024), the output voltage switching circuit (300b) can output a third voltage (V3) (e.g., about 17V) during a dead time interval. A voltage difference of 5V or more may occur with respect to the output voltage (about 23V) of the ideal output voltage graph (1022).

[0109] In one embodiment, referring to the output voltage graph (1026), the output voltage switching circuit (600) can output a voltage of about 22V during the dead time interval. The voltage difference from the output voltage (about 23V) of the ideal output voltage graph (1022) can be within about 1V. Additionally, referring to 1028, the output voltage of the output voltage switching circuit (600) can be improved compared to the output voltage switching circuit (300b).

[0110] FIGS. 11a and FIGS. 11b illustrate a power amplifier gain supplied with an output voltage according to one embodiment of the present disclosure, compared with an ideal situation.

[0111] With reference to FIGS. 11a and 11b, the simulation results of the power amplifier (720) of FIG. 7, in which the multi-level output voltage switching circuit (600) of FIG. 6 supplies the output voltage, are described below.

[0112] Referring to FIG. 11a, a power amplifier gain graph (1100) over time is shown, and for a more detailed explanation, a power amplifier gain graph (1120) at a specific time is described below with reference to FIG. 11b. The values ​​listed in the graphs are merely examples to aid in understanding the present disclosure and do not limit the present disclosure.

[0113] Referring to FIG. 11b, a power amplifier gain graph (1122) of an ideal circuit, a power amplifier gain graph (1124) of FIG. 4 in which the multi-level output voltage switching circuit (300b) of FIG. 3b supplies the output voltage, and a power amplifier gain graph (1126) of FIG. 7 in which the multi-level output voltage switching circuit (600) of FIG. 6 supplies the output voltage are shown. For example, the dead time of the ideal circuit may be 0 seconds. For example, the dead time of the multi-level output voltage switching circuit (300b, 600) may be 10ns. However, this is merely an example, and the dead time may be any specific value greater than 0 seconds.

[0114] In one embodiment, referring to the gain graph (1124) of the power amplifier, the power amplifier of FIG. 4 can provide a gain of about 20 dB during the dead time interval. A gain difference of more than 3 dB may occur compared to the gain of about 23 dB of the ideal power amplifier gain graph (1122).

[0115] In one embodiment, referring to the gain graph (1126) of the power amplifier, the power amplifier of FIG. 7 can provide a gain of about 22 dB during the dead time interval. The difference in gain from the gain of about 23 dB of the ideal power amplifier gain graph (1122) can be within 1 dB. Additionally, referring to 1128, it can be seen that the gain of the power amplifier in the gain graph (1126) is improved compared to the gain graph (1124) of the power amplifier.

[0116] [Table 2] shows the Error Vector Magnitude (EVM) values ​​according to the circuit topology. EVM can represent an indicator of the linearity of the power amplifier. For example, the lower the EVM, the better the linearity of the power amplifier. Referring to the description of FIG. 10b described above, it can be seen that the output voltage of the output voltage switching circuit (600) is improved. Therefore, compared to the output voltage switching circuit (300b), it can be seen that the EVM value of the output voltage switching circuit (600) is improved to be similar to the EVM value of an ideal circuit.

[0117]

[0118] FIG. 12 illustrates a multi-level output voltage switching circuit including an inverter according to one embodiment of the present disclosure.

[0119] Referring to FIG. 12, in one embodiment, the phase inversion circuit (660) of the multi-level output voltage switching circuit (600) of FIG. 6 may include an inverter (1260) of the multi-level output voltage switching circuit (1200) of FIG. 12. The output voltage switching circuit (1200) of FIG. 12 is identical to the output voltage switching circuit (600) of FIG. 6 except for the inverter (1260). In FIG. 12, the same configuration as in FIG. 6 is illustrated using the same reference numerals. Therefore, in describing the configurations of FIG. 12, descriptions that overlap with the foregoing descriptions are omitted, and the description of FIG. 6 is included by reference.

[0120] In one embodiment, the inverter (1260) may be connected to the second control input node (652) and the fourth control input node (656). The inverter (1260) may invert the phase of the input signal to output an opposite phase signal. For example, it may receive a signal from the fourth control input node (656), invert the phase, and output an opposite phase signal to the second control input node (652).

[0121] FIGS. 13a and FIGS. 13b illustrate a multi-level output voltage switching circuit including a logic operation circuit according to one embodiment of the present disclosure.

[0122] Referring to FIG. 13a, in one embodiment, the multi-level output voltage switching circuit (1300a) may be a 4-level output voltage switching circuit. The 4-level may refer to four voltage levels: a first voltage (V1), a second voltage (V2), a third voltage (V3), and a fourth voltage (V4). For example, the fourth voltage (V4) may be input through a fourth voltage (V4) node (1310). The first voltage (V1) may be greater than the fourth voltage (V4), the fourth voltage (V4) may be greater than the second voltage (V2), and the second voltage (V2) may be greater than the third voltage (V3). In FIG. 13a, configurations identical to those in FIG. 6 are illustrated using the same reference numerals. Therefore, in describing the configurations of FIG. 13a, descriptions that overlap with the foregoing descriptions are omitted, and the description of FIG. 6 is included by reference.

[0123] In one embodiment, the multi-level output voltage switching circuit (1300a) may further include a fifth transistor (1340), a sixth transistor (1342), and a logic operation circuit (1360) in the multi-level output voltage switching circuit (600) of FIG. 6. The switch control unit (620) may further supply a fourth control signal (S4).

[0124] In one embodiment, the second control signal (S2) and the third control signal (S3) may be input through a logic operation circuit (1360). The input signals may be output through an OR gate (1362) and a phase inversion circuit (1364) and input through a fifth control input node (1355). The fourth control signal (S4) may be input through a sixth control input node (1356). For example, different control signals may be input to the back-to-back connected fifth transistor (1340) and sixth transistor (1342), respectively. For example, the fifth transistor (1340) may be controlled by the output signals of the logic operation circuit (1360) of the second control signal (S2) and the third control signal (S3), and the sixth transistor (1342) may be controlled by the fourth control signal (S4).

[0125] In one embodiment, the fifth transistor (1340) may be connected to the fourth voltage (V4) node (1310), the sixth transistor (1342), and the fifth control input node (1355). The sixth transistor (1342) may be connected to the sixth control input node (1356), the output voltage node (630), and the fifth transistor (1340). For example, the fifth transistor (1340) and the sixth transistor (1342) may be connected back-to-back. For example, the source node of the sixth transistor (1342) may be connected to the source node of the fifth transistor (1340). For example, the drain node of the sixth transistor (1342) may be connected to the drain node of the fifth transistor (1340).

[0126] In one embodiment, the logic operation circuit (1360) may be connected to the third control input node (654), the fourth control input node (656), and the fifth control input node (1355). The logic operation circuit (1360) may include an OR gate (1362) and a phase inversion circuit (1364). The OR gate (1362) may be connected to the third control input node (654), the fourth control input node (656), and the phase inversion circuit (1364). The phase inversion circuit (1364) may be connected to the OR gate (1362) and the fifth control input node (1355). The logic operation circuit (1360) may perform a logic operation on the input signal and output the result with the phase inverted. For example, the signal from the third control input node (654) and the signal from the fourth control input node (656) are received, an OR logic operation is performed through the OR gate (1362), and the phase is inverted through the phase inversion circuit (1364) and output through the fifth control input node (1355). For example, the phase inversion circuit (1364) may include a NOT gate or an inverter. However, it is not limited thereto and may include any circuit capable of inverting the phase.

[0127] Referring to FIG. 13b, in one embodiment, the logic operation circuit (1360) of the multi-level output voltage switching circuit (1300a) of FIG. 13a may be implemented with a NOR gate (1365) instead of an OR gate (1362) and a phase inversion circuit (1364). The multi-level output voltage switching circuit (1300b) of FIG. 13b is identical to the output voltage switching circuit (1300a) of FIG. 13a except for the NOR gate (1365). In FIG. 13b, the same configurations as in FIG. 6 and FIG. 13a are illustrated using the same reference numerals. Therefore, in describing the configurations of FIG. 13b, descriptions that overlap with the foregoing descriptions are omitted, and the descriptions of FIG. 6 and FIG. 13a are included by reference.

[0128] In one embodiment, the second control signal (S2) and the third control signal (S3) can be input to the NOR gate (1365). The input signals can be output to the fifth control input node (1355) through the NOR gate (1365).

[0129] In one embodiment, the NOR gate (1365) may be connected to the third control input node (654), the fourth control input node (656), and the fifth control input node (1355). The NOR gate (1365) may perform a logical operation on the input signal and output it. For example, it may receive the signal from the third control input node (654) and the signal from the fourth control input node (656), perform a NOR logical operation through the NOR gate (1365), and output it to the fifth control input node (1355).

[0130] FIG. 14 illustrates a multi-level output voltage switching circuit with an extended output voltage level according to one embodiment of the present disclosure.

[0131] Referring to FIG. 14, in one embodiment, the multi-level output voltage switching circuit (1400) may be an n-level output voltage switching circuit. The n-levels are a first voltage (V1), ..., an n-1th voltage (V n-1 ), and the nth voltage (V n It can mean n voltage levels of ). The first voltage (V1) may be greater than the second voltage (V2), ..., the n-2nd voltage (V n-2 ) is the n-1st voltage (V n-1 It can be greater than ), and the n-1th voltage (V n-1 ) is the nth voltage (V nIt can be greater than ). n can be any integer greater than or equal to 3. For example, when n=3, the multi-level output voltage switching circuit (1400) can be the multi-level output voltage switching circuit (600) of FIG. 6. For example, when n=4, the multi-level output voltage switching circuit (1400) can be the multi-level output voltage switching circuit (1300a) of FIG. 13a.

[0132] In one embodiment, the multi-level output voltage switching circuit (1400) may include a switch control unit (1420), a transistor (1440) associated with a first voltage (V1), transistors (1441, 1442) back-to-back connected to an OR gate (1464) associated with a second voltage (V2) and a phase inversion circuit (1465), transistors (1443, 1444) back-to-back connected to an OR gate (1462) associated with an n-2 voltage and a phase inversion circuit (1463), transistors (1445, 1446) back-to-back connected to a phase inversion circuit (1460) associated with an n-1 voltage, and a transistor (1447) associated with an n-th voltage. The switch control unit (1420) may include a first control signal (S1), a second control signal (S2), ..., an n-2 control signal (S n-2 ), n-1th control signal (S n-1 ), and the nth control signal (S n Can supply ).

[0133] In one embodiment, two back-to-back connected transistors of the multi-level output voltage switching circuit (1400) can each be controlled by a separate control signal. The two back-to-back connected transistors can be controlled separately by inverting the phase of the transistor control signal associated with a voltage lower than the switching voltage. For example, the n-1th voltage (V n-1 The transistor (1446) of the back-to-back connected transistors (1445, 1446) associated with ) is the n-1st control signal (S n-1 It is controlled by ), and the transistor (1445) is the nth control signal (Sn ) can be controlled as a phase-inverted signal through a phase inversion circuit (1460). For example, the n-2nd voltage (V n-2 The transistor (1444) of the back-to-back connected transistors (1443, 1444) associated with ) is the n-2nd control signal (S n-2 It is controlled by ), and the transistor (1443) is the nth control signal (S n ) and the n-1st control signal (S n-1 ) can be controlled by a logical operation through an OR gate (1462) and a phase-inverted signal through a phase inversion circuit (1463). For example, transistor (1442) of back-to-back connected transistors (1441, 1442) associated with the second voltage (V2) is controlled by the second control signal (S2), and transistor (1441) is controlled by the nth control signal (S n ..., the fourth control signal (S4) and the third control signal (S3) can be logically operated through an OR gate (1464) and controlled into a phase-inverted signal through a phase inversion circuit (1465). For example, the phase inversion circuit (1460, 1463, 1465) may include a NOT gate or an inverter. However, it is not limited thereto and may include any circuit capable of inverting the phase.

[0134] FIGS. 15a and 15b illustrate a multi-level output voltage waveform according to one embodiment of the present disclosure in comparison to an ideal situation.

[0135] Referring to FIGS. 15a and 15b, output voltage graphs (1500a, 1500b) over time are illustrated. The output voltage graph (1500a) of FIG. 15a illustrates the simulation results of the multi-level output voltage switching circuit (1300a) of FIG. 13a. The output voltage graph (1500b) of FIG. 15b illustrates the simulation results of the multi-level (n=7) output voltage switching circuit (1400) of FIG. 14. The values ​​described in the graphs are merely examples to aid in understanding the present disclosure and do not limit the present disclosure.

[0136] Referring to FIG. 15a, an output voltage graph (1502) of an ideal circuit, an output voltage graph (1504) of a circuit in which the multi-level output voltage switching circuit (300b) of FIG. 3b is extended to 4 levels, and an output voltage graph (1506) of a multi-level output voltage switching circuit (1300a) of FIG. 13a are shown. For example, the dead time of the ideal circuit may be 0 seconds. For example, the dead time of the multi-level output voltage switching circuit may be 10 ns. However, this is merely an example, and the dead time may be any specific value greater than 0 seconds.

[0137] In one embodiment, referring to the output voltage graph (1504), the output voltage switching circuit (300b) can output a fourth voltage (V4) (e.g., about 12V) during a dead time interval. A voltage difference of 11V or more can occur with respect to the output voltage (about 23V) of the ideal output voltage graph (1502).

[0138] In one embodiment, referring to the output voltage graph (1506), the output voltage switching circuit (1300a) can output a voltage of approximately 22V during the dead time interval. The voltage difference from the output voltage (approximately 23V) of the ideal output voltage graph (1502) can be within 1V. Additionally, referring to 1508, the output voltage of the output voltage switching circuit (1300a) can be improved compared to a circuit in which the output voltage switching circuit (300b) is extended to 4 levels.

[0139] Referring to FIG. 15b, an output voltage graph (1522) of an ideal circuit, an output voltage graph (1524) of a circuit in which the multi-level output voltage switching circuit (300b) of FIG. 3b is extended to 7 levels, and an output voltage graph (1526) of a 7-level (n=7) output voltage switching circuit (1400) of FIG. 14 are shown. For example, the dead time of the ideal circuit may be 0 seconds. For example, the dead time of the 7-level output voltage switching circuit may be 10 ns. However, this is merely an example, and the dead time may be any specific value greater than 0 seconds.

[0140] In one embodiment, referring to the output voltage graph (1524), the output voltage switching circuit (300b) can output a seventh voltage (V7) (e.g., about 3V) during a dead time interval. A voltage difference of 9V or more may occur with respect to the output voltage (about 12V) of the ideal output voltage graph (1522).

[0141] In one embodiment, referring to the output voltage graph (1526), ​​the output voltage switching circuit (1400) can output a voltage of about 11V during the dead time interval. The voltage difference from the output voltage (about 12V) of the ideal output voltage graph (1522) can be within 1V. Additionally, referring to 1528, the output voltage of the output voltage switching circuit (1400) can be improved when the output voltage switching circuit (300b) is extended to 7 levels.

[0142] FIGS. 16a and 16b illustrate a multi-level output voltage switching circuit including a deadtime detection circuit and a multiplexer according to one embodiment of the present disclosure.

[0143] Referring to FIG. 16a, in one embodiment, the dead-time detection multi-level output voltage switching circuit (1600a) may further include a first multiplexer (2:1 Mux) (1680), a second multiplexer (2:1 Mux) (1682), and a dead-time detection circuit (1670) in the multi-level output voltage switching circuit (1300a) of FIG. 13a. The configuration of the dead-time detection multi-level output voltage switching circuit (1600a) is identical to that of the multi-level output voltage switching circuit (1300a), except for the first multiplexer (2:1 Mux) (1680), the second multiplexer (2:1 Mux) (1682), and the dead-time detection circuit (1670). In FIG. 16a, the same configuration as in FIG. 6 and FIG. 13a is illustrated using the same reference numerals. Accordingly, in describing the configurations of FIG. 16a, descriptions that overlap with the aforementioned descriptions are omitted, and the descriptions of FIG. 6 and FIG. 13a are included by reference.

[0144] In one embodiment, the dead time detection circuit (1670) may be connected to a first multiplexer (1680) and a second multiplexer (1682). The dead time detection circuit (1670) may be connected to a switch control unit (620). For example, the dead time detection circuit (1670) may output an enable signal through the control of the switch control unit (620). For example, the enable signal may be input to the first multiplexer (1680) and the second multiplexer (1682).

[0145] In one embodiment, the first multiplexer (1680) may be connected to the deadtime detection circuit (1670), the second control input node (652), the third control input node (654), and the first phase inversion circuit (660). For example, the first multiplexer (1680) may receive the second control signal (S2), the third control signal (S3) which is an inverted phase signal with its phase reversed through the first phase inversion circuit (660), and an operation signal. For example, the first multiplexer (1680) may select and output either the second control signal (S2) or the third control signal (S3) which is an inverted phase signal with its phase reversed through the first phase inversion circuit (660) based on the operation signal. For example, when the second control signal (S2) is output, the back-to-back connected second transistor (642) and third transistor (644) may be controlled by the same signal, the second control signal (S2). For example, if the third control signal (S3) outputs an opposite phase signal with its phase inverted through the first phase inversion circuit (660), the back-to-back connected second transistor (642) is controlled by the opposite phase signal with its phase inverted through the first phase inversion circuit (660), and the third transistor (644) can be controlled by the second control signal (S2).

[0146] In one embodiment, the second multiplexer (1682) may be connected to the deadtime detection circuit (1670), the fifth control input node (1355), the sixth control input node (1356), and the logic operation circuit (1360). The logic operation circuit (1360) may include an OR gate (1362) and a second phase inversion circuit (1364). For example, the second multiplexer (1682) may receive the fourth control signal (S4), the second control signal (S2), and the third control signal (S3) as signals output through the logic operation circuit (1360), and an operation signal. For example, the second multiplexer (1682) may select and output the fourth control signal (S4) or one of the signals output through the logic operation circuit (1360) as the second control signal (S2) and the third control signal (S3) based on the operation signal. For example, when the fourth control signal (S4) is output, the back-to-back connected fifth transistor (1340) and sixth transistor (1342) can be controlled by the same signal, the fourth control signal (S4). For example, when the second control signal (S2) and the third control signal (S3) are output signals through the logic operation circuit (1360), the back-to-back connected fifth transistor (1340) is controlled by the signals of the second control signal (S2) and the third control signal (S3) output through the logic operation circuit (1360), and the sixth transistor (1342) can be controlled by the fourth control signal (S4).

[0147] Referring to FIG. 16b, the dead-time detection multi-level output voltage switching circuit (1600b) may represent a circuit in which the voltage levels of the dead-time detection multi-level output voltage switching circuit (1600a) of FIG. 16a are extended. This can be understood as the multi-level output voltage switching circuit (1400) of FIG. 14 further comprising a dead-time detection circuit (1670) and a plurality of multiplexers (1685). For example, the multiplexer (1683) may, based on an operating signal, a second control signal (S2) or an nth control signal (Sn ..., the fourth control signal (S4) and the third control signal (S3) can be logically operated on through an OR gate (1464), and one of the phase-inverted signals can be selected and output through a phase inversion circuit (1465). For example, when the second control signal (S2) is output, the back-to-back connected second transistor (1441) and third transistor (1442) can be controlled by the same signal, the second control signal (S2). For example, the nth control signal (S n ), ..., when the fourth control signal (S4) and the third control signal (S3) are logically operated on through the OR gate (1464) and a phase-inverted signal is output through the phase inversion circuit (1465), the back-to-back connected second transistor (1441) is the nth control signal (S n ..., the fourth control signal (S4) and the third control signal (S3) are logically operated through the OR gate (1464) and controlled as a phase-inverted signal through the phase inversion circuit (1465), and the third transistor (1442) can be controlled as the second control signal (S2).

[0148] FIGS. 17a and FIGS. 17b illustrate a multi-level output voltage switching circuit including a current sense unit according to one embodiment of the present disclosure.

[0149] Referring to FIG. 17a, in one embodiment, the dead-time detection multi-level output voltage switching circuit (1700a) may further include a current measuring unit (1790) in the dead-time detection multi-level output voltage switching circuit (1600a) of FIG. 16a. The configuration of the dead-time detection multi-level output voltage switching circuit (1700a) is identical to that of the dead-time detection multi-level output voltage switching circuit (1600a) except for the current measuring unit (1790). In FIG. 17a, the same configuration as in FIG. 6, FIG. 13a, and FIG. 16a is illustrated using the same reference numerals. Therefore, in describing the configurations of FIG. 17a, descriptions that overlap with the foregoing descriptions are omitted, and the descriptions of FIG. 6, FIG. 13a, and FIG. 16a are included by reference.

[0150] In one embodiment, the current measuring unit (1790) may be connected to the dead time detection circuit (1670), the fourth transistor (646), and the output voltage node (630). For example, when current is measured in the current measuring unit (1790), the first multiplexer (1680) may output an inverted phase signal through the first phase inversion circuit (660) based on the operation signal of the dead time detection circuit (1670). For example, when the inverted phase signal through the first phase inversion circuit (660) is output as the third control signal (S3), the back-to-back connected second transistor (642) may be controlled to the inverted phase signal through the first phase inversion circuit (660), and the third transistor (644) may be controlled to the second control signal (S2).

[0151] For example, when current is measured in the current measuring unit (1790), the second multiplexer (1682) may output a signal through the logic operation circuit (1360) in which the second control signal (S2) and the third control signal (S3) are output based on the operation signal of the dead time detection circuit (1670). The logic operation circuit (1360) may include an OR gate (1362) and a second phase inversion circuit (1364). For example, when the second control signal (S2) and the third control signal (S3) are output through the logic operation circuit (1360), the back-to-back connected fifth transistor (1340) may be controlled by the signal through the logic operation circuit (1360) in which the second control signal (S2) and the third control signal (S3) are output, and the sixth transistor (1342) may be controlled by the fourth control signal (S4).

[0152] Referring to FIG. 17b, the dead-time detection multi-level output voltage switching circuit (1700b) may represent a circuit in which the voltage levels of the dead-time detection multi-level output voltage switching circuit (1700a) of FIG. 17a are extended. This can be understood as the multi-level output voltage switching circuit (1400) of FIG. 14 further comprising a dead-time detection circuit (1670), a plurality of multiplexers (1685), and a current measuring unit (1790). For example, when current is measured at the current measuring unit (1790), the multiplexer (1683) transmits a second control signal (S2) or an nth control signal (S) based on the operation signal of the dead-time detection circuit (1670). n ..., the fourth control signal (S4) and the third control signal (S3) can be logically operated on through an OR gate (1464), and one of the phase-inverted signals can be selected and output through a phase inversion circuit (1465). For example, when the second control signal (S2) is output, the back-to-back connected second transistor (1441) and third transistor (1442) can be controlled by the same signal, the second control signal (S2). For example, the nth control signal (Sn ), ..., when the fourth control signal (S4) and the third control signal (S3) are logically operated on through the OR gate (1464) and a phase-inverted signal is output through the phase inversion circuit (1465), the back-to-back connected second transistor (1441) is the nth control signal (S n ..., the fourth control signal (S4) and the third control signal (S3) are logically operated through the OR gate (1464) and controlled as a phase-inverted signal through the phase inversion circuit (1465), and the third transistor (1442) can be controlled as the second control signal (S2).

[0153] FIG. 18 illustrates an operation for controlling a transistor of an output voltage switching circuit according to one embodiment of the present disclosure.

[0154] In one embodiment, the electronic device may include a first transistor associated with a first voltage, a second transistor and a third transistor associated with a second voltage, and a fourth transistor associated with a third voltage. In one embodiment, the first signal may mean a signal to turn on the transistor, and the second signal may mean a signal to turn off the transistor. In one embodiment, the source node of the third transistor may be connected to the source node of the second transistor, or the drain node of the third transistor may be connected to the drain node of the second transistor.

[0155] In operation 1820, the electronic device may perform the operation of inputting a first signal to the gate node of the first transistor or the gate node of the fourth transistor. Operation 1820 may correspond to the first operation (700a) of FIG. 7.

[0156] In operation 1840, the electronic device inputs a second signal to the gate node of the first transistor, the gate node of the third transistor, and the gate node of the fourth transistor, and the signal input to the gate node of the fourth transistor can be input to the gate node of the second transistor through a phase inversion circuit. Operation 1840 may correspond to the second operation (700b) of FIG. 7.

[0157] In operation 1860, the electronic device can input a first signal to the gate node of the third transistor. Operation 1860 may correspond to the third operation (700c) of FIG. 7.

[0158] FIG. 19a illustrates a multi-level output voltage switching circuit comprising a delay circuit, an OR gate, and a pulse width increasing circuit according to one embodiment of the present disclosure.

[0159] Referring to FIG. 19a, in one embodiment, the multi-level output voltage switching circuit (1900a) may be a 3-level output voltage switching circuit. In FIG. 19a, the same configurations as in FIG. 6 are illustrated using the same reference numerals. Therefore, in describing the configurations of FIG. 19a, descriptions that overlap with the foregoing descriptions are omitted, and the description of FIG. 6 is included by reference.

[0160] 3-level may refer to three voltage levels: a first voltage (V1), a second voltage (V2), and a third voltage (V3). The first voltage (V1) can be input through the first voltage (V1) node (610). The second voltage (V2) can be input through the second voltage (V2) node (612). The third voltage (V3) can be input through the third voltage (V3) node (614).

[0161] In one embodiment, the multi-level output voltage switching circuit (1900a) may include a switch control unit (620), a first transistor (640), a second transistor (642), a third transistor (644), a fourth transistor (646), a first delay circuit (1920), a second delay circuit (1922), a third delay circuit (1924), a pulse width increase circuit (1940), and an OR gate (1960). The switch control unit (620) may supply a first control signal (S1), a second control signal (S2), and a third control signal (S3). The control signal may refer to a signal input to a transistor gate to turn the transistor on or off. For example, in the case of an N-channel MOSFET operating at 1 volt (V), the control signal may be a 1-volt signal or a 0-volt signal. For example, in the case of an N-channel MOSFET operating at 5 volts, the control signal can be a 5-volt signal or a 0-volt signal.

[0162] FIG. 19b illustrates a delay circuit and a pulse width increasing circuit according to one embodiment of the present disclosure.

[0163] Referring to FIG. 19b, in one embodiment, a first control signal (S1) and a second control signal (S2) may be ORed through an OR gate (1960) and output as an OR logic operation signal (1970). For example, the pulse width of the first control signal (S1) and the second control signal (S2) may be 20ns. Here, 20ns is merely an example and the present disclosure is not limited thereto. The OR logic operation signal (1970) may be a signal that turns off a switch during dead time. The OR logic operation signal (1970) may be input to a pulse width increase circuit (1940). The pulse width increase circuit (1940) may OR the OR logic operation signal (1970) and the time delay signal (1971) of the OR logic operation signal (1970) to output a pulse width increase signal (1974). For example, the delay signal (1971) of the OR logic operation signal (1970) may be a signal that delays the OR logic operation signal (1970) by 10ns. Here, 10ns is merely an example and the present disclosure is not limited thereto. The pulse width increase signal (1974) may be a signal formed by increasing the pulse width of the first control signal (S1) to 30ns and increasing the pulse width of the second control signal (S2) to 30ns and adding them together. The pulse width increase signal (1974) may be a signal that turns on the switch during dead time. Accordingly, the pulse width increase circuit (1940) can receive the OR logic operation signal (1970), which is a signal that turns off the switch during dead time, as input by processing the control signal, and output the pulse width increase signal (1974), which is a signal that turns on the switch during dead time. For example, processing a control signal may mean delaying the control signal and / or increasing the pulse width of the control signal.For the sake of convenience of explanation, a pulse width increase circuit in which the first control signal (S1) and the second control signal (S2) are input via an OR logic operation has been described above; however, the present disclosure is not limited thereto, and a pulse width increase circuit in which a plurality of control signals are input can be implemented similarly. For example, a pulse width increase circuit in which the first control signal (S1), the second control signal (S2), and the third control signal (S3) are input via an OR operation can operate identically or similarly to the pulse width increase circuit (1940).

[0164] In one embodiment, the first control signal (S1) may be input to the first delay circuit (1920). For example, the pulse width of the first control signal (S1) may be 20ns. 20ns is merely an example and is not limited thereto. The first delay circuit (1920) may output a time delay signal (1980) of the first control signal (S1). For example, the time delay signal (1980) of the first control signal (S1) may be a signal that delays the first control signal (S1) by 5ns. Thus, by delaying the first control signal (S1) by the first delay circuit (1920), the pulse width increase signal (1974) may be advanced by 5ns relative to the time delay signal (1980) of the first control signal (S1). Here, 5ns is merely an example and is not limited thereto. The description of the first delay circuit (1920) in FIG. 19b can be applied in the same / similar way to the second delay circuit (1922) and the third delay circuit (1924).

[0165] Referring again to FIG. 19a, in one embodiment, a first control signal (S1) can be output as a delayed signal of the first control signal (S1) through a first delay circuit (1920) and input through a first control input node (650). A second control signal (S2) can be output as a delayed signal of the second control signal (S2) through a second delay circuit (1922) and input through a third control input node (654). Additionally, the first control signal (S1) and the second control signal (S2) can be OR logically operated through an OR gate (1960) to output an OR logical operation signal. The OR logical operation signal can be output as a pulse width increase signal through a pulse width increase circuit (1940) and input through a second control input node (652). The third control signal (S3) can be output as a delay signal of the third control signal (S3) through the third delay circuit (1924) and input through the fourth control input node (656). For example, different control signals can be input to the back-to-back connected second transistor (642) and third transistor (644), respectively. For example, the first transistor (640) can be controlled by the delay signal of the first control signal (S1). For example, the third transistor (644) can be controlled by the delay signal of the second control signal (S2), and the second transistor (642) can be controlled by the OR logic operation signal of the first control signal (S1) and the second control signal (S2) as a signal with increased pulse width. As a result, when the first transistor (640) or the third transistor (644) is turned on, the second transistor (642) can be turned on. For example, the fourth transistor (646) can be controlled by the delay signal of the third control signal (S3).

[0166] In one embodiment, the first transistor (640) may be connected to a first control input node (650) connected to a first delay circuit (1920), a first voltage (V1) node (610), and an output voltage node (630). The second transistor (642) may be connected to a second control input node (652) connected to a pulse width increase circuit (1940), a second voltage (V2) node (612), and a third transistor (644). The third transistor (644) may be connected to a third control input node (654) connected to a second delay circuit (1922), an output voltage node (630), and the second transistor (642). For example, the second transistor (642) and the third transistor (644) may be connected back-to-back. For example, the source node of the third transistor (644) may be connected to the source node of the second transistor (642). For example, the drain node of the third transistor (644) can be connected to the drain node of the second transistor (642). The fourth transistor (646) can be connected to the fourth control input node (656) to which the third delay circuit (1924) is connected, the third voltage (V3) node (614), and the output voltage node (630).

[0167] In one embodiment, the OR gate (1960) may be connected to a first delay circuit (1920), a second delay circuit (1922), and a pulse width increase circuit (1940). The OR gate (1960) may perform an OR logic operation on an input signal and output an OR logic operation signal. For example, the OR gate (1960) may receive a signal input to the first delay circuit (1920) and a signal input to the second delay circuit (1922), perform an OR logic operation on the input signals, and output an OR logic operation signal to the pulse width increase circuit (1940). The OR gate of the present disclosure may include any operator capable of performing a logic operation identical to an OR logic operation.

[0168] The multi-level output voltage switching circuit (1900a) can perform the same / similar operation as the multi-level output voltage switching circuit (600) described in FIGS. 7, FIGS. 8, and FIGS. 9 as described in the description regarding FIGS. 19a and FIGS. 19b, and can obtain the same / similar result as the simulation result of the multi-level output voltage switching circuit (600) described in FIGS. 10a, FIGS. 10b, FIGS. 11a, and FIGS. 11b.

[0169] FIG. 20 illustrates a multi-level output voltage switching circuit comprising a delay circuit, an OR gate, and a pulse width increasing circuit according to one embodiment of the present disclosure.

[0170] Referring to FIG. 20, in one embodiment, the multi-level output voltage switching circuit (2000) may be a 4-level output voltage switching circuit. The 4-level may refer to four voltage levels: a first voltage (V1), a second voltage (V2), a third voltage (V3), and a fourth voltage (V4). For example, the fourth voltage (V4) may be input through a fourth voltage (V4) node (2010). The first voltage (V1) may be greater than the second voltage (V2), the second voltage (V2) may be greater than the fourth voltage (V4), and the fourth voltage (V4) may be greater than the third voltage (V3). In FIG. 20, configurations identical to those in FIG. 6, FIG. 19a, and FIG. 19b are illustrated using the same reference numerals. Accordingly, in describing the configurations of FIG. 20, descriptions that overlap with the aforementioned descriptions are omitted, and the descriptions of FIG. 6, FIG. 19a, and FIG. 19b are included by reference.

[0171] In one embodiment, the multi-level output voltage switching circuit (2000) may further include a fifth transistor (2040), a sixth transistor (2042), a fourth delay circuit (2020), a pulse width increase circuit (2030), and an OR gate (2060) in the multi-level output voltage switching circuit (1900a) of FIG. 19a. The switch control unit (620) may further supply a fourth control signal (S4).

[0172] In one embodiment, the first control signal (S1), the second control signal (S2), and the fourth control signal (S4) can be input through an OR gate (2060). The input signals can be OR logically operated through the OR gate to output an OR logical operation signal. The OR logical operation signal can be output as a pulse width increase signal through a pulse width increase circuit (2030) and input through the fifth control input node (2055). The fourth control signal (S4) can be input through the sixth control input node (2056). For example, different control signals can be input to the back-to-back connected fifth transistor (2040) and sixth transistor (2042), respectively. For example, the fifth transistor (2040) can be controlled to increase the pulse width of the OR logical operation signal of the first control signal (S1), the second control signal (S2), and the fourth control signal (S4). For example, the sixth transistor (1342) can be controlled by a delay signal of the fourth control signal (S4). As a result, when the first transistor (640), the third transistor (644), or the sixth transistor (2042) is turned on, the fifth transistor (2040) can be turned on.

[0173] In one embodiment, the fifth transistor (2040) may be connected to the fifth control input node (2055) to which the pulse width increase circuit (2030) is connected, the fourth voltage (V4) node (2010), and the sixth transistor (2042). The sixth transistor (2042) may be connected to the fifth transistor (2040) to the sixth control input node (2056) to which the fourth delay circuit (2020) is connected, the output voltage node (630), and the fifth transistor (2040). For example, the fifth transistor (2040) and the sixth transistor (2042) may be connected back-to-back. For example, the source node of the sixth transistor (2042) may be connected to the source node of the fifth transistor (2040). For example, the drain node of the sixth transistor (2042) may be connected to the drain node of the fifth transistor (2040).

[0174] In one embodiment, the OR gate (2060) may be connected to a first delay circuit (1920), a second delay circuit (1922), a fourth delay circuit (2020), and a pulse width increase circuit (2030). The OR gate (2060) may perform an OR logic operation on an input signal and output an OR logic operation signal. For example, the OR gate (2060) may receive a signal input to the first delay circuit (1920), a signal input to the second delay circuit (1922), and a signal input to the fourth delay circuit (2020), perform an OR logic operation on the input signal, and output an OR logic operation signal to the pulse width increase circuit (2030). The OR gate of the present disclosure may include any operator capable of performing a logic operation identical to an OR logic operation.

[0175] In one embodiment, the first control signal (S1), the second control signal (S2), and the fourth control signal (S4) may be OR logically operated through an OR gate (2060) and output as an OR logically operated signal. For example, the pulse width of the first control signal (S1), the second control signal (S2), and the fourth control signal (S4) may be 20ns. Here, 20ns is merely an example and the present disclosure is not limited thereto. The OR logically operated signal may be a signal that turns off a switch during dead time. The OR logically operated signal may be input to a pulse width increase circuit (2030). The pulse width increase circuit (2030) may OR logically operate the OR logically operated signal and the delay signal of the OR logically operated signal to output a pulse width increase signal. For example, the delay signal of the OR logically operated signal may be a signal that delays the OR logically operated signal by 10ns. Here, 10ns is merely an example and the present disclosure is not limited thereto. The pulse width increase signal may be a signal formed by increasing the pulse width of the first control signal (S1) to 30ns, increasing the pulse width of the second control signal (S2) to 30ns, and increasing the pulse width of the fourth control signal (S4) to 30ns and adding them together. The pulse width increase signal may be a signal that turns on the switch during dead time. Accordingly, the pulse width increase circuit (2030) can process the control signal to receive an OR logic operation signal, which is a signal that turns off the switch during dead time, and output a pulse width increase signal, which is a signal that turns on the switch during dead time. For example, processing the control signal may mean delaying the control signal and / or increasing the pulse width of the control signal.

[0176] In one embodiment, the fourth control signal (S4) may be input to the fourth delay circuit (2020). For example, the pulse width of the fourth control signal (S4) may be 20ns. 20ns is merely an example and is not limited thereto. The fourth delay circuit (2020) may output a delay signal of the fourth control signal (S4). For example, the delay signal of the fourth control signal (S4) may be a signal that delays the fourth control signal (S4) by 5ns. Thus, by delaying the fourth control signal (S4), the pulse width increase signal may be advanced by 5ns relative to the delay signal of the fourth control signal (S4). Here, 5ns is merely an example and is not limited thereto.

[0177] The multi-level output voltage switching circuit (2000) can obtain results identical or similar to the simulation results (1500a) of the multi-level output voltage switching circuit (1300a) described in FIG. 15a, as described in the description regarding FIG. 20.

[0178] FIG. 21 illustrates a multi-level output voltage switching circuit with an extended output voltage level according to one embodiment of the present disclosure.

[0179] Referring to FIG. 21, in one embodiment, the multi-level output voltage switching circuit (2100) may be an n-level output voltage switching circuit. The n-levels are a first voltage (V1), ..., an n-1th voltage (V n-1 ), and the nth voltage (V n It can mean n voltage levels of ). The first voltage (V1) may be greater than the second voltage (V2), ..., the n-2nd voltage (V n-2 ) is the n-1st voltage (V n-1 It can be greater than ), and the n-1th voltage (V n-1 ) is the nth voltage (V nIt can be greater than ). n can be any integer greater than or equal to 3. For example, when n=3, the multi-level output voltage switching circuit (2100) can be the multi-level output voltage switching circuit (1900a) of FIG. 19a. For example, when n=4, the multi-level output voltage switching circuit (2100) can be the multi-level output voltage switching circuit (2000) of FIG. 20.

[0180] In one embodiment, the multi-level output voltage switching circuit (2100) may include a switch control unit (2120), a delay circuit (2110) and a transistor (2140) associated with a first voltage (V1), a delay circuit (2112) and an OR gate (2160) associated with a second voltage (V2), a pulse width increase circuit (2130) and back-to-back connected transistors (2141, 2142), a delay circuit (2114) and an OR gate (2162) associated with an n-2 voltage, a pulse width increase circuit (2132) and back-to-back connected transistors (2143, 2144), a delay circuit (2116) and an OR gate (2164) associated with an n-1 voltage, a pulse width increase circuit (2143) and back-to-back connected transistors (2145, 2146), and a delay circuit (2118) and a transistor (2147) associated with an n-th voltage. There is. The switch control unit (2120) includes a first control signal (S1), a second control signal (S2), ..., an n-2nd control signal (S n-2 ), n-1th control signal (S n-1 ), and the nth control signal (S n Can supply ).

[0181] In one embodiment, two back-to-back connected transistors of a multi-level output voltage switching circuit (2100) can each be controlled by a separate control signal. The two back-to-back connected transistors can be controlled separately by processing the transistor control signal associated with a voltage equal to or higher than the switching voltage. For example, processing the control signal may mean delaying the control signal and / or increasing the pulse width of the control signal.

[0182] For example, the transistor (2142) of the back-to-back connected transistors (2141, 2142) associated with the second voltage (V2) can be controlled by the delay signal of the second control signal (S2) output through the delay circuit (2112). The transistor (2141) can be controlled by the pulse width increase signal output through the pulse width increase circuit (2130), which is the OR logic operation signal of the first control signal (S1) and the second control signal (S2) output through the OR gate (2160).

[0183] For example, the n-2nd voltage (V n-2 The transistor (2144) of the back-to-back connected transistors (2143, 2144) associated with ) is the n-2nd control signal (S n-2 ) is the n-2nd control signal (S) output through the delay circuit (2114) n-2 It can be controlled by a delay signal of ). The transistor (2143) is controlled by a first control signal (S1), a second control signal (S2), ..., an n-2nd control signal (S n-2 The OR logic operation signal output through the OR gate (2162) can be controlled by the pulse width increase signal output through the pulse width increase circuit (2132).

[0184] For example, the n-1th voltage (V n-1 The transistor (2146) of the back-to-back connected transistors (2145, 2146) associated with ) is the n-1st control signal (S n-1) is the n-1st control signal (S) output through the delay circuit (2116) n-1 It can be controlled by a delay signal of ). The transistor (2145) is controlled by a first control signal (S1), a second control signal (S2), ..., an n-2nd control signal (S n-2 ), n-1th control signal (S n-1 The OR logic operation signal output through the OR gate (2162) can be controlled by the pulse width increase signal output through the pulse width increase circuit (2164). As a result, when transistor (2140) or transistor (2142) is turned on, transistor (2141) can be turned on. The OR gate of the present disclosure may include any operator capable of performing a logic operation identical to the OR logic operation.

[0185] The multi-level output voltage switching circuit (2100) can obtain results identical or similar to the simulation results (1500b) of the multi-level output voltage switching circuit (1400) described in FIG. 15b, as described in the description regarding FIG. 21.

[0186] The explosive growth of wireless data traffic and the emergence of 6G communication systems require efficient and compact power amplifiers (PAs) for next-generation base stations. Envelope tracking (ET) improves PA efficiency by dynamically adjusting the supply voltage for RF signals. However, integrating high-voltage and broadband supply modulators into ET systems presents significant design challenges. Conventional research on multi-level supply modulators aims to reduce switching losses and improve efficiency. While discrete implementations using multiple power stages have demonstrated reasonable performance, they often face difficulties due to increased complexity for base station integration, larger form factors, and limited scalability. Therefore, considering the need to integrate a large number of PAs and supply modulators into base stations for 5G / 6G MIMO systems, a multi-level supply modulator implemented as a fully integrated circuit is proposed in this disclosure.

[0187] FIG. 22 illustrates a Supply Modulator Integrated Circuit (SMIC) according to one embodiment of the present disclosure.

[0188] Referring to FIG. 22, in one embodiment, the SMIC (2200) may include a Switched-Capacitor Voltage Divider (SCVD), a Serial Peripheral Interface (SPI), Digital Logic for Level Selection Switch (LSSW), an LSSW Low side, and an LSSW High side. For example, the SMIC (2200) may be a 6G digital Envelope Tracking (DET) SMIC fabricated using a 130-nm Bipolar-CMOS-DMOS (BCD) process. For example, the SMIC (2200) may be fabricated using a 130-nm BCD process to minimize the size of the Digital Envelope Tracking (DET) module in both the Memory Management Unit (MMU) and the Radio Unit (RU). For example, the area of ​​the SMIC (2200) may be 7.0 mm x 3.5 mm. Such figures are merely examples and are not limited thereto. SMIC (2200) can provide a compact and efficient solution for ET-based power amplifier systems in 5G / 6G MIMO base stations.

[0189] FIG. 23 illustrates a Switched-Capacitor Voltage Divider (SCVD) according to one embodiment of the present disclosure.

[0190] Referring to FIG. 23, in one embodiment, the SCVD (2300) comprises six power transistors and five off-chip capacitors (C F , C O It may include ). For example, SCVD (2300) has a 1 MHz external clock (CK SCVD_P , CK SCVD_NUsing ), four voltage levels (V1, V2, V3, and V4) can be generated from two external supply voltages (V1 and V4). The SCVD (2300) can ensure reliable high-voltage operation by using a synchronous bootstrap circuit to provide a gate driver voltage to the power transistor. Additionally, the SCVD (2300) can operate with a level shifter to ensure accurate switching of the transistor even in high-voltage regions.

[0191] FIG. 24a illustrates a 4-level LSSW (Level Selection Switch) according to one embodiment of the present disclosure.

[0192] Referring to FIG. 24a, in one embodiment, a 4-level LSSW (2400a) may include Digital Logic for LSSW (2420), level shifters and gate drivers (2440), and transistors (M1, M2, M3, M4, M5, M6). The 4-level LSSW (2400a) may correspond to the multi-level output voltage switching circuit (2000) of FIG. 20 when described excluding the level shifters and gate drivers (2440). For example, the first voltage (V1), second voltage (V2), third voltage (V3), and fourth voltage (V4) of FIG. 20 may correspond to V4, V3, V2, and V1 of FIG. 24a, respectively. For example, the first transistor (640), second transistor (642), third transistor (644), fourth transistor (646), fifth transistor (2040), and sixth transistor (2042) of FIG. 20 may correspond to M6, M4, M5, M1, M2, and M3 of FIG. 24a, respectively.

[0193] In one embodiment, Digital Logic for LSSW (2420) comprises forward control signals (V F1, V F2 , V F3 , and V F4 ) and reverse control signals (V R2 , V R3 Can supply ). Forward control signals (V F1 , V F2 , V F3 , and V F4 ) may be a signal controlling the forward switches (M1, M3, M5, and M6). For example, the forward switch (M1) is a forward control signal (V F1 It can be controlled by ), and the forward switch (M3) is a forward control signal (V F1 It can be controlled by ), and the forward switch (M1) is a forward control signal (V F2 It can be controlled by ), and the forward switch (M5) is a forward control signal (V F3 It can be controlled by ), and the forward switch (M6) is a forward control signal (V F4 It can be controlled by ). Reverse control signals (V R2 , V R3 ) may be a signal controlling the reverse switch (M2, M4). For example, the reverse switch (M2) is a reverse control signal (V R2 It can be controlled by ), and the reverse switch (M4) is a reverse control signal (V R3 It can be controlled by ). In one embodiment, forward control signals (V F1 , V F2 , V F3 , and V F4 ) and reverse control signals (V R2 , V R3 ) can be input to the corresponding forward switches (M1, M3, M5, M6) and reverse switches (M2, M4), respectively, through a level shifter and a gate driver.

[0194] In one embodiment, Digital Logic for LSSW (2420) may be understood to include the switch control unit (620) of FIG. 20, delay circuits (1920, 1922, 1924, 2020), OR gates (1960, 2060), and pulse width increase circuits (1940, 2030). For example, a forward control signal (V F1 ) may be a signal in which the third control signal (S3) of FIG. 20 is output through the third delay circuit (1924). Forward control signal (V F2 ) may be a signal in which the fourth control signal (S4) of FIG. 20 is output through the fourth delay circuit (2020). Forward control signal (V F3 ) may be a signal in which the second control signal (S2) of FIG. 20 is output through the second delay circuit (1922). Forward control signal (V F4 ) may be a signal in which the first control signal (S1) of FIG. 20 is output through the first delay circuit (1920). For example, a reverse control signal (V R2 ) may be a signal output through a pulse width increase circuit (2030) of an OR logic operation signal, which is output through an OR gate (2060) of the first control signal (S1), second control signal (S2), and fourth control signal (S4) of FIG. 20. Reverse control signal (V R3 ) may be a signal that is an OR logic operation signal output through an OR gate (1960) of the first control signal (S1) and the second control signal (S2) of FIG. 20, and is output through a pulse width increase circuit (1940).

[0195] In FIG. 24a, the same configurations as in FIG. 6, FIG. 19a, FIG. 19b, and FIG. 20 are illustrated using the same reference numerals. Therefore, in describing the configurations of FIG. 24a, descriptions that overlap with the aforementioned descriptions are omitted, and the descriptions of FIG. 6, FIG. 19a, FIG. 19b, and FIG. 20 are included by reference.

[0196] The 4-level LSSW (2400a) of FIG. 24a can be applied as a 3-level LSSW or an n-level LSSW. For example, the 3-level LSSW can correspond to the multi-level output voltage switching circuit (1900a) of FIG. 19a. For example, the n-level LSSW can correspond to the multi-level output voltage switching circuit (2100) of FIG. 21.

[0197] In one embodiment, the 4-level LSSW (2400a) may use a single transistor for the V1 and V4 voltage levels and back-to-back connected transistors for the V2 and V3 levels to generate the 4-level switch output voltage. Since the output voltage of the 4-level LSSW (2400a) switches between V1 and V4, back-to-back connected transistors may be required in the V2 and V3 paths to prevent reverse current caused by the body diodes of the transistors. For example, the forward switch (M3) and the reverse switch (M2) may be back-to-back connected transistors. The forward switch (M5) and the reverse switch (M4) may be back-to-back connected transistors.

[0198] In one embodiment, the forward switches (M1, M3, M5, M6) of the 4-level LSSW (2400a) are forward control signals (V F1 , V F2 , V F3 , V F4 It can be controlled by ). The reverse switch (M2, M4) is controlled by the reverse control signal (V R2 , V R3 It can maintain the output voltage during the switching dead time by being independently controlled by ). For example, the reverse control signal (V Rn ) is the corresponding forward control signal (V Fn ) and simultaneous activation (V Rn =V Fn Compared to a conventional switching method in which ) is used, the switching method of the present disclosure has a corresponding forward control signal (V Fn) or a forward control signal of a higher voltage level (V Fn+1 or V Fn+2 When ) is activated, the reverse control signal (V Rn ) can be enabled. Two back-to-back connected transistors can be controlled separately by processing a transistor control signal associated with a voltage equal to or higher than the switching voltage. For example, processing the control signal may mean delaying the control signal and / or increasing the pulse width of the control signal. Through this, the switching method of the present disclosure can effectively prevent output voltage drop during the switching dead time.

[0199] In one embodiment, VDD for the level shifters and gate drivers (2440) of the 4-level LSSW (2400a) can be generated by the bootstrap circuit of FIG. 24b.

[0200] FIG. 24b illustrates a bootstrap circuit for an LSSW according to one embodiment of the present disclosure.

[0201] Referring to FIG. 24b, in one embodiment, the bootstrap circuit (2400b) has a source voltage (V Lx A 100kHz external clock may be used to maintain a voltage difference of ) and 5V. The bootstrap circuit (2400b) provides VDD (V for the level shifters and gate drivers (2440). BOOTx Can generate ).

[0202] FIGS. 25a and FIGS. 25b illustrate simulation results of an SMIC according to one embodiment of the present disclosure.

[0203] Referring to FIG. 25a, the measured output voltage waveform of the SMIC (2200) of FIG. 22 operating at a supply modulation switching frequency of 4 MHz is described below. The values ​​listed in the graph are merely examples to aid in understanding the present disclosure and do not limit the present disclosure.

[0204] In one embodiment, the SMIC (2200) may receive two external supply voltages, namely V1=30V and V4=48V, from a power supply, and intermediate voltages V2=36V and V3=42V may be generated internally by the SCVD (2300). A switching dead time may be maintained to mitigate potential efficiency degradation during voltage switching. The switching method of the present disclosure may ensure voltage continuity through a reverse switching current path during the dead time. Compared to a conventional switching method (2520), the switching method of the present disclosure (2540) may improve the output voltage by approximately 6.9V during the dead time, as observed in the measurement results.

[0205] With reference to FIG. 25b, the efficiency graph of the SMIC (2200) of FIG. 22 is described below. In one embodiment, the SMIC (2200) can achieve efficiencies of 98.9% and 94.5% at switching frequencies of 1 MHz and 10 MHz, respectively, and the average output power can be 32.0 W. Through this, the SMIC (2200) of the present disclosure can have the highest efficiency among single-chip integrated supply modulators operating at 48 V.

[0206] FIG. 26 illustrates an operation for controlling a transistor of an output voltage switching circuit according to one embodiment of the present disclosure.

[0207] In one embodiment, the electronic device may include a first transistor associated with a first voltage, a second transistor and a third transistor associated with a second voltage, and a fourth transistor associated with a third voltage. In one embodiment, the first signal may mean a signal to turn on the transistor, and the second signal may mean a signal to turn off the transistor. In one embodiment, the source node of the third transistor may be connected to the source node of the second transistor, or the drain node of the third transistor may be connected to the drain node of the second transistor.

[0208] In operation 2620, the electronic device may perform the operation of inputting a first signal to the gate node of a first transistor connected to a first delay circuit. Operation 2620 may correspond to the first operation (700a) of FIG. 7.

[0209] In operation 2640, the electronic device may input a second signal to the gate node of a first transistor connected to a first delay circuit, the gate node of a third transistor connected to a second delay circuit, and the gate node of a fourth transistor connected to a third delay circuit, and input a first signal to the gate node of a second transistor connected to a first pulse width increase circuit. Operation 2640 may correspond to the second operation (700b) of FIG. 7. In one embodiment, the first pulse width increase circuit may be connected to a first OR gate to which the first delay circuit and the second delay circuit are connected. In one embodiment, the first OR gate may receive a signal input to the first delay circuit and a signal input to the second delay circuit and output a first OR logic operation signal. The first pulse width increase circuit may receive the first OR logic operation signal and output a first pulse width increase signal. The first pulse width increase signal may be a first signal input to the gate node of the second transistor.

[0210] In operation 2660, the electronic device may input a first signal to the gate node of a third transistor connected to a second delay circuit. Operation 2660 may correspond to the third operation (700c) of FIG. 7.

[0211] In one embodiment, an electronic device including an output voltage switching circuit may be provided. The electronic device may include a first transistor connected to a first voltage node, an output voltage node, and a first control input node. The electronic device may include a second transistor connected to a second voltage node, a third transistor, and a second control input node. The electronic device may include a third transistor connected to a third control input node, an output voltage node, and the second transistor. In the electronic device, the source node of the third transistor may be connected to the source node of the second transistor, or the drain node of the third transistor may be connected to the drain node of the second transistor. The electronic device may include a fourth transistor connected to a third voltage node, an output voltage node, and a fourth control input node. The electronic device may include a first phase inversion circuit connecting the second control input node and the fourth control input node.

[0212] In one embodiment, in the electronic device, the first phase inversion circuit receives a signal from the fourth control input node and can invert the phase of the signal and output it through the second control input node.

[0213] In one embodiment, the electronic device may include an N-channel MOSFET (N-channel Metal Oxide Semiconductor Field Effect Transistor) or a P-channel MOSFET.

[0214] In one embodiment, in the electronic device, the first voltage may be greater than the second voltage. In one embodiment, in the electronic device, the second voltage may be greater than the third voltage.

[0215] In one embodiment, in the electronic device, the output voltage node may be connected to a power amplifier.

[0216] In one embodiment, in the electronic device, the first phase inversion circuit may include a NOT gate.

[0217] In one embodiment, in the electronic device, the first phase inversion circuit may include an inverter.

[0218] In one embodiment, the electronic device may include a fifth transistor connected to a fourth voltage node, a sixth transistor, and a fifth control input node. In one embodiment, the electronic device may include a sixth transistor connected to a sixth control input node, an output voltage node, and the fifth transistor. In one embodiment, in the electronic device, the source node of the sixth transistor may be connected to the source node of the fifth transistor, or the drain node of the sixth transistor may be connected to the drain node of the fifth transistor. In one embodiment, the electronic device may include a logic operation circuit connecting the third control input node, the fourth control input node, and the fifth control input node.

[0219] In one embodiment, the logic operation circuit in the electronic device may include an OR gate and a second phase inversion circuit. In one embodiment, the OR gate in the electronic device may be connected to the third control input node, the fourth control input node, and the second phase inversion circuit. In one embodiment, the second phase inversion circuit in the electronic device may be connected to the OR gate and the fifth control input node.

[0220] In one embodiment, the logic operation circuit in the electronic device may include a NOR gate.

[0221] In one embodiment, in the electronic device, the first voltage may be greater than the fourth voltage. In one embodiment, in the electronic device, the fourth voltage may be greater than the second voltage.

[0222] In one embodiment, the electronic device may include a deadtime detection circuit connected to a first multiplexer and a second multiplexer. In one embodiment, the electronic device may include the first multiplexer connected to the deadtime detection circuit, the second control input node, the third control input node, and the first phase inversion circuit. In one embodiment, the electronic device may include the second multiplexer connected to the deadtime detection circuit, the fifth control input node, the sixth control input node, and the logic operation circuit.

[0223] In one embodiment, the electronic device may include a current measuring unit connected to the dead time detection circuit, the fourth transistor, and the output voltage node.

[0224] In one embodiment, a method performed by an electronic device may be provided. The electronic device may include a first transistor associated with a first voltage, a second transistor and a third transistor associated with a second voltage, and a fourth transistor associated with a third voltage. The method may include the step of inputting a first signal to the gate node of the first transistor or the gate node of the fourth transistor. The method may include the step of inputting a second signal to the gate node of the first transistor, the gate node of the third transistor, and the gate node of the fourth transistor, and inputting the signal input to the gate node of the fourth transistor to the gate node of the second transistor through a phase inversion circuit. The method may include the step of inputting the first signal to the gate node of the third transistor. In the method, the source node of the third transistor may be connected to the source node of the second transistor, or the drain node of the third transistor may be connected to the drain node of the second transistor.

[0225] In one embodiment, in the method, the first signal may be a signal for turning on the transistor. In one embodiment, in the method, the second signal may be a signal for turning off the transistor.

[0226] In one embodiment, in the method, the transistor may include an N-channel Metal-Oxide-Semiconductor Field Effect Transistor or a P-channel MOSFET.

[0227] In one embodiment, in the method, the first voltage may be greater than the second voltage. In one embodiment, in the method, the second voltage may be greater than the third voltage.

[0228] In one embodiment, the method may include the step of outputting the voltage through the transistor. In one embodiment, the method may include the step of supplying the output voltage to a power amplifier.

[0229] In one embodiment, in the method, the phase inversion circuit may include a NOT gate.

[0230] In one embodiment, in the method, the phase inversion circuit may include an inverter.

[0231] In one embodiment, an electronic device including an output voltage switching circuit may be provided. The electronic device may include a first control input node connected to a first delay circuit and a first transistor connected to a first voltage node and an output voltage node. The electronic device may include a second control input node connected to a first pulse width increase circuit and a second transistor connected to a second voltage node and a third transistor. The electronic device may include a third control input node connected to a second delay circuit and the third transistor connected to the output voltage node and the second transistor. In the electronic device, the source node of the third transistor may be connected to the source node of the second transistor, or the drain node of the third transistor may be connected to the drain node of the second transistor. The electronic device may include a fourth control input node connected to a third delay circuit and a fourth transistor connected to a third voltage node and the output voltage node. The electronic device may include a first OR gate connecting the first delay circuit, the second delay circuit, and the first pulse width increase circuit.

[0232] In one embodiment, in the electronic device, the first OR gate can receive a signal input to the first delay circuit and a signal input to the second delay circuit and output a first OR logic operation signal. In the electronic device, the first pulse width increase circuit can receive the first OR logic operation signal and output a first pulse width increase signal.

[0233] In one embodiment, the electronic device may include a fifth control input node connected to a second pulse width increase circuit and a fifth transistor connected to a fourth voltage node and a sixth transistor. The electronic device may include a sixth control input node connected to a fourth delay circuit and the sixth transistor connected to the output voltage node and the fifth transistor. In the electronic device, the source node of the sixth transistor may be connected to the source node of the fifth transistor, or the drain node of the sixth transistor may be connected to the drain node of the fifth transistor. The electronic device may include a second OR gate connecting the first delay circuit, the second delay circuit, the fourth delay circuit, and the second pulse width increase circuit.

[0234] In one embodiment, in the electronic device, the second OR gate can receive a signal input to the first delay circuit, a signal input to the second delay circuit, and a signal input to the fourth delay circuit, and output a second OR logic operation signal. In the electronic device, the second pulse width increase circuit can receive the second OR logic operation signal and output a second pulse width increase signal.

[0235] In one embodiment, in the electronic device, the second voltage is greater than the fourth voltage, and the fourth voltage may be greater than the third voltage.

[0236] In one embodiment, a method performed by an electronic device may be provided. The electronic device may include a first transistor associated with a first voltage, a second transistor and a third transistor associated with a second voltage, and a fourth transistor associated with a third voltage. The method may include the step of inputting a first signal to the gate node of the first transistor connected to a first delay circuit. The method may include the step of inputting a second signal to the gate node of the first transistor connected to the first delay circuit, the gate node of the third transistor connected to a second delay circuit, and the gate node of the fourth transistor connected to a third delay circuit, and inputting the first signal to the gate node of the second transistor connected to a first pulse width increase circuit. In the method, the first pulse width increase circuit may be connected to a first OR gate connected to the first delay circuit and the second delay circuit. The method may include the step of inputting the first signal to the gate node of the third transistor connected to the second delay circuit. In the above method, the source node of the third transistor may be connected to the source node of the second transistor, or the drain node of the third transistor may be connected to the drain node of the second transistor.

[0237] In one embodiment, in the method, the first OR gate may receive a signal input to the first delay circuit and a signal input to the second delay circuit and output a first OR logic operation signal. In the method, the first pulse width increase circuit may receive the first OR logic operation signal and output a first pulse width increase signal. In the method, the first pulse width increase signal may be the first signal input to the gate node of the second transistor.

[0238] In one embodiment, in the method, the first signal may be a signal for turning on the transistor and the second signal may be a signal for turning off the transistor.

[0239] The foregoing description of the present disclosure is for illustrative purposes only, and those skilled in the art will understand that other specific forms can be easily modified without altering the technical spirit or essential features of the present disclosure. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive. For example, each component described as a single unit may be implemented in a distributed manner, and components described as distributed may likewise be implemented in a combined form.

[0240] The scope of the present disclosure is defined by the claims set forth below rather than by the detailed description above, and all modifications or variations derived from the meaning and scope of the claims and equivalent concepts thereof should be interpreted as being included within the scope of the present disclosure.

Claims

1. A first transistor connected to a first control input node connected to a first delay circuit, a first voltage node, and an output voltage node; A second control input node connected to a first pulse width increase circuit, a second voltage node, and a second transistor connected to a third transistor; A third control input node connected to a second delay circuit and the third transistor connected to the output voltage node and the second transistor, wherein the source node of the third transistor is connected to the source node of the second transistor or the drain node of the third transistor is connected to the drain node of the second transistor; A fourth control input node connected to a third delay circuit, a third voltage node, and a fourth transistor connected to the output voltage node; and An electronic device comprising a first OR gate connecting the first delay circuit, the second delay circuit, and the first pulse width increase circuit.

2. In Paragraph 1, The first OR gate receives a signal input to the first delay circuit and a signal input to the second delay circuit, outputs a first OR logic operation signal, and The above first pulse width increase circuit is an electronic device that receives the first OR logic operation signal and outputs the first pulse width increase signal.

3. In Paragraph 1, The above transistor is an electronic device comprising an N-channel MOSFET (N-channel Metal Oxide Semiconductor Field Effect Transistor) or a P-channel MOSFET.

4. In Paragraph 1, The first voltage is greater than the second voltage, and An electronic device in which the second voltage is greater than the third voltage.

5. In Paragraph 1, The above output voltage node is an electronic device connected to a power amplifier.

6. In Paragraph 1, A fifth control input node connected to a second pulse width increase circuit, a fourth voltage node, and a fifth transistor connected to a sixth transistor; A sixth control input node connected to a fourth delay circuit and the output voltage node and the sixth transistor connected to the fifth transistor, wherein the source node of the sixth transistor is connected to the source node of the fifth transistor or the drain node of the sixth transistor is connected to the drain node of the fifth transistor; and An electronic device further comprising a second OR gate connecting the first delay circuit, the second delay circuit, the fourth delay circuit, and the second pulse width increase circuit.

7. In Paragraph 6, The second OR gate receives a signal input to the first delay circuit, a signal input to the second delay circuit, and a signal input to the fourth delay circuit, outputs a second OR logic operation signal, and The above second pulse width increase circuit is an electronic device that receives the above second OR logic operation signal and outputs a second pulse width increase signal.

8. In Paragraph 6, The second voltage is greater than the fourth voltage, and An electronic device in which the above-mentioned fourth voltage is greater than the above-mentioned third voltage.

9. In a method performed by an electronic device, the electronic device comprises a first transistor associated with a first voltage, a second transistor and a third transistor associated with a second voltage, and a fourth transistor associated with a third voltage, and A step of inputting a first signal to the gate node of the first transistor connected to the first delay circuit; A step of inputting a second signal to the gate node of the first transistor connected to the first delay circuit, the gate node of the third transistor connected to the second delay circuit, and the gate node of the fourth transistor connected to the third delay circuit, and inputting the first signal to the gate node of the second transistor connected to the first pulse width increase circuit. The first pulse width increase circuit is connected to a first OR gate to which the first delay circuit and the second delay circuit are connected; and The method includes the step of inputting the first signal to the gate node of the third transistor connected to the second delay circuit, A method in which the source node of the third transistor is connected to the source node of the second transistor, or the drain node of the third transistor is connected to the drain node of the second transistor.

10. In Paragraph 9, The first OR gate receives a signal input to the first delay circuit and a signal input to the second delay circuit, and outputs a first OR logic operation signal. The first pulse width increase circuit receives the first OR logic operation signal as input and outputs the first pulse width increase signal, and A method in which the first pulse width increase signal is the first signal input to the gate node of the second transistor.

11. In Paragraph 9, The first signal above is a signal that turns on the transistor, and A method in which the second signal is a signal to turn off the transistor.

12. In Paragraph 9, A method in which the transistor comprises an N-channel MOSFET (N-channel Metal-Oxide-Semiconductor Field Effect Transistor) or a P-channel MOSFET.

13. In Paragraph 9, The first voltage is greater than the second voltage, and A method in which the second voltage is greater than the third voltage.

14. In Paragraph 9, A step of outputting the voltage through the transistor; and A method further comprising the step of supplying the above output voltage to a power amplifier.

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