CS-JL device and manufacturing method therefor, and electronic device
By first fabricating the Core layer and dummy gate structure, and then etching the Core layer to form the Shell layer, the problem of uncontrollable doping concentration and thickness of CS-JL devices is solved, realizing performance improvement and applicability for 3D integration.
Patent Information
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- GUANGDONG GREATER BAY AREA INST OF INTEGRATED CIRCUIT & SYST
- Filing Date
- 2024-11-20
- Publication Date
- 2026-05-21
AI Technical Summary
After the CS-JL device is fabricated, the doping concentration and thickness of the Core layer and Shell layer deviate from the ideal parameters, resulting in increased off-state leakage current and significant performance degradation.
First, the core layer, dummy gate structure, sidewall structure, source, and drain are prepared. Then, the dummy gate structure is removed and the core layer is etched. Finally, the shell layer and gate structure are formed to avoid the influence of high-temperature process on impurity diffusion in the channel region and to precisely control the doping concentration and thickness.
It effectively reduces the off-state leakage current of CS-JL devices, improves device performance, is suitable for 3D integration applications, and is compatible with high-κ metal gate-back gate processes.
Smart Images
Figure CN2024133181_21052026_PF_FP_ABST
Abstract
Description
A CS-JL device and its fabrication method, and an electronic device.
[0001] This application claims priority to Chinese Patent Application No. 2024116321788, filed on November 14, 2024, entitled "A CS-JL Device and its Fabrication Method, Electronic Device", the entire contents of which are incorporated herein by reference. Technical Field
[0002] This application relates to the field of semiconductor technology, and in particular to a CS-JL device and its fabrication method, and electronic equipment. Background Technology
[0003] As Moore's theorem continues to advance, device dimensions are shrinking and channel lengths are shortening, leading to a decline in the gate control capability of traditional bulk silicon devices and a severe short-channel effect. Junctionless (JL) devices, due to their excellent subthreshold characteristics, offer advantages such as a high on-off current ratio and low drain-induced barrier lowering (DIBL), making them a viable technological approach to address the short-channel effect. Because their channel and source / drain doping types are the same and the doping concentration is relatively high (approximately 10⁻⁶), they are suitable for addressing this issue. 19 cm 3 Therefore, the process is simple and suitable for 3D process integration with a low thermal budget.
[0004] However, due to the high doping concentration of the channel in JL devices, problems such as low carrier mobility, strong random doping fluctuations, and difficulty in channel depletion at zero gate voltage leading to a negative threshold voltage exist. To address these issues, researchers have proposed an improved planar JL device, where the channel consists of a highly doped Si (Core layer) at the bottom and an undoped Si (Shell layer) at the top, known as the CS-JL (Coreshell Junctionless) device. The CS-JL device features a positive threshold voltage, high charge capacity, high mobility, and large drive current. While inheriting the advantages of JL devices, it avoids a series of problems caused by the high doping concentration of the channel in traditional JL devices, and will play an important role in future 3D integration applications.
[0005] However, currently, the doping concentration and thickness of the Core and Shell layers of the CS-JL device deviate from the ideal parameters after fabrication, resulting in increased off-state leakage current and significant performance degradation. Summary of the Invention
[0006] In view of the above problems, this application provides a CS-JL device and its fabrication method, as well as an electronic device, which can obtain a Core layer and Shell layer with precise controllable doping concentration and thickness, thereby improving the performance of the CS-JL device. The specific solution is as follows:
[0007] The first aspect of this application provides a method for fabricating a CS-JL device, the method comprising:
[0008] Provide a substrate;
[0009] A core layer is formed on one side of the substrate;
[0010] A dummy gate structure, a sidewall structure, a source, and a drain are formed on the side of the Core layer facing away from the substrate.
[0011] Remove the dummy gate structure and etch a portion of the Core layer;
[0012] A Shell layer is formed on the surface of the exposed Core layer;
[0013] A gate structure is formed on the Shell layer.
[0014] Preferably, in the above-described method for fabricating the CS-JL device, before forming the Core layer, the method further includes:
[0015] A buried oxide layer is formed on one side of the substrate.
[0016] Preferably, in the above-described method for fabricating the CS-JL device, the step of removing the dummy gate structure and etching a portion of the Core layer includes:
[0017] The dummy gate structure is removed by dry etching or wet etching, and part of the Core layer is etched.
[0018] Preferably, in the above-described method for fabricating the CS-JL device, the step of removing the dummy gate structure and etching a portion of the Core layer includes:
[0019] The dummy gate structure is removed using a sacrificial oxide process, and a portion of the Core layer is etched.
[0020] Preferably, in the above-described method for fabricating the CS-JL device, the step of removing the dummy gate structure and etching a portion of the Core layer includes:
[0021] The dummy gate structure is removed using atomic layer stripping technology, and part of the Core layer is etched.
[0022] Preferably, in the above-described method for fabricating the CS-JL device, after forming the source and the drain, the method further includes:
[0023] The source and drain are processed using a metallization process.
[0024] Preferably, in the above-described method for fabricating the CS-JL device, the step of forming a dummy gate structure on the side of the Core layer facing away from the substrate includes:
[0025] A dummy gate dielectric layer and a dummy gate are formed on the side of the Core layer facing away from the substrate.
[0026] Preferably, in the above-described method for fabricating the CS-JL device, forming a gate structure on the Shell layer includes:
[0027] A gate dielectric layer and a high-k metal gate are formed on the Shell layer.
[0028] A second aspect of this application provides a CS-JL device, which is obtained by the fabrication method of any of the above-described CS-JL devices.
[0029] A third aspect of this application provides an electronic device, which includes the CS-JL device described above.
[0030] By employing the above technical solution, this application provides a CS-JL device and its fabrication method, as well as an electronic device. The fabrication method of the CS-JL device first fabricates a Core layer, then fabricates a dummy gate structure, a sidewall structure, a source, and a drain. Subsequently, a Shell layer is fabricated by removing the dummy gate structure, and finally, a gate structure is formed. This effectively avoids the influence of the high temperatures required during the fabrication of the sidewall structure, source, and drain on the diffusion of impurities in the channel region. It is beneficial to accurately control the doping concentration and thickness of the Core layer and the Shell layer, reduce the off-state leakage current of the CS-JL device, and improve its device performance. Attached Figure Description
[0031] The above and other features, advantages, and aspects of the embodiments of this disclosure will become more apparent from the accompanying drawings and the following detailed description. Throughout the drawings, the same or similar reference numerals denote the same or similar elements. It should be understood that the drawings are schematic, and the originals and elements are not necessarily drawn to scale.
[0032] Figure 1 is a schematic flowchart of a method for fabricating a CS-JL device according to an embodiment of the present invention;
[0033] Figures 2-10 are schematic diagrams of some structures corresponding to the preparation method shown in Figure 1. Detailed Implementation
[0034] The embodiments of this application are described below with reference to the accompanying drawings. The terminology used in the implementation section of this application is only for explaining specific embodiments and is not intended to limit the application. Those skilled in the art will understand that, with technological advancements and the emergence of new scenarios, the technical solutions provided in the embodiments of this application are also applicable to similar technical problems. It should be noted that the directional terms appearing in this invention are based on the relative positional relationships shown in the accompanying drawings and should not be considered as absolute limitations on this application.
[0035] Based on the information provided in the background art, the applicant has found that current research on planar CS-JL devices is mainly based on simulation modeling and lacks a mature device manufacturing process. Solving the manufacturability problem of CS-JL devices is a necessary condition for obtaining experimental data and conducting in-depth basic research and application.
[0036] Since CS-JL devices have a highly doped Core layer and an undoped Shell layer, both with a thickness of several nanometers, variations in doping concentration and thickness have a significant impact on the performance of CS-JL devices. Therefore, the applicant found that the main challenge in manufacturing CS-JL devices lies in obtaining Core and Shell layers with precisely controllable doping concentration and thickness.
[0037] From a device structure perspective, both CS-JL devices and FDSOI (Fully Depleted Silicon On Insulator) devices are based on SOI substrates. The main difference lies in the channel region. The fabrication process for planar CS-JL devices is compatible with that of FDSOI. Existing CS-JL device fabrication schemes are primarily based on the basic process flow of FDSOI devices, with adjustments made accordingly.
[0038] The existing CS-JL device fabrication process involves first forming a Core layer with a high doping concentration, then using epitaxial technology to fabricate a Shell layer of a certain thickness without doping, followed by processes such as gate dielectric layer, gate, sidewall, and source / drain.
[0039] However, the applicant discovered that after both the Core and Shell layers were fabricated, the growth processes of the sidewalls and source / drain layers all required high-temperature annealing, with the highest annealing temperature required for source / drain activation. This higher annealing temperature caused dopants (such as phosphorus) in the Core layer to diffuse extensively into the undoped Shell layer, resulting in a slower doping gradient and a larger Core layer. Consequently, the doping concentration and thickness of both the Core and Shell layers deviated from ideal parameters, leading to increased off-state leakage current and significant performance degradation in the CS-JL device.
[0040] Based on this, this application provides a CS-JL device and its fabrication method and electronic device, which can solve the problem of uncontrollable doping concentration and thickness of the Core layer and Shell layer caused by element diffusion due to high temperature, and improve the performance of CS-JL device.
[0041] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.
[0042] Referring to Figure 1, Figure 1 is a schematic flowchart of a method for fabricating a CS-JL device according to an embodiment of the present invention. The method for fabricating a CS-JL device according to an embodiment of the present invention includes:
[0043] S101: As shown in Figure 2, a substrate 11 is provided.
[0044] In this embodiment of the invention, the substrate 11 includes, but is not limited to, an SOI substrate.
[0045] In an optional embodiment of the present invention, as shown in FIG3, the fabrication method of the CS-JL device further includes, before forming the Core layer:
[0046] A buried oxide layer 12 is formed on one side of the substrate 11.
[0047] Among them, the buried oxygen layer 12 is also known in the field as the BOX layer.
[0048] S102: As shown in FIG4, a Core layer 13 is formed on one side of the substrate 11.
[0049] In the actual process, when fabricating SOI wafers, a wafer with a high doping concentration of the top silicon layer can be customized to obtain a highly doped Core layer 13.
[0050] S103: As shown in Figures 5-7, a dummy gate structure, a sidewall structure, a source, and a drain are formed on the side of the Core layer 13 away from the substrate.
[0051] As shown in Figure 5, a dummy gate structure is stacked above the highly doped Core layer 13, wherein the dummy gate structure includes a dummy gate dielectric layer 14 and a dummy gate 15. That is, the dummy gate structure is formed on the side of the Core layer 13 away from the substrate 11, including: forming a dummy gate dielectric layer 14 and a dummy gate 15 on the side of the Core layer 13 away from the substrate 11.
[0052] As shown in Figure 6, the sidewall structure 16 is grown based on the pseudo-gate structure.
[0053] As shown in Figure 7, this includes, but is not limited to, highly doped source 17 and drain 18 with convex shapes obtained by epitaxial processes.
[0054] In an optional embodiment of the present invention, after forming the source 17 and the drain 18, the fabrication method of the CS-JL device further includes:
[0055] The source electrode 17 and the drain electrode 18 are processed using a metallization process.
[0056] In other words, after the source electrode 17 and drain electrode 18 are prepared, the source electrode 17 and drain electrode 18 can be metallized to form silicide.
[0057] At this point, a process step with a high thermal budget was completed before the preparation of the Shell layer, avoiding the phenomenon in traditional processes where high temperatures cause Core 13 doping to diffuse into the Shell layer.
[0058] After completing the above process steps, we can then consider the preparation of the Shell layer, as shown in the following steps.
[0059] S104: As shown in Figure 8, remove the dummy gate structure and etch part of the Core layer 13.
[0060] In this process, the dummy gate structure is removed by etching, that is, the dummy gate dielectric layer 14 and dummy gate 15 are removed, and part of the Core layer 13 is etched to reserve space for the preparation of the Shell layer.
[0061] Understandably, removing the dummy gate structure through etching is similar to the gate-last process for high-κ metal gates. After removing all the dummy gate structures, it is still necessary to continue etching to a certain depth in the initial highly doped Core layer 13 to reserve space for the preparation of the Shell layer.
[0062] In an optional embodiment of the present invention, removing the dummy gate structure and etching a portion of the Core layer 13 includes:
[0063] The dummy gate structure is removed by dry etching or wet etching, and part of the Core layer 13 is etched.
[0064] In an optional embodiment of the present invention, removing the dummy gate structure and etching a portion of the Core layer 13 includes:
[0065] The dummy gate structure is removed using a sacrificial oxide process, and part of the Core layer 13 is etched.
[0066] In an optional embodiment of the present invention, removing the dummy gate structure and etching a portion of the Core layer 13 includes:
[0067] The dummy gate structure was removed using atomic layer etch (ALE) technology, and part of the Core layer 13 was etched.
[0068] It should be noted that step S104 is crucial for accurately forming the shell region, and the etching process must be carefully selected. In this embodiment of the invention, three different etching schemes can be selected: ordinary etching (dry etching, wet etching), sacrificial oxide layer process, and atomic layer stripping technology. The specific choice can be made based on the existing process equipment.
[0069] Among the three different etching schemes mentioned above, the ALE process is the optimal choice. This process selectively etches on a per-atom-layer basis, ensuring that different aperture areas are fabricated on the same wafer with the same etching rate and depth. This is beneficial for fabricating shell layers with the same depth and regular shape. Furthermore, this process is self-limiting, meaning it automatically stops after etching one atomic layer, allowing for repeated etching to achieve the desired depth. It eliminates the need for etching barrier layers to control the etching depth, offering advantages such as simple process steps and high etching precision.
[0070] S105: As shown in Figure 9, a Shell layer 19 is formed on the surface of the exposed Core layer 13.
[0071] This includes, but is not limited to, growing an undoped Shell layer 19 in a reserved Shell region using atomic layer epitaxy.
[0072] S106: As shown in Figure 10, a gate structure is formed on the Shell layer 19.
[0073] A gate structure is stacked above the Shell layer 19, wherein the gate structure includes a gate dielectric layer 20 and a high-k metal gate 21. That is, the gate structure is formed on the Shell layer 19, including forming a gate dielectric layer 20 and a high-k metal gate 21 on the Shell layer 19.
[0074] As described above, the high-temperature annealing processes required for the growth of the sidewall structure, source 17, and drain 18 in the CS-JL device, as well as the high-temperature annealing processes required for the activation of source 17 and drain 18, are all completed before the preparation of the Shell layer 19. This effectively avoids the influence of the high temperatures required for the activation of source 17 and drain 18 on the diffusion of impurities in the channel region, effectively reduces the thermal budget of the Shell layer 19, and facilitates precise control of the doping concentration and thickness of the Shell layer 19 and Core layer 13, thereby producing a CS-JL device with better performance.
[0075] In other words, compared with the existing technical solutions (the manufacturing method of first preparing the Shell layer and then performing a series of processes such as gate and source drain), the technical solution of this application innovatively proposes a method of first completing the process that requires high temperature and then preparing the Shell layer 19, which can manufacture CS-JL devices with Core layer 13 and Shell layer 19 close to the ideal process parameters.
[0076] Furthermore, the fabrication method of the CS-JL device provided in this embodiment is compatible with the high-k metal gate (HTMG) gate-last process, making it suitable for 3D integration. At advanced process nodes, the gate-last process is often used to reduce thermal budget and improve device performance. This solution, combined with the gate-last process, helps to apply CS-JL devices to 3D integration applications with lower thermal budgets.
[0077] It should be noted that the current CS-JL device is still in the research and development stage and there is no corresponding mature process flow. Based on the CS-JL device fabrication method provided in this application, considering that the undoped Shell layer is easily affected by the doping diffusion of the Core layer at higher temperatures, the technical solution of this application optimizes the process flow of the CS-JL device from the perspective of thermal budget, which is conducive to the manufacturing of CS-JL devices.
[0078] Based on the above embodiments of the present invention, another embodiment of the present invention also provides a CS-JL device, which is obtained by the preparation method of the CS-JL device described in the above embodiments.
[0079] Based on the above embodiments of the present invention, another embodiment of the present invention provides an electronic device, which includes the CS-JL device described in the above embodiments.
[0080] The foregoing has provided a detailed description of the CS-JL device, its fabrication method, and electronic equipment provided by the present invention. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.
[0081] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. Regarding the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to in the method section.
[0082] It should also be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that elements inherent to a process, method, article, or apparatus that comprises a list of elements, or elements inherent to such processes, methods, articles, or apparatus, are also included. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.
[0083] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims
1. A method for fabricating a CS-JL device, characterized in that, The fabrication method of the CS-JL device includes: Provide a substrate; A core layer is formed on one side of the substrate; A dummy gate structure, a sidewall structure, a source, and a drain are formed on the side of the Core layer facing away from the substrate. Remove the dummy gate structure and etch a portion of the Core layer; A Shell layer is formed on the surface of the exposed Core layer; A gate structure is formed on the Shell layer.
2. The method for fabricating the CS-JL device according to claim 1, characterized in that, Before forming the Core layer, the fabrication method of the CS-JL device further includes: A buried oxide layer is formed on one side of the substrate.
3. The method for fabricating the CS-JL device according to claim 1, characterized in that, The removal of the dummy gate structure and the etching of a portion of the Core layer include: The dummy gate structure is removed by dry etching or wet etching, and part of the Core layer is etched.
4. The method for fabricating the CS-JL device according to claim 1, characterized in that, The removal of the dummy gate structure and the etching of a portion of the Core layer include: The dummy gate structure is removed using a sacrificial oxide process, and a portion of the Core layer is etched.
5. The method for fabricating the CS-JL device according to claim 1, characterized in that, The removal of the dummy gate structure and the etching of a portion of the Core layer include: The dummy gate structure is removed using atomic layer stripping technology, and part of the Core layer is etched.
6. The method for fabricating the CS-JL device according to claim 1, characterized in that, After forming the source and the drain, the fabrication method of the CS-JL device further includes: The source and drain are processed using a metallization process.
7. The method for fabricating the CS-JL device according to claim 1, characterized in that, The formation of the dummy gate structure on the side of the Core layer away from the substrate includes: A dummy gate dielectric layer and a dummy gate are formed on the side of the Core layer facing away from the substrate.
8. The method for fabricating the CS-JL device according to any one of claims 1-7, characterized in that, The formation of the gate structure on the Shell layer includes: A gate dielectric layer and a high-k metal gate are formed on the Shell layer.
9. A CS-JL device, characterized in that, The CS-JL device is obtained by the method for preparing the CS-JL device according to any one of claims 1-8.
10. An electronic device, characterized in that, The electronic device includes the CS-JL device as described in claim 9.