Gate driving circuit and display device

Abstract

A gate driving circuit and a display device. The gate driving circuit is provided with cascaded shift register units, and each shift register unit comprises fourteen transistors (M1, M2, M3, M4, M5, M6, M7, M8, M9, M10, M11, M12, M13, M14), three capacitors (C1, C2, C3), a signal input terminal (Input), a signal output terminal (EOUT), and two timing control terminals (CLK1, CLK2). In the gate driving circuit, by precisely controlling a voltage relationship and a control signal in the circuit, the stability and response speed of the gate driving circuit are improved, the function of the gate driving circuit is realized, and the smoothness of circuit output and the occupation of layout space are balanced.

Description

Gate driving circuit and display device Technical Field

[0001] This invention relates to the field of display devices, and more specifically, to a gate driving circuit and a display device. Background Technology

[0002] With the increasing popularity of OLED display technology, AMOLED display panels have received widespread attention due to their superior display performance. In AMOLED technology, the gate driving circuit plays a crucial role, responsible for controlling the light emission state of the control panel line by line to achieve high-quality image display. Existing gate driving circuits typically employ a multi-stage cascaded structure, where each stage not only transmits control signals to the next stage but also transmits gate driving signals to the display area.

[0003] However, in practical applications, existing gate drive circuits may exhibit insufficient stability and low reliability during signal switching. This is mainly due to improper control of the voltage relationship between the positive and negative constant voltage signals in the circuit, making it difficult to accurately control the conduction and cutoff states of the transistors under certain operating conditions. Therefore, how to reduce the number of thin-film transistors (TFTs) required while maintaining high-efficiency output capability, in order to minimize layout space occupation, has become an urgent problem to be solved in the current technical field.

[0004] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of the present invention, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0005] In view of this, the present invention provides a gate driving circuit and a display device, which solves the instability and reliability problems faced by the prior art when switching between high voltage and low voltage signals by adopting a cascaded shift register unit structure and combining multiple timing control signals.

[0006] One aspect of the present invention provides a gate driving circuit configured with cascaded shift register units, the shift register units comprising:

[0007] The first transistor is used to switch the current path between the second negative constant voltage signal and the output voltage signal in response to the voltage signal of the first node.

[0008] The second transistor is used to switch the current path between the positive voltage signal and the output voltage signal in response to the voltage signal of the second node.

[0009] The third transistor is used to switch the current path between the first negative constant voltage signal and the first node in response to the voltage signal of the fifth node.

[0010] The fourth transistor is used to switch the current path between the sixth node and the first node in response to the voltage signal of the fourth node;

[0011] The fifth transistor is used to switch the current path between the first timing control signal and the third node in response to the voltage signal of the input voltage signal.

[0012] The sixth transistor is used to switch the current path between the positive voltage signal and the third node in response to the voltage signal of the first timing control signal;

[0013] The seventh transistor is used to switch the current path between the seventh and fifth nodes in response to the voltage signal of the third node;

[0014] The eighth transistor is used to switch the current path between the input voltage signal and the fifth section in response to the voltage signal of the first timing control signal;

[0015] The ninth transistor is used to switch the current path between the fifth node and the second node in response to a positive voltage signal.

[0016] The tenth transistor is used to switch the current path between the positive voltage signal and the sixth node in response to the voltage signal of the second timing control signal;

[0017] The eleventh transistor is used to switch the current path between the first negative constant voltage signal and the seventh node in response to the voltage signal of the second timing control signal.

[0018] The twelfth transistor is used to switch the current path between the fourth node and the third node in response to a positive voltage signal.

[0019] The thirteenth transistor is used to switch the current path between the first negative constant voltage signal and the eighth node in response to the voltage signal of the third node.

[0020] The fourteenth transistor is used to switch the current path between the second timing control signal and the eighth node in response to the voltage signal of the second node;

[0021] The first capacitor is coupled between the eighth node and the second node;

[0022] The second capacitor is coupled between the first negative voltage constant voltage signal and the first node;

[0023] The third capacitor is coupled between the second timing control signal and the fourth node.

[0024] In some embodiments, at least one of the first transistor, second transistor, third transistor, fourth transistor, fifth transistor, sixth transistor, seventh transistor, eighth transistor, ninth transistor, tenth transistor, eleventh transistor, twelfth transistor, thirteenth transistor, and fourteenth transistor is configured as a series structure of two thin-film transistors sharing the same gate.

[0025] In some embodiments, at least one of the first transistor, second transistor, third transistor, fourth transistor, fifth transistor, sixth transistor, seventh transistor, eighth transistor, ninth transistor, tenth transistor, eleventh transistor, twelfth transistor, thirteenth transistor, and fourteenth transistor is provided with a back gate.

[0026] In some embodiments, the first transistor, second transistor, third transistor, fourth transistor, fifth transistor, sixth transistor, seventh transistor, eighth transistor, ninth transistor, tenth transistor, eleventh transistor, twelfth transistor, thirteenth transistor, and fourteenth transistor are all N-type thin-film transistors.

[0027] In some embodiments, the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, the ninth transistor, the tenth transistor, the eleventh transistor, the twelfth transistor, the thirteenth transistor, and the fourteenth transistor are all P-type thin-film transistors.

[0028] In some embodiments, the input voltage signal of the first-stage shift register unit is a pulse signal, and the input voltage signals of the remaining shift register units are the output voltage signals of the previous-stage shift register unit.

[0029] In some embodiments, the duty cycle of both the first timing control signal and the second timing control signal is no greater than 1 / 2.

[0030] In some embodiments, the first timing control signal and the second timing control signal are both square wave signals with the same output frequency, and are arranged sequentially in time.

[0031] In some embodiments, the difference between the first negative constant voltage signal and the second negative constant voltage signal is less than the threshold voltage of the sixth transistor and the threshold voltage of the seventh transistor.

[0032] Another aspect of the present invention provides a display device including the gate driving circuit described above.

[0033] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit the invention.

[0034] The gate driving circuit of the present invention significantly improves the stability and response speed of the gate driving circuit by precisely controlling the voltage relationship and control signal in the circuit. While realizing the function of the gate driving circuit, it also balances the smoothness of the circuit output and the occupation of layout space, providing a more efficient and reliable solution for the widespread application of display panels. Attached Figure Description

[0035] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention. It is obvious that the drawings described below correspond only to some embodiments of the invention, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0036] Figure 1 shows a cascaded schematic diagram of the gate drive circuit of the present invention;

[0037] Figure 2 shows a circuit diagram of the shift register unit according to the first embodiment of the present invention;

[0038] Figure 3a is a schematic diagram of the conduction state of the shift register unit under the first timing of the first embodiment of the present invention;

[0039] Figure 3b is a timing diagram of the shift register unit of the first embodiment of the present invention under the first timing condition;

[0040] Figure 4a is a schematic diagram of the conduction state of the shift register unit under the second timing of the first embodiment of the present invention;

[0041] Figure 4b is a timing diagram of the shift register unit of the first embodiment of the present invention under the second timing;

[0042] Figure 5a is a schematic diagram of the conduction state of the shift register unit under the third timing according to the first embodiment of the present invention;

[0043] Figure 5b is a timing diagram of the shift register unit of the first embodiment of the present invention under the third timing.

[0044] Figure 6a is a schematic diagram of the conduction state of the shift register unit under the fourth timing according to the first embodiment of the present invention;

[0045] Figure 6b is a timing diagram of the shift register unit of the first embodiment of the present invention under the fourth timing.

[0046] Figure 7a is a schematic diagram of the conduction state of the shift register unit under the fifth timing according to the first embodiment of the present invention;

[0047] Figure 7b is a timing diagram of the shift register unit of the first embodiment of the present invention under the fifth timing.

[0048] Figure 8 shows a circuit diagram of the shift register unit according to the second embodiment of the present invention;

[0049] Figure 9 shows a circuit diagram of the shift register unit according to the third embodiment of the present invention. Detailed Implementation

[0050] The following specific examples illustrate the implementation methods of this application. Those skilled in the art can easily understand the other advantages and effects of this application from the content disclosed herein. This application can also be implemented or applied through other different specific embodiments, and various details in this application can be modified or changed according to different viewpoints and application systems without departing from the spirit of this application. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this application can be combined with each other.

[0051] The embodiments of this application will now be described in detail with reference to the accompanying drawings, so that those skilled in the art can easily implement the application. This application may be embodied in many different forms and is not limited to the embodiments described herein.

[0052] In this application, the terms "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics represented in connection with that embodiment or example, which are included in at least one embodiment or example of this application. Furthermore, the specific features, structures, materials, or characteristics represented may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate different embodiments or examples represented in this application, as well as features of different embodiments or examples.

[0053] Furthermore, the terms "first" and "second" are used for illustrative purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the representation of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0054] For the purpose of clearly describing this application, devices that are not relevant to the description are omitted, and the same or similar components throughout the specification are given the same reference numerals.

[0055] Throughout this specification, when it is said that a device is "connected" to another device, this includes not only "direct connection" but also "indirect connection" by placing other components in between. Furthermore, when it is said that a device "comprises" a certain constituent element, unless otherwise stated otherwise, this does not exclude other constituent elements, but rather implies that other constituent elements may be included.

[0056] Furthermore, the technical terms used herein are used only to refer to specific embodiments and are not intended to limit this application. The singular form used herein, unless the statement explicitly indicates otherwise, also includes the plural form. As used herein, the singular forms “a,” “an,” and “the” are intended to also include the plural forms unless the context indicates otherwise. It should be further understood that the word “comprising” as used in the specification means to specify a particular feature, region, integer, step, operation, element, and / or component, and does not exclude the presence or addition of other features, regions, integers, steps, operations, elements, and / or components. The terms “comprising” and “including” indicate the presence of a feature, step, operation, component, element, type, and / or group, but do not exclude the presence, occurrence, or addition of one or more other features, steps, operations, components, elements, types, and / or groups. The terms “or” and “and / or” as used herein are to be interpreted as inclusive, or mean any one or any combination thereof. Therefore, "A, B, or C" or "A, B, and / or C" means "any one of the following: A; B; C; A and B; A and C; B and C; A, B, and C". Exceptions to this definition will only occur if the combination of components, functions, steps, or operations is inherently mutually exclusive in some way.

[0057] Although not explicitly defined, all terms, including technical and scientific terms used herein, shall have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. Terms defined in commonly used dictionaries shall be further interpreted as having a meaning consistent with the relevant technical literature and the content of this present application, and shall not be over-interpreted as having an ideal or overly formulaic meaning unless otherwise defined.

[0058] In this embodiment of the invention, a solution is provided to address the problems existing in the prior art. Figure 1 is a schematic diagram of the cascaded gate drive circuit shown in this embodiment of the invention. In Figure 1, four cascaded shift register units are used as an example. The input terminal Input of the first-stage shift register unit E1 receives the start pulse signal STV as the input signal. The output terminal Eout[1] of the first-stage shift register unit E1 outputs the light-emitting drive signal as the input signal of the second-stage shift register unit E2. The output terminal Eout[1] of the first-stage shift register unit E1 is connected to the input terminal Input of the second-stage shift register unit E2. The output terminal Eout[2] of the second-stage shift register unit E2 outputs the light-emitting drive signal as the input signal of the third-stage shift register unit E3. The output terminal Eout[2] of the second-stage shift register unit E2 is connected to the input terminal Input of the third-stage shift register unit E3. The signal output terminal Eout[3] of the third-stage shift register unit E3 outputs a light-emitting driving signal as the input signal of the fourth-stage shift register unit E4. The signal output terminal Eout[3] of the third-stage shift register unit E3 is connected to the signal input terminal Input of the fourth-stage shift register unit E4. ... Subsequent shift register units repeat this process to form a gate driving circuit. In the first-stage shift register unit, the first timing control terminal CLK1 is connected to the first timing control signal line CKV1 to receive the first timing control signal. The second timing control terminal CLK2 is connected to the second timing control signal line CKV2 to receive the second timing control signal. In the second-stage shift register unit, the first timing control terminal CLK1 is connected to the second timing control signal line CKV2 to receive the second timing control signal. The second timing control terminal CLK2 is connected to the first timing control signal line CKV1 to receive the first timing control signal. In the third-stage shift register unit, the first timing control terminal CLK1 is connected to the first timing control signal line CKV1 to receive the first timing control signal. The second timing control terminal CLK2 is connected to the second timing control signal line CKV2 to receive the second timing control signal. In the fourth-stage shift register unit, the first timing control terminal CLK1 is connected to the first timing control signal line CKV1 to receive the first timing control signal. The second timing control terminal CLK2 is connected to the second timing control signal line CKV2 to receive the second timing control signal. ...and so on, resulting in a cyclical connection of the timing control terminals to the timing control signal lines between two shift register units to receive the timing control signals.

[0059] Figure 2 is a circuit diagram of the shift register unit according to the first embodiment of the present invention. As shown in Figure 2, the gate drive circuit of the first embodiment of the present invention is configured with cascaded shift register units, which include: a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, a twelfth transistor M12, a thirteenth transistor M13, and a fourteenth transistor M14. In this embodiment, the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, the eighth transistor M8, the ninth transistor M9, the tenth transistor M10, the eleventh transistor M11, the twelfth transistor M12, the thirteenth transistor M13, and the fourteenth transistor M14 are described as N-type thin-film transistors, but this is not a limitation. The first transistor M1 responds to the voltage signal at the first node n1 and switches the current path between the second negative constant voltage signal VEE2 and the output voltage signal at the output terminal Eout. The second transistor M2 responds to the voltage signal at the second node n2 and switches the current path between the positive voltage signal VDD and the output voltage signal at the output terminal Eout. The third transistor M3 responds to the voltage signal at the fifth node n5 and switches the current path between the first negative constant voltage signal VEE1 and the first node n1. The fourth transistor M4 responds to the voltage signal at the fourth node n4 and switches the current path between the sixth node n6 and the first node n1. The fifth transistor M5 responds to the voltage signal at the signal input terminal Input and switches the current path between the first timing control signal received at the first timing control terminal CLK1 and the third node n3; the sixth transistor M6 responds to the voltage signal of the first timing control signal received at the first timing control terminal CLK1 and switches the current path between the positive voltage signal VDD and the third node n3. The seventh transistor M7 is used to switch the current path between the seventh node n7 and the fifth node n5 in response to the voltage signal of the third node n3. The eighth transistor M8 is used to switch the current path between the signal input terminal Input and the fifth node n5 in response to the voltage signal of the first timing control signal received at the first timing control terminal CLK1. The ninth transistor M9 is used to switch the current path between the fifth node n5 and the second node n2 in response to the voltage signal of the positive voltage signal VDD. The tenth transistor M10 is used to switch the current path between the positive voltage signal VDD and the sixth node n6 in response to the voltage signal of the second timing control signal received at the second timing control terminal CLK2.The eleventh transistor M11 is used to switch the current path between the first negative constant voltage signal VEE1 and the seventh node n7 in response to the voltage signal of the second timing control signal received by the second timing control terminal CLK2. The twelfth transistor M12 is used to switch the current path between the fourth node n4 and the third node n3 in response to the voltage signal of the positive voltage signal VDD. The thirteenth transistor M13 is used to switch the current path between the first negative constant voltage signal VEE1 and the eighth node n8 in response to the voltage signal of the third node n3. The fourteenth transistor M14 is used to switch the current path between the second timing control signal received by the second timing control terminal CLK2 and the eighth node n8 in response to the voltage signal of the second node n2. The first capacitor C1 is coupled between the eighth node n8 and the second node n2. The second capacitor C2 is coupled between the first negative constant voltage signal VEE1 and the first node n1. The third capacitor C3 is coupled between the second timing control signal received by the second timing control terminal CLK2 and the fourth node n4. Among them, the positive voltage signal VDD is a positive constant voltage signal, and the first negative constant voltage signal VEE1 and the second negative constant voltage signal VEE2 are both negative constant voltage signals. The first negative constant voltage signal VEE1 is lower than the second negative constant voltage signal VEE2.

[0060] In some optional embodiments, VEE1-VEE2 < Vth_M6, that is, the difference between the first negative constant voltage signal VEE1 and the second negative constant voltage signal VEE2 is less than the threshold voltage of the sixth transistor M6; VEE1-VEE2 < Vth_M7, that is, the difference between the first negative constant voltage signal VEE1 and the second negative constant voltage signal VEE2 is less than the threshold voltage of the seventh transistor M7.

[0061] In some optional embodiments, the high-level voltages of the pulse signal STE of the input voltage signal at the signal input terminal Input, the first timing control signal received by the first timing control terminal CLK1, and the second timing control signal received by the second timing control terminal CLK2 are equal to the VDD voltage.

[0062] In some optional embodiments, the low-level voltages of the pulse signal STE of the input voltage signal at the signal input terminal, the first timing control signal received by the first timing control terminal CLK1, and the second timing control signal received by the second timing control terminal CLK2 are equal to the voltage of the first negative constant voltage signal VEE1.

[0063] In some optional embodiments, the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, the eighth transistor M8, the ninth transistor M9, the tenth transistor M10, the eleventh transistor M11, the twelfth transistor M12, the thirteenth transistor M13, and the fourteenth transistor M14 are all P-type thin-film transistors. The on-state level of the P-type thin-film transistor is low, and its off-state level is high. The circuit connection scheme of the P-type thin-film transistor is not shown in the circuit diagram, but it is understood that by replacing the N-type thin-film transistor in the shift register unit shown in Figure 2 with a P-type thin-film transistor, those skilled in the art can easily deduce the need for adaptive adjustment of the high and low voltage level relationships of other signals in the circuit, which will not be elaborated here.

[0064] In some optional embodiments, the input voltage signal of the signal input terminal Input of the first-stage shift register unit is a pulse signal STV, and the input voltage signal of the signal input terminal Input of the other shift register units is the output voltage signal of the output terminal Eout of the previous-stage shift register unit, but this is not a limitation.

[0065] In some optional embodiments, the duty cycle of the first timing control signal received by the first timing control terminal CLK1 and the duty cycle of the second timing control signal received by the second timing control terminal CLK2 are both 1 / 2, but this is not a limitation. In this embodiment, the duty cycle is the high-level time to the period time.

[0066] In some optional embodiments, the first timing control signal and the second timing control signal are both square wave signals with the same output frequency and are arranged sequentially in time, but this is not a limitation.

[0067] In some optional embodiments, the phase difference between the first timing control signal and the second timing control signal is 180°, but this is not a limitation.

[0068] The working principle of the shift register unit of the present invention under various timing conditions will be specifically described below with reference to Figures 3 to 7.

[0069] Figure 3a is a schematic diagram of the conduction state of the shift register unit under the first timing T1 of the first embodiment of the present invention. Figure 3b is a timing diagram of the shift register unit under the first timing of the first embodiment of the present invention. As shown in Figures 3a and 3b, when the shift register unit of the first embodiment of the present invention is in the first timing, the states of each transistor are as follows: the first transistor M1, the fifth transistor M5, the ninth transistor M9, the tenth transistor M10, the eleventh transistor M11, and the twelfth transistor M12 are all turned on, while the second transistor M2, the third transistor M3, the fourth transistor M4, the sixth transistor M6, the seventh transistor M7, the eighth transistor M8, the thirteenth transistor M13, and the fourteenth transistor M14 are all turned off. The first timing control signal received by the first timing control terminal CLK1 outputs a low level, causing the sixth transistor M6 and the eighth transistor M8 to turn off. The input voltage signal of the shift register unit is a pulse signal STE, which outputs a high level, turning on the fifth transistor M5. The third node n3 and the fourth node n4 are written with low levels, turning off the seventh transistor M7, the fourth transistor M4, and the thirteenth transistor M13. The second node n2 is low, turning off the second transistor M2. The second timing control terminal CLK2 receives the second timing control signal and outputs a high level, turning on the tenth transistor M10. The first node n1 remains high, turning on the first transistor M1. Finally, the output voltage signal at the output terminal Eout outputs the second negative constant voltage signal VEE2 at a low potential.

[0070] Figure 4a is a schematic diagram of the conduction state of the shift register unit under the second timing T2 of the first embodiment of the present invention. Figure 4b is a timing diagram of the shift register unit under the second timing of the first embodiment of the present invention. As shown in Figures 4a and 4b, when the shift register unit of the first embodiment of the present invention is in the second timing, the states of each transistor are as follows: the first transistor M1, the tenth transistor M10, and the eleventh transistor M11 are all off, and the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, the eighth transistor M8, the ninth transistor M9, the twelfth transistor M12, the thirteenth transistor M13, and the fourteenth transistor M14 are all on. In this configuration, the first timing control terminal CLK1 receives a high-level output signal from the first timing control signal. The input voltage signal of the shift register unit is a pulse signal STE, which is written high to the second node n2 and the fifth node n5. The voltage of the second node n2 is equivalent to the voltage signal of the positive voltage signal VDD, causing the second transistor M2 and the third transistor M3 to conduct. The first negative constant voltage signal VEE1 is written low to the first node n1, causing the first transistor M1 to turn off. In this case, the gate-drain voltage Vgd of the second transistor M2 is 0V, which is lower than its threshold voltage Vth, while the gate-source voltage Vgs is VDD-VEE2, which is greater than Vth. Therefore, the second transistor M2 is in the saturation region. In this state, the output terminal Eout can be expressed as Eout=V(n2)-Vth_M2, and its value is less than the voltage signal of the positive voltage signal VDD. The second timing control signal received by the second timing control terminal CLK2 is output as a low level. Since the second node n2 is at a high level at this time, the fourteenth transistor is turned on, which turns off the tenth transistor M10 and the eleventh transistor M11. Therefore, the eighth node n8 is at a low level.

[0071] Figure 5a is a schematic diagram of the conduction state of the shift register unit under the third timing T3 of the first embodiment of the present invention. Figure 5b is a timing diagram of the shift register unit under the third timing of the first embodiment of the present invention. As shown in Figures 5a and 5b, when the shift register unit of the first embodiment of the present invention is in the third timing, the states of each transistor are as follows: the first transistor M1, the fourth transistor M4, the sixth transistor M6, the seventh transistor M7, the eighth transistor M8, and the thirteenth transistor M13 are all off, while the second transistor M2, the third transistor M3, the fifth transistor M5, the ninth transistor M9, the tenth transistor M10, the eleventh transistor M11, the twelfth transistor M12, and the fourteenth transistor M14 are all on. The first timing control signal received by the first timing control terminal CLK1 outputs a low level, causing the eighth transistor M8 and the sixth transistor M6 to be off. The input voltage signal of the shift register unit is a pulse signal STE, which outputs a high level, turning on the fifth transistor M5. The first timing control signal received by the first timing control terminal CLK1 outputs a low level and writes it to the third node n3 and the fourth node n4, turning off the seventh transistor M7 and the fourth transistor M4. The second timing control signal received by the second timing control terminal CLK2 outputs a high level, turning on the eighth node n8, which in turn turns on the second transistor M2, making the second node n2 high. When the first timing control signal received by the first timing control terminal CLK1 outputs a low level and the second timing control signal received by the second timing control terminal CLK2 outputs a high level, the fourteenth transistor M14 turns on, causing the voltage of the eighth node n8 to jump from a low level to a high level, with a voltage step of ΔV(n8) = VDD - VEE1. A first capacitor C1 exists between the eighth node n8 and the second node n2. Through capacitive coupling, the potential of the second node n2 is increased. Specifically, V(n2) = VDD + (VDD - VEE1) * (C1 / Cn2), where Cn2 is the total capacitance of the second node n2, including the first capacitor C1, the transistor capacitance of the second transistor M2, and the parasitic capacitance of the metal traces of the second node n2. Under this condition, the gate-drain voltage Vgd of the second transistor M2 is V(n2) - VDD, which is greater than its threshold voltage Vth_M2. Therefore, the second transistor M2 operates in the linear region. At this time, the output voltage of Eout can reach the positive voltage signal VDD, ensuring normal operation and stable output of the circuit in this state.

[0072] Figure 6a is a schematic diagram of the conduction state of the shift register unit under the fourth timing T4 of the first embodiment of the present invention. Figure 6b is a timing diagram of the shift register unit under the fourth timing of the first embodiment of the present invention. As shown in Figures 6a and 6b, when the shift register unit of the first embodiment of the present invention is in the fourth timing, the states of each transistor are as follows: the first transistor M1, the second transistor M2, the third transistor M3, the fifth transistor M5, the tenth transistor M10, the eleventh transistor M11, and the fourteenth transistor M14 are all off, while the fourth transistor M4, the sixth transistor M6, the seventh transistor M7, the eighth transistor M8, the ninth transistor M9, the twelfth transistor M12, and the thirteenth transistor M13 are all on. The second timing control signal received by the second timing control terminal CLK2 outputs a low level, causing the tenth transistor M10 and the eleventh transistor M11 to be off, and the first node n1 maintains the low level of the previous moment, causing the first transistor M1 to be off. The first timing control terminal CLK1 receives the first timing control signal and outputs a high level, turning on the sixth transistor M6, causing the third node n3 to write a high level, turning on the thirteenth transistor M13, and causing the eighth node n8 to write a low level. The input voltage signal of the shift register unit is the pulse signal STE, which outputs a low level, causing the fifth transistor M5 to turn off. The first timing control terminal CLK1 receives the first timing control signal and outputs a high level, causing the second node n2 to write a low level STE, and turning off the second transistor M2. Finally, the output voltage signal of the output terminal Eout remains at the high potential of the previous moment.

[0073] Figure 7a is a schematic diagram of the conduction state of the shift register unit under the fifth timing T5 of the first embodiment of the present invention. Figure 7b is a timing diagram of the shift register unit under the fifth timing of the first embodiment of the present invention. As shown in Figures 7a and 7b, when the shift register unit of the first embodiment of the present invention is in the fifth timing, the states of each transistor are as follows: the first transistor M, the fourth transistor M4, the seventh transistor M7, the ninth transistor M9, the tenth transistor M10, the eleventh transistor M11, the twelfth transistor M12, and the thirteenth transistor M13 are all turned on, while the second transistor M2, the third transistor M3, the fifth transistor M5, the sixth transistor M6, the eighth transistor M8, and the fourteenth transistor M14 are all turned off. Among them, the first timing control signal received by the first timing control terminal CLK1 outputs a low level, causing the sixth transistor M6 to be turned off, the third node n3 maintains the high level of the previous moment, causing the thirteenth transistor M13 to be turned on, and causing the eighth node n8 to be written with a low level. A high level at the third node n3 turns on the seventh node n7. The second timing control signal received at the second timing control terminal CLK2 outputs a high level, turning on the eleventh transistor M11. This causes the first negative voltage constant signal VEE1 written to the second node n2 to go low, turning off the second transistor M2. The high level output of the second timing control signal received at the second timing control terminal CLK2 turns on the tenth transistor M10. This results in the fourth node n4 and the third node n3 both having a high level, turning on the fourth transistor M4. A high level is then written to the first node n1, turning on the first transistor M1. Finally, the output voltage signal at the output terminal Eout outputs a low potential for the second negative voltage constant signal VEE2.

[0074] In this embodiment, due to the voltage characteristics of the circuit nodes, there is a voltage step when the output terminal Eout switches from low to high level. This phenomenon is related to the threshold voltage Vth of the second transistor M2. The specific principle is as follows: In the third timing T3, the first timing control terminal CLK1 is at a low level, and the second timing control terminal CLK2 is at a high level, causing the fourteenth transistor M14 to turn on, thereby causing the voltage of the eighth node n8 to jump from low to high level. The voltage step is ΔV(n8) = VDD - VEE1. The eighth node n8 and the second node n2 are capacitively coupled through the first capacitor C1, which raises the potential of the second node n2. The calculation formula is V(n2) = VDD + (VDD - VEE1) * (C1 / Cn2), where Cn2 is the total capacitance of the second node n2, including the first capacitor C1, the transistor capacitance of the second transistor M2, and the parasitic capacitance of the metal traces of the second node n2. At this point, the gate-drain voltage Vgd of the second transistor M2, V(n2) - VDD, is greater than its threshold voltage Vth_M2. Therefore, the second transistor M2 operates in the linear region, allowing the output voltage of Eout to reach the voltage of the positive voltage signal VDD. It should be noted that if further control of the step effect when the output Eout switches from low to high is required, additional circuitry is needed, which will occupy more layout space. Therefore, during circuit design, a selective balance between output smoothness and layout space resources should be made based on the characteristics and requirements of the circuit.

[0075] Figure 8 is a circuit diagram of the shift register unit according to the second embodiment of the present invention. This embodiment aims to solve the problem in the prior art where the failure of a single thin-film transistor (TFT) causes the entire circuit to malfunction when a conductor phenomenon occurs. In conventional gate driving circuits, the failure of a single TFT may affect the reliability and stability of the entire driving circuit, thereby reducing the performance of the display. The present invention also provides a gate driving circuit configured with a cascaded shift register unit. At least one of the first transistor M1, second transistor M2, third transistor M3, fourth transistor M4, fifth transistor M5, sixth transistor M6, seventh transistor M7, eighth transistor M8, ninth transistor M9, tenth transistor M10, eleventh transistor M11, twelfth transistor M12, thirteenth transistor M13, and fourteenth transistor M14 in the shift register unit is configured as a series structure of two TFTs sharing the same gate. The connection relationship of other devices in the shift register unit is the same as in the first embodiment, and will not be repeated here. The present invention improves the fault tolerance of the circuit by designing and configuring a cascaded shift register unit, in which at least one transistor is configured as a series structure of two TFTs sharing the same gate. As shown in Figure 8, the eighth transistor M8 includes two series-connected thin-film transistors (TFTs), M8a and M8b, sharing the same gate node. In this series-connected TFT structure, if one TFT becomes conductive, the other TFT can still function normally, ensuring the continuous operation of the circuit. For example, if the probability of a single TFT failing due to conductivity is 0.0001, the probability of both series-connected TFTs failing simultaneously is 0.00012, or 10^-8. This design significantly improves the reliability of the gate drive circuit, ensuring its normal operation even in the face of potential failures, thereby significantly enhancing the overall performance and lifespan of the display.

[0076] Figure 9 is a circuit diagram of the shift register unit according to the third embodiment of the present invention. The present invention also provides a gate drive circuit configured with cascaded shift register units. At least one of the following transistors in the shift register unit—the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, the eighth transistor M8, the ninth transistor M9, the tenth transistor M10, the eleventh transistor M11, the twelfth transistor M12, the thirteenth transistor M13, and the fourteenth transistor M14—has a back gate. The connection relationships of other devices in the shift register unit are the same as in the first embodiment, and will not be repeated here. This embodiment improves upon the problem of a negative threshold voltage Vth faced by conventional gate drive circuits under high-load operating conditions. To enhance output capability, the first transistor M1 and the second transistor M2 are typically designed with a large width-to-length ratio W / L, which leads to a negative Vth, thus affecting output performance. As shown in Figure 9, this invention also provides a gate driving circuit configured with cascaded shift register units. The first transistor M1 and the second transistor M2 of the shift register units both have back gates. By setting back gates in these two transistors and applying an appropriate negative voltage, their Vth can be effectively shifted in the positive direction, thereby improving circuit stability. Furthermore, under long-term stress conditions, Vth may drift positively, making it difficult to output a positive voltage signal VDD. By adjusting the back gate voltage to a positive voltage, the Vth of subsequent transistors, such as the sixth transistor M6 and the seventh transistor M7, can be shifted negatively, effectively improving the problem of reduced output capability due to stress. In summary, the back gate design not only allows for Vth adjustment but also ensures rapid switching between positive and negative voltages during charging and discharging, optimizing the overall circuit performance.

[0077] Based on the same inventive concept, embodiments of the present invention also provide a display device, including the gate driving circuit described above in the embodiments of the present invention. This display device can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator. Implementation of this display device can refer to the embodiments of the gate driving circuit described above; repeated technical solutions and effects will not be described again.

[0078] In summary, the gate driving circuit and display panel of the present invention solve the instability problem that may occur when switching between high and low voltage signals in the prior art by providing a new gate driving circuit. Specifically, the circuit precisely controls the relationship between the positive voltage signal VDD and the first negative constant voltage signal VEE1 and the second negative constant voltage signal VEE2, ensuring that VEE1 is lower than VEE2 and VEE1-VEE2 is less than the threshold voltage, thereby effectively preventing accidental conduction when the M6 ​​and M7 transistors should be turned off. In addition, the level design of the control signal enables stable and accurate signal transmission under specific conditions. This innovation significantly improves the reliability and response speed of the circuit, ensuring that the AMOLED display panel can operate quickly and stably during display, ultimately providing a better visual experience and higher product stability.

[0079] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A gate drive circuit characterized by comprising: The system is configured with cascaded shift register units, each shift register unit comprising: The first transistor is used to switch the current path between the second negative constant voltage signal and the output voltage signal in response to the voltage signal of the first node. The second transistor is used to switch the current path between the positive voltage signal and the output voltage signal in response to the voltage signal of the second node. The third transistor is used to switch the current path between the first negative constant voltage signal and the first node in response to the voltage signal of the fifth node. The fourth transistor is used to switch the current path between the sixth node and the first node in response to the voltage signal of the fourth node; The fifth transistor is used to switch the current path between the first timing control signal and the third node in response to the voltage signal of the input voltage signal. The sixth transistor is used to switch the current path between the positive voltage signal and the third node in response to the voltage signal of the first timing control signal; The seventh transistor is used to switch the current path between the seventh and fifth nodes in response to the voltage signal of the third node; The eighth transistor is used to switch the current path between the input voltage signal and the fifth node in response to the voltage signal of the first timing control signal; The ninth transistor is used to switch the current path between the fifth node and the second node in response to a positive voltage signal. The tenth transistor is used to switch the current path between the positive voltage signal and the sixth node in response to the voltage signal of the second timing control signal; The eleventh transistor is used to switch the current path between the first negative constant voltage signal and the seventh node in response to the voltage signal of the second timing control signal. The twelfth transistor is used to switch the current path between the fourth node and the third node in response to a positive voltage signal. The thirteenth transistor is used to switch the current path between the first negative constant voltage signal and the eighth node in response to the voltage signal of the third node. The fourteenth transistor is used to switch the current path between the second timing control signal and the eighth node in response to the voltage signal of the second node; A first capacitor is coupled between the eighth node and the second node; The second capacitor is coupled between the first negative voltage constant voltage signal and the first node; The third capacitor is coupled between the second timing control signal and the fourth node.

2. The gate drive circuit according to claim 1, characterized by At least one of the first, second, third, fourth, fifth, sixth, seventh, eighth, ninth, tenth, eleventh, twelfth, thirteenth, and fourteenth transistors is configured as a series structure of two thin-film transistors sharing the same gate.

3. The gate drive circuit according to claim 1, characterized by At least one of the first transistor, second transistor, third transistor, fourth transistor, fifth transistor, sixth transistor, seventh transistor, eighth transistor, ninth transistor, tenth transistor, eleventh transistor, twelfth transistor, thirteenth transistor, and fourteenth transistor is provided with a back gate.

4. The gate drive circuit according to claim 1, characterized by The first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, the ninth transistor, the tenth transistor, the eleventh transistor, the twelfth transistor, the thirteenth transistor, and the fourteenth transistor are all N-type thin-film transistors.

5. The gate drive circuit according to claim 1, characterized by The first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, the ninth transistor, the tenth transistor, the eleventh transistor, the twelfth transistor, the thirteenth transistor, and the fourteenth transistor are all P-type thin-film transistors.

6. The gate drive circuit according to claim 1, characterized by The input voltage signal of the first-stage shift register unit is a pulse signal, and the input voltage signal of the remaining shift register units is the output voltage signal of the previous-stage shift register unit.

7. The gate drive circuit according to claim 1, characterized by The duty cycle of both the first timing control signal and the second timing control signal is no greater than 1 / 2.

8. The gate drive circuit according to claim 7, characterized by Both the first timing control signal and the second timing control signal are square wave signals with the same output frequency, and are arranged sequentially in time.

9. The gate drive circuit according to claim 1, characterized by The difference between the first negative constant voltage signal and the second negative constant voltage signal is less than the threshold voltage of the sixth transistor and the threshold voltage of the seventh transistor.

10. A display device, characterized by comprising: Includes the gate drive circuit according to any one of claims 1 to 9.

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