Data coding method, data decoding method, apparatus and system

Abstract

The present application relates to the technical field of computers. Provided are a data coding method, a data decoding method, an apparatus and a system. By calculating r first elements in a first syndrome on the basis of check submatrixes of a check matrix and a data set associated with the check submatrixes in data to be coded, a computing device can automatically calculate the first syndrom. During calculation of the r first elements of the first syndrome, a first intermediate calculation result obtained during calculation of a target first subelement when i<a target number can be reused, and by taking into account a first subelement associated with a (j+1)th check submatrix in an i-th first element when i≥the target number, the target first subelement when i≥the target number is obtained. In this way, the complexity of calculating the first elements in the first syndrome when i≥the target number is reduced, thus improving the calculation efficiency of the first syndrome and the processing efficiency of the whole data coding process.

Description

Data encoding and decoding methods, devices and systems

[0001] This application claims priority to Chinese Patent Application No. 202411630667.X, filed on November 14, 2024, entitled “Data Encoding and Decoding Method, Apparatus and System”, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of computer technology, specifically to data encoding and decoding methods, apparatus, and systems. Background Technology

[0003] In order to ensure the reliability of the data storage system, data replication technology is widely used in the data storage process. For example, at least one copy of the original data is kept in the data storage system. However, this method leads to high storage costs for the data storage system.

[0004] Erasure coding (EC) is a data encoding technique. It divides the original data into blocks, encodes these blocks to create redundant blocks, and then decodes these redundant blocks to recover the lost data in the event of data loss. This ensures the reliability of the data storage system and can also reduce storage costs. However, current erasure coding and decoding methods suffer from high computational complexity and low efficiency. Summary of the Invention

[0005] This application provides a data encoding and decoding method, apparatus, and system that can solve the problems of high computational complexity and low computational efficiency in the process of obtaining redundant blocks based on data block encoding and recovering lost data based on redundant blocks decoding.

[0006] Firstly, a data encoding method is provided, comprising: acquiring data to be encoded; performing a first corrector calculation based on the data to be encoded and a parity check matrix; and generating a first corrector. The first corrector is used to generate parity symbols for the data to be encoded. The parity check matrix includes N parity check sub-matrices, where N is a positive integer, and the N parity check sub-matrices are divided according to the target codeword length. The first corrector includes r first elements, where r is a preset number of parity symbols, and each first element includes N first sub-elements associated with the N parity check sub-matrices respectively. During the execution of the first corrector calculation, for the target first sub-element associated with the j-th parity check matrix in the i-th first element, two cases are considered: one is when i < the target number, the target first sub-element is determined based on a first data group and the j-th parity check matrix, where the first data group is the data group associated with the j-th parity check matrix in the data to be encoded. Second, when i ≥ the target number, the target first element is determined based on the first sub-element associated with the (j+1)th parity sub-matrix in the i-th first element of the first intermediate calculation result. The first intermediate calculation result is the intermediate calculation result obtained in the process of calculating the first sub-element associated with the j-th parity sub-matrix in the z-th first element, where z is the remainder of i divided by the target number. Then, r parity symbols for the data to be encoded are generated based on the first corrector. The i-th parity symbol among the r parity symbols is associated with the i-th first element in the first corrector. The r parity symbols are used to generate the encoded codewords for the data to be encoded, and the codeword length is the target codeword length.

[0007] In this embodiment, by calculating r first elements in the first corrector based on the check sub-matrix of the check matrix and the data group associated with the check sub-matrix in the data to be encoded, the computing device can automatically calculate the first corrector. Furthermore, this first corrector can be used to generate r check symbols in the data to be encoded, where r can be any number, enabling the data encoding method provided in this embodiment to generate codewords containing any number of check symbols, thus having a wide range of applications. In the process of calculating the r first elements of the first corrector, the first intermediate calculation result obtained in calculating the target first sub-element when i < the target number can be reused, and combined with the first sub-element associated with the (j+1)th check sub-matrix in the i-th first element when i ≥ the target number, the target first sub-element when i ≥ the target number is obtained. This reduces the computational complexity of the first elements in the first corrector when i ≥ the target number, improving the computational efficiency of the first corrector and the overall processing efficiency of the data encoding process.

[0008] In one possible implementation, the data encoding system includes M registers. A first data group includes first sub-data and second sub-data. The w-th register among the M registers is used to store first intermediate data, which is determined based on the first sub-data and the second intermediate data. The g-th register among the M registers is used to store second intermediate data, which is determined based on the second sub-data. Determining the target first sub-element based on the first data group and the j-th parity sub-matrix includes: storing data from the first data group into the M registers; updating the first intermediate data in the w-th register when the first sub-data has been stored in the w-th register; updating the second intermediate data in the g-th register when the second sub-data has been stored in the g-th register; then updating the first intermediate data in the w-th register again based on the updated second intermediate data in the g-th register and the updated first intermediate data in the w-th register; and finally determining the target first sub-element based on the updated first intermediate data in the w-th register.

[0009] In this implementation, multiple registers are used to store the data (including first intermediate data and second intermediate data) required in the calculation of the first target sub-element. This provides storage space for intermediate calculation results during the calculation of the first target sub-element, reducing access latency in memory and improving the processing efficiency of the data storage system. In the calculation of the first target sub-element, the first intermediate data in register w is first updated based on the first sub-data. Then, after updating the second intermediate data in register g based on the second sub-data, the first intermediate data in register w is updated again based on the updated second intermediate data in register g, thus obtaining the first target sub-element. This achieves incremental calculation, meaning that the intermediate data in the corresponding register is updated immediately after each sub-data is stored. There is no update waiting time for registers (e.g., the time spent waiting for the second sub-data to be stored in register w after storing the first sub-data), improving the processing efficiency of the data encoding system.

[0010] In one possible implementation, if r ≤ the first quantity, M equals the first quantity; if the first quantity < r < the second quantity, M equals the sum of r and the preset quantity; if r ≥ the second quantity, M equals the third quantity; the first quantity is less than the second quantity; the second quantity is less than or equal to the third quantity.

[0011] In this implementation, the number of registers required is reduced for all possible values ​​of r, thereby lowering the space complexity in the data encoding process.

[0012] In one possible implementation, the verification matrix is ​​determined based on a target finite field, where the target finite field is F. 16 [x] / (1+αx+x2 ), where / represents the modular operation, and α is the finite field F 16 =F2[α] / (1+α+α) 2 +α 3 +α 4 The elements in ) are variables, where x is a variable.

[0013] In this implementation, the target finite field F 16 [x] / (1+αx+x 2 The target finite field F has 256 distinct elements, and all operations on this finite field can be performed using cyclic shifts and XOR operations. Multiplication requires only 2 to 3 XOR operations, reducing computational complexity. 16 [x] / (1+αx+x 2 The parity check matrix is ​​constructed based on the Vandermonde matrix, which gives the parity check matrix some special properties (such as the property that the second row elements can be grouped, which allows the parity check matrix to be divided into N parity check submatrices). Then, the subsequent encoding and decoding operations are performed based on these properties of the parity check matrix, which helps to reduce the computational complexity and thus enables the software and hardware to implement it efficiently.

[0014] In one possible implementation, the target number is 15.

[0015] In this implementation, the polynomial ring F 16 [x] = F2[x] / (1+α+…+α) 4 Any element μ in ) i For (0≤i<16), we have: μ i 16 =μ i ,μ i ∈F 16 [x] means that each check matrix has 15 elements per column in a cycle. Therefore, the target number is set to 15 so that the first intermediate calculation result can be reused to simplify the calculation of the first check when i≥15, so as to generate a codeword containing a check symbol with r and r>15.

[0016] In one possible implementation, generating r check symbols for the data to be encoded based on the first corrector includes: obtaining a first set of equations for determining the r check symbols based on the first corrector and the first Vandermonde matrix; the first Vandermonde matrix is ​​obtained based on the r×r order of the check matrix; and performing the calculation of the first set of equations to obtain the r check symbols.

[0017] In this implementation, the unknowns in the first system of equations are check symbols, and r check symbols can be directly obtained by solving the first system of equations.

[0018] In one possible implementation, the calculation of the first system of equations is performed, resulting in r check symbols, including:

[0019] The first Vandermonde matrix in the first set of equations is decomposed into at least one upper triangular matrix and at least one lower triangular matrix to obtain the first preprocessed set of equations; the calculation of the first preprocessed set of equations is performed to obtain r check symbols.

[0020] In this implementation, the special structure of the upper triangular matrix and the lower triangular matrix simplifies matrix operations (such as finding the determinant and the inverse matrix), thereby reducing the computational complexity of the first preprocessing equation set and improving the efficiency of obtaining r verification symbols.

[0021] Secondly, a data decoding method is provided, comprising: acquiring data to be decoded, the data to be decoded including ρ failed symbols and non-failed symbols. Then, a second corrector calculation is performed based on the data to be decoded and a parity check matrix. The second corrector is used to generate ρ reconstructed symbols from the ρ failed symbols. The parity check matrix includes N parity check sub-matrices, where N is a positive integer, and the N parity check sub-matrices are divided based on the target codeword length. The second corrector includes ρ second elements, where ρ ≤ r, and r is the number of parity symbols. Each second element includes N second sub-elements associated with the N parity check sub-matrices respectively. During the second corrector calculation, for the target second sub-element associated with the h-th parity check matrix in the l-th second element, there are two cases: one is when l < the target number, the target second sub-element is determined based on the second data group and the h-th parity check matrix, where the second data group is the data group associated with the h-th parity check matrix among the non-failed symbols. Second, when l ≥ the target number, based on the second intermediate calculation result and the second sub-element associated with the (h+1)th check matrix in the lth second element, the target second sub-element is determined. The second intermediate calculation result is the intermediate calculation result obtained in the process of calculating the second sub-element associated with the hth check matrix in the mth second element, where m is the remainder when l is divided by the target number. Subsequently, based on the second corrector, ρ reconstructed symbols of ρ failed symbols are generated; where the lth reconstructed symbol among the ρ reconstructed symbols is associated with the lth second element in the second corrector, and the ρ reconstructed symbols are used to obtain the decoded data of the data to be decoded.

[0022] In this embodiment, by calculating ρ second elements in the second corrector based on the check sub-matrix of the check matrix and the data group associated with the check sub-matrix in the unfailed symbols, the computing device can automatically calculate the second corrector. Furthermore, this second corrector can be used to generate ρ reconstructed symbols from ρ failed symbols of the decoded data, where ρ ≤ r, and r is the number of check symbols, enabling the data decoding method provided in this embodiment to recover reconstructed symbols from a number of failed symbols less than or equal to the number of check symbols. In the process of calculating the ρ second elements of the second corrector, the second intermediate calculation result obtained in determining the second sub-element when l < the target number can be reused, and combined with the second sub-element associated with the (h+1)th check sub-matrix in the lth first element when l ≥ the target number, the target second sub-element when l ≥ the target number is obtained. Thus, the computational complexity of the second elements in the second corrector is reduced when l ≥ the target number, improving the computational efficiency of the second corrector and the overall processing efficiency of the data decoding process.

[0023] In one possible implementation, the data decoding system includes M registers. A second data set includes third and fourth sub-data. The u-th register among the M registers stores third intermediate data, which is determined based on the third and fourth sub-data. The s-th register among the M registers stores fourth intermediate data, which is determined based on the fourth sub-data. Determining the target second sub-element based on the second data set and the h-th parity sub-matrix includes: storing data from the second data set into the M registers; updating the third intermediate data in the u-th register when the third sub-data has been stored there; updating the fourth intermediate data in the s-th register when the fourth sub-data has been stored there; updating the third intermediate data in the u-th register again based on the updated fourth intermediate data in the s-th register and the updated third intermediate data in the u-th register; and finally, determining the target second sub-element based on the updated third intermediate data in the u-th register.

[0024] In this embodiment, multiple registers are used to store the data (including third and fourth intermediate data) required for calculating the second target sub-element. This provides storage space for intermediate calculation results during the calculation of the second target sub-element, reducing the access latency of storing it in memory and improving the processing efficiency of the data storage system. During the calculation of the second target sub-element, the third intermediate data in the u-th register is first updated based on the third sub-data. Then, after the fourth intermediate data in the s-th register has been updated based on the fourth sub-data, the third intermediate data in the w-th register is updated again based on the updated fourth intermediate data in the s-th register, thus obtaining the second target sub-element. This achieves incremental calculation, meaning that the intermediate data in the corresponding register is updated immediately after each sub-data is stored. There is no update waiting time for the registers (e.g., the time required to store the third sub-data in the u-th register and then wait for the fourth sub-data to be stored in the u-th register), improving the processing efficiency of the data decoding system.

[0025] In one possible implementation, if ρ < r, update the value of ρ to be equal to the value of r.

[0026] In this implementation, since the maximum number of recoverable failed symbols during the decoding process is equal to the number of check symbols, when ρ < r, the first r-ρ unfailed symbols of the data to be decoded can be omitted. Instead, these unfailed symbols and the ρ failed symbols can be combined to form r failed symbols. Subsequently, the r reconstructed data symbols of the r failed symbols can be obtained by solving the second set of equations, thus reducing the amount of data that needs to be acquired.

[0027] In one possible implementation, based on the second corrector, ρ reconstructed symbols of ρ failed symbols are generated, including:

[0028] Based on the second corrector and the second Vandermonde matrix, a second set of equations is obtained to determine the ρ reconstructed symbols of the ρ failed symbols; the second Vandermonde matrix is ​​a matrix of order ρ×ρ in the verification matrix, where the ρ rows of the ρ×ρ order include the first ρ rows of the verification matrix, and the ρ columns of the ρ×ρ order include the columns of the verification matrix related to the ρ failed symbols.

[0029] The calculation of the second set of equations is performed to obtain ρ reconstructed symbols from ρ failed symbols.

[0030] In this implementation, the unknowns in the second set of equations are the reconstructed symbols of the failed symbols, and the reconstructed symbols can be obtained directly by solving the first set of equations.

[0031] In one possible implementation, the calculation of the second set of equations is performed to obtain ρ reconstructed symbols from the ρ failed symbols, including:

[0032] The second Vandermonde matrix in the second system of equations is decomposed into at least one upper triangular matrix and at least one lower triangular matrix to obtain the second preprocessed system of equations.

[0033] The calculation of the second preprocessing equation set is performed to obtain ρ reconstructed symbols from ρ failed symbols.

[0034] In this implementation, the special structure of the upper triangular matrix and the lower triangular matrix simplifies matrix operations (such as finding the determinant and the inverse matrix), thereby reducing the computational complexity of the second preprocessing equation set and improving the efficiency of obtaining ρ reconstructed symbols.

[0035] Thirdly, a data encoding device is provided, including a first acquisition module, a first corrector generation module, and an encoding module.

[0036] The first acquisition module is used to acquire the data to be encoded.

[0037] The first corrector generation module is used to perform first corrector calculation based on the data to be encoded and the parity check matrix to generate the first corrector. The first corrector is used to generate the parity symbols of the data to be encoded. The parity check matrix includes N parity sub-matrices, where N is a positive integer, and the N parity sub-matrices are divided according to the target codeword length. The first corrector includes r first elements, where r is the preset number of parity symbols. Each first element includes N first sub-elements associated with the N parity sub-matrices. During the first corrector calculation, for the target first sub-element associated with the j-th parity sub-matrice in the i-th first element, two cases are considered: one is when i < the target number, the target first sub-element is determined based on the first data group and the j-th parity sub-matrice, where the first data group is the data group in the data to be encoded associated with the j-th parity sub-matrice. Second, when i ≥ the target number, the target first element is determined based on the first sub-element associated with the (j+1)th check sub-matrix in the first element of the first intermediate calculation result. The first intermediate calculation result is the intermediate calculation result obtained in the process of calculating the first sub-element associated with the jth check sub-matrix in the zth first element, where z is the remainder of i divided by the target number.

[0038] The encoding module is used to generate r check symbols for the data to be encoded based on the first corrector. The i-th check symbol among the r check symbols is related to the i-th first element in the first corrector. These r check symbols are used to generate the encoded codewords for the data to be encoded, and the codeword length is the target codeword length.

[0039] In one possible implementation, the data encoding system includes M registers; the w-th register among the M registers is used to store first intermediate data, which is determined based on first sub-data and second intermediate data; the g-th register among the M registers is used to store second intermediate data, which is determined based on second sub-data; the first sub-data and second sub-data are data in a first data group; a first corrector generation module is further used to store data from the first data group into the M registers; when the first sub-data has been stored in the w-th register, update the first intermediate data in the w-th register; when the second sub-data has been stored in the g-th register, update the second intermediate data in the g-th register; based on the updated second intermediate data in the g-th register and the updated first intermediate data in the w-th register, update the first intermediate data in the w-th register again; and determine the target first sub-element based on the updated first intermediate data in the w-th register.

[0040] In one possible implementation, if r ≤ the first quantity, M equals the first quantity; if the first quantity < r < the second quantity, M equals the sum of r and the preset quantity; if r ≥ the second quantity, M equals the third quantity; the first quantity is less than the second quantity; and the second quantity is not greater than the third quantity.

[0041] In one possible implementation, the verification matrix is ​​determined based on a target finite field, where the target finite field is F. 16 [x] / (1+αx+x 2 ), where / represents the modular operation, and α is the finite field F 16 =F2[α] / (1+α+α) 2 +α 3 +α 4 The elements in ) are variables, where x is a variable.

[0042] In one possible implementation, the target number is 15.

[0043] In one possible implementation, the encoding module is further configured to obtain a first set of equations for determining r check symbols based on the first corrector and the first Vandermonde matrix; the first Vandermonde matrix is ​​obtained based on the r×r order of the check matrix; and the calculation of the first set of equations is performed to obtain r check symbols.

[0044] In one possible implementation, the encoding module is further configured to decompose the first Vandermonde matrix in the first set of equations into at least one upper triangular matrix and at least one lower triangular matrix to obtain a first preprocessed set of equations; and to perform calculations on the first preprocessed set of equations to obtain r check symbols.

[0045] Fourthly, a data decoding device is provided, including a second acquisition module, a second corrector generation module, and a decoding module.

[0046] The second acquisition module is used to acquire the data to be decoded; the data to be decoded includes ρ failed symbols and non-failed symbols.

[0047] The second corrector generation module is used to perform second corrector calculation based on the data to be decoded and the parity check matrix to generate the second corrector. The second corrector is used to generate ρ reconstructed symbols from ρ failed symbols. The parity check matrix includes N parity check matrices, where N is a positive integer, and the N parity check matrices are divided based on the target codeword length. The second corrector includes ρ second elements, where ρ ≤ r, and r is the number of parity symbols. Each second element includes N second sub-elements associated with the N parity check matrices. During the second corrector calculation, for the target second sub-element associated with the h-th parity check matrix in the l-th second element, there are two cases: First, if l < the target number, the target second sub-element is determined based on the second data set and the h-th parity check matrix. The second data set is the data set associated with the h-th parity check matrix from the non-failed symbols. Second, when l ≥ the target number, the target second element is determined based on the second intermediate calculation result and the second sub-element associated with the (h+1)th check sub-matrix in the lth second element. The second intermediate calculation result is the intermediate calculation result obtained in the process of calculating the second sub-element associated with the hth check sub-matrix in the mth second element, where m is the remainder of l divided by the target number.

[0048] The decoding module is used to generate ρ reconstructed symbols from ρ failed symbols based on the second corrector; wherein the l-th reconstructed symbol among the ρ reconstructed symbols is related to the l-th second element in the second corrector, and the ρ reconstructed symbols are used to obtain the decoded data of the data to be decoded.

[0049] In one possible implementation, the data decoding system includes M registers; the u-th register among the M registers is used to store third intermediate data, which is determined based on third sub-data and fourth intermediate data; the s-th register among the M registers is used to store fourth intermediate data, which is determined based on fourth sub-data; the third and fourth sub-data are data in a second data group; a second corrector generation module is further used to store data from the second data group into the M registers; when the third sub-data has been stored in the u-th register, the third intermediate data in the u-th register is updated; when the fourth sub-data has been stored in the s-th register, the fourth intermediate data in the s-th register is updated; based on the updated fourth intermediate data in the s-th register and the updated third intermediate data in the u-th register, the third intermediate data in the u-th register is updated again; and the target second sub-element is determined based on the updated third intermediate data in the u-th register.

[0050] In one possible implementation, if ρ < r, update the value of ρ to be equal to the value of r.

[0051] In one possible implementation, the decoding module is further configured to obtain a second set of equations for determining ρ reconstructed symbols of ρ failed symbols based on the second corrector and the second Vandermonde matrix; the second Vandermonde matrix is ​​a matrix of order ρ×ρ in the parity check matrix, with ρ rows including the first ρ rows of the parity check matrix and ρ columns including the columns containing the ρ failed symbols in the parity check matrix; the calculation of the second set of equations is performed to obtain the ρ reconstructed symbols of the ρ failed symbols.

[0052] In one possible implementation, the decoding module is further configured to decompose the second Vandermonde matrix in the second equation set into at least one upper triangular matrix and at least one lower triangular matrix to obtain the second preprocessed equation set; and to perform the calculation of the second preprocessed equation set to obtain ρ reconstructed symbols of ρ failed symbols.

[0053] Fifthly, a data encoding and decoding system is provided, including an encoder and a decoder, wherein the encoder is used to perform a data encoding method as described in the first aspect, and the decoder is used to perform a data decoding method as described in the second aspect.

[0054] Sixthly, a computing device is provided, comprising a processor and a memory. The processor is configured to execute instructions stored in the memory to cause the computing device to perform a data encoding method as described in the first aspect or a data decoding method as described in the second aspect.

[0055] In a seventh aspect, a chip system is provided, comprising a processor and a power supply circuit. The power supply circuit supplies power to the processor, which performs operational steps such as the data encoding method of the first aspect or the data decoding method of the second aspect.

[0056] Eighthly, a computer program product comprising instructions is provided, which, when executed by at least one computing device, cause the at least one computing device to perform a data encoding method as described in the first aspect or a data decoding method as described in the second aspect.

[0057] Based on the implementation methods provided in the above aspects, this application can be further combined to provide more implementation methods.

[0058] The following description includes more specific details about the implementation methods provided for the above aspects. Attached Figure Description

[0059] Figure 1 shows a schematic diagram of an encoding / decoding related method;

[0060] Figure 2 shows a schematic diagram of another encoding / decoding related method;

[0061] Figure 3 shows a schematic diagram of the architecture of a data encoding and decoding system provided in an embodiment of this application;

[0062] Figure 4 shows a flowchart of an encoding method provided in an embodiment of this application;

[0063] Figure 5 shows a schematic diagram of the second row elements of the verification matrix H provided in the embodiment of this application;

[0064] Figure 6 shows a flowchart of another encoding method provided in an embodiment of this application;

[0065] Figure 7 shows a schematic diagram of the computational structure of an encoding method provided in an embodiment of this application;

[0066] Figure 8 shows a schematic diagram of a verification matrix provided in an embodiment of this application;

[0067] Figure 9 shows a flowchart of another encoding method provided in an embodiment of this application;

[0068] Figure 10 shows a flowchart of a decoding method provided in an embodiment of this application;

[0069] Figure 11 shows a flowchart of another decoding method provided in an embodiment of this application;

[0070] Figure 12 shows a flowchart of another decoding method provided in an embodiment of this application;

[0071] Figure 13 shows a schematic diagram of a magnetoelectric disk storage system provided in an embodiment of this application;

[0072] Figure 14 shows a schematic diagram of the structure of a data encoding device provided in an embodiment of this application;

[0073] Figure 15 shows a schematic diagram of a data decoding device provided in an embodiment of this application;

[0074] Figure 16 shows a schematic diagram of the structure of the computing device provided in an embodiment of this application. Detailed Implementation

[0075] The terms "first," "second," "third," and "fourth," etc., used in the specification, claims, and drawings of this application are used to distinguish different objects, not to describe a specific order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or apparatuses.

[0076] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a mutually exclusive, independent, or alternative embodiment. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0077] The terms “component,” “module,” “system,” etc., used in this specification are used to refer to computer-related entities, hardware, firmware, combinations of hardware and software, software, or software in execution. For example, a component can be, but is not limited to, a process running on a processor, a processor, an object, an executable file, an execution thread, a program, and / or a computer. As illustrated, applications running on electronic devices and electronic devices themselves can be components. One or more components may reside in a process and / or an execution thread, and components may be located on a single computer and / or distributed among two or more computers. Furthermore, these components can be executed from various computer-readable media on which various data structures are stored. Components can communicate, for example, via local and / or remote processes based on signals having one or more data packets (e.g., data from two components interacting with another component between a local system, a distributed system, and / or a network, such as the Internet interacting with other systems via signals).

[0078] To facilitate understanding, the terminology used in this application will be introduced first.

[0079] (1) Maximum Distance Separable Codes (MDS codes): In communication and data storage systems, MDS codes are often used to ensure high reliability and integrity of data. Because they have the largest minimum distance, MDS codes can effectively correct or detect errors even in the worst-case environment of noise and errors.

[0080] (2) Reed-Muller transform (RM transform): This is the process of converting a Boolean function into a polynomial form, typically using a bivariate finite field. The Boolean function is a function defined in the domain... An n-ary function or mapping to the range F2 is denoted as f(x1,…,x). n Let f(x) be abbreviated as f(x), where x = x1, ..., x2. n ,(x1,…,x n ) is the binary representation of x.

[0081] (3) Erasure Code (EC): This is an encoding technique. It enables the encoding of data through erasure coding. If symbols in the encoded data become invalid (e.g., missing), and the number of invalid symbols is within design limits, the damaged encoded data can be decoded using the corresponding erasure coding to restore the original data. For example, erasure coding encodes the data blocks (i.e., information symbols, one data block equals one information symbol) contained in the original data to obtain redundant blocks (i.e., check symbols, one redundant block equals one check symbol). The redundant blocks and the data blocks in the original data together constitute the encoded codeword of the original data. In the event of missing information symbols in the encoded codeword of the data storage system, the lost information symbols can be recovered by decoding the redundant blocks. Erasure coding can be applied to data storage systems and data transmission systems to encode data managed or transmitted by these systems. The data can include data from various fields such as images, text, and audio.

[0082] (4) Reed-Solomon (RS) coding: This is an error correction coding method based on finite fields. During encoding, the method converts the data to be encoded into a polynomial form and performs a series of calculations to generate check symbols. During decoding, the method can effectively correct up to a certain number of invalid symbols by decoding the check symbols. Check symbols are redundant data appended to the end of the data, used to detect or correct errors generated during the transmission or storage of the data to be decoded. Invalid symbols refer to those symbols that cannot be correctly decoded or identified due to various reasons (such as transmission errors, storage corruption, improper processing, etc.).

[0083] However, in the implementation of erasure coding and decoding methods, the computational scale of generating check symbols during the encoding process is large, involving high computational complexity and low computational efficiency. Similarly, the computational scale of recovering information for each lost information symbol during the decoding process is large, involving high computational complexity and low computational efficiency.

[0084] As an example, please refer to Figure 1, which illustrates a schematic diagram of an encoding / decoding related method. The encoding method shown in Figure 1 is an RS encoding method based on the RM transform. The method involves constructing an RS code over a finite field based on the Vandermonde matrix. Then, based on the properties of the RM transform and the Vandermonde matrix, the corrector is quickly calculated, thus completing the encoding. Figure 1 shows the encoding under a code length N = 16 (i.e., x0, x1, x2, x3, x4, x5, x6, x7, x8, x9, x...). 10 ,x 11 ,x 12 ,x 13 ,x 14 ,x 15 The computational dependencies involved in the RM transformation. Specifically, the parent nodes in the tree (e.g., y0, y1, y2, y3, y4, y5, y6, y7, y8, y9, y... in the diagram)... 10 ,y 11 ,y 12 ,y 13 ,y 14 The sum of two child nodes means that intermediate computation results at lower levels of the tree are shared in computations at higher levels.

[0085] As shown in Figure 1, the RS coding method based on RM transform involves a large amount of interleaving at the lower levels (which can also be understood as a long step size for data processing) and performs calculations on the data at the length of the entire codeword or at a long step size. Thus, the RS coding method based on RM transform has a large computational scale and involves multiplication operations over a finite field, resulting in high computational complexity and low computational efficiency.

[0086] As an example, please refer to FIG. 2, which illustrates a schematic diagram of another encoding and decoding related method. The encoding method shown in FIG. 2 is a 4-point scale RS encoding and decoding method based on the Lin-Chung-Han Fourier transform (Lin-Chung-Han Fast Fourier Transform, LCH-FFT), that is, encoding K data symbols based on a finite field to generate R encoded symbols, and then designing a set of bases on the finite field where and and s0(x) = x, s j (x) = s j-1 (x)s j-1 (x - v j-1 ), (1 ≤ j ≤ m), where v i (0 ≤ i < m) belongs to the basis of the finite field . The LCH-FFT algorithm implements the Fast Fourier Transform (FFT) and the Inverse Fast Fourier Transform (IFFT) based on the above bases on the finite field , so that the fast encoding and decoding of RS codes can be realized through FFT and IFFT on the finite field (the schematic diagrams of the above 4-point scale FFT and IFFT algorithms are shown in a of FIG. 2 and b of FIG. 2 respectively).

[0087] As can be seen from FIG. 2, the RS encoding method based on LCH-FFT also involves multiplication operations on the finite field, and implements erasure decoding based on LCH-FFT. Thus, the entire process of the RS encoding method based on LCH-FFT has a high computational complexity and low computational efficiency. At the same time, the RS encoding algorithm based on LCH-FFT is difficult to be compatible with traditional RS code decoding algorithms such as (Reed-Solomon Improved Berlekamp-Massey, RiBM).

[0088] This application provides a data encoding method, including: acquiring data to be encoded, and performing a first corrector calculation based on the data to be encoded and a parity check matrix. The first corrector is used to generate parity symbols for the data to be encoded. The parity check matrix includes N parity check sub-matrices, where N is a positive integer, and the N parity check sub-matrices are divided according to the target codeword length. The first corrector includes r first elements, where r is a preset number of parity symbols, and each first element includes N first sub-elements associated with the N parity check sub-matrices respectively. During the calculation of the first corrector, for the target first sub-element associated with the j-th parity check matrix in the i-th first element, two cases are considered: one is when i < the target number, the target first sub-element is determined based on a first data group and the j-th parity check matrix, where the first data group is the data group associated with the j-th parity check matrix in the data to be encoded. Second, when i ≥ the target number, the target first element is determined based on the first sub-element associated with the (j+1)th parity sub-matrix in the i-th first element of the first intermediate calculation result. The first intermediate calculation result is the intermediate calculation result obtained in the process of calculating the first sub-element associated with the j-th parity sub-matrix in the z-th first element, where z is the remainder of i divided by the target number. Then, r parity symbols for the data to be encoded are generated based on the first corrector. The i-th parity symbol among the r parity symbols is associated with the i-th first element in the first corrector. The r parity symbols are used to generate the encoded codewords for the data to be encoded, and the codeword length is the target codeword length.

[0089] In this application's embodiments, the data to be encoded refers to data that needs to be encoded. This data can include data from various fields, such as one or more of images, text, and audio.

[0090] In the embodiments of this application, the corrector calculated and used in the data encoding method may be referred to as the first corrector.

[0091] The data encoding method provided in this application calculates r first elements in a first corrector based on the check sub-matrix of the check matrix and the data group associated with the check sub-matrix in the data to be encoded, enabling the computing device to automatically calculate the first corrector. Furthermore, this first corrector can be used to generate r check symbols in the data to be encoded, where r can be any number, allowing the data encoding method provided in this application to generate codewords containing any number of check symbols, thus having a wide range of applications. In the process of calculating the r first elements of the first corrector, the first intermediate calculation result obtained in calculating the target first sub-element when i < the target number can be reused, and combined with the first sub-element associated with the (j+1)th check sub-matrix in the i-th first element when i ≥ the target number, the target first sub-element when i ≥ the target number is obtained. This reduces the computational complexity of the first elements in the first corrector when i ≥ the target number, improving the computational efficiency of the first corrector and the overall processing efficiency of the data encoding process.

[0092] This application provides a data decoding method, including: acquiring data to be decoded, the data to be decoded including ρ failed symbols and non-failed symbols. Then, a second corrector calculation is performed based on the data to be decoded and a parity check matrix. The second corrector is used to generate ρ reconstructed symbols from the ρ failed symbols. The parity check matrix includes N parity check sub-matrices, where N is a positive integer, and the N parity check sub-matrices are divided based on the target codeword length. The second corrector includes ρ second elements, where ρ ≤ r, and r is the number of parity symbols. Each second element includes N second sub-elements associated with the N parity check sub-matrices respectively. During the second corrector calculation, for the target second sub-element associated with the h-th parity check matrix in the l-th second element, there are two cases: one is when l < the target number, the target second sub-element is determined based on the second data group and the h-th parity check matrix, where the second data group is the data group associated with the h-th parity check matrix among the non-failed symbols. Second, when l ≥ the target number, based on the second intermediate calculation result and the second sub-element associated with the (h+1)th check matrix in the lth second element, the target second sub-element is determined. The second intermediate calculation result is the intermediate calculation result obtained in the process of calculating the second sub-element associated with the hth check matrix in the mth second element, where m is the remainder when l is divided by the target number. Subsequently, based on the second corrector, ρ reconstructed symbols of ρ failed symbols are generated; where the lth reconstructed symbol among the ρ reconstructed symbols is associated with the lth second element in the second corrector, and the ρ reconstructed symbols are used to obtain the decoded data of the data to be decoded.

[0093] In the embodiments of this application, the data to be decoded refers to all or part of the encoded codewords that need to be decoded, and the encoded codewords can be encoded codewords obtained by encoding the data provided in the embodiments of this application.

[0094] Here, the codeword refers to the encoded data. A codeword includes multiple symbols (including information symbols and check symbols). Symbols are data bits. Lost symbols refer to data bits lost during storage or transmission. Lost symbols include information symbols and / or check symbols. Unlost symbols refer to data bits that are preserved intact during storage or transmission. Unlost symbols include information symbols and / or check symbols.

[0095] In the embodiments of this application, the corrector calculated and used in the data decoding method may be referred to as the second corrector.

[0096] The data decoding method provided in this application calculates ρ second elements in the second corrector based on the check sub-matrix of the check matrix and the data group associated with the check sub-matrix in the unfailed symbols. This enables the computing device to automatically calculate the second corrector. Furthermore, this second corrector can be used to generate ρ reconstructed symbols from ρ failed symbols in the decoded data, where ρ ≤ r, and r is the number of check symbols. This allows the data decoding method provided in this application to recover reconstructed symbols from a number of failed symbols less than or equal to the number of check symbols, making the method widely applicable. In the process of calculating the ρ second elements of the second corrector, the second intermediate calculation result obtained in determining the second sub-elements when l < the target number can be reused. Simultaneously, the second sub-elements associated with the (h+1)th check sub-matrix in the l-th first element when l ≥ the target number are combined to obtain the target second sub-elements when l ≥ the target number. This reduces the computational complexity of the second elements in the second corrector when l ≥ the target number, improving the computational efficiency of the second corrector and the overall processing efficiency of the data decoding process.

[0097] The data encoding and decoding method proposed in this application can be used in various types of communication systems or data storage systems. As an example, the data storage system may include optical disc storage systems, disk storage systems, magnetic tape storage systems, solid-state storage systems, or storage systems composed of optical discs, disks, magnetic tapes, solid-state storage, or a mixture of multiple storage media.

[0098] Figure 3 is a schematic diagram of the architecture of the data encoding and decoding system provided in an embodiment of this application. As shown in Figure 3, the data encoding and decoding system 100 may include a data access device 110, a first computing device 120, and a second computing device 130.

[0099] Data access device 110 is used to read data (e.g., data to be encoded and data to be decoded) and write data (e.g., encoded codewords and decoded data). Data access device 110 includes a storage medium 111, a rack 112, and a controller 113. Storage medium 111 is used to store data. Storage medium 111 may include optical discs, magnetic disks, magnetic tapes, solid-state storage, or a combination of multiple storage media. Rack 112 is used to load storage media, such as optical discs, and to perform data writing or reading operations on the storage media. Rack 112 may include an optical drive, an optical disc tray, and a robotic arm (not shown in Figure 3). The optical drive is used for writing or reading data. The optical disc tray is used to hold optical discs. The robotic arm is used to insert storage media into the optical drive. Controller 113 is used to control the movement of rack 112. Data access device 110 may also include an I / O interface 114, which can be used to transmit data with other components or devices in the system. For example, data access device 110 transmits the read data to be encoded to the first computing device 120 through I / O interface 114.

[0100] The first computing device 120 is used to obtain data to be encoded from the data access device 110 and to encode the data to be encoded to obtain a check symbol. The encoding process can be implemented by the data encoding method provided in the embodiments of this application.

[0101] In one possible implementation, the first computing device 120 can write the check symbol to a different storage location in the data access device than the storage location of the data to be encoded. If it is subsequently discovered that some of the data to be encoded is lost, the lost data can be recovered using the data decoding method provided in this application embodiment.

[0102] In another possible implementation, the first computing device 120 can generate encoded codewords based on the check symbol and the data to be encoded, and transmit the encoded codewords to the second computing device 130. However, during data transmission, due to noise in the transmission channel, the transmitted encoded codewords may be erased or erroneous. Therefore, the second computing device 130 needs to decode the received encoded codewords (hereinafter referred to as the data to be decoded for ease of distinction) to generate reconstructed symbols for the failed symbols. The decoding process can be implemented using the data decoding method provided in the embodiments of this application.

[0103] If required by business needs, the second computing device 130 can also re-encode the decoded data using the data encoding method provided in this application embodiment for transmission to other devices or storage.

[0104] The data access device 110 and the first computing device 120, and the first computing device 120 and the second computing device 130, can be connected by wired or wireless means.

[0105] It is worth noting that Figure 3 is merely a schematic diagram of the architecture of a data encoding and decoding system provided in an embodiment of this application, and the positional relationships between the devices, components, modules, etc. shown in Figure 3 do not constitute any limitation.

[0106] For example, in Figure 3, storage medium 111 is disposed in data access device 110. In other cases, storage medium 111 may also be a component outside of data access device 110.

[0107] For example, in Figure 3, the first computing device 120 is an external device of the data access device 110. In other cases, the first computing device 120 may also be located on the data access device 110.

[0108] The data encoding method provided in the embodiments of this application is described in detail below. Figure 4 is a schematic flowchart of a data encoding method provided in an embodiment of this application. The method shown in Figure 4 can be executed by a computing device, for example, by the processor of a first computing device 120, or by the processor of a second computing device 130. The method includes S101-S103, as follows:

[0109] S101. Obtain the data to be encoded.

[0110] In this embodiment of the application, the data to be encoded includes multiple symbols (e.g., 16 symbols, namely x0, x1, x2, x3, x4, x5, x6, x7, x8, x9, x...). 10 ,x 11 ,x 12 ,x 13 ,x 14 ,x 15 The symbols in the data to be encoded, along with the symbols in the data to be encoded, are called information symbols.

[0111] For ease of description, let the length of the data to be encoded be k, that is, the data to be encoded includes k information symbols.

[0112] S102. Calculate the first corrector based on the data to be encoded and the check matrix to obtain the first corrector used to generate the check symbol of the data to be encoded.

[0113] The parity check matrix comprises N parity submatrices, where N is a positive integer. These N submatrices are divided according to the target codeword length. The target codeword length refers to the length of the encoded codeword after the data to be encoded is completed. It is equal to the sum of the number of information symbols and the number of parity symbols in the data to be encoded, and can be expressed as target codeword length n = k + r, where r is the preset number of parity symbols.

[0114] The first corrector includes r first elements, and each first element includes N first sub-elements associated with the N corrector matrices respectively.

[0115] The parity-check matrix (PCM) is used to detect and correct errors in the data to be encoded during transmission and storage. It is essentially a coefficient matrix of a set of parity-check equations. The number of rows in the PCM is the same as the number of parity symbols, and the number of columns is the same as the length of the target codeword of the data to be encoded.

[0116] In one possible implementation, the verification matrix is ​​based on the target finite field F. 16 [x] / (1+αx+x 2 Constructed by ), where / denotes the modular operation, and α is the finite field F. 16 =F2[α] / (1+α+α) 2 +α 3 +α 4 The elements in ) are variables, where x is a variable.

[0117] Due to F 16 =F2[α] / (1+α+α) 2 +α 3 +α 4 Let F be a finite field with 16 elements. 16 =F2[α] / (1+α+α) 2 +α 3 +α 4 The basis vectors on α can be represented as: α = [1, α, α] 2 ,α 3 Define the binary vector of the number g as: β g =[b0,b1,b2,b3] T Then any element μ g ∈F 16 It can be represented as: μ g =α·β g ,0≤g<16,

[0118] Next, the verification matrix H is constructed using the Vandermonde matrix. A Vandermonde matrix can be represented as:

[0119] It can be seen that the parity-check matrix H is completely determined by the elements of its second row (the elements of the first row are 1, and the elements of the second and subsequent rows can be obtained from the elements of the second row). The elements of the second row are defined by the finite field F. 16 [x] / (1+αx+x 2 If the matrix is ​​composed of different elements μg and μf in the first row, then the elements in the second row can be represented as: μgx + μf, 0 ≤ g, f ≤ 16. When n ≤ 256, the constructed parity-check matrix satisfies the MDS property.

[0120] When n≤256, the second row of the verification moments H can be grouped:

[0121] Where, γ j =x+μ j-1 γ j Let Gj represent the grouping coefficient of the j-th group, N be the number of groups, G0 be the element of the first group, and Gj be the grouping coefficient of the j-th group. j Given the j-th group of elements, the parity check matrix H can be represented as:

[0122] Since the second row element of the parity matrix H is derived from the finite field F 16 [x] / (1+αx+x 2 The second row of the parity check matrix H is composed of different elements, as shown in Figure 5, and can be represented by n. j Let represent the number of elements contained in each group. The first group (i.e., j=0) contains 16 elements, and the subsequent groups each contain 15 elements. Then the target codeword length n satisfies:

[0123] Based on the principle of grouping the elements in the second row of the parity check matrix H, the parity check matrix H can also be divided into N parity check submatrices, as follows:

[0124] Wherein, the j-th check submatrix The first parity submatrix H0 has a size of r×16, and each of the remaining parity submatrixes has a size of r×15, thus realizing the division of the parity matrix into parity submatrixes based on the target codeword length.

[0125] In addition, due to F 16 =F2[α] / (1+α+α) 2 +α 3 +α 4 Then all polynomials in the ring F 16 =F2[α] / (1+α+α) 2 +α 3 +α 4 All operations on the polynomial ring F2[x] / (1+α) can be performed first. 5 The operation is performed on the polynomial 1 + α + ... + α at the end of the calculation. 4 This reduces computational complexity.

[0126] In this implementation, the target finite field F 16 [x] / (1+αx+x 2The target finite field F has 256 distinct elements, and all operations on this finite field can be performed using cyclic shifts and XOR operations. Multiplication requires only 2 to 3 XOR operations, reducing computational complexity. 16 [x] / (1+αx+x 2 The parity check matrix is ​​constructed based on the Vandermonde matrix, which gives the parity check matrix some special properties (such as the property that the second row elements can be grouped, which allows the parity check matrix to be divided into N parity check submatrices). Then, the subsequent encoding and decoding operations are performed based on these properties of the parity check matrix, which helps to reduce the computational complexity and thus enables the software and hardware to implement it efficiently.

[0127] For each check symbol, the element associated with that check symbol (i.e., the first element) in the first corrector can be calculated from the check matrix. For r check symbols, r first elements associated with each of the r check symbols can be calculated. These r first elements constitute the first corrector, which can be represented as the first corrector S = [S0, ..., S...]. r-1 ], where S0,…,S r-1 Each is a first element.

[0128] Therefore, it can be seen that the r first elements and r check symbols in the first corrector are in one-to-one correspondence. In other words, each check symbol in the r check symbols corresponds to one of the first elements in the first corrector, that is, each check symbol in the r check symbols is associated with one of the first elements in the first corrector.

[0129] After dividing the parity check matrix into N parity check submatrices, for the first element associated with each parity symbol, a component of the first element (i.e., the first child element) can be calculated using a parity check submatrix. Furthermore, the N parity check submatrices can each be used to calculate N first child elements. For any given first child element, the parity check submatrix used to calculate that first child element can be called the parity check submatrix associated with that first child element.

[0130] Taking a first element S0 as an example, the first element S0 = [S 0,1 ,…,S 0,N ], where S 0,1 ,…,S 0,N Each element represents a first child element. Thus, each first element can include N first child elements. Calculating r first elements requires calculating N×r first child elements, and these N×r first child elements constitute the first corrector.

[0131] During the calculation of the first corrector, for the first sub-element (which can be called the target first sub-element) associated with the j-th check matrix in the i-th first element, there are two calculation methods:

[0132] Method (1): When i < target quantity, determine the first target sub-element based on the first data group and the j-th check sub-matrix; the first data group is the data group in the data to be encoded that is associated with the j-th check sub-matrix.

[0133] Among them, the first data group X j X j Including n j There are 1 data point, n when j = 0. j =16, X0={x 0,0 ,x 1,0 ,…,x 15,0 When j≠0, n j =15, X j ={x 1,j ,…,x 15,j}

[0134] Due to F in the polynomial ring 16 [x] = F2[x] / (1+α+…+α) 4 Any element μ in ) i For (0≤i<16), we have: μ i 16 = μ i ,μ i ∈F 16 [x], then each check submatrix cycles through 15 elements per column, meaning the target quantity is 15. The MDS property is determined by the grouping coefficient λ. i Guarantee. That is, for each first element, the first 15 first sub-elements are calculated. The values ​​of the first 15 first sub-elements can be reused when calculating the subsequent first sub-elements. Method (1) is the method for determining the first 15 first sub-elements.

[0135] In some implementations, determining the target first sub-element based on the first data group and the j-th check sub-matrix can be achieved by calculating formula ①, which is as follows: S i,j =S i,j+1 +(x+μ j-1 ) i S i,j ′,0≤i<15,0≤j<N ①

[0136] Among them, S i,j It is the first child element of the target, S i,j ′ is the first intermediate calculation result, when j = N-1, S i,j+1 =0.

[0137] In some implementations, S i,j ′ is the product of the first data set and the elements in the first row of the j-th parity submatrix, excluding 0, (x+μj-1 ) i Let be the coefficient of the i-th row in the j-th check submatrix.

[0138] During the execution of calculation formula ①, if j = r, S i,j+1 =0.

[0139] Method (2): Based on the first intermediate calculation result and the first sub-element associated with the (j+1)th check sub-matrix in the i-th first element, determine the target first sub-element; the first intermediate calculation result is the intermediate calculation result obtained in the process of calculating the first sub-element associated with the j-th check sub-matrix in the z-th first element, where z is the remainder of i divided by the target number.

[0140] Method (2) is the method for determining the first child element after the first 15 first child elements.

[0141] In some implementations, the target first sub-element can be determined based on the first intermediate calculation result and the first sub-element in the i-th first element that is associated with the (j+1)-th check sub-matrix, which can be achieved by calculation formula ②, as follows:

[0142] S i,j =S i,j+1 +(x+μ j-1 ) i S z,j ′,z=i mod 15,15≤i<r,0≤j<N ②

[0143] By setting z = i mod 15, the intermediate calculation results in determining the first child element of the target when 0 ≤ i < 15 can be reused. This allows the calculation process for determining the first child element of the target when 15 ≤ i < r to only require calculating the result with (x + μ) mod 15. j ) i Multiplication and S i,j+1 The addition method reduces the computational complexity when the number of check symbols is large.

[0144] S103. Generate r check symbols for the data to be encoded based on the first corrector, wherein the i-th check symbol among the r check symbols is related to the i-th first element in the first corrector, and the r check symbols are used to generate the encoded codeword of the data to be encoded, and the codeword length of the encoded codeword is the target codeword length.

[0145] If we denote the encoded codeword as c, then it can be divided into c T =[p T |m T ], where the vector contains r check symbols, the vector m contains k bits of data to be encoded, and p T m is the transpose of pT This is the transpose of m. Accordingly, the parity check matrix H can be divided into two submatrices H = [H...]. p |H m ], where H p Let H be an r×r Vandermonde matrix consisting of the first r columns of the parity-check matrix H. m For the r×(nr) order Vandermonde matrix formed by the last nr columns of the parity check matrix, the first corrector S = H m ·m, check symbol It can be seen that the check symbol can be passed get.

[0146] In one possible implementation, S103 may include: obtaining a first set of equations for determining r check symbols based on the first corrector and the first Vandermonde matrix; the first Vandermonde matrix is ​​obtained based on the r×r order of the check matrix; and performing the calculation of the first set of equations to obtain r check symbols.

[0147] The first Vandermonde matrix is ​​the aforementioned H. p The first system of equations is a linear system of equations.

[0148] In this implementation, the unknowns in the first system of equations are check symbols, and r check symbols can be directly obtained by solving the first system of equations.

[0149] In one possible implementation, performing the calculation of the first set of equations to obtain r check symbols may include: decomposing the first Vandermonde matrix in the first set of equations into at least one upper triangular matrix and at least one lower triangular matrix to obtain a first preprocessed set of equations; and performing the calculation of the first preprocessed set of equations to obtain r check symbols.

[0150] This implementation is based on the LU decomposition of the Vandermonde matrix. L (Lower Triangular Matrix) refers to the lower triangular matrix, where all elements above the diagonal are zero; U (Upper Triangular Matrix) refers to the upper triangular matrix, where all elements below the diagonal are zero.

[0151] Assume H p If the matrix is ​​a 4th order Vandermonde matrix, it can be decomposed into three upper triangular matrices and three lower triangular matrices, as shown below:

[0152] Then, by solving the first set of preprocessing equations, r check symbols can be obtained.

[0153] In this implementation, the special structure of the upper triangular matrix and the lower triangular matrix simplifies matrix operations (such as finding the determinant and the inverse matrix), thereby reducing the computational complexity of the first preprocessing equation set and improving the efficiency of obtaining r verification symbols.

[0154] Finally, based on r check symbols and the data to be encoded, the encoded codeword c is obtained.

[0155] In this embodiment, by calculating r first elements in the first corrector based on the check sub-matrix of the check matrix and the data group associated with the check sub-matrix in the data to be encoded, the computing device can automatically calculate the first corrector. Furthermore, this first corrector can be used to generate r check symbols in the data to be encoded, where r can be any number, enabling the data encoding method provided in this embodiment to generate codewords containing any number of check symbols, thus having a wide range of applications. In the process of calculating the r first elements of the first corrector, the first intermediate calculation result obtained in calculating the target first sub-element when i < the target number can be reused, and combined with the first sub-element associated with the (j+1)th check sub-matrix in the i-th first element when i ≥ the target number, the target first sub-element when i ≥ the target number is obtained. This reduces the computational complexity of the first elements in the first corrector when i ≥ the target number, improving the computational efficiency of the first corrector and the overall processing efficiency of the data encoding process.

[0156] In one embodiment, the method shown in S101-S103 is applied to a data encoding system, as shown in FIG6. The data encoding system includes M registers. The first data group includes a first sub-data and a second sub-data. The w-th register among the M registers is used to store the first intermediate data, which is determined based on the first sub-data and the second intermediate data. The g-th register among the M registers is used to store the second intermediate data, which is determined based on the second sub-data.

[0157] In method (1), the step of determining the target first sub-element based on the first data group and the j-th check sub-matrix may include:

[0158] S201. Store the data in the first data group into M registers.

[0159] Each piece of data in the first data group can be stored in at least one register, and each register can store at least one piece of data from the first data group.

[0160] In some implementations, the data in the first data group is stored sequentially into M registers in reverse or partially reverse order. For example, the first data group X... j ={x1,j ,…,x 15,j}, its data order is x 1,j →x 15,j Then the order in which the data is stored in the M registers is x. 15,j →x 0,j .

[0161] S202, if the first sub-data has been stored in the w-th register, update the first intermediate data in the w-th register.

[0162] Before the first sub-data is stored in the w-th register, the w-th register may or may not store the first intermediate data, or it may store some initial first intermediate data.

[0163] If the first intermediate data is not stored in the w-th register, the computation required to update the first intermediate data in the w-th register is computation S. i,j The calculations related to the first sub-data point during the process of ', for example, if the first sub-data point is x. 15,j S i,j ′ for S 13,j ', calculate S 13,j During the process of ′ and x 15,j The relevant calculation is α 2 x 15,j Therefore, the first intermediate data in the w-th register after the update is α. 2 x 15,j .

[0164] Given that the w-th register stores some initial first intermediate data, the computation required to update the first intermediate data in the w-th register is computation S. i,j The calculations related to the first sub-data and the initial first intermediate data during the process of '', for example, the first sub-data is x. 8,j The initial first intermediate data is α. 2 x 15,j S i,j ′ for S 13,j ', calculate S 13,j During the process of ′ and x 8,j and α 2 x 15,j The relevant calculation is α 2 x 15,j α 4 x 8,j and α 2 x 15,j +α 4 x 8,j Therefore, the first intermediate data in the w-th register after the update is α. 2 x 15,j +α4 x 8,j .

[0165] S203. If the second sub-data has been stored in the g-th register, update the second intermediate data in the g-th register.

[0166] Similarly, before the second sub-data is stored in the g-th register, and before the second intermediate data is stored in the g-th register, the computation required to update the second intermediate data in the g-th register is to calculate S. i,j The calculations related to the second sub-data during the process; given that some initial second intermediate data is stored in the g-th register, the calculation required to update the second intermediate data in the g-th register is calculation S. i,j The calculations related to the second sub-data and the initial second intermediate data during the process of ′.

[0167] S204. Based on the updated second intermediate data in the g-th register and the updated first intermediate data in the w-th register, update the first intermediate data in the w-th register again.

[0168] Similarly, the calculation of updating the first intermediate data in the w-th register again is to calculate S. i,j The calculations involved in the process are related to the second intermediate data in the updated g-th register and the first intermediate data in the updated w-th register.

[0169] In some implementations, steps S202-S204 are performed at least once during the process of determining the target first sub-element, until the first intermediate data in the w-th register is updated to S again after the at least one execution. i,j ′ or includes all data that is expected to be stored in all w-th registers.

[0170] Use T1,…,T M Represents M registers, T0 is only S 0,j The symbol for ' does not introduce additional registers, so when i = 0,...,14, S i,j The calculation process for S is as follows: 0,j ′=T0 S 1,j =T1+αT2+α 2 T3+α 3 T4 S 2,j ′=T1+α 2 T2+α 4 T3+aT4 S 4,j ′=T1+α 4 T2+α 3 T3+α 2 T4

[0171] S 7,j ′=T 14 =α 3 x 15,j +αx 8,j +α 4 x 4,j +S 12,j ′(T 18 (without x) 0,j ,x 1,j ,x 2,j Item) + S 2,j ' S 8,j ′=T1+α 3 T2+αT3+α 4 T4 S 10,j ′=T 13 =T 13 +T8 S 11,j ′=T 15 =α 4 x 15,j +α 3 x 8,j +α 2 x 4,j +S 6,j ′(T 11 (x0, x1, x2 terms not included) + S 1,j ′

[0172] S 13,j ′=T 16 =α 2 x 15,j +α 4 x 8,j +αx 4,j +S 8,j ′+S 3,j ′(T 10 (without x) 0,j ,x 1,j ,x 2,j item)

[0173] S 14,j ′=T 17 =αx 15,j +α 2 x 8,j +α 3 x 4,j +S 9,j ′(T 12 (without x) 0,j ,x 1,j ,x 2,j Item) + S4,j ′

[0174] Among them, the superscript of T represents the update time of the register. The larger the superscript of the same register, the newer the data stored in the register. The data stored in the register at each moment will be retained in the register.

[0175] The calculation structure obtained based on the above calculation process is shown in Figure 7.

[0176] In a possible implementation manner, if r ≤ the first quantity, M is equal to the first quantity; if the first quantity < r < the second quantity, M is equal to the sum of r and the preset quantity; if r ≥ the second quantity, M is equal to the third quantity; the first quantity is less than the second quantity; the second quantity is less than or equal to the third quantity.

[0177] From the above calculation process, it can be seen that the first quantity is 5, the second quantity is 15. When r ≤ 5, calculating all S i,j ′ requires 5 registers; when 5 < r < 15, calculating all S i,j ′ requires r + 4 registers, that is, the preset quantity is 4; when r = 15, calculating all S i,j ′ requires 18 registers. When r > 15, based on calculation formula ②, it can be seen that only the first 15 S i,j ′ need to be calculated, and i,j ′ requires 15 registers. The subsequent S i,j ′ can reuse the first 15 S i,j ′. Therefore, calculating all S

[0178] ′ also requires 18 registers, that is, the third quantity is 18. That is to say, when r ≥ 15, the number of registers required is fixed and does not increase with the increase of r.

[0179] Table 1

[0180] S205. Determine the target first sub - element based on the first intermediate data in the w - th register after the second update.

[0181] Based on the first intermediate data in the w - th register after the second update, calculate the multiplication of the first intermediate data in the w - th register after the second update and (x + μ j ) i and S i,j+1The addition results in the target first sub - element.

[0182] Exemplarily, in the case of (n,k)=(181,169), r = 12. The first sub - matrix H0 of the RS code check matrix H of 169+12 is given in the form of Figure 8. H p The first 12 columns of the check matrix form a 12×12 Vandermonde matrix, as shown in the shaded part of Figure 8.

[0183] The check matrix H is divided into 12 sub - matrices H0, H1, …, H 11 , N = 12, n0 = 16, n i = 15, (0 < i < 11).

[0184] Then S i,j ′(0 < i < 11, 0 ≤ j < 11) is calculated as follows: S 0,j ′ = T0; S 1,j ′ = T5 = T1+αT2+α 2 T3+α 3 T4; S 2,j ′ = T5 = T1+α 2 T2+α 4 T3+aT4; S 4,j ′ = T5 = T1+α 4 T2+α 3 T3+α 2 T4; S 8,j ′ = T5 = T1+α 3 T2+aT3+α 4 T4; S 10,j ′ = T 13 = T 13 +T8; S 11,j ′ = T 15 = a[[ID=6|0]] 4 x 15 +a 3 x8+a 2 x4+S 6,j ′(T 11 )(without adding x0, x1, x2 terms)+S 1,j ′; [[ID=7|5]]

[0185] According to the above - mentioned S201 - S205 and the calculation process of S i,j ′(0 < i < 11, 0 ≤ j < 11), store data in M registers and update the stored data, specifically as follows:

[0186] Store T 11,j = T0;

[0187] Enter x 15,j :storage storage Store T8 = x 15,j Store T9 = x 15,j Storage T 14 =α 3 *x 15,j Storage T 15 =α 4 *x 15,j ;

[0188] Enter x 14,j :storage renew

[0189] Enter x 13,j :storage renew Storage T 13 =x 13,j ;

[0190] Enter x 12,j :renew renew renew renew renew renew storage storage renew

[0191] Enter x 11,j :renew Store T7 = x 11,j ,renew

[0192] Enter x 10,j :renew renew renew renew

[0193] Enter x 9,j Update T9 = T9 + x 9,j ,renew renew renew renew

[0194] Enter x j,j :renew renew renew Update T j =Tj +x j,j Update T 14 =T 14 +α*x 8,j Update T 15 =T 15 +α 3 *x 8,j ;

[0195] Enter x 7,j :renew renew

[0196] Enter x 5,j :renew renew renew renew renew Update T 13 =T 13 +x 5,j ,renew

[0197] Enter x 6,j :renew renew renew Update T9 = T9 + x 6,j Update T 10 =T 10 +α 2 *T9, update T 11 =T 11 +α 4 *T9, update T 12 =T 12 +α*T9, update T 14 =T 14 +α 3 *T9;

[0198] Enter x 4,j :renew renew renew renew renew renew renew Update T 15 =T 15 +α 2 *x 4,j ;

[0199] Enter x 3,j :renew renew Update T7 = T7 + x 3,j Update T8 = T8 + x 3,j Update T 10 =T 10 +α 4 *T7, update T 11 =T 11 +α 3 *T7, update T 12 =T 12 +α 2 *T7, update T 14 =T 14 +α*T7, update T 15 =T 15 +T 11 Update T 13 =T 13 +(α 3 +α 2 T8;

[0200] Enter x 2,j :renew renew renew Update T 10 =T 10 +α 3 *x 2,j Update T 11 =T 11 +α*x 2,j Update T 12 =T 12 +α 4 *x 2,j ;

[0201] Enter x 1,j :renew renew renew Update T 10 =T 10 +x 1,j Update T 11 =T 11 +x 1,j Update T 12 =T 12 +x 1,j ;

[0202] When j = 0, input x 0,0 :renew

[0203] S is obtained through the above steps. i,jAfter ′(0 < i < 11, 0 ≤ j < 12), calculate each first sub-element. The calculation process is as follows:

[0204] S 0,j = T0; S 1,j = S 1,j+1 +(x + μ j-1 )S 1,j ′; S 2,j = S 2,j+1 +(x + μ j-1 ) 2 S 2,j ′; S 4,j = S 4,j+1 +(x + μ j-1 ) 4 S 4,j ′; S 8,j = S 8,j+1 +(x + μ j-1 ) 8 S 8,j ′; S 3,j = S 3,j+1 +(x + μ j-1 ) 3 S 3,j ′; S 6,j = S 6,j+1 +(x + μ j-1 ) 6 S 6,j ′; S 9,j = S 9,j+1 +(x + μ j-1 ) 9 S 9,j ′; S 5,j = S 5,j+1 +(x + μ j-1 ) 5 S 5,j ′; S 10,j = S 5,j+1 +(x + μ j-1 ) 10 S 10,j ′; S 7,j = S 7,j+1 +(x + μ j-1 ) 7 S 7,j ′; S 11,j = S5, j+1 +(x + μ j-1 ) 11 S 11,j ′;

[0205] After calculating 12×12 first sub-elements, the first correction sub is obtained

[0206] After that, through The solution yielded 12 check symbols.

[0207] In this embodiment, multiple registers are used to store the data (including first intermediate data and second intermediate data) required in the calculation of the target first sub-element. This provides storage space for intermediate calculation results during the calculation of the target first sub-element, reducing the access latency of storing it in memory and improving the processing efficiency of the data storage system. In the calculation of the target first sub-element, the first intermediate data in register w is first updated based on the first sub-data. Then, after the second intermediate data in register g is updated based on the second sub-data, the first intermediate data in register w is updated again based on the updated second intermediate data in register g, thus obtaining the target first sub-element. This achieves incremental calculation, meaning that the intermediate data in the corresponding register is updated immediately after each sub-data is stored, without waiting for both the first and second sub-data to be stored in register w. The target first sub-element is then obtained by updating the first intermediate data in register w all at once from register w. This avoids update waiting time (e.g., the time spent waiting for the second sub-data to be stored in register w after storing the first sub-data), improving the processing efficiency of the data encoding system.

[0208] For ease of understanding, as an example, an example of a data encoding method is described below. Please refer to Figure 9, which is a flowchart illustrating another encoding method provided in an embodiment of this application. As shown in Figure 9, the method includes S301-S304, as detailed below:

[0209] S301, Read the raw data from k information disks.

[0210] Among them, the information disk is used to store information symbols, and one information disk stores one information symbol. Figure 9 shows four information disks (information disk one, information disk two, information disk three and information disk four), i.e., k=4.

[0211] S302. The first corrector is obtained through the improved RM transformation method.

[0212] The principle of the improved RM transformation method is as described in S102 above, and will not be elaborated further.

[0213] S303. Solve the first system of equations by LU decomposition to obtain r check symbols.

[0214] S304. Write r check symbols to r redundant disks.

[0215] The redundant disks are used to store check symbols, with one redundant disk storing one check symbol. Figure 9 illustrates three redundant disks (redundant disk one, redundant disk two, and redundant disk three), i.e., r = 3.

[0216] The implementation of S301-S303 can refer to the specific description of S101-S103, and can achieve the same or similar beneficial effects.

[0217] The following describes in detail the data decoding method provided in the embodiments of this application. Figure 10 is a schematic flowchart of a data decoding method provided in an embodiment of this application. The method shown in Figure 10 can be executed by a computing device, for example, by the processor of a first computing device 120, or by the processor of a second computing device 130. The data decoding method shown in Figure 10 can be used to decode the encoded codewords obtained by the data encoding method shown in Figure 4 and / or Figure 6. The method includes S401-S403, as follows:

[0218] S401, Obtain the data to be decoded.

[0219] The data to be decoded includes ρ failed symbols and non-failed symbols, and the length of the data to be decoded is ≤n.

[0220] S402. Calculate the second corrector based on the data to be decoded and the parity check matrix to obtain the second corrector used to generate ρ reconstructed symbols for ρ failed symbols.

[0221] The check matrix includes N check sub-matrices, where N is a positive integer. The N check sub-matrices are divided according to the target codeword length. The second check matrix includes ρ second elements, where ρ≤r. Each second element includes N second sub-elements associated with the N check sub-matrices respectively.

[0222] The data to be decoded (e.g., encoded codewords obtained using the data encoding methods shown in Figures 4 and / or 6) includes information symbols and check symbols, wherein there are r check symbols and k information symbols, where r + k = n. In the data to be decoded, some of the n symbol positions are invalid. In this embodiment, invalid symbols are called invalid symbols, and non-invalid symbols are called non-invalid symbols.

[0223] In some possible implementations, all ρ failed symbols in the data to be decoded can be information symbols. In other possible implementations, the ρ failed symbols in the data to be decoded can include both information symbols and check symbols.

[0224] The process of dividing the parity matrix into N parity submatrices is as shown in S102, which will not be elaborated here.

[0225] The reconstruction symbol is the failure symbol recovered based on the second corrector.

[0226] During the calculation of the second corrector, for the target second sub-element associated with the h-th check matrix in the l-th second element, there are two calculation methods:

[0227] Method (3): When l < target quantity, determine the target second sub-element based on the second data group and the h-th check sub-matrix; the second data group is the data group associated with the h-th check sub-matrix among the non-failed symbols.

[0228] Among them, the second data group X h X h Including n h There are 1 data point, n when h = 0. h =16, X0={x 0,0 ,x 1,0 ,…,x 15,0 When h≠0, n h =15, X h ={x 1,h ,…,x 15,h}

[0229] In this embodiment of the application, the target second sub-element can be determined based on the second data group and the h-th check sub-matrix by calculation formula ①, where h is equivalent to calculation formula ①j and l is equivalent to calculation formula ①i.

[0230] Method (4): When l ≥ target quantity, the target second sub-element is determined based on the second intermediate calculation result and the second sub-element associated with the (h+1)th check sub-matrix in the lth second element; the second intermediate calculation result is the intermediate calculation result obtained in the process of calculating the second sub-element associated with the hth check sub-matrix in the mth second element, where m is the remainder of l divided by the target quantity.

[0231] In this embodiment of the application, the target second element can be determined by calculation formula ② based on the second sub-element associated with the h-th check sub-matrix in the w-th second element and the second sub-element associated with the (h+1)-th check sub-matrix in the l-th second element. h is equivalent to calculation formula ②j, l is equivalent to calculation formula ②i, and m is equivalent to calculation formula ②z.

[0232] S403. Based on the second corrector, generate ρ reconstructed symbols from ρ failed symbols; wherein, the l-th reconstructed symbol among the ρ reconstructed symbols is related to the l-th second element in the second corrector, and the ρ reconstructed symbols are used to obtain the decoded data of the data to be decoded.

[0233] Let e ​​represent ρ failed symbols, and ce represent n-ρ non-failed symbols. This represents a submatrix of order r×(N-ρ) from H, where the (N-ρ) columns include all columns except those corresponding to the ρ failure symbols. The second corrector... Failure symbol It can be seen that the check symbol can be passed get.

[0234] In one possible implementation, a second set of equations is obtained based on the second corrector and the second Vandermonde matrix to determine the ρ reconstructed symbols of the ρ failed symbols; the second Vandermonde matrix is ​​a matrix of order ρ×ρ in the check matrix, where the ρ rows of the ρ×ρ matrix include the first ρ rows of the check matrix, and the ρ columns of the ρ×ρ matrix include the columns in the check matrix related to the ρ failed symbols; the calculation of the second set of equations is performed to obtain the ρ reconstructed symbols of the ρ failed symbols.

[0235] When ρ = r, the second Vandermonde matrix H e It is an r×ρ submatrix of the verification matrix H, where the ρ columns include the columns in H corresponding to the failure symbols.

[0236] When ρ < r, the second Vandermonde matrix H e Let H be a ρ×ρ submatrix of the verification matrix H, where ρ rows are the first ρ rows of H and ρ columns are the columns in H that correspond to the failure symbols.

[0237] The second set of equations is a linear system.

[0238] In this implementation, the unknowns in the second set of equations are the verification symbols. By solving the second set of equations, the ρ reconstructed symbols of the ρ failed symbols can be obtained directly.

[0239] In one possible implementation, the calculation of the second set of equations is performed to obtain ρ reconstructed symbols of ρ failed symbols, including: decomposing the second Vandermonde matrix in the second set of equations into at least one upper triangular matrix and at least one lower triangular matrix to obtain the second preprocessing set of equations; and performing the calculation of the second preprocessing set of equations to obtain ρ reconstructed symbols of ρ failed symbols.

[0240] In this embodiment of the application, the method used to calculate the second preprocessing equation set is the same as the method used to calculate the first preprocessing equation set.

[0241] In this implementation, the special structure of the upper triangular matrix and the lower triangular matrix simplifies matrix operations (such as finding the determinant and the inverse matrix), thereby reducing the computational complexity of the second preprocessing equation set and improving the efficiency of obtaining ρ reconstructed symbols.

[0242] In one possible implementation, if ρ < r, the value of ρ is updated to be equal to the value of r. That is, when acquiring the data to be decoded, the first r-ρ non-expired symbols are not acquired.

[0243] In this implementation, since the maximum number of recoverable failed symbols during the decoding process is equal to the number of check symbols, when ρ < r, the first r-ρ unfailed symbols of the data to be decoded can be omitted. Instead, these unfailed symbols and the ρ failed symbols can be combined to form r failed symbols. Subsequently, the r reconstructed data symbols of the r failed symbols can be obtained by solving the second set of equations, thus reducing the amount of data that needs to be acquired.

[0244] In this embodiment, by calculating ρ second elements in the second corrector based on the check sub-matrix of the check matrix and the data group associated with the check sub-matrix in the unfailed symbols, the computing device can automatically calculate the second corrector. Furthermore, this second corrector can be used to generate ρ reconstructed symbols from ρ failed symbols of the decoded data, where ρ ≤ r, and r is the number of check symbols, enabling the data decoding method provided in this embodiment to recover reconstructed symbols from a number of failed symbols less than or equal to the number of check symbols. In the process of calculating the ρ second elements of the second corrector, the second intermediate calculation result obtained in determining the second sub-element when l < the target number can be reused, and combined with the second sub-element associated with the (h+1)th check sub-matrix in the lth first element when l ≥ the target number, the target second sub-element when l ≥ the target number is obtained. Thus, the computational complexity of the second elements in the second corrector is reduced when l ≥ the target number, improving the computational efficiency of the second corrector and the overall processing efficiency of the data decoding process.

[0245] In one embodiment, the method shown in S401-S403 is applied to a data decoding system, as shown in FIG11. The data decoding system includes M registers, and the second data group includes a third sub-data and a fourth sub-data. The u-th register among the M registers is used to store the third intermediate data, which is determined based on the third sub-data and the fourth intermediate data. The s-th register among the M registers is used to store the fourth intermediate data, which is determined based on the fourth sub-data.

[0246] In method (3), determining the target second sub-element based on the second data group and the h-th check sub-matrix may include:

[0247] S501. Store the data in the second data group into M registers.

[0248] In this embodiment, the specific description of storing the data in the second data group into M registers can be referred to the specific description of storing the data in the first data group into M registers.

[0249] S502. If the third sub-data has been stored in the u-th register, update the third intermediate data in the u-th register.

[0250] Before the third sub-data has been stored in the w-th register, the w-th register may or may not contain the third intermediate data, or it may contain some initial third intermediate data.

[0251] If the third intermediate data is not stored in the u-th register, the computation required to update the third intermediate data in the u-th register is computation S. i,j The calculations related to the third sub-data during the process of ′.

[0252] Given that the u-th register stores some initial third intermediate data, the computation required to update the third intermediate data in the u-th register is computation S. i,j The calculations related to the third sub-data and the initial third intermediate data during the process of ′.

[0253] S503. If the fourth sub-data has been stored in the s-th register, update the fourth intermediate data in the s-th register.

[0254] Similarly, before the fourth sub-data is stored in the s-th register, and before the fourth intermediate data is stored in the s-th register, the calculation required to update the fourth intermediate data in the s-th register is to calculate S. i,j The calculations related to the fourth sub-data during the process; given that some initial fourth intermediate data is stored in the s-th register, the calculation required to update the fourth intermediate data in the s-th register is the calculation S. i,j The calculations related to the fourth sub-data and the initial fourth intermediate data during the process of ′.

[0255] S504. Based on the fourth intermediate data in the updated s-th register and the third intermediate data in the updated u-th register, update the third intermediate data in the u-th register again.

[0256] In some implementations, steps S202-S204 are performed at least once during the determination of the target second sub-element, until the third intermediate data in the u-th register is updated to S again after the at least one execution. i,j ′ or includes all data that is expected to be stored in all u-th registers.

[0257] The calculations for updating the third intermediate data in the u-th register and the fourth intermediate data in the s-th register in S502-S504 can be referred to in S202-S204, and will not be elaborated further.

[0258] S505. Determine the target fourth sub-element based on the third intermediate data in the u-th register after the second update.

[0259] Based on the third intermediate data in the u-th register after the second update, calculate the third intermediate data in the u-th register after the second update and (x+μ) j ) i Multiplication and S i,j+1 The addition yields the second element of the target.

[0260] In the application embodiment, multiple registers are used to store the data (including third and fourth intermediate data) required in the calculation of the target second sub-element. This provides storage space for intermediate calculation results during the calculation of the target second sub-element, reducing the access latency of storing it in memory and improving the processing efficiency of the data storage system. In the calculation of the target second sub-element, the third intermediate data in the u-th register is first updated based on the third sub-data. Then, after the fourth intermediate data in the s-th register has been updated based on the fourth sub-data, the third intermediate data in the w-th register is updated again based on the updated fourth intermediate data in the s-th register, thus obtaining the target second sub-element. This achieves incremental calculation, meaning that the intermediate data in the corresponding register is updated immediately after each sub-data is stored, without waiting for both the third and fourth sub-data to be stored in the u-th register. The target second sub-element is then obtained by updating the third intermediate data in the u-th register all at once, avoiding update waiting time (e.g., the time spent waiting for the fourth sub-data to be stored in the u-th register after storing the third sub-data), thus improving the processing efficiency of the data decoding system.

[0261] For ease of understanding, as an example, an example of a decoding method is described below. Please refer to Figure 12, which is a flowchart illustrating another decoding method provided in an embodiment of this application. As shown in Figure 12, the method includes S601-S604:

[0262] S601, Read data from an undamaged disk.

[0263] Among them, the non-failed disk is used to store non-failed symbols, and one non-failed disk stores one non-failed symbol. Figure 12 shows four non-failed disks (non-failed disk one, non-failed disk two, non-failed disk three and non-failed disk four).

[0264] S602. The second corrector is obtained using the improved RM transformation method.

[0265] S603. Solve the second set of equations using LU decomposition to obtain ρ reconstructed symbols from ρ failed symbols.

[0266] S604. Write ρ reconstruction symbols to the failure disk.

[0267] Among them, the failure disk is used to store the failure symbol before failure and the reconstruction symbol after recovery. One non-failure disk stores one reconstruction symbol. Figure 12 shows three non-failure disks (failure disk one, failure disk two and failure disk three).

[0268] The implementation of S601-S604 can refer to the specific description of S401-S403, and can achieve the same or similar beneficial effects.

[0269] Please refer to Figure 13, which is a schematic diagram of a magnetoelectric disk storage system. The data encoding method provided in the embodiments of this application described in detail above with reference to Figures 4, 6 and 9, and the data decoding method provided in the embodiments of this application described in detail above with reference to Figures 10 to 12, can both be applied to the magnetoelectric disk storage system shown in Figure 13.

[0270] During the process of burning raw data to disk using the magnetoelectric disk data storage system shown in Figure 13, the disk storage array includes at least n disks, and the raw data is divided into k data blocks (m0,…,m). k-1 Using the data encoding method described in detail in Figures 4, 6, and 9, k data blocks are encoded, resulting in r = nk redundant blocks (p0, ..., p...). t-1 The k data blocks and r redundant blocks are stored in n disks respectively. The r redundant blocks can accommodate any r disk failures. That is, if any r disks fail, the failed data can be correctly decoded from the data in the other k = nr disks that have not failed. The decoding process is implemented by the data decoding method described in detail in Figures 10 to 12.

[0271] Figure 13 illustrates, for example, the three storage devices included in the storage array of the magnetoelectric disk storage system.

[0272] It is understood that, in order to achieve the functions in the above embodiments, the computing device includes hardware structures and / or software modules corresponding to the execution of each function. Those skilled in the art should readily recognize that, based on the units and method steps described in conjunction with the embodiments disclosed in this application, this application can be implemented in hardware or a combination of hardware and computer software. Whether a function is executed in hardware or by computer software driving hardware depends on the specific application scenario and design constraints of the technical solution.

[0273] The data encoding method provided according to the embodiments of this application has been described in detail above with reference to Figures 4 to 9. The data encoding apparatus provided according to this application will now be described with reference to Figure 14. These apparatuses can be used to implement the functions of the processor in the above method embodiments, and therefore can also achieve the beneficial effects of the above method embodiments.

[0274] As shown in Figure 14, the data encoding device includes a first acquisition module 1101, a first corrector generation module 1102, and an encoding module 1103.

[0275] The first acquisition module 1101 is used to acquire the data to be encoded. For a more detailed description of the step / process implemented by the first acquisition module 1101, please refer to S101 in Figure 4 and its related description.

[0276] The first corrector generation module 1102 is used to perform first corrector calculation based on the data to be encoded and the parity check matrix to obtain a first corrector for generating parity symbols for the data to be encoded. The parity check matrix includes N parity check matrices, where N is a positive integer, and the N parity check matrices are divided according to the target codeword length. The first corrector includes r first elements, where r is the preset number of parity symbols. Each first element includes N first sub-elements associated with the parity check matrices respectively. During the first corrector calculation, for the target first sub-element associated with the j-th parity check matrix in the i-th first element:

[0277] When i < target quantity, the first target sub-element is determined based on the first data group and the j-th check sub-matrix; the first data group is the data group in the data to be encoded that is associated with the j-th check sub-matrix;

[0278] When i ≥ the target number, the target first element is determined based on the first intermediate calculation result and the first sub-element associated with the (j+1)th check sub-matrix in the i-th first element; the first intermediate calculation result is the intermediate calculation result obtained in the process of calculating the first sub-element associated with the j-th check sub-matrix in the z-th first element, where z is the remainder of i divided by the target number.

[0279] For a more detailed description of the step / process implemented by the first corrector generation module 1102, please refer to S102 and its related description in Figure 4.

[0280] Encoding module 1103 is used to generate r check symbols for the data to be encoded based on the first corrector. The i-th check symbol among the r check symbols is related to the i-th first element in the first corrector. The r check symbols are used to generate the encoded codewords for the data to be encoded, and the codeword length is the target codeword length. For a more detailed description of this step / process implemented by encoding module 1103, please refer to S103 in Figure 4 and its related description.

[0281] In one possible implementation, the first data group includes first sub-data and second sub-data; the w-th register of the M registers is used to store first intermediate data, which is determined based on the first sub-data and the second intermediate data; the g-th register of the M registers is used to store second intermediate data, which is determined based on the second sub-data; the first corrector generation module 1102 is further configured to: store data in the first data group into the M registers; update the first intermediate data in the w-th register when the first sub-data has been stored in the w-th register; update the second intermediate data in the g-th register when the second sub-data has been stored in the g-th register; update the first intermediate data in the w-th register again based on the updated second intermediate data in the g-th register and the updated first intermediate data in the w-th register; and determine the target first sub-element based on the updated first intermediate data in the w-th register. For a more detailed description of this step / process implemented by the first corrector generation module 1102, please refer to S201-S205 in Figure 6 and its related description.

[0282] In one possible implementation, if r ≤ the first quantity, M equals the first quantity; if the first quantity < r < the second quantity, M equals the sum of r and the preset quantity; if r ≥ the second quantity, M equals the third quantity; the first quantity is less than the second quantity; the second quantity is less than or equal to the third quantity.

[0283] In one possible implementation, the verification matrix is ​​determined based on a target finite field, where the target finite field is F. 16 [x] / (1+αx+x 2 ), where / represents the modular operation, and α is the finite field F 16 =F2[α] / (1+α+α) 2 +α 3 +α 4 The elements in ) are variables, where x is a variable.

[0284] In one possible implementation, the target number is 15.

[0285] In one possible implementation, the encoding module 1103 is further configured to obtain a first set of equations for determining r check symbols based on the first corrector and the first Vandermonde matrix; the first Vandermonde matrix is ​​obtained based on the r×r order of the check matrix; and the calculation of the first set of equations is performed to obtain r check symbols.

[0286] In one possible implementation, the encoding module 1103 is further configured to decompose the first Vandermonde matrix in the first equation set into at least one upper triangular matrix and at least one lower triangular matrix to obtain the first preprocessed equation set; and to perform the calculation of the first preprocessed equation set to obtain r check symbols.

[0287] The data decoding method provided according to the embodiments of this application has been described in detail above with reference to Figures 10 to 12. The data decoding apparatus provided according to this application will now be described with reference to Figure 15. These apparatuses can be used to implement the functions of the processor in the above method embodiments, and therefore can also achieve the beneficial effects of the above method embodiments.

[0288] As shown in Figure 15, the data decoding device includes a second acquisition module 1201, a second corrector generation module 1202, and a decoding module 1203.

[0289] The second acquisition module 1201 is used to acquire the data to be decoded, which includes ρ failed symbols and non-failed symbols.

[0290] For a more detailed description of the step / process implemented by the second acquisition module 1201, please refer to S401 and its related description in Figure 10.

[0291] The second corrector generation module 1202 is used to perform second corrector calculation based on the data to be decoded and the parity check matrix to obtain a second corrector for generating ρ reconstructed symbols for ρ failed symbols. The parity check matrix includes N parity check matrices, where N is a positive integer, and the N parity check matrices are divided based on the target codeword length. The second corrector includes ρ second elements, where ρ≤r, and r is the number of parity symbols. Each second element includes N second sub-elements associated with the N parity check matrices respectively. During the second corrector calculation, for the target second sub-element associated with the h-th parity check matrix in the l-th second element:

[0292] When l < target quantity, the target second sub-element is determined based on the second data group and the h-th check sub-matrix; the second data group is the data group associated with the h-th check sub-matrix among the non-failed symbols.

[0293] When l ≥ the target number, the target second sub-element is determined based on the second intermediate calculation result and the second sub-element associated with the (h+1)th check sub-matrix in the lth second element; the second intermediate calculation result is the intermediate calculation result obtained in the process of calculating the second sub-element associated with the hth check sub-matrix in the mth second element, where m is the remainder of l divided by the target number.

[0294] For a more detailed description of the step / process implemented by the second corrector generation module 1202, please refer to S402 and its related description in Figure 10.

[0295] Decoding module 1203 is used to generate ρ reconstructed symbols from ρ failed symbols based on the second corrector; wherein the l-th reconstructed symbol among the ρ reconstructed symbols is related to the l-th second element in the second corrector, and the ρ reconstructed symbols are used to obtain the decoded data of the data to be decoded. For a more detailed description of this step / process implemented by decoding module 1203, please refer to S403 in Figure 10 and its related description.

[0296] In one possible implementation, the data decoding system includes M registers, and the second data group includes third sub-data and fourth sub-data; the u-th register among the M registers is used to store third intermediate data, which is determined based on the third sub-data and the fourth intermediate data; the s-th register among the M registers is used to store fourth intermediate data, which is determined based on the fourth sub-data; the second corrector generation module 1202 is further used to store data in the second data group into the M registers; when the third sub-data has been stored in the u-th register, update the third intermediate data in the u-th register; when the fourth sub-data has been stored in the s-th register, update the fourth intermediate data in the s-th register; based on the updated fourth intermediate data in the s-th register and the updated third intermediate data in the u-th register, update the third intermediate data in the u-th register again; and determine the target second sub-element based on the updated third intermediate data in the u-th register.

[0297] For a more detailed description of the step / process implemented by the second corrector generation module 1202, please refer to S501-S505 in Figure 11 and their related descriptions.

[0298] In one possible implementation, if ρ < r, update the value of ρ to be equal to the value of r.

[0299] In one possible implementation, the decoding module 1203 is further configured to obtain a second set of equations for determining ρ reconstructed symbols of ρ failed symbols based on the second corrector and the second VanderMonde matrix; the second VanderMonde matrix is ​​a matrix of order ρ×ρ in the parity check matrix, wherein the ρ rows of the ρ×ρ order include the first ρ rows of the parity check matrix, and the ρ columns of the ρ×ρ order include the columns in the parity check matrix related to the ρ failed symbols; the calculation of the second set of equations is performed to obtain the ρ reconstructed symbols of the ρ failed symbols.

[0300] In one possible implementation, the decoding module 1203 is further configured to decompose the second Vandermonde matrix in the second equation set into at least one upper triangular matrix and at least one lower triangular matrix to obtain the second preprocessed equation set; and to perform the calculation of the second preprocessed equation set to obtain ρ reconstructed symbols of ρ failed symbols.

[0301] The devices can be implemented in software or hardware. For example, the implementation of a data encoding device will be described below.

[0302] As an example of a software functional unit, a data encoding device can include code running on a computing instance. This computing instance can be at least one of a physical host (computing device), a virtual machine, a container, or other computing devices. Furthermore, the aforementioned computing devices can be one or more. For example, the data encoding device can include code running on multiple hosts / virtual machines / containers. It should be noted that the multiple hosts / virtual machines / containers used to run the application can be distributed within the same region or in different regions. The multiple hosts / virtual machines / containers used to run the code can be distributed within the same Availability Zone (AZ) or in different AZs, each AZ including one or more geographically proximate data centers. Typically, a region can include multiple AZs.

[0303] Similarly, multiple hosts / virtual machines / containers used to run this code can be distributed within the same VPC or across multiple VPCs. Typically, a VPC is set up within a single region. Communication between two VPCs within the same region, and between VPCs in different regions, requires a communication gateway to be set up within each VPC to enable interconnection between VPCs.

[0304] As an example of a hardware functional unit, a data encoding device may include at least one computing device, such as a server. Alternatively, the data encoding device may be a device implemented using an ASIC or a PLD. The aforementioned PLD may be implemented using a CPLD, FPGA, GAL, or any combination thereof.

[0305] The data encoding device comprises multiple computing devices that can be distributed within the same region or in different regions. Similarly, the data encoding device comprises multiple computing devices that can be distributed within the same Availability Zone (AZ) or in different AZs. Likewise, the YY device comprises multiple computing devices that can be distributed within the same Virtual Private Cloud (VPC) or in multiple VPCs. These multiple computing devices can be any combination of computing devices such as servers, ASICs, PLDs, CPLDs, FPGAs, and GALs.

[0306] Similarly, a data decoding device can be implemented based on the above-described implementation method of the data encoding device.

[0307] This application also provides a computing device 800. As shown in FIG16, the computing device 800 includes: a bus 802, a processor 804, a memory 806, and a communication interface 808. The processor 804, the memory 806, and the communication interface 808 communicate with each other via the bus 802. The computing device 800 can be a server or a terminal device. It should be understood that this application does not limit the number of processors and memories in the computing device 800. Optionally, the processor 804 of the computing device 800 can be connected to a display or input device through the communication interface 808.

[0308] Bus 802 can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. Buses can be categorized as address buses, data buses, control buses, etc. For ease of illustration, only one line is used in Figure 16, but this does not imply that there is only one bus or one type of bus. Bus 802 can include pathways for transmitting information between various components of computing device 800 (e.g., memory 806, processor 804, communication interface 808).

[0309] Processor 804 may include any one or more processors such as a central processing unit (CPU), a graphics processing unit (GPU), a microprocessor (MP), or a digital signal processor (DSP). In this embodiment, processor 804 is used to execute the steps or operations of the data encoding method provided in Figures 2 to 6 of this embodiment.

[0310] The memory 806 may include volatile memory, such as random access memory (RAM). The processor 804 may also include non-volatile memory, such as read-only memory (ROM), flash memory, hard disk drive (HDD), or solid state drive (SSD).

[0311] The memory 806 stores executable program code, and the processor 804 executes the executable program code to implement the functions of the aforementioned first acquisition module 1101, first corrector generation module 1102, and encoding module 1103, and / or the second acquisition module 1201, second corrector generation module 1202, and decoding module 1203, thereby implementing the data encoding method provided in Figures 4 to 9 of this application embodiment, and / or the data decoding method provided in Figures 10 to 12 of this application embodiment. That is, the memory 806 stores instructions for executing the data encoding method provided in Figures 4 to 9 of this application embodiment, and / or instructions for executing the data decoding method provided in Figures 10 to 12 of this application embodiment.

[0312] The communication interface 808 uses transceiver modules such as, but not limited to, network interface cards and transceivers to enable communication between the computing device 800 and other devices or communication networks.

[0313] The display can include various display devices that can perform display functions, such as plasma displays and liquid crystal displays. The computing device 800 can perform data display functions through the display.

[0314] Input devices can include various input devices such as keyboards, mice, and touch screens that enable user input.

[0315] This application also provides a chip system. The chip system may include a processor and a power supply circuit. The power supply circuit is used to supply power to the processor, and the processor is used to execute the steps or operations of the data encoding method provided in Figures 4 to 9 of this application and / or the data decoding method provided in Figures 10 to 12 of this application.

[0316] This application also provides a computer program product containing instructions. The computer program product may be a software or program product containing instructions, capable of running on a computing device or stored on any usable medium. When the computer program product runs on at least one computing device, it causes the at least one computing device to perform the steps or operations of the data encoding method provided in Figures 4 to 9 of this application and / or the data decoding method provided in Figures 10 to 12 of this application, for example, instructions for performing the steps or operations of the data encoding method provided in Figures 4 to 9 of this application and / or the data decoding method provided in Figures 10 to 12 of this application.

[0317] This application also provides a computer-readable storage medium. The computer-readable storage medium can be any available medium that a computing device can store, or a data storage device such as a data center containing one or more available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid-state drive). The computer-readable storage medium includes instructions that instruct a computing device to perform the steps or operations of the data encoding method provided in Figures 4 to 9 of this application and / or the data decoding method provided in Figures 10 to 12 of this application, for example, instructions for performing the steps or operations of the data encoding method provided in Figures 4 to 9 of this application and / or the data decoding method provided in Figures 10 to 12 of this application.

[0318] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the protection scope of the technical solutions of the embodiments of this application.

[0319] The terms “first,” “second,” “third,” and “fourth,” etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish different objects, not to define a specific order.

[0320] In the embodiments of this application, the terms "exemplary" or "for example" are used to indicate that something is an example, illustration, or description. Any embodiment or design that is described as "exemplary" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design. Specifically, the use of the terms "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

Claims

1. A data encoding method characterized by, include: Obtain the data to be encoded; Based on the data to be encoded and the parity check matrix, a first corrector calculation is performed to obtain a first corrector used to generate the parity symbols for the data to be encoded. The parity check matrix includes N parity sub-matrices, where N is a positive integer. The N parity sub-matrices are divided according to the target codeword length. The first corrector includes r first elements, where r is the preset number of the parity symbols. Each first element includes N first sub-elements associated with the parity sub-matrices respectively. During the first corrector calculation, for the target first sub-element associated with the j-th parity sub-matrix in the i-th first element: When i < target quantity, the target first sub-element is determined based on the first data group and the j-th check sub-matrix; the first data group is the data group in the data to be encoded that is associated with the j-th check sub-matrix; When i ≥ target quantity, the target first sub-element is determined based on the first intermediate calculation result and the first sub-element in the i-th first element that is associated with the (j+1)-th verification sub-matrix; The first intermediate calculation result is the intermediate calculation result obtained in the process of calculating the first sub-element associated with the j-th verification sub-matrix in the z-th first element, where z is the remainder of i divided by the target number; Based on the first corrector, r check symbols are generated for the data to be encoded, wherein the i-th check symbol among the r check symbols is related to the i-th first element in the first corrector, and the r check symbols are used to generate the encoded codeword of the data to be encoded, wherein the codeword length of the encoded codeword is the target codeword length.

2. The method of claim 1, wherein, The data encoding system includes M registers, and the first data group includes a first sub-data and a second sub-data. The w-th register among the M registers is used to store first intermediate data, which is determined based on the first sub-data and the second intermediate data; the g-th register among the M registers is used to store second intermediate data, which is determined based on the second sub-data. Determining the target first sub-element based on the first data group and the j-th verification sub-matrix includes: The data in the first data group is stored in the M registers; If the first sub-data has been stored in the w-th register, update the first intermediate data in the w-th register; If the second sub-data has been stored in the g-th register, update the second intermediate data in the g-th register; Based on the updated second intermediate data in the g-th register and the updated first intermediate data in the w-th register, the first intermediate data in the w-th register is updated again; The target first sub-element is determined based on the first intermediate data in the w-th register after the update.

3. The method of claim 2, wherein, If r ≤ the first quantity, M equals the first quantity; if the first quantity < r < the second quantity, M equals the sum of r and the preset quantity; if r ≥ the second quantity, M equals the third quantity; the first quantity is less than the second quantity; the second quantity is less than or equal to the third quantity.

4. The method according to any one of claims 1-3, characterized in that, The check matrix is determined based on a target finite field F 16 [x] / (1+αx+x 2 ), where / denotes modulo operation, α is an element in a finite field F 16 = F2[α] / (1+α+α 2 +α 3 +α 4 ), x is a variable.

5. The method according to any one of claims 1-4, characterized in that, The target quantity is 15.

6. The method according to any one of claims 1 to 5, characterized in that, The step of generating r check symbols for the data to be encoded based on the first corrector includes: Based on the first corrector and the first Vandermonde matrix, a first set of equations is obtained to determine the r check symbols; the first Vandermonde matrix is ​​obtained based on the r×r order of the check matrix. Executing the calculation of the first set of equations yields r check symbols.

7. The method of claim 6, wherein, The calculation of the first set of equations yields r check symbols, including: The first Vandermonde matrix in the first set of equations is decomposed into at least one upper triangular matrix and at least one lower triangular matrix to obtain the first preprocessed set of equations. The calculation of the first preprocessed equation set is performed to obtain r verification symbols.

8. A data decoding method characterized by comprising: include: Acquire the data to be decoded, which includes ρ failed symbols and non-failed symbols; Based on the data to be decoded and the parity check matrix, a second corrector calculation is performed to obtain a second corrector for generating ρ reconstructed symbols for the ρ failed symbols; the parity check matrix includes N parity check sub-matrices, where N is a positive integer, and the N parity check sub-matrices are divided according to the target codeword length; the second corrector includes ρ second elements, where ρ≤r, and r is the number of parity symbols; each second element includes N second sub-elements associated with the N parity check sub-matrices respectively; during the second corrector calculation, for the target second sub-element associated with the h-th parity check matrix in the l-th second element: When l < target quantity, the target second sub-element is determined based on the second data group and the h-th check sub-matrix; the second data group is the data group among the non-failed symbols associated with the h-th check sub-matrix; When l ≥ the target number, the target second sub-element is determined based on the second intermediate calculation result and the second sub-element in the lth second element that is associated with the (h+1)th verification sub-matrix; The second intermediate calculation result is the intermediate calculation result obtained in the process of calculating the second sub-element associated with the h-th verification sub-matrix in the m-th second element, where m is the remainder of l divided by the target number; Based on the second corrector, ρ reconstructed symbols are generated from the ρ failed symbols; wherein, the l-th reconstructed symbol among the ρ reconstructed symbols is related to the l-th second element in the second corrector, and the ρ reconstructed symbols are used to obtain the decoded data of the data to be decoded.

9. The method of claim 8, wherein, The data decoding system includes M registers, and the second data group includes a third sub-data and a fourth sub-data; The u-th register among the M registers is used to store the third intermediate data, which is determined based on the third sub-data and the fourth intermediate data; the s-th register among the M registers is used to store the fourth intermediate data, which is determined based on the fourth sub-data. Determining the target second sub-element based on the second data group and the h-th verification sub-matrix includes: The data in the second data group is stored in the M registers; If the third sub-data has been stored in the u-th register, update the third intermediate data in the u-th register; If the fourth sub-data has been stored in the s-th register, update the fourth intermediate data in the s-th register; Based on the fourth intermediate data in the updated s-th register and the third intermediate data in the updated u-th register, the third intermediate data in the u-th register is updated again; The target second sub-element is determined based on the third intermediate data in the u-th register after the update.

10. The method according to claim 8 or 9, characterized in that, If ρ < r, update the value of ρ to be equal to the value of r.

11. The method according to any one of claims 8-10, characterized in that, The step of generating ρ reconstructed symbols from the ρ failed symbols based on the second corrector includes: Based on the second corrector and the second Vandermonde matrix, a second set of equations is obtained to determine the ρ reconstructed symbols of the ρ failed symbols; the second Vandermonde matrix is ​​a matrix of order ρ×ρ in the verification matrix, wherein the ρ rows of the ρ×ρ matrix include the first ρ rows of the verification matrix, and the ρ columns of the ρ×ρ matrix include the columns of the verification matrix related to the ρ failed symbols. The calculation of the second set of equations is performed to obtain the ρ reconstructed symbols of the ρ failed symbols.

12. The method of claim 11, wherein, The calculation of the second set of equations yields ρ reconstructed symbols from the ρ failed symbols, including: The second Vandermond matrix in the second system of equations is decomposed into at least one upper triangular matrix and at least one lower triangular matrix to obtain the second preprocessed system of equations. The calculation of the second preprocessing equation set is performed to obtain the ρ reconstructed symbols of the ρ failed symbols.

13. A data encoding apparatus characterized by comprising: include: The first acquisition module is used to acquire the data to be encoded. The first corrector generation module is used to perform a first corrector calculation based on the data to be encoded and the parity check matrix to obtain a first corrector for generating parity symbols for the data to be encoded. The parity check matrix includes N parity check sub-matrices, where N is a positive integer. The N parity check sub-matrices are divided according to the target codeword length. The first corrector includes r first elements, where r is the preset number of parity symbols. Each first element includes N first sub-elements associated with the N parity check sub-matrices respectively. During the execution of the first corrector calculation, for the target first sub-element associated with the j-th parity check matrix in the i-th first element: When i < target quantity, the target first sub-element is determined based on the first data group and the j-th check sub-matrix; the first data group is the data group in the data to be encoded that is associated with the j-th check sub-matrix; When i ≥ target quantity, the target first sub-element is determined based on the first intermediate calculation result and the first sub-element in the i-th first element that is associated with the (j+1)-th verification sub-matrix; The first intermediate calculation result is the intermediate calculation result obtained in the process of calculating the first sub-element associated with the j-th verification sub-matrix in the z-th first element, where z is the remainder of i divided by the target number; The encoding module is used to generate r check symbols of the data to be encoded based on the first corrector, wherein the i-th check symbol among the r check symbols is related to the i-th first element in the first corrector, and the r check symbols are used to generate the encoded codeword of the data to be encoded, wherein the codeword length of the encoded codeword is the target codeword length.

14. A data decoding apparatus characterized by comprising: include: The second acquisition module is used to acquire the data to be decoded, which includes ρ failed symbols and non-failed symbols. The second corrector generation module is used to perform a second corrector calculation based on the data to be decoded and the parity check matrix to obtain a second corrector for generating ρ reconstructed symbols for the ρ failed symbols; the parity check matrix includes N parity check matrices, where N is a positive integer, and the N parity check matrices are divided according to the target codeword length; the second corrector includes ρ second elements, where ρ≤r, and r is the number of parity symbols; each second element includes N second sub-elements associated with the N parity check matrices respectively; during the execution of the second corrector calculation, for the target second sub-element associated with the h-th parity check matrix in the l-th second element: When l < target quantity, the target second sub-element is determined based on the second data group and the h-th check sub-matrix; the second data group is the data group among the non-failed symbols associated with the h-th check sub-matrix; When l ≥ the target number, the target second sub-element is determined based on the second intermediate calculation result and the second sub-element in the lth second element that is associated with the (h+1)th verification sub-matrix; The second intermediate calculation result is the intermediate calculation result obtained in the process of calculating the second sub-element associated with the h-th verification sub-matrix in the m-th second element, where m is the remainder of l divided by the target number; The decoding module is used to generate p reconstructed symbols of the p failed symbols based on the second corrector; wherein the l-th reconstructed symbol of the p reconstructed symbols is related to the l-th second element in the second corrector, and the p reconstructed symbols are used to obtain the decoded data of the data to be decoded.

15. A data coding system characterized by The system includes an encoder and a decoder, wherein the encoder is used to perform the method of any one of claims 1-7, and the decoder is used to perform the method of any one of claims 8-12.

16. A computing device, comprising: The computing device includes a processor and a memory; the processor is configured to execute instructions stored in the memory to cause the computing device to perform the method as claimed in any one of claims 1-7 or 8-12.

17. A computer program product comprising instructions, characterized in that, When the instructions are executed by at least one computing device, the at least one computing device performs the method as claimed in any one of claims 1-7 or 8-12.

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