Server booting method and apparatus, non-volatile computer-readable storage medium, and electronic device

Abstract

The present application discloses a server booting method and apparatus, a storage medium, and an electronic device. A processor, a channel controller, a memory, and a display are deployed on a server, and a basic input / output system is installed on the processor. The method is applied to the basic input / output system, and comprises: receiving a booting instruction; in response to the booting instruction, executing a startup operation for booting the server; generating a target interface of a target interface type when the startup operation is executed to a target startup stage; in the target startup stage, calling the target interface to acquire target booting information from the memory by means of a target channel of the channel controller; and controlling the display to display the target booting information thereon. By using the described technical solution, problems in the related art, such as low stability of displaying booting information by servers during booting processes, are solved, thereby achieving the technical effect of improving the stability of displaying booting information by servers during booting processes.

Description

Server power-on methods and devices, non-volatile computer-readable storage media and electronic devices

[0001] Cross-references to related applications

[0002] This application claims priority to Chinese Patent Application No. 202411611605.4, filed on November 12, 2024, entitled "Method and Apparatus for Powering On a Server, Storage Medium and Electronic Device", the entire contents of which are incorporated herein by reference. Technical Field

[0003] This application relates to the field of computers, and in particular to a method and apparatus for powering on a server, a non-volatile computer-readable storage medium, and an electronic device. Background Technology

[0004] In today's information age, servers, as the core equipment of data centers, are crucial to enterprise operations due to their stability and reliability.

[0005] In existing technologies, the process of a server obtaining special offer information before powering on typically involves the CPU (Central Processing Unit) sending an IPMI (Intelligent Platform Management Interface) command to the EEPROM (Electrically Erasable Programmable Read-Only Memory) via the BMC (Baseboard Management Controller). The BMC then reads the special offer information from the EEPROM and transmits it to the CPU, which then displays the information on the server screen. However, the feasibility of this method is highly dependent on the stability of the link between the CPU and the BMC. If the link malfunctions or the IPMI command fails to transmit correctly, the CPU cannot obtain the special offer information from the EEPROM, resulting in the inability to display this information correctly on the server screen. Furthermore, the interdependence between the CPU and the BMC can also affect the stability of the server.

[0006] There is still no effective solution to the problem of low stability in the display of boot information during the boot process of related technologies. Summary of the Invention

[0007] This application provides a server power-on method and apparatus, a non-volatile computer-readable storage medium and an electronic device, to at least solve the problem of low stability in the display of power-on information during the power-on process of the server in the related art.

[0008] According to one embodiment of this application, a method for powering on a server is provided. The server is equipped with a processor, a channel controller, a memory, and a display. The processor is connected to the memory via the channel controller and is also connected to the display. A basic input / output system is installed on the processor. The method is applied to the basic input / output system and includes:

[0009] Receive power-on command;

[0010] In response to the power-on command, execute the startup operation to boot the server;

[0011] If the startup operation reaches the target startup phase, a target interface of the target interface type is generated, wherein the target interface type is an interface type that the basic input / output system is allowed to call during the target startup phase;

[0012] During the target startup phase, the target interface is invoked to obtain target boot information from the memory through the target channel of the channel controller, wherein the target channel is configured to provide communication between the processor and the memory;

[0013] Control the display to show the target power-on information.

[0014] Optionally, the target interface for generating the target interface type includes:

[0015] In the basic input / output system, a target interface program is constructed, wherein the target interface program is configured to generate an interface of the target interface type;

[0016] The target interface of the target interface type is obtained by executing the target interface program.

[0017] Optionally, the step of calling the target interface to obtain target power-on information from the memory through the target channel of the channel controller includes:

[0018] The target channel is selected from multiple channels on the channel controller;

[0019] The target channel is invoked to retrieve the target power-on information from the memory;

[0020] Perform a temporary storage operation on the target boot information.

[0021] Optionally, the channel controller includes multiple sub-channel controllers connected in parallel, and each sub-channel controller includes at least one candidate channel among its multiple channels. The step of selecting the target channel from the multiple channels on the channel controller includes: selecting one candidate channel as the target channel from the multiple candidate channels corresponding to the multiple sub-channel controllers, and each of the remaining multiple candidate channels is configured to retrieve the target power-on information from the memory in place of the target channel when the target channel fails to work properly.

[0022] Optionally, performing a temporary storage operation on the target boot information includes:

[0023] An initial data structure for the target data type is constructed in the basic input / output system, wherein the data structure for the target data type is a data structure that can be recorded during the target startup phase;

[0024] The target boot information is stored in the initial data structure to obtain the target data structure.

[0025] Optionally, the step of constructing the initial data structure for the target data type in the basic input / output system includes:

[0026] In the case of the PEI phase initialization for the pre-expandable firmware interface during the target startup phase, an empty data structure that allows recording during the PEI phase is constructed in the basic input / output system; the empty data structure that allows recording during the PEI phase is determined as the initial data structure of the target data type.

[0027] Optionally, before displaying the target power-on information on the control display, the method further includes:

[0028] When the startup operation reaches the reference startup phase, the target data structure in the basic input / output system is obtained, wherein the basic input / output system in the reference startup phase is configured to load the operating system of the server before the server is powered on;

[0029] The target boot information is read from the target data structure.

[0030] Optionally, before receiving the power-on command, the method further includes:

[0031] Receive a reference storage instruction, wherein the reference storage instruction is used to instruct the storage of the server's boot information;

[0032] In response to the reference storage instruction, the storage location information of the memory is obtained from the target channel, wherein the storage location information is used to indicate the location of currently allowed information to be stored in the memory;

[0033] Construct a target storage instruction carrying the storage location information and the target power-on information, wherein the target storage instruction is used to instruct the memory to store the target power-on information to the location indicated by the storage location information;

[0034] The target storage instruction is sent to the memory through the target channel, wherein the target power-on information stored in the memory is used to be displayed on the display when the server is powered on again.

[0035] Optionally, before obtaining the storage location information of the memory from the target channel, the method further includes:

[0036] Generate a target switching instruction, wherein the target switching instruction is used to instruct the target channel in the channel controller to be switched to the open state;

[0037] Execute the target switching instruction.

[0038] Optionally, the generation of the target switching instruction includes:

[0039] Obtain the controller address of the channel controller, and the channel address of the target channel in the channel controller;

[0040] The controller address and the channel address are added to the initial switching instruction to obtain the target switching instruction.

[0041] Optionally, obtaining the controller address of the channel controller and the channel address of the target channel in the channel controller includes:

[0042] The processor obtains the controller address of the channel controller and the channel address of the target channel in the channel controller through the integrated circuit bus I2C tool.

[0043] Optionally, obtaining the controller address of the channel controller includes:

[0044] Generate a target acquisition instruction, wherein the target acquisition instruction is used to acquire the address of the device connected to the processor;

[0045] Execute the target acquisition command.

[0046] Optionally, obtaining the storage location information of the memory from the target channel includes:

[0047] Generate a target lookup instruction, wherein the target lookup instruction is used to find the address of the device connected to the target channel of the channel controller;

[0048] Execute the target search instruction and determine the found address as the storage location information.

[0049] Optionally, executing the target search instruction and determining the found address as the storage location information includes:

[0050] The target lookup instruction is executed to find the address of the area in the memory region of the memory connected to the target channel that stores the target boot information, and at the same time, it is checked whether the memory has been successfully accessed.

[0051] If successful access to the memory is detected, the address found by the target lookup instruction is determined as the storage location information.

[0052] Optionally, the construction of the target storage instruction carrying the storage location information and the target boot information includes:

[0053] Get the initial storage instruction;

[0054] Collect the memory address of the memory;

[0055] The first add position is located from the initial storage instruction, wherein the first add position is the position preceding the operation type character in the initial storage instruction, and the operation type character is a character used to indicate the execution of a write operation;

[0056] The memory address is added to the first add position in the initial storage instruction to obtain a first storage instruction, wherein the first storage instruction is used to instruct information to be written to the memory;

[0057] The second addition position is located from the first storage instruction, wherein the second addition position is the position between the operation type character and the memory address in the first storage instruction;

[0058] The storage location information is added to the second add position in the first storage instruction to obtain a second storage instruction, wherein the second storage instruction is used to instruct information to be written to the position indicated by the storage location information in the memory;

[0059] The third addition position is located from the second storage instruction, wherein the third addition position is the position between the operation type character and the storage position information in the second storage instruction;

[0060] The target boot information is added to the third add position in the second storage instruction to obtain the target storage instruction, wherein the target storage instruction is used to instruct the target boot information to be written to the position indicated by the storage location information in the memory.

[0061] Optionally, the step of calling the target interface to obtain target power-on information from the memory through the target channel of the channel controller includes:

[0062] The target interface is invoked to retrieve special offer information from the memory through the target channel of the channel controller. The target power-on information includes the special offer information, which is used to indicate the information of the customer to which the server belongs.

[0063] According to another embodiment of the present application, a server power-on device is also provided. The server has a processor, a channel controller, a memory, and a display deployed on it. The processor is connected to the memory via the channel controller and is also connected to the display. A basic input / output system is installed on the processor. The device is applied to the basic input / output system and includes:

[0064] The first receiving module is configured to receive power-on commands;

[0065] The first response module is configured to respond to the power-on command and execute a startup operation to boot the server.

[0066] The first generation module is configured to generate a target interface of a target interface type when the startup operation reaches the target startup phase, wherein the target interface type is an interface type that the basic input / output system is allowed to call during the target startup phase;

[0067] The calling module is configured to, during the target startup phase, call the target interface to obtain target boot information from the memory through the target channel of the channel controller, wherein the target channel is used to provide communication between the processor and the memory;

[0068] The control module is configured to control the display to show the target power-on information.

[0069] According to yet another embodiment of this application, a computer program product is also provided, including a computer program that is executed by a processor using the steps of any of the above method embodiments.

[0070] According to yet another embodiment of this application, a computer-readable storage medium is also provided, wherein a computer program is stored therein, and the computer program is configured to perform the steps in any of the above method embodiments when it is run.

[0071] According to yet another embodiment of this application, an electronic device is also provided, including a memory and a processor, wherein the memory stores a computer program and the processor is configured to run the computer program to perform the steps in any of the above method embodiments.

[0072] This application proposes a server booting method. The server is equipped with a processor, a channel controller, a memory, and a display. The processor is connected to the memory via the channel controller and is also connected to the display. A basic input / output system (PIS) is installed on the processor. The PIS first receives a boot command, then responds to the boot command by executing a startup operation to guide the server to boot. Then, when the startup operation reaches the target boot stage, a target interface of a target interface type is generated. The target interface type can be any interface type allowed by the PIS during the target boot stage. Subsequently, during the target boot stage, the target interface is called to retrieve the target boot interface from the memory via the target channel of the channel controller. The target channel provides communication between the processor and memory. Finally, the target boot information is displayed on the control screen. This is achieved by generating a target interface of the type allowed by the Basic Input / Output System (BMC) during the target boot phase, and then using this target interface to retrieve the target boot information from memory through the target channel of the channel controller. This allows the BMC to directly access memory via the channel controller, independent of the stability of the link between the CPU and the BMC. Even if the link malfunctions or IPMI commands cannot be transmitted normally, the target boot information can still be retrieved normally, avoiding the delays and failures that may occur when indirectly reading the target boot information stored in memory through the BMC in related technologies. This technical solution solves the problem of low stability in displaying boot information during server boot in related technologies, achieving a significant improvement in the stability of boot information display during server boot. Attached Figure Description

[0073] Figure 1 is a hardware structure block diagram of a computer device for a server power-on method according to an embodiment of this application;

[0074] Figure 2 is a flowchart of a server power-on method according to an embodiment of this application;

[0075] Figure 3 is a deployment structure diagram of hardware devices on a server according to an embodiment of this application;

[0076] Figure 4 is a schematic diagram of a server startup operation according to an embodiment of this application;

[0077] Figure 5 is a flowchart of a method for reading target boot information before server boot according to an embodiment of this application;

[0078] Figure 6 is a flowchart of a method for writing target boot information before server boot according to an embodiment of this application;

[0079] Figure 7 is a schematic diagram of a server startup method according to an embodiment of this application;

[0080] Figure 8 is a structural block diagram of a server power-on device according to an embodiment of this application;

[0081] Figure 9 is a schematic diagram of an electronic device according to an embodiment of this application. Detailed Implementation

[0082] The embodiments of this application will be described in detail below with reference to the accompanying drawings and examples.

[0083] It should be noted that the terms "first," "second," etc., in the specification, claims, and drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0084] The methods and embodiments provided in this application can be executed in a server device or a similar computing device. Taking a server device as an example, FIG1 is a hardware structure block diagram of a computer device for a server power-on method according to an embodiment of this application. As shown in FIG1, the server device may include one or more (only one is shown in FIG1) processors 102 (processor 102 may include, but is not limited to, microprocessors MCU or programmable logic devices FPGA, etc.) and a memory 104 configured to store data. The server device may also include a transmission device 106 configured for communication and an input / output device 108. Those skilled in the art will understand that the structure shown in FIG1 is only illustrative and does not limit the structure of the server device. For example, the server device may also include more or fewer components than shown in FIG1, or have a different configuration than shown in FIG1.

[0085] The memory 104 may be configured to store computer programs, such as application software programs and modules, like the computer program corresponding to the server boot method in this embodiment. The processor 102 executes various functional applications and data processing by running the computer programs stored in the memory 104, thus implementing the aforementioned method. The memory 104 may include high-speed random access memory and non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory 104 may further include memory remotely located relative to the processor 102, and these remote memories can be connected to the server device via a network. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.

[0086] The transmission device 106 is configured to receive or transmit data via a network. Optional examples of the network may include a wireless network provided by the communication provider of the server device. In one example, the transmission device 106 includes a Network Interface Controller (NIC), which can connect to other network devices via a base station to communicate with the Internet. In another example, the transmission device 106 may be a Radio Frequency (RF) module configured to communicate wirelessly with the Internet.

[0087] This embodiment provides a method for powering on a server. Figure 2 is a flowchart of a server power-on method according to an embodiment of this application. As shown in Figure 2, a processor, a channel controller, a memory, and a display are deployed on the server. The processor is connected to the memory through the channel controller and is also connected to the display. A basic input / output system is installed on the processor. The method is applied to the basic input / output system, and the process includes the following steps:

[0088] Step S12: Receive power-on command;

[0089] Step S14: In response to the power-on command, execute the startup operation to boot the server;

[0090] Step S16: If the startup operation reaches the target startup stage, generate a target interface of the target interface type, wherein the target interface type is an interface type that the basic input / output system is allowed to call during the target startup stage;

[0091] Step S18: During the target startup phase, the target interface is invoked to obtain target power-on information from the memory through the target channel of the channel controller, wherein the target channel is configured to provide communication between the processor and the memory;

[0092] Step S110: Control the display to show the target power-on information.

[0093] Optionally, in this embodiment, Figure 3 is a deployment structure diagram of a hardware device on a server according to an embodiment of this application. As shown in Figure 3, the processor is connected to the memory through a channel controller and to the display. The processor is equipped with a basic input / output system. The processor may be, but is not limited to, a CPU (Central Processing Unit); the channel controller may be, but is not limited to, a hardware device that can provide data transmission and communication services to devices connected on both sides of its channel and supports the SMBus (System Management Bus) protocol, such as CA9548 (i.e., PCA9548); the memory may be, but is not limited to, non-volatile memory, such as EEPROM (Electrically Erasable Programmable Read-Only Memory); the display may be, but is not limited to, a device that can display boot information; and the basic input / output system may be, but is not limited to, a BIOS (Basic Input Output System) or UEFI (Unified Extensible Firmware Interface).

[0094] Optionally, in this embodiment, after receiving the power-on command, the basic input / output system responds to the command and performs the server power-on startup operation, which mainly includes the following four stages: SEC (Security) stage, PEI (Pre-EFI Initialization) stage, DXE (Driver Execution Environment) stage, and BDS (Boot Device Selection) stage.

[0095] Optionally, in this embodiment, when the startup operation reaches the target startup stage, a target interface of the target interface type is generated. The target interface type may be, but is not limited to, the interface type that the Basic Input / Output System (PIS) allows to call during the target startup stage. The target startup stage may be, but is not limited to, the stage where the operation to obtain target boot information needs to be performed. For example, if the operation to obtain target boot information needs to be performed during the PEI stage, then the target startup stage is the PEI stage. Correspondingly, if the interface type that the PIS allows to call during the PEI stage is PEI, then the target interface type is PEI, and the target interface is the PEI interface.

[0096] Optionally, in this embodiment, Figure 4 is a schematic diagram of a server startup operation according to an embodiment of this application. As shown in Figure 4, the channel controller CA9548 includes multiple channels, including CA9548 channel 1, CA9548 channel 2, and CA9548 channel 3, etc. Each channel is responsible for managing and controlling the data transmission and communication between the devices connected to its two sides. Assuming there is a spare channel CA9548 channel 5, it can be set to provide data transmission and communication for the basic input / output system and the memory, that is, the target channel is CA9548 channel 5. Then, when the target startup stage is the PEI stage, the method of calling the target interface to obtain the target startup information from the memory through the target channel of the channel controller can include, but is not limited to, the following steps: when the startup operation performed by the basic input / output system reaches the PEI stage, the PEI (target interface type) interface is called to obtain the target startup information from the EEPROM (memory) through CA9548 channel 5 (target channel). The target startup information can be information that needs to be used before the server is powered on, such as special offer information, etc. The special offer information can indicate the information of the customer to which the server belongs.

[0097] Optionally, in this embodiment, after the basic input / output system obtains the target boot information, it completes the server boot-up operation, enters the operating system, and displays the target boot information on the display.

[0098] Optionally, in this embodiment, as shown in Figure 3, the basic input / output system is connected to the memory through a channel controller. The channel controller can be composed of multiple channel controllers (such as CA9548) connected in parallel. Each CA9548 has multiple channels. The spare channel, CA9548 channel 5, can be specifically set up for data transmission and communication between the basic input / output system and the memory. One CA9548 channel 5 is selected as the target channel, while other CA9548 channels 5 are selected as candidate channels. When the target channel cannot work properly, a working CA9548 channel 5 can be selected from the candidate channels as the new target channel. Through this redundancy mechanism of multiple channel controllers connected in parallel, higher stability can be provided for data transmission and communication between the basic input / output system and the memory.

[0099] As an optional approach, the target interface of the generated target interface type includes:

[0100] S21, Construct a target interface program in the basic input / output system, wherein the target interface program is configured to generate an interface of the target interface type;

[0101] S22, Execute the target interface program to obtain the target interface of the target interface type.

[0102] Optionally, in this embodiment, Figure 5 is a flowchart of a method for reading target boot information before server boot according to an embodiment of this application. As shown in Figure 5, if the target startup stage is set to the PEI stage, then the method for generating a PEI interface (target interface) of type PEI (target interface type) may include, but is not limited to, the following steps: constructing a PEI type module (target interface program) in the basic input / output system that can generate a PEI interface, and obtaining the PEI type interface by running the program.

[0103] As an optional solution, the step of calling the target interface to obtain target power-on information from the memory through the target channel of the channel controller includes:

[0104] S31, Select the target channel from the multiple channels on the channel controller;

[0105] S32, call the target channel to obtain the target power-on information from the memory;

[0106] S33, perform a temporary storage operation on the target power-on information.

[0107] Optionally, in this embodiment, as shown in Figure 5, the method of calling the target interface (PEI interface) to obtain the target power-on information (special offer information) from the memory (EEPROM) through the target channel (CA9548 channel 5) of the channel controller (CA9548) may include, but is not limited to, the following steps: when the CPU accesses CA9548 via the SMBus protocol, it detects whether the accessed channel is CA9548 channel 5. If the detected channel is CA9548 channel 5, the special offer information is read from the EEPROM area through CA9548 channel 5, and the read information is temporarily stored for later use. If the detected channel is not CA9548 channel 5, the process is terminated, and no further reading operation is performed.

[0108] As an optional solution, the temporary storage operation on the target boot information includes:

[0109] S41, Construct an initial data structure for the target data type in the basic input / output system, wherein the data structure for the target data type is a data structure that can be recorded during the target startup phase;

[0110] S42, store the target power-on information into the initial data structure to obtain the target data structure.

[0111] Optionally, in this embodiment, as shown in Figure 5, the temporary storage operation of the target boot information, i.e., the information read by the CPU from the EEPROM area through CA9548 channel 5 via the SMBus protocol, can include, but is not limited to, the following steps: First, construct an empty target data type data structure (initial data structure) in the basic input / output system. The target data type data structure is a data structure that can be recorded in the PEI stage, such as a HOB (Hand-Off Block). Then, store the target boot information in the empty HOB to obtain the target data structure.

[0112] As an optional approach, before displaying the target power-on information on the control display, the method further includes:

[0113] S51, when the startup operation reaches the reference startup phase, the target data structure in the basic input / output system is obtained, wherein the basic input / output system in the reference startup phase is configured to load the operating system of the server before the server is powered on;

[0114] S52, read the target power-on information from the target data structure.

[0115] Optionally, in this embodiment, the reference startup phase may be, but is not limited to, the last stage of the startup operation of the server in the basic input / output system, namely the BDS stage. At the same time, the basic input / output system in this stage can load the server's operating system before the server is powered on. As shown in Figure 5, before displaying the startup information on the display, when the startup operation reaches the BDS stage, the target data structure is obtained, the target startup information (special offer information) stored in the target data structure (HOB) is read, and the read target startup information is displayed on the display.

[0116] As an optional approach, before receiving the power-on command, the method further includes:

[0117] S61, Receive a reference storage instruction, wherein the reference storage instruction is used to instruct the storage of the server's boot information;

[0118] S62, in response to the reference storage instruction, obtain the storage location information of the memory from the target channel, wherein the storage location information is used to indicate the location of currently allowed storage information in the memory;

[0119] S63, construct a target storage instruction carrying the storage location information and the target power-on information, wherein the target storage instruction is used to instruct the memory to store the target power-on information to the location indicated by the storage location information;

[0120] S64, the target storage instruction is sent to the memory through the target channel, wherein the target power-on information stored in the memory is used to be displayed on the display when the server is powered on again.

[0121] Optionally, in this embodiment, as shown in Figure 4, before receiving the power-on command, the target power-on information needs to be stored in the memory. The method of storing the target power-on information to the corresponding location in the memory area may include, but is not limited to, the following steps: First, the processor (CPU) receives the reference storage command and responds to the command, performing a storage operation for the power-on information of the server; then, it obtains the storage location information in the EEPROM area (the location information that can store the target power-on information), then constructs a target storage command carrying the storage location information and the target power-on information, and sends the target storage command to the EEPROM through the target channel (CA9548 channel 5).

[0122] Optionally, in this embodiment, the above-described S61-S64 can be executed under the operating system via an I2C tool, but is not limited to.

[0123] As an optional approach, before obtaining the storage location information of the memory from the target channel, the method further includes:

[0124] S71, Generate a target switching instruction, wherein the target switching instruction is used to instruct the target channel in the channel controller to be switched to the open state;

[0125] S72, execute the target switching instruction.

[0126] Optionally, in this embodiment, FIG6 is a flowchart of a method for writing target boot information before server boot according to an embodiment of the present application. As shown in FIG6, before obtaining the storage location information in the EEPROM area, it is necessary to ensure that the target channel is in the open state. The method of setting the target channel to the open state can be, but is not limited to, sending a target switching command using an I2C tool.

[0127] As an optional solution, the generation of target switching instructions includes:

[0128] S81, obtain the controller address of the channel controller and the channel address of the target channel in the channel controller;

[0129] S82, add the controller address and the channel address to the initial switching instruction to obtain the target switching instruction.

[0130] Optionally, in this embodiment, as shown in Figure 6, the CPU first uses the I2C (Inter-Integrated Circuit) tool to access the CA9548 via the SMBus protocol and obtains the controller address of the channel controller (i.e., the address of the CA9548) and the channel address of the target channel (i.e., the address of CA9548 channel 5). Assuming that the address of the CA9548 and the address of CA9548 channel 5 are 0x70 and 0x20 respectively, the address of the CA9548 and the address of CA9548 channel 5 are added to the initial switching instruction ". / i2cset –y 0" to obtain the target switching instruction ". / i2cset –y 0 0x70 0x20" and execute it, thereby switching the CA9548 to CA9548 channel 5, that is, setting CA9548 channel 5 to the enabled state.

[0131] As an optional solution, obtaining the controller address of the channel controller includes:

[0132] S91, Generate a target acquisition instruction, wherein the target acquisition instruction is used to acquire the address of the device connected to the processor;

[0133] S92, execute the target acquisition command.

[0134] Optionally, in this embodiment, as shown in Figure 6, the controller address (i.e., the address of CA9548) of the channel controller connected to the CPU is acquired by the target acquisition command ". / i2cdetect –y 0". At the same time, it is detected whether CA9548 is successfully accessed. If the return value after executing the target acquisition command is 0x70, it means that CA9548 is successfully accessed and the address of CA9548 is 0x70. The subsequent operation continues. If it is not detected, the process is terminated and no further operation is performed.

[0135] As an optional solution, obtaining the storage location information of the memory from the target channel includes:

[0136] S101, Generate a target lookup instruction, wherein the target lookup instruction is used to find the address of the device connected to the target channel of the channel controller;

[0137] S102, execute the target search instruction and determine the found address as the storage location information.

[0138] Optionally, in this embodiment, as shown in Figure 6, after switching to the target channel CA9548 channel 5, the target lookup instruction ". / i2cdetect –y 0" is used to find the address (i.e., storage location information) of the target boot information area stored in the memory region connected to CA9548 channel 5. At the same time, it is checked whether the EEPROM is successfully accessed. If the return value after executing the target lookup instruction is, for example, 0x01 0x02, it means that the EEPROM is successfully accessed and the address of the target boot information area stored in the memory region is 0x01 0x02. This address is determined as the storage location information, and subsequent operations continue. If it is not detected, the process is terminated and no further operations are performed.

[0139] As an optional approach, the construction of the target storage instruction carrying the storage location information and the target boot information includes:

[0140] S111, Obtain initial storage instruction;

[0141] S112, Collect the memory address of the memory;

[0142] S113, locate the first addition position from the initial storage instruction, wherein the first addition position is the position preceding the operation type character in the initial storage instruction, wherein the operation type character is a character used to indicate the execution of a write operation;

[0143] S114, add the memory address to the first add position in the initial storage instruction to obtain a first storage instruction, wherein the first storage instruction is used to instruct information to be written to the memory;

[0144] S115, locate the second addition position from the first storage instruction, wherein the second addition position is the position between the operation type character and the memory address in the first storage instruction;

[0145] S116, the storage location information is added to the second addition position in the first storage instruction to obtain a second storage instruction, wherein the second storage instruction is used to instruct information to be written to the position indicated by the storage location information in the memory;

[0146] S117, Locate the third addition position from the second storage instruction, wherein the third addition position is the position between the operation type character and the storage position information in the second storage instruction;

[0147] S118, the target power-on information is added to the third add position in the second storage instruction to obtain the target storage instruction, wherein the target storage instruction is used to instruct the target power-on information to be written to the position indicated by the storage location information in the memory.

[0148] Optionally, in this embodiment, as shown in FIG6, the method for constructing the target storage instruction carrying storage location information and target boot information may include, but is not limited to:

[0149] Step 1: Obtain the initial storage command ". / i2cset –y 0i", where the last "i" in the initial storage command ". / i2cset –y 0i" is an operation character representing input (using the first letter of "input");

[0150] Step 2: Obtain the EPPROM address (assuming it is 0x50) using the target search command ". / i2cdetect -y 0", and collect the data at address 0x50;

[0151] Step 3: Determine the position preceding the operation type character ("i") in the initial storage command ". / i2cset –y 0i" as the first addition position;

[0152] Step 4: Add the memory address (0x50) to the first add position in the initial store instruction to obtain the first store instruction ". / i2cset –y 0 0x50 i", which indicates that information is written to the memory.

[0153] Step 5: Determine the position between the operation type character ("i") and the memory address (0x50) in the first storage instruction ". / i2cset –y 0 0x50 i" as the second addition position;

[0154] Step 6: Add the storage location information (0x01 0x02) to the second add position in the first storage instruction to obtain the second storage instruction ". / i2cset –y 0 0x50 0x01 0x02 i". The second storage instruction can instruct the target boot information to be written to the position indicated by the storage location information in the EEPROM area.

[0155] Step 7: Determine the position between the operation type character ("i") and the storage location information (0x01 0x02) in the second storage command ". / i2cset –y 0 0x50 0x01 0x02 i" as the third addition position;

[0156] Step 8: Add the target boot information (special offer information, such as 0x66) to the third add position in the second storage instruction ". / i2cset –y 0 0x50 0x01 0x02 i", resulting in the target storage instruction ". / i2cset –y 0 0x50 0x01 0x02 0x66 i". The target storage instruction can instruct the writing of the target boot information (0x66) to the position (0x01 0x02) indicated by the storage location information in memory (0x50).

[0157] Optionally, in this embodiment, as shown in FIG6, the instruction to write the target boot information (0x66) at the location (0x01 0x02) indicated by the storage location information in the memory (0x50) can be ". / i2cset –y 0 0x50 0x01 0x02; . / i2cget –y 0 0x50".

[0158] This embodiment provides a method for powering on a server. Figure 7 is a schematic diagram of a server power-on method according to an embodiment of this application. As shown in Figure 7, the method mainly includes the following steps:

[0159] First, under the OS system, the customer's requested special offer information is written to the EEPROM using an I2C tool. An optional method is as follows: The CPU accesses the CA9548 via the SMBus protocol and executes the command ". / i2cdetect –y 0". The I2C address of the CA9548 is 0x70. Then, the command ". / i2cset –y 0 0x70 0x20" is executed. This command switches the CA9548 to channel 5, where 0x20 represents switching to channel 5, effectively enabling channel 5. After switching to channel 5, the command ". / i2cdetect –y 0" is executed again to check if a value exists at the specified address. If detected, the EEPROM address is 0x50. To fill the EEPROM with special offer information, the command is “. / i2cset –y 0 0x50 0x01 0x02 0x66 i”. This command means to write 0x66 to the 0x01 0x02 bit in the EEPROM.

[0160] Then, during the PEI stage, the BIOS accesses the special offer information from the EEPROM via the HOB. One possible approach is to create a PEI type module that reads the EEPROM from the CPU via SMBus. The module determines whether the CPU is accessing CA9548 channel 5 via the CA9548 protocol. If it's not CA9548 channel 5, the process terminates. If it is, the BIOS accesses the EEPROM area via CA9548 channel 5 and reads the special offer information. A HOB is then created for the PEI stage, and the special offer information is stored in the HOB.

[0161] Finally, the BIOS retrieves the special offer information from the HOB during the BDS stage and displays it on the post screen. Alternatively, the BIOS can read the special offer information from the HOB during the BDS stage and display it on the post screen.

[0162] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal device (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods described in the various embodiments of this application.

[0163] This embodiment also provides a server power-on device, which is configured to implement the above embodiments and preferred embodiments; details already described will not be repeated. As used below, the term "module" can be a combination of software and / or hardware that implements a predetermined function. Although the device described in the following embodiments is preferably implemented in software, hardware implementation, or a combination of software and hardware, is also possible and contemplated.

[0164] Figure 8 is a structural block diagram of a server power-on device according to an embodiment of this application; as shown in Figure 8, a processor, a channel controller, a memory, and a display are deployed on the server. The processor is connected to the memory through the channel controller, and the processor is also connected to the display. A basic input / output system is installed on the processor. The device is applied to the basic input / output system and includes:

[0165] The first receiving module 802 is configured to receive power-on commands;

[0166] The first response module 804 is configured to respond to the power-on command and perform a startup operation to boot the server.

[0167] The first generation module 806 is configured to generate a target interface of a target interface type when the startup operation reaches the target startup stage, wherein the target interface type is an interface type that the basic input / output system is allowed to call during the target startup stage;

[0168] The calling module 808 is configured to, during the target startup phase, call the target interface to obtain target boot information from the memory through the target channel of the channel controller, wherein the target channel is configured to provide communication between the processor and the memory;

[0169] The control module 810 is configured to control the display to show the target power-on information.

[0170] In one exemplary embodiment, the first generation module includes:

[0171] A construction unit is configured to construct a target interface program in the basic input / output system, wherein the target interface program is used to generate an interface of the target interface type;

[0172] The first execution unit is configured to execute the target interface program to obtain the target interface of the target interface type.

[0173] In one exemplary embodiment, the module includes:

[0174] The filtering unit is configured to filter out the target channel from a plurality of channels on the channel controller;

[0175] The calling unit is configured to call the target channel to retrieve the target power-on information from the memory;

[0176] The second execution unit is configured to perform a temporary storage operation on the target boot information.

[0177] In one exemplary embodiment, the second execution unit is configured as follows:

[0178] An initial data structure for the target data type is constructed in the basic input / output system, wherein the data structure for the target data type is a data structure that can be recorded during the target startup phase;

[0179] The target boot information is stored in the initial data structure to obtain the target data structure.

[0180] In one exemplary embodiment, the apparatus further includes:

[0181] The acquisition module is configured to acquire the target data structure in the basic input / output system before the target boot information is displayed on the control display, when the boot operation is executed to the reference boot phase, wherein the basic input / output system in the reference boot phase is configured to load the operating system of the server before the server boots up;

[0182] The reading module is configured to read the target boot information from the target data structure.

[0183] In one exemplary embodiment, the apparatus further includes:

[0184] The second receiving module is configured to receive a reference storage instruction before receiving the power-on instruction, wherein the reference storage instruction is used to instruct the power-on information of the server to be stored.

[0185] The second response module is configured to respond to the reference storage instruction by obtaining the storage location information of the memory from the target channel, wherein the storage location information is used to indicate the location of currently allowed information to be stored in the memory;

[0186] The construction module is configured to construct a target storage instruction carrying the storage location information and the target boot information, wherein the target storage instruction is used to instruct the memory to store the target boot information to the location indicated by the storage location information;

[0187] The sending module is configured to send the target storage instruction to the memory via the target channel, wherein the target power-on information stored in the memory is used to display on the display when the server is powered on again.

[0188] In one exemplary embodiment, the apparatus further includes:

[0189] The second generation module is configured to generate a target switching instruction before obtaining the storage location information of the memory from the target channel, wherein the target switching instruction is used to instruct the target channel in the channel controller to be switched to the on state;

[0190] The execution module is configured to execute the target switching instruction.

[0191] In one exemplary embodiment, the second generation module includes:

[0192] The first acquisition unit is configured to acquire the controller address of the channel controller and the channel address of the target channel in the channel controller;

[0193] The first adding unit is configured to add the controller address and the channel address to the initial switching instruction to obtain the target switching instruction.

[0194] In an exemplary embodiment, the first acquisition unit is configured as follows:

[0195] Generate a target acquisition instruction, wherein the target acquisition instruction is used to acquire the address of the device connected to the processor;

[0196] Execute the target acquisition command.

[0197] In one exemplary embodiment, the second generation module includes:

[0198] The generation unit is configured to generate a target lookup instruction, wherein the target lookup instruction is used to look up the address of the device connected to the target channel of the channel controller;

[0199] The third execution unit is configured to execute the target search instruction and determine the found address as the storage location information.

[0200] In one exemplary embodiment, the building module includes:

[0201] The second acquisition unit is configured to acquire the initial storage instruction;

[0202] The acquisition unit is configured to acquire the memory address of the memory;

[0203] The first positioning unit is configured to locate a first addition position from the initial storage instruction, wherein the first addition position is the position preceding the operation type character in the initial storage instruction, and the operation type character is a character used to indicate the execution of a write operation;

[0204] The second adding unit is configured to add the memory address to the first adding position in the initial storage instruction to obtain a first storage instruction, wherein the first storage instruction is used to instruct information to be written to the memory;

[0205] The second positioning unit is configured to locate a second addition position from the first storage instruction, wherein the second addition position is the position between the operation type character and the memory address in the first storage instruction;

[0206] The third adding unit is configured to add the storage location information to the second adding position in the first storage instruction to obtain a second storage instruction, wherein the second storage instruction is used to instruct information to be written to the position indicated by the storage location information in the memory;

[0207] The third positioning unit is configured to locate a third addition position from the second storage instruction, wherein the third addition position is the position between the operation type character and the storage position information in the second storage instruction;

[0208] The fourth adding unit is configured to add the target boot information to the third adding position in the second storage instruction to obtain the target storage instruction, wherein the target storage instruction is used to instruct the writing of the target boot information to the position indicated by the storage position information in the memory.

[0209] It should be noted that the above modules can be implemented by software or hardware. For the latter, they can be implemented in the following ways, but are not limited to: all the above modules are located in the same processor; or, the above modules are located in different processors in any combination.

[0210] Embodiments of this application also provide a computer program product, including a computer program that, when executed by a processor, implements the steps of the methods described in various embodiments of this application; the computer program product further includes a non-volatile computer-readable storage medium storing the computer program, which, when executed by a processor, implements the steps of the methods described in various embodiments of this application.

[0211] Embodiments of this application also provide a computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps in any of the above method embodiments when run.

[0212] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard disk, magnetic disk, or optical disk.

[0213] An embodiment of this application also provides an electronic device. FIG9 is a schematic diagram of an electronic device according to an embodiment of this application. As shown in FIG9, the electronic device includes a memory and a processor. The memory stores a computer program, and the processor is configured to run the computer program to perform the steps in any of the above method embodiments.

[0214] In one exemplary embodiment, the electronic device may further include a transmission device and an input / output device, wherein the transmission device is connected to the processor and the input / output device is connected to the processor.

[0215] The optional examples in this embodiment can refer to the examples described in the above embodiments and exemplary implementations, and will not be repeated here.

[0216] Obviously, those skilled in the art should understand that the modules or steps of this application described above can be implemented using general-purpose computing devices. They can be centralized on a single computing device or distributed across a network of multiple computing devices. They can be implemented using computer-executable program code, and thus can be stored in a storage device for execution by a computing device. In some cases, the steps shown or described can be performed in a different order than those presented here, or they can be fabricated as separate integrated circuit modules, or multiple modules or steps can be fabricated as a single integrated circuit module. Thus, this application is not limited to any particular combination of hardware and software.

[0217] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the principles of this application should be included within the protection scope of this application.

Claims

1. A method for starting up a server, characterized by, A processor, a channel controller, a memory, and a display are deployed on the server. The processor is connected to the memory via the channel controller and is also connected to the display. A basic input / output system is installed on the processor. The method is applied to the basic input / output system and includes: Receive power-on command; In response to the power-on command, execute the startup operation to boot the server; If the startup operation reaches the target startup phase, a target interface of the target interface type is generated, wherein the target interface type is an interface type that the basic input / output system is allowed to call during the target startup phase; During the target startup phase, the target interface is invoked to obtain target boot information from the memory through the target channel of the channel controller, wherein the target channel is configured to provide communication between the processor and the memory; Control the display to show the target power-on information.

2. The method according to claim 1, characterized in that, The target interface for generating the target interface type includes: In the basic input / output system, a target interface program is constructed, wherein the target interface program is configured to generate an interface of the target interface type; The target interface of the target interface type is obtained by executing the target interface program.

3. The method according to claim 1, characterized in that, The step of calling the target interface to obtain target boot information from the memory through the target channel of the channel controller includes: The target channel is selected from multiple channels on the channel controller; The target channel is invoked to retrieve the target power-on information from the memory; Perform a temporary storage operation on the target boot information.

4. The method according to claim 3, characterized in that, The channel controller includes multiple sub-channel controllers connected in parallel, and each sub-channel controller includes at least one candidate channel among its multiple channels. The step of selecting the target channel from the multiple channels on the channel controller includes: One candidate channel is selected from the multiple candidate channels corresponding to the multiple sub-channel controllers as the target channel. Each of the remaining multiple candidate channels is configured to retrieve the target power-on information from the memory in place of the target channel when the target channel fails to work properly.

5. The method according to claim 3, characterized in that, The temporary storage operation on the target boot information includes: An initial data structure for the target data type is constructed in the basic input / output system, wherein the data structure for the target data type is a data structure that can be recorded during the target startup phase; The target boot information is stored in the initial data structure to obtain the target data structure.

6. The method according to claim 5, characterized in that, The initial data structure for constructing the target data type in the basic input / output system includes: In the case of the PEI phase initialization for the pre-expandable firmware interface during the target startup phase, an empty data structure is constructed in the basic input / output system that allows data to be recorded during the PEI phase. The empty data structure that is allowed to be recorded in the PEI stage is determined as the initial data structure of the target data type.

7. The method according to claim 5, characterized in that, Before displaying the target power-on information on the control display, the method further includes: When the startup operation reaches the reference startup phase, the target data structure in the basic input / output system is obtained, wherein the basic input / output system in the reference startup phase is configured to load the operating system of the server before the server is powered on; The target boot information is read from the target data structure.

8. The method according to claim 1, characterized in that, Before receiving the power-on command, the method further includes: Receive a reference storage instruction, wherein the reference storage instruction is used to instruct the storage of the server's boot information; In response to the reference storage instruction, the storage location information of the memory is obtained from the target channel, wherein the storage location information is used to indicate the location of currently allowed information to be stored in the memory; Construct a target storage instruction carrying the storage location information and the target power-on information, wherein the target storage instruction is used to instruct the memory to store the target power-on information to the location indicated by the storage location information; The target storage instruction is sent to the memory through the target channel, wherein the target power-on information stored in the memory is used to be displayed on the display when the server is powered on again.

9. The method according to claim 8, characterized in that, Before obtaining the storage location information of the memory from the target channel, the method further includes: Generate a target switching instruction, wherein the target switching instruction is used to instruct the target channel in the channel controller to be switched to the open state; Execute the target switching instruction.

10. The method according to claim 9, characterized in that, The generated target switching instruction includes: Obtain the controller address of the channel controller, and the channel address of the target channel in the channel controller; The controller address and the channel address are added to the initial switching instruction to obtain the target switching instruction.

11. The method according to claim 10, characterized in that, The step of obtaining the controller address of the channel controller and the channel address of the target channel in the channel controller includes: The processor obtains the controller address of the channel controller and the channel address of the target channel in the channel controller through the integrated circuit bus I2C tool.

12. The method according to claim 10, characterized in that, Obtaining the controller address of the channel controller includes: Generate a target acquisition instruction, wherein the target acquisition instruction is used to acquire the address of the device connected to the processor; Execute the target acquisition command.

13. The method according to claim 8, characterized in that, The step of obtaining the storage location information of the memory from the target channel includes: Generate a target lookup instruction, wherein the target lookup instruction is used to find the address of the device connected to the target channel of the channel controller; Execute the target search instruction and determine the found address as the storage location information.

14. The method according to claim 13, characterized in that, The step of executing the target search instruction and determining the found address as the storage location information includes: The target lookup instruction is executed to find the address of the area in the memory region of the memory connected to the target channel that stores the target boot information, and at the same time, it is checked whether the memory has been successfully accessed. If successful access to the memory is detected, the address found by the target lookup instruction is determined as the storage location information.

15. The method according to claim 8, characterized in that, The construction of the target storage instruction carrying the storage location information and the target boot information includes: Get the initial storage instruction; Collect the memory address of the memory; The first add position is located from the initial storage instruction, wherein the first add position is the position preceding the operation type character in the initial storage instruction, and the operation type character is a character used to indicate the execution of a write operation; The memory address is added to the first add position in the initial storage instruction to obtain a first storage instruction, wherein the first storage instruction is used to instruct information to be written to the memory; The second addition position is located from the first storage instruction, wherein the second addition position is the position between the operation type character and the memory address in the first storage instruction; The storage location information is added to the second add position in the first storage instruction to obtain a second storage instruction, wherein the second storage instruction is used to instruct information to be written to the position indicated by the storage location information in the memory; The third addition position is located from the second storage instruction, wherein the third addition position is the position between the operation type character and the storage position information in the second storage instruction; The target boot information is added to the third add position in the second storage instruction to obtain the target storage instruction, wherein the target storage instruction is used to instruct the target boot information to be written to the position indicated by the storage location information in the memory.

16. The method according to claim 1, characterized in that, The step of calling the target interface to obtain target boot information from the memory through the target channel of the channel controller includes: The target interface is invoked to retrieve special offer information from the memory through the target channel of the channel controller. The target power-on information includes the special offer information, which is used to indicate the information of the customer to which the server belongs.

17. A server power-on device, characterized in that, A processor, channel controller, memory, and display are deployed on the server. The processor is connected to the memory via the channel controller and is also connected to the display. A basic input / output system is installed on the processor. The device is applied to the basic input / output system and includes: The first receiving module is configured to receive power-on commands; The first response module is configured to respond to the power-on command and execute a startup operation to boot the server. The first generation module is configured to generate a target interface of a target interface type when the startup operation reaches the target startup phase, wherein the target interface type is an interface type that the basic input / output system is allowed to call during the target startup phase; The calling module is configured to, during the target startup phase, call the target interface to obtain target boot information from the memory through the target channel of the channel controller, wherein the target channel is configured to provide communication between the processor and the memory; The control module is configured to control the display to show the target power-on information.

18. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the method described in any one of claims 1 to 16.

19. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, wherein the computer program, when executed by a processor, implements the steps of the method described in any one of claims 1 to 16.

20. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the steps of the method described in any one of claims 1 to 16.

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