Semiconductor device

Abstract

The present application discloses a semiconductor device, comprising: a semiconductor layer, and a trench gate structure, the semiconductor layer being provided with a first surface and a second surface which are opposite to each other; at least a portion of the trench gate structure is located in a trench extending from the first surface to the second surface of the semiconductor layer; the semiconductor layer comprises a shielding layer extending along a second direction and located between the trench gate structure and the second surface of the semiconductor layer; a bottom spacing of the trench gate structure extending in a first direction is adjacent to the shielding layer; the first direction and the second direction are parallel to the first surface of the semiconductor layer, and an included angle that is not 0 degrees is formed between the first direction and the second direction. In the semiconductor device provided by the present application, the shielding layer provided with multiple beam-shaped structures and extending along the second direction is formed below the trench extending along the first direction. By controlling the width of a spacing region between adjacent beam-shaped structures in the first direction, and the width of the beam-shaped structure, an electric field at a bottom corner of the trench gate is optimized, and on-resistance is reduced.

Description

semiconductor devices Cross-references to related applications

[0001] This application claims priority to Chinese Patent Application No. 202411620301.4, filed on November 13, 2024, entitled "Semiconductor Device", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This invention relates to the field of semiconductor device technology, and more specifically, to a semiconductor device having a trench gate structure. Background Technology

[0003] Compared to planar transistor structures, vertical transistor structures offer advantages in balancing blocking voltage and on-resistance within the same area. When power device modules or multiple discrete devices are used in the same system, the characteristic variations between transistor devices are also an important consideration for the robustness of the integrated system. During manufacturing, transistors undergo numerous and different process steps, thus their device characteristics vary depending on the manufacturing process.

[0004] As a power semiconductor device, MOSFETs offer various methods to improve their on-resistance (Rsp) or switching loss. For trench transistors, the electric field concentrates at the bottom corner of the trench during operation, resulting in poor voltage withstand and reliability.

[0005] To compensate for this drawback, shielding is required at the bottom corners of the trench. However, traditional shielding methods often lead to increased on-resistance, require thicker hard mask layers, or result in larger design dimensions. Summary of the Invention

[0006] In view of the above problems, the object of the present invention is to provide a semiconductor device in which a shielding layer having a plurality of beam-like structures and extending in a second direction is formed under a trench extending in a first direction. By controlling the width of the spacing region between adjacent beam-like structures along the first direction and the width of the beam-like structures, the electric field at the bottom corner of the trench gate is optimized, while reducing the on-resistance.

[0007] According to one aspect of the present invention, a semiconductor device is provided, comprising: a semiconductor layer and a trench gate structure, the semiconductor layer having opposing first and second surfaces, at least a portion of the trench gate structure being located in a trench extending from the first surface to the second surface of the semiconductor layer, wherein the semiconductor layer includes: a shielding layer extending in a second direction, the shielding layer being located between the trench gate structure and the second surface of the semiconductor layer, the bottom of the trench gate structure extending in a first direction being spaced adjacent to the shielding layer, the first direction and the second direction being parallel to the first surface of the semiconductor layer, the first direction and the second direction forming a non-zero angle.

[0008] Optionally, the shielding layer includes a plurality of beam-like structures extending along a second direction, and the plurality of beam-like structures are spaced apart along a first direction.

[0009] Optionally, the angle between the first direction and the second direction is greater than 45° and less than 135°.

[0010] Optionally, along the first direction, the interval region between two adjacent beam-like structures and an adjacent beam-like structure form a cell region, wherein the spacing width of the interval region along the first direction is greater than or equal to the width of the beam-like structure.

[0011] Optionally, in the cell region, the ion doping concentration of the shielding layer is increased to reduce the width of the beam-like structure.

[0012] Optionally, the ratio of the width of the beam-like structure to the spacing width of the interval region is greater than or equal to 1 / 3 and less than or equal to 1.

[0013] Optionally, the semiconductor layer further includes: a source region located between adjacent trench gate structures, extending from a first surface to a second surface of the semiconductor layer, and adjacent to a sidewall of one of the trench gate structures on one side; a body region located between adjacent trench gate structures, adjacent to the sidewalls of the adjacent trench gate structures on both sides, and a portion of the upper surface of the body region adjacent to the lower surface of the source region; and an epitaxial layer located between the body region and the second surface of the semiconductor layer, the epitaxial layer separating the adjacent beam-like structures and adjacent to a portion of the lower surface of the body region.

[0014] Optionally, the shielding layer and the body region are of a second conductivity type.

[0015] Optionally, the doping concentration of the shielding layer is greater than the doping concentration of the body region.

[0016] Optionally, the distance between the lower surface of the trench gate structure and the first surface is greater than the distance between the lower surface of the body region and the first surface.

[0017] Optionally, the semiconductor layer further includes: a body contact region located between two source regions adjacent to the trench gate structure, the source regions separating the body contact region from the trench gate structure, the body contact region extending from the first surface to the second surface and adjacent to the body region, wherein the body contact region is of a second conductivity type.

[0018] Optionally, the body contact area extends along a first direction; or the body contact area includes a plurality of regions spaced apart along the first direction, with each region of the body contact area on the first surface surrounded by the source region.

[0019] Optionally, the trench gate structure includes a gate dielectric layer and a gate conductor, the gate dielectric layer covering the inner surface of the trench, the gate conductor located in the trench, and the gate dielectric layer located between the gate conductor and the semiconductor layer to separate the gate conductor and the semiconductor layer.

[0020] Optionally, the semiconductor layer further includes: a substrate located between the epitaxial layer and the second surface; a drain contact region located on the side of the substrate near the second surface; a source metal layer located on the first surface of the semiconductor layer, at least adjacent to a portion of the source region; and an interlayer dielectric layer located between the first surface of the semiconductor layer and the source metal layer, wherein the interlayer dielectric layer separates the trench gate structure from the source metal layer.

[0021] Optionally, the semiconductor layer includes a SiC semiconductor layer or a Si semiconductor layer.

[0022] The semiconductor device provided by the present invention forms a shielding layer under a trench extending along a first direction. The shielding layer includes a plurality of beam-like structures extending along a second direction. By controlling the spacing width between adjacent beam-like structures and the width of the beam-like structures along the first direction, the electric field at the bottom corner of the trench gate is optimized, and the on-resistance is reduced. The angle between the extension direction of the trench gate structure and the extension direction of the beam-like structures can be an acute angle, a right angle, or an obtuse angle.

[0023] Furthermore, in this application, the beam-like structure of the shielding layer extending along the second direction does not form channels in the area contacting the trench gate; channels are only formed in the area between adjacent beam-like structures. Therefore, the narrower the width of the beam-like structure along the first direction, the more it helps to reduce the on-resistance. Moreover, the shielding layer does not require ultra-high-energy ion implantation, thus the width of the shielding layer along the first direction can be effectively controlled during the manufacturing process.

[0024] Furthermore, along the first direction, a spacing between adjacent beam-like structures in the shielding layer and an adjacent shielding layer form a cell region. Within a cell region, controlling the width of the shielding layer along the first direction to be smaller than the spacing between adjacent shielding layers can maintain the withstand voltage and reliability of the semiconductor device at a certain level while improving the Rsp (on-resistance) characteristics. Specifically, within a cell region, the ratio of the width of the beam-like structure to the spacing between adjacent beam-like structures is less than or equal to 1 but greater than or equal to 1 / 3.

[0025] It should be noted that the above general description and the following detailed description are merely exemplary and explanatory and do not limit this application. Attached Figure Description

[0026] The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the invention with reference to the accompanying drawings, in which:

[0027] Figure 1 shows a three-dimensional structural schematic diagram of a semiconductor device according to a first embodiment of the present invention;

[0028] Figure 2 shows a schematic cross-sectional view of a semiconductor device taken along line AA in Figure 1 according to a first embodiment of the present invention;

[0029] Figure 3 shows a schematic cross-sectional view of a semiconductor device taken along line BB in Figure 1 according to a first embodiment of the present invention;

[0030] Figure 4 shows a schematic cross-sectional view of a semiconductor device taken along line CC in Figure 1 according to a first embodiment of the present invention;

[0031] Figure 5 shows a schematic cross-sectional view of a semiconductor device taken along line DD in Figure 1 according to a first embodiment of the present invention;

[0032] Figure 6 shows the positional relationship between the shielding layer and the trench along the horizontal plane of the semiconductor device according to the first embodiment of the present invention;

[0033] Figure 7 shows the positional relationship between the shielding layer and the trench along the horizontal plane of the semiconductor device according to the second embodiment of the present invention;

[0034] Figure 8 shows the positional relationship between the shielding layer and the trench along the horizontal plane of a semiconductor device according to a third embodiment of the present invention;

[0035] Figure 9 shows the positional relationship between the shielding layer and the trench along the horizontal plane of a semiconductor device according to a fourth embodiment of the present invention;

[0036] Figure 10 shows a three-dimensional structural schematic diagram of a semiconductor device according to a fifth embodiment of the present invention;

[0037] Figure 11 shows a schematic cross-sectional view of a semiconductor device taken along line CC in Figure 10 according to a fifth embodiment of the present invention. Detailed Implementation

[0038] The present application will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are indicated by similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale. Furthermore, some well-known parts may not be shown. For simplicity, the semiconductor structure obtained after several steps can be depicted in a single figure.

[0039] It should be understood that when describing the structure of a device, when referring to a layer or region as being "above" or "on top of" another layer or region, it can mean that it is directly above another layer or region, or that there are other layers or regions between it and another layer or region. Furthermore, if the device is flipped, that layer or region will be located "below" or "under" another layer or region.

[0040] To describe a situation where it is directly above another layer or another area, this article will use expressions such as "directly above" or "above and adjacent to".

[0041] Power devices typically include an active element region, an edge-terminating region, and a crack-stop or shielding region. The active element region includes an array of active elements. This disclosure relates to active element structures. The dimensions of the active elements may vary depending on product requirements, and there may be volume regions between active elements within the active element region.

[0042] Many specific details of this application, such as the structure, materials, dimensions, processing techniques, and methods of the devices, are described below to provide a clearer understanding of the application. However, as those skilled in the art will understand, this application may be implemented without adhering to these specific details.

[0043] The specific embodiments of the present invention will be described in further detail below with reference to the accompanying drawings and examples.

[0044] Figure 1 shows a three-dimensional structural schematic diagram of a semiconductor device according to a first embodiment of the present invention; Figure 2 shows a cross-sectional schematic diagram of the semiconductor device along line AA in Figure 1 according to a first embodiment of the present invention; Figure 3 shows a cross-sectional schematic diagram of the semiconductor device along line BB in Figure 1 according to a first embodiment of the present invention; Figure 4 shows a cross-sectional schematic diagram of the semiconductor device along line CC in Figure 1 according to a first embodiment of the present invention; Figure 5 shows a cross-sectional schematic diagram of the semiconductor device along line DD in Figure 1 according to a first embodiment of the present invention. In Figure 1, the structure above the semiconductor layer and part of the trench gate structure are omitted to more clearly illustrate the positional relationships between the various structures and regions.

[0045] As shown in Figures 1 to 5, the semiconductor device 10 of the first embodiment of this application includes a semiconductor layer 100, a plurality of trench gate structures 150 located in the semiconductor layer 100, an interlayer dielectric layer 160 located on the semiconductor layer 100, and a source metal layer 170. The semiconductor layer 100 has a first surface and a second surface disposed opposite to each other, and a plurality of trenches 102 extending from the first surface to the second surface of the semiconductor layer 100, wherein the plurality of trench gate structures 150 are located in the corresponding trenches 102.

[0046] In this embodiment, the semiconductor layer 100 is, for example, a SiC substrate, a Si substrate, or a stacked structure consisting of a SiC substrate and an epitaxial layer. However, the embodiments of this application are not limited to this, and those skilled in the art can make other settings for the material and number of layers of the semiconductor layer 100 as needed.

[0047] Semiconductor layer 100 includes a substrate 101, an epitaxial layer 103, a masking layer 120, a body region 110, a source region 130, a body contact region 140, and a drain contact region 180. The source region 130, substrate 101, and epitaxial layer 103 are of a first conductivity type, while the body region 110, body contact region 140, and masking layer 120 are of a second conductivity type. The doping concentration of the body contact region 140 is greater than that of the body region 110. The first conductivity type is the opposite of the second conductivity type. The first conductivity type is either P-type or N-type, and the second conductivity type is the other of P-type and N-type.

[0048] The trench gate structure 150 includes a gate dielectric layer 151 and a gate conductor 152. The gate dielectric layer 151 covers the inner surface of the trench 102, the gate conductor 152 is located in the trench 102, and the gate dielectric layer 151 is located between the semiconductor layer 100 and the gate conductor 152, serving to separate the semiconductor layer 100 and the gate conductor 152. Multiple trench gate structures 150 extend along a first direction, i.e., the first direction is the length direction of the trench gate structure 150, and the multiple trench gate structures 150 are spaced apart along a second direction, i.e., the second direction is the width direction of the trench gate structure 150, and a third direction is the direction from the second surface of the semiconductor layer 100 to the first surface. Optionally, the first direction, the second direction, and the third direction represent the X-axis, Y-axis, and Z-axis directions, respectively, and each of the first direction, the second direction, and the third direction is perpendicular to the others. The trench gate structure 150 has two sidewalls 150a and a lower surface 150b. Optionally, the Y-axis direction is either the <11-20> direction or the <1-100> direction, and the plane of the sidewall 150a is either the (11-20) plane or the (1-100) plane.

[0049] The body region 110 is located between two adjacent trench gate structures 150 and extends along both the width and length directions of the trench gate structure. One side of the body region 110 is adjacent to the sidewall 150a of one of the trench gate structures 150, and the other side is adjacent to the sidewall 150a of the other trench gate structure 150. Furthermore, the distance between the lower surface of the body region 110 and the first surface is smaller than the distance between the lower surface of the trench gate structure 150 and the first surface.

[0050] Source region 130 extends from the first surface of semiconductor layer 100 to the second surface, adjacent to body region 110. Simultaneously, source region 130 is located between two adjacent trench gate structures 150 and adjacent to a sidewall 150a of trench gate structure 150. Body contact region 140 is located between source regions 130, dividing the source region 130 between two adjacent trench gate structures 150 into two parts. Each part of source region 130 is adjacent to a sidewall 150a of one of the adjacent trench gate structures 150. That is, in the second direction, source region 130, body contact region 140, and source region 130 are sequentially located between adjacent trench gate structures 150 on the first surface of semiconductor layer 100; in the third direction, source region 130 and body contact region 140 are located above body region 110. In this embodiment, FIG1 shows the case where body contact region 140 extends along the first direction, thereby dividing the source region 130 between two adjacent trench gate structures 150 into two parts. The depth of the body contact region 140 extending from the first surface to the second surface in the semiconductor layer 100 is greater than the depth of the source region 130 extending in the semiconductor layer 100, but less than the depth of the body region 110 extending in the semiconductor layer 100. The bottom of the trench of the trench gate structure 150 is located below the body region 110. That is, the depth of the trench gate structure 150 extending from the first surface to the second surface of the semiconductor layer 100 is greater than the depth of the body region 110 extending in the semiconductor layer 100.

[0051] The substrate 101 is located below the body region 110, that is, on the side close to the second surface of the semiconductor layer 100. The epitaxial layer 103 is located between the body region 110 and the substrate 101. The drain contact region 180 is adjacent to the substrate 101 and is located on the side surface of the substrate 101 away from the epitaxial layer 103, that is, the drain contact region 180 extends from the second surface of the semiconductor layer 100 to the first surface.

[0052] The shielding layer 120 is located below the body region 110 and the trench gate structure 150, specifically adjacent to the lower surface of the body region 110 and the lower surface 150b and part of the side surface of the trench gate structure 150. The shielding layer 120 includes a plurality of beam-like structures extending along a second direction and spaced apart along a first direction. The upper surface of one beam-like structure alternately abuts the lower surfaces of the plurality of body regions 110 and the plurality of trench gate structures 150. Since the plurality of beam-like structures are spaced apart along the first direction, the gap between two adjacent beam-like structures exposes the lower surfaces of the body region 110 and the trench gate structure 150 along the first direction. Furthermore, along the extension direction of the beam-like structures, the first ends of the plurality of beam-like structures are connected together, and the second ends of the plurality of beam-like structures are also connected together, for example, referring to FIG6.

[0053] Referring to Figure 2, in a cross-section of the semiconductor device 10 taken from a vertical plane of a beam-like structure having a shielding layer 120 along the second direction, the lower surface of the shielding layer 120 extends to a substantially uniform depth within the semiconductor layer 100. However, as described above, the upper surface of the shielding layer 120 alternately adjoins the lower surfaces of multiple body regions 110 and multiple trench gate structures 150 in the second direction. In this region, since the shielding layer 120 covers the entire bottom of the trench gate structure 150, and the area below the body regions 110 is also covered by the shielding layer 120, current cannot flow through this region, and a channel cannot be formed. Simultaneously, since the shielding layer 120 is in direct contact with the bottom of the trench gate structure 150, the shielding layer 120 effectively protects the bottom corners of the trench gate structure 150 from being damaged in this region.

[0054] Referring to Figure 3, in a cross-section of the semiconductor device 10 taken from a vertical plane of a beam-shaped structure along the second direction without the shielding layer 120, the lower surface of the body region 110 is in direct contact with the epitaxial layer 103. Since this gap region lacks the shielding layer 120, and the bottom of the trench gate structure 150 is also in direct contact with the epitaxial layer 103, there are no factors hindering current flow in this gap region. Therefore, this gap region represents the most ideal structure for reducing on-resistance.

[0055] Interlayer dielectric layers 160 are located on the first surface of semiconductor layer 100. Multiple interlayer dielectric layers 160 extend along a first direction and are spaced apart along a second direction, such that the bottom of the interlayer dielectric layers 160 can cover the exposed portion of trench gate structure 150 on the first surface of semiconductor layer 100, and at least expose a portion of the surface of source region 130 and body contact region 140 on the first surface. Source metal layer 170 is located on the first surface of semiconductor layer 100 and contacts at least a portion of the exposed surface of source region 130 and body contact region 140 on the first surface. Interlayer dielectric layers 160 are used to isolate trench gate structure 150 from source metal layer 170. Source metal layer 170 and interlayer dielectric layers 160 can be multilayer structures of different materials. As an example of a multilayer source metal layer 170, source metal layer 170 includes a tungsten (W) layer directly covering body contact region 140 and source region 130, and an aluminum copper (AlCu) layer directly covering the tungsten layer. Optionally, this embodiment also includes a portion not shown in the figure, such as opening a gate contact region directly above the gate conductor 152, so that the gate conductor 152 is connected to the gate metal layer, the gate contact region is directly located on the gate conductor 152, and the gate conductor 152 is isolated from the source metal layer 170 through the interlayer dielectric layer 160.

[0056] Referring to Figure 4, in a cross-sectional view of the semiconductor device 10 taken along the first direction in the region located in the source region 130, since this cross-section is relatively close to the body contact region 140, there is no interlayer dielectric layer 160 above the source region 130. Of course, in the region closer to the trench gate structure 150, in order to ensure the isolation effect of the interlayer dielectric layer 160, the interlayer dielectric layer 160 can cover part of the upper surface of the source region 130. Therefore, in the cross-sectional view of the semiconductor device 10 taken in the region closer to the trench gate structure 150, there can also be an interlayer dielectric layer 160 on the source region 130.

[0057] In this embodiment, further referring to Figures 4 and 5, multiple beam-shaped structures of the shielding layer 120 are arranged at intervals along the first direction. In order for the beam-shaped structures to also shield the bottom of the trench gate 150 between adjacent beam-shaped structures, it is necessary to consider the width Wa of the beam-shaped structure along the first direction and the width Wb of the interval region between two adjacent beam-shaped structures. In this way, the bottom of the trench gate structure 150 can be shielded while a semiconductor device with low on-resistance can be manufactured.

[0058] Specifically, for example, a cell region may include a beam-like structure and an adjacent spacer region (W = Wa + Wb) along a width W in the first direction. Since the beam-like structure region does not form a channel within this cell region, a narrower beam-like structure width Wa is more conducive to reducing the on-resistance Ron. In this embodiment, the beam-like structure width Wa is less than or equal to the spacer region width Wb. Furthermore, this application does not require ultra-high energy ion implantation (above 2.5 MeV), thus making it easier to achieve a narrower beam-like structure width Wa in terms of process technology.

[0059] Furthermore, while ensuring the withstand voltage and reliability of semiconductor devices, a smaller ratio (Wa / Wb) of the beam structure width Wa to the spacing region width Wb improves the Rsp (on-resistance) characteristics of the semiconductor device. Therefore, the beam structure width Wa can be set to be smaller than the spacing region width Wb between two adjacent beam structures. Simultaneously, by increasing the ion concentration of the shielding layer 120, the beam structure width Wa within a unit cell region can be further narrowed, while the spacing region width Wb between two adjacent beam structures can be widened.

[0060] In this embodiment, the ratio (Wa / Wb) between the width Wa of the beam structure and the width Wb of the interval between two adjacent beam structures is less than or equal to 1 and greater than or equal to 1 / 3.

[0061] Furthermore, since the beam-like structure already has a portion that contacts the body region 110 in its extension direction, no additional pick-up layer is needed to connect the shielding layer 120 and the body region 110.

[0062] The semiconductor device in this embodiment can be a metal-oxide-semiconductor field-effect transistor (MOSFET) or an insulated-gate bipolar transistor (IGBT), for example, by setting the conductivity type of the drain contact region 180 to a first conductivity type or a second conductivity type. However, this embodiment is not limited to this, and those skilled in the art can make other settings for the conductivity type of each region in the semiconductor layer 100 as needed to make the semiconductor device a MOSFET or an IGBT.

[0063] In this embodiment, when the semiconductor device is in the ON state, the portion of the body region 110 adjacent to the sidewalls 150a on both sides of the trench gate structure 150 is inverted, thereby forming a channel. Moreover, since the multiple beam-like structures of the shielding layer 120 are spaced apart along the second direction, the channel current can only flow from the region between two adjacent beam-like structures. By controlling the width of the beam-like structures along the first direction and the spacing between two adjacent beam-like structures along the first direction, the bottom corner of the trench gate structure 150 in the channel region can be protected from being broken down by the electric field, thereby reducing the turn-on resistance of the semiconductor device and improving the overall performance of the device.

[0064] Furthermore, the semiconductor device in this embodiment also includes a drain metal layer (not shown), located on the second surface of the semiconductor layer 100, and connected to the drain contact region 180.

[0065] Figure 7 shows the positional relationship between the shielding layer and the trench along the horizontal plane of a semiconductor device according to a second embodiment of the present invention.

[0066] As shown in Figure 7, the similarities between the semiconductor device of the second embodiment and the first embodiment will not be repeated here, but can be referred to the descriptions in Figures 1 to 6. The difference is that, compared with the first embodiment, in the shielding layer 120 of the second embodiment, the first ends of the multiple beam-like structures along the extension direction of the beam-like structures are not connected together, and the second ends of the multiple beam-like structures are not connected together. Thus, the shielding layer 120 includes multiple parallel and mutually separated beam-like structures, and adjacent beam-like structures are separated by an epitaxial layer.

[0067] Figure 8 shows the positional relationship between the shielding layer and the trench along the horizontal plane of a semiconductor device according to a third embodiment of the present invention.

[0068] As shown in Figure 8, the similarities between the semiconductor device of the third embodiment and the first embodiment will not be repeated here, but can be referred to the descriptions in Figures 1 to 6. The difference is that, compared with the first embodiment, the angle between the second direction (Y) and the first direction (X) of the beam-like structure extending in the shielding layer 120 in the third embodiment is an obtuse angle. Specifically, the range of the angle between the second direction (Y) and the first direction (X) of the beam-like structure extending in the shielding layer 120 is greater than 90° and less than 135°.

[0069] Figure 9 shows the positional relationship between the shielding layer and the trench along the horizontal plane of a semiconductor device according to a fourth embodiment of the present invention.

[0070] As shown in Figure 9, the similarities between the semiconductor device of the fourth embodiment and the first embodiment will not be repeated here, but can be referred to the descriptions in Figures 1 to 6. The difference is that, compared with the first embodiment, the beam-like structure in the shielding layer 120 in the fourth embodiment has an acute angle between its extended second direction (Y) and first direction (X). Specifically, the angle between the extended second direction (Y) and first direction (X) of the beam-like structure in the shielding layer 120 is greater than 45° and less than 90°.

[0071] Figure 10 shows a three-dimensional structural schematic diagram of a semiconductor device according to a fifth embodiment of the present invention; Figure 11 shows a cross-sectional schematic diagram of the semiconductor device according to a fifth embodiment of the present invention, taken along line CC in Figure 10.

[0072] As shown in Figures 10 and 11, the similarities between the semiconductor device of the fifth embodiment and the first embodiment will not be repeated here, but can be referred to the descriptions in Figures 1 to 6. The difference is that, compared with the first embodiment, the body contact region 140 in the fifth embodiment includes a plurality of block-shaped regions, and the plurality of block-shaped regions are arranged at intervals along a first direction. On the first surface, the body contact region 140 is surrounded by the source region 130.

[0073] The semiconductor device provided by the present invention forms a shielding layer under a trench extending along a first direction. The shielding layer includes a plurality of beam-like structures extending along a second direction. By controlling the spacing between adjacent beam-like structures and the width of the beam-like structures along the first direction, the electric field at the bottom corner of the trench gate is optimized, and the on-resistance is reduced. The angle between the extension direction of the trench gate structure and the extension direction of the beam-like structures can be an acute angle, a right angle, or an obtuse angle.

[0074] Furthermore, in this application, the beam-like structure of the shielding layer extending along the second direction does not form channels in the area contacting the trench gate; channels are only formed in the area between adjacent beam-like structures. Therefore, the narrower the width of the beam-like structure along the first direction, the more it helps to reduce the on-resistance. Moreover, the shielding layer does not require ultra-high-energy ion implantation, thus the width of the shielding layer along the first direction can be effectively controlled during the manufacturing process.

[0075] Furthermore, along the first direction, a spacing between adjacent beam-like structures in the shielding layer and an adjacent shielding layer form a cell region. Within a cell region, the width of the shielding layer along the first direction is controlled to be less than the spacing between adjacent shielding layers, thereby maintaining the withstand voltage and reliability of the semiconductor device at a certain level while improving Rsp. Specifically, within a cell region, the ratio of the width of the beam-like structure to the spacing between adjacent beam-like structures is less than or equal to 1 but greater than or equal to 1 / 3.

[0076] As described above, these embodiments of the present invention do not exhaustively cover all details, nor do they limit the invention to the specific embodiments described. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to effectively utilize the invention and its modifications. The invention is limited only by the claims and their full scope and equivalents.

Claims

1. A semiconductor device, comprising: A semiconductor layer and a trench gate structure, the semiconductor layer having opposing first and second surfaces, the trench gate structure being at least partially located in a trench extending from the first surface to the second surface of the semiconductor layer. The semiconductor layer includes: A shielding layer extending along a second direction is located between the trench gate structure and the second surface of the semiconductor layer. The bottom of the trench gate structure extending along a first direction is spaced adjacent to the shielding layer. The first direction and the second direction are parallel to the first surface of the semiconductor layer, and the first direction and the second direction form a non-zero angle.

2. The semiconductor device according to claim 1, wherein, The shielding layer includes multiple beam-like structures extending along a second direction, and the multiple beam-like structures are spaced apart along a first direction.

3. The semiconductor device according to claim 2, wherein, The angle between the first direction and the second direction is greater than 45° and less than 135°.

4. The semiconductor device according to claim 2, wherein, Along the first direction, the interval region between two adjacent beam-like structures and an adjacent beam-like structure form a cell region. In the cell region, the spacing width of the interval region along the first direction is greater than or equal to the width of the beam-like structure.

5. The semiconductor device according to claim 4, wherein, In the cell region, the ion doping concentration of the shielding layer is increased to reduce the width of the beam-like structure.

6. The semiconductor device according to claim 4 or 5, wherein, The ratio of the width of the beam-like structure to the spacing width of the interval region is greater than or equal to 1 / 3 and less than or equal to 1.

7. The semiconductor device according to claim 6, wherein, The semiconductor layer further includes: The source region is located between adjacent trench gate structures, extends from the first surface of the semiconductor layer to the second surface, and is adjacent to the sidewall of one of the trench gate structures on one side. The body region is located between adjacent trench gate structures, and its two sides are respectively adjacent to the sidewalls of the adjacent trench gate structures. A portion of the upper surface of the body region is adjacent to the lower surface of the source region. An epitaxial layer is located between the body region and the second surface of the semiconductor layer, the epitaxial layer separating the adjacent beam-like structures and adjacent to a portion of the lower surface of the body region.

8. The semiconductor device according to claim 7, wherein, The shielding layer and the body region are of the second conductivity type.

9. The semiconductor device according to claim 8, wherein, The doping concentration of the shielding layer is greater than the doping concentration of the body region.

10. The semiconductor device according to claim 7, wherein, The distance between the lower surface of the trench gate structure and the first surface is greater than the distance between the lower surface of the body region and the first surface.

11. The semiconductor device according to claim 7, wherein, The semiconductor layer further includes: A body contact region is located between two source regions adjacent to the trench gate structure. The source regions divide the body contact region from the trench gate structure. The body contact region extends from the first surface to the second surface and is adjacent to the body region. The body contact area is of the second conductivity type.

12. The semiconductor device according to claim 11, wherein, The body contact area extends along a first direction; or The body contact area includes a plurality of regions spaced apart along a first direction, and each region of the body contact area on the first surface is surrounded by the source region.

13. The semiconductor device according to claim 11, wherein, The trench gate structure includes a gate dielectric layer and a gate conductor. The gate dielectric layer covers the inner surface of the trench, the gate conductor is located in the trench, and the gate dielectric layer is located between the gate conductor and the semiconductor layer to separate the gate conductor and the semiconductor layer.

14. The semiconductor device according to claim 13, wherein, The semiconductor layer further includes: A substrate is located between the epitaxial layer and the second surface; The drain contact region is located on the side of the substrate closer to the second surface; A source metal layer is located on the first surface of the semiconductor layer and is at least adjacent to a portion of the source region; An interlayer dielectric layer is located between the first surface of the semiconductor layer and the source metal layer, and the interlayer dielectric layer separates the trench gate structure from the source metal layer.

15. The semiconductor device according to claim 1, wherein, The semiconductor layer includes a SiC semiconductor layer or a Si semiconductor layer.

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