Semiconductor device and manufacturing method therefor
By forming trenches and integrating ferroelectric dielectric and electrode layers in semiconductor devices, the problems of integration density and operating speed of ferroelectric memory during integrated circuit miniaturization are solved, realizing fast read and write of highly integrated and non-volatile memory.
Patent Information
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- WUXI CHINA RESOURCES MICROELECTRONICS
- Filing Date
- 2025-11-04
- Publication Date
- 2026-05-21
AI Technical Summary
In the process of integrated circuit miniaturization, it is difficult to improve the integration density of existing ferroelectric memories, and there are challenges in the miniaturization of traditional 1T1C memory cells.
A trench is formed in a semiconductor device, and a ferroelectric dielectric layer and an electrode layer are formed in the trench and on the surface of the active region. The spontaneous polarization characteristics of the ferroelectric dielectric layer and the reversal of the external electric field are used to control the channel turn-on voltage difference between the source and drain regions, thereby realizing non-volatile storage and fast read/write operations.
It improves the integration of semiconductor devices and enables non-volatile storage and fast read/write operations, solving the problems of integration and miniaturization in traditional ferroelectric memories.
Smart Images
Figure CN2025132378_21052026_PF_FP_ABST
Abstract
Description
A semiconductor device and its manufacturing method Cross-references to related applications
[0001] This patent application claims priority to Chinese Patent Application No. 202411623268.0, filed on November 13, 2024, entitled “A Semiconductor Device and a Method for Manufacturing the Same Thereof,” the entire contents of which are incorporated herein by reference. Technical Field
[0002] This application relates to the field of semiconductor technology, and more specifically to a semiconductor device and a method for manufacturing the same. Background Technology
[0003] Ferroelectric RAM (FRAM) is a new type of memory that combines the non-volatility of read-only memory (ROM) with the non-volatility of random access memory (RAM), and has advantages such as high durability, high-speed read and write speed and low power consumption. It has been widely used in various fields.
[0004] The basic memory cell of ferroelectric memory is a 1T1C (1 Transistor-1 Capacitor) memory cell. A conventional 1T1C memory cell requires a transistor and a ferroelectric capacitor. The ferroelectric capacitor generally adopts a MIM (metal / insulator / metal) structure, which includes a metal layer as the lower electrode, a ferroelectric thin film material as the dielectric layer, and a metal layer as the upper electrode.
[0005] As integrated circuits continue to shrink according to Moore's Law, semiconductor devices are becoming smaller and more complex, leading to higher requirements for device integration. Summary of the Invention
[0006] The summary section introduces a series of simplified concepts, which will be further explained in detail in the detailed description section. This summary section is not intended to limit the key and essential technical features of the claimed technical solution, nor is it intended to determine the scope of protection of the claimed technical solution.
[0007] To address the existing problems, this application provides a method for manufacturing a semiconductor device, comprising:
[0008] A substrate having a first conductivity type is provided, the substrate including an active region;
[0009] The active region is etched to form trenches in the active region;
[0010] A ferroelectric dielectric layer is formed, which covers the bottom and sidewalls of the trench and a portion of the surface of the active region along a first direction;
[0011] An electrode layer is formed, which fills the remaining portion of the trench and covers the ferroelectric layer located on the surface of the active region;
[0012] A source region and a drain region having a second conductivity type are formed in the active region, and the source region and the drain region are respectively located on both sides of the trench along a first direction.
[0013] For example, the trench extends through the active region along a second direction, which is perpendicular to the first direction.
[0014] For example, after etching the active region to form a trench in the active region, the method further includes the step of forming a doped region having a first conductivity type in the substrate, the doped region being attached to the bottom and sidewalls of the trench and to a portion of the surface of the active region along the first direction, the doping concentration of the doped region being greater than or less than the doping concentration of the substrate, and the ends of the source and drain regions contacting the doped region.
[0015] For example, after forming the trench and before forming the ferroelectric dielectric layer, the step of forming an isolation dielectric layer is included, the isolation dielectric layer covering the bottom and sidewalls of the trench and covering a portion of the surface of the active region along a first direction, the ferroelectric dielectric layer covering the isolation dielectric layer.
[0016] For example, the material of the isolation dielectric layer includes silicon dioxide, silicon oxynitride, hafnium dioxide or titanium oxide, and / or the thickness of the isolation dielectric layer ranges from 1 angstrom to 100 angstroms.
[0017] For example, after forming the ferroelectric dielectric layer and before forming the electrode layer, the step of forming an adhesive layer is further included, the adhesive layer covering the ferroelectric dielectric layer and the electrode layer covering the adhesive layer.
[0018] For example, after forming a source region and a drain region having a second conductivity type in the active region, the method further includes:
[0019] An interlayer dielectric layer is formed, which covers the surface of the substrate;
[0020] A first conductive plug, a second conductive plug, and a third conductive plug are formed in the interlayer dielectric layer, wherein the bottom of the first conductive plug is connected to the electrode layer, the bottom of the second conductive plug is connected to the source region, and the bottom of the third conductive plug is connected to the drain region.
[0021] A first conductive layer, a second conductive layer, and a third conductive layer are formed on the interlayer dielectric layer. The first conductive layer is electrically connected to the electrode layer through a first conductive plug, the second conductive layer is electrically connected to the source region through a second conductive plug, and the third conductive layer is electrically connected to the drain region through a third conductive plug.
[0022] For example, the thickness of the ferroelectric dielectric layer ranges from 30 angstroms to 150 angstroms.
[0023] Exemplarily, the substrate further includes an isolation region surrounding the active region, wherein a shallow trench isolation structure is formed in the isolation region, and the method further includes:
[0024] Shallow trenches are formed by etching a certain depth from the surface of the substrate.
[0025] A silicon oxide layer is formed within the shallow trench to form a shallow trench isolation structure.
[0026] Another aspect of this application provides a semiconductor device, comprising:
[0027] A substrate having a first conductivity type, including an active region;
[0028] A trench located in the active region and extending from the surface of the substrate into the substrate;
[0029] A ferroelectric dielectric layer covers the bottom and sidewalls of the trench and a portion of the surface of the active region along a first direction;
[0030] An electrode layer that fills the remaining portion of the trench and covers the ferroelectric dielectric layer located on the surface of the active region;
[0031] A source region and a drain region having a second conductivity type are located in the active region and are respectively located on both sides of the trench along a first direction.
[0032] For example, it also includes:
[0033] A doped region having a first conductivity type is located in the substrate, the doped region adhering to the bottom and sidewalls of the trench and to a portion of the surface of the active region along the first direction, the doping concentration of the doped region being greater than or less than the doping concentration of the substrate, and the ends of the source and drain regions contacting the doped region; and / or
[0034] An isolation dielectric layer covers the bottom and sidewalls of the trench and a portion of the surface of the active region along a first direction; the ferroelectric dielectric layer covers the isolation dielectric layer; and / or
[0035] An adhesive layer covers the ferroelectric dielectric layer, and the electrode layer covers the adhesive layer.
[0036] For example, it also includes:
[0037] An interlayer dielectric layer covers the surface of the substrate;
[0038] A first conductive plug, a second conductive plug, and a third conductive plug penetrate the interlayer dielectric layer, wherein the bottom of the first conductive plug is connected to the electrode layer, the bottom of the second conductive plug is connected to the source region, and the bottom of the third conductive plug is connected to the drain region.
[0039] A first conductive layer, a second conductive layer, and a third conductive layer are located on the interlayer dielectric layer, wherein the first conductive layer is electrically connected to the electrode layer through the first conductive plug, the second conductive layer is electrically connected to the source region through the second conductive plug, and the third conductive layer is electrically connected to the drain region through the third conductive plug.
[0040] For example, the substrate further includes an isolation region surrounding the active region, wherein a shallow trench isolation structure is formed in the isolation region, and the doped region is attached to a portion of the surface of the shallow trench isolation structure along a second direction, the second direction being perpendicular to the first direction.
[0041] For example, the substrate further includes an isolation region surrounding the active region, wherein a shallow trench isolation structure is formed in the isolation region, and the ferroelectric layer covers a portion of the surface of the shallow trench isolation structure along a second direction perpendicular to the first direction.
[0042] For example, the substrate further includes an isolation region surrounding the active region, wherein a shallow trench isolation structure is formed in the isolation region, and the isolation dielectric layer covers a portion of the surface of the shallow trench isolation structure along a second direction perpendicular to the first direction.
[0043] The semiconductor device and manufacturing method of the present application form a trench in the active region, and form a ferroelectric dielectric layer and an electrode layer in the trench and on a portion of the surface of the active region. By utilizing the spontaneous polarization characteristics of the ferroelectric dielectric layer and combining it with the reversal of the external electric field generated by the voltage applied to the electrode layer, the turn-on voltage difference of the channel between the source and drain regions is controlled, thereby realizing non-volatile storage and fast read / write operations. This is equivalent to integrating a ferroelectric capacitor into a transistor, thereby improving the integration density of the device. Attached Figure Description
[0044] The following drawings, which are incorporated herein by reference and are used to understand this application, illustrate embodiments of the invention and their descriptions to explain the principles of the invention.
[0045] In the attached image:
[0046] Figure 1 shows a flowchart of a method for manufacturing a semiconductor device according to an exemplary embodiment of this application;
[0047] Figures 2A-2I show schematic cross-sectional views of a semiconductor device obtained by sequentially implementing a method for manufacturing a semiconductor device according to an exemplary embodiment of this application, along a first direction.
[0048] Figure 3 shows a schematic cross-sectional view along a second direction of a semiconductor device obtained by sequentially implementing a semiconductor device manufacturing method according to an exemplary embodiment of this application.
[0049] Figure 4 shows a top view schematic diagram of a semiconductor device obtained by sequentially implementing a semiconductor device manufacturing method according to an exemplary embodiment of this application. Detailed Implementation
[0050] The present application will now be described more fully with reference to the accompanying drawings, in which embodiments of the present application are illustrated. However, the present application can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the present application to those skilled in the art. In the drawings, for clarity, the dimensions and relative dimensions of layers and regions may be exaggerated. The same reference numerals denote the same elements throughout.
[0051] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this application, the first element, component, area, layer, or portion discussed below may be referred to as the second element, component, area, layer, or portion.
[0052] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “under” the other element or feature will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.
[0053] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.
[0054] Embodiments of the application are described herein with reference to cross-sectional views illustrating ideal embodiments (and intermediate structures). Thus, variations from the shapes shown can be anticipated due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the application should not be limited to the specific shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing processes. For example, implantation regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implantation regions to non-implantation regions. Similarly, buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes are not intended to show the actual shapes of the regions of the device and are not intended to limit the scope of the application.
[0055] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art. It will also be understood that terms as defined in commonly used dictionaries shall be interpreted as having a meaning consistent with their meaning in the relevant field and / or the context of this specification, and not as in an ideal or overly formal sense, unless expressly defined herein.
[0056] To fully understand this application, detailed steps and structures will be presented in the following description to illustrate the technical solutions proposed in this application. Preferred embodiments of this application are described in detail below; however, in addition to these detailed descriptions, this application may have other implementation methods.
[0057] Therefore, in view of the aforementioned technical problems, this application proposes a method for manufacturing a semiconductor device, as shown in Figure 1, which mainly includes the following steps:
[0058] Step S1, providing a substrate having a first conductivity type, the substrate including an active region;
[0059] Step S2, etching the active region to form a trench in the active region;
[0060] Step S3: Form a ferroelectric dielectric layer that covers the bottom and sidewalls of the trench and a portion of the surface of the active region along the first direction;
[0061] Step S4, forming an electrode layer that fills the remaining portion of the trench and covers the ferroelectric layer located on the surface of the active region;
[0062] Step S5: A source region and a drain region having a second conductivity type are formed in the active region, and the source region and the drain region are located on both sides of the trench along a first direction.
[0063] The semiconductor device manufacturing method of this application forms a trench in the active region and forms a ferroelectric dielectric layer and an electrode layer in the trench and on a portion of the surface of the active region. By utilizing the spontaneous polarization characteristics of the ferroelectric dielectric layer and combining it with the reversal of the external electric field generated by the voltage applied to the electrode layer, the turn-on voltage difference between the source and drain regions of the channel is controlled, thereby achieving non-volatile storage and fast read / write operations. This is equivalent to integrating a ferroelectric capacitor into a transistor, thereby improving the integration density of the device.
[0064] Example 1
[0065] The manufacturing method of the semiconductor device of this application will now be described in detail with reference to Figures 1 to 4. Figure 1 shows a flowchart of the manufacturing method of the semiconductor device according to an exemplary embodiment of this application. Figures 2A-2I show cross-sectional schematic diagrams of the semiconductor device obtained by sequentially implementing the manufacturing method of the semiconductor device according to an exemplary embodiment of this application along a first direction. Figure 3 shows cross-sectional schematic diagrams of the semiconductor device obtained by sequentially implementing the manufacturing method of the semiconductor device according to an exemplary embodiment of this application along a second direction. Figure 4 shows a top view schematic diagram of the semiconductor device obtained by sequentially implementing the manufacturing method of the semiconductor device according to an exemplary embodiment of this application.
[0066] For example, the method for manufacturing the semiconductor device of this application includes the following steps:
[0067] First, step S1 is performed, providing a substrate having a first conductivity type, the substrate including an active region.
[0068] The semiconductor device can be any suitable type of device known to those skilled in the art. In this embodiment, the technical solution of the present invention is explained and illustrated mainly by taking the case of the semiconductor device being a ferroelectric memory as an example.
[0069] In one example, as shown in Figure 2A, the substrate 200 is a bulk silicon substrate, which may be at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, InGaAs and other III / V compound semiconductors, or the substrate 200 may include a multilayer structure composed of these semiconductors, or the substrate 200 may be silicon-on-insulator (SOI), silicon-on-insulator stacked (SSOI), silicon-on-insulator stacked germanium (S-SiGeOI), silicon-on-insulator (SiGeOI), and germanium-on-insulator (GeOI), etc.
[0070] In one example, as shown in Figures 2A, 3, and 4, the substrate 200 includes an active region 2001. More specifically, the substrate 200 also includes an isolation region 2002 surrounding the active region 2001, wherein a shallow trench isolation structure 201 is formed in the isolation region 2002. Exemplarily, forming the shallow trench isolation structure 201 may include the following steps: etching a certain depth of the substrate 200 from its surface to form a shallow trench; and forming a silicon oxide layer within the shallow trench to form the shallow trench isolation structure 201.
[0071] In one example, the first conductivity type can be either N-type or P-type.
[0072] Next, step S2 is performed, as shown in Figure 2B, to etch the active region 2001 to form a trench 202 in the active region 2001.
[0073] In one example, various etching processes conventional in the art (e.g., wet or dry etching processes) can be used to etch a portion of the active region 2001 to form a trench 202 in the active region 2001. The width and depth of the trench 202 should be reasonably set according to actual needs.
[0074] In one example, as shown in FIG2C, after etching the active region 2001 to form a trench 202 in the active region 2001, the step further includes forming a doped region 203 having a first conductivity type in the substrate 200. The doped region 203 is attached to the bottom and sidewalls of the trench 202 and to a portion of the surface of the active region 2001 along a first direction X. The doping concentration of the doped region 203 is greater than or less than the doping concentration of the substrate 200, and the ends of the subsequently formed source region 208 and drain region 209 contact the doped region 203 (as seen in FIG2H and FIG2I, the right end of the source region 208 and the left end of the drain region 209 contact the doped region 203 attached to the surface of the active region 2001). For example, the doped region 203 is located at the position where the channel is formed between the source region 208 and the drain region 209. By forming a doped region 203 with a doping concentration greater than or less than that of the substrate 200 (here, the doping concentration of the substrate 200 is the doping concentration at the substrate 200 where the channel is originally formed), the external electric field strength required for channel conduction can be easily adjusted. For example, the doped region 203 can be formed by diffusion or ion implantation processes, or any other suitable process can be used, which is not limited in this application. For example, as shown in FIG3, the doped region 203 can also be attached to a portion of the surface of the isolation region 2002 along the second direction Y. Specifically, the doped region 203 can also be attached to a portion of the surface of the shallow trench isolation structure 201 along the second direction Y. For example, as shown in FIG2H, the first direction X is the arrangement direction of the source region 208, the trench 202 and the drain region 209 (that is, the first direction X is the direction of the line connecting the source region 208 and the drain region 209), and the source region 208, the trench 202 and the drain region 209 are arranged sequentially in the first direction X; as shown in FIG4, the second direction Y is perpendicular to the first direction X.
[0075] Next, step S3 is performed, as shown in FIG2E, to form a ferroelectric dielectric layer 205. The ferroelectric dielectric layer 205 covers the bottom and sidewalls of the trench 202 and covers part of the surface of the active region 2001 along the first direction X.
[0076] In one example, various deposition methods commonly used in the art can be employed to form the ferroelectric dielectric layer 205. For example, it can be formed using chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD). Exemplarily, the ferroelectric dielectric layer 205 is made of zirconium-doped hafnium oxide, wherein the doping ratio of zirconium, hafnium, and oxygen is approximately 0.5 / 0.5 / 2. Zirconium-doped hafnium oxide (HZO, Hf) 1-x Zr x Hafnium oxide (HfO) is an extension of hafnium oxide (HfO)-based ferroelectric materials and is a novel type of ferroelectric material. Compared to traditional ferroelectric materials, the components of HfO... 1-x Zr xHafnium dioxide (HfO2) and zirconium dioxide (ZrO2) of O2 have been applied to the gate oxide of MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) and the dielectric layer of DRAMs (Dynamic Random Access Memory). Therefore, HZO ferroelectric materials are well compatible with CMOS (Complementary Metal-Oxide-Semiconductor) processes and exhibit strong ferroelectricity even at ultra-thin thicknesses of around 10 nm, demonstrating excellent scalability. For example, the thickness of the ferroelectric dielectric layer 205 can range from 30 angstroms to 150 angstroms, or it can be any other suitable thickness range. For example, as shown in FIG3, the ferroelectric dielectric layer 205 can also cover a portion of the surface of the isolation region 2002 along the second direction Y. Specifically, the ferroelectric dielectric layer 205 can also cover a portion of the surface of the shallow trench isolation structure 201 along the second direction Y.
[0077] In one example, as shown in FIG2D, after forming trench 202 and before forming ferroelectric layer 205, the step of forming isolation dielectric layer 204 is included. Isolation dielectric layer 204 covers the bottom and sidewalls of trench 202 and covers a portion of the surface of active region 2001 along a first direction X. Ferroelectric layer 205 covers isolation dielectric layer 204. Exemplarily, as shown in FIG3, isolation dielectric layer 204 may also cover a portion of the surface of isolation region 2002 along a second direction Y. Specifically, isolation dielectric layer 204 may also cover a portion of the surface of shallow trench isolation structure 201 along the second direction Y. Exemplarily, doped region 203 is formed first, and then isolation dielectric layer 204 is formed.
[0078] In one example, the isolation dielectric layer 204 serves as an isolation layer and can be used to improve the interface states between the substrate 200 and the ferroelectric dielectric layer 205, thereby reducing defects and improving device reliability. Exemplarily, the isolation dielectric layer 204 can be formed using various deposition methods commonly used in the art, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD). Exemplarily, the material of the isolation dielectric layer 204 includes silicon dioxide, silicon oxynitride, hafnium dioxide, or titanium oxide, or any other suitable material. Exemplarily, the thickness of the isolation dielectric layer 204 ranges from 1 angstrom to 100 angstroms, or any other suitable thickness range.
[0079] Next, step S4 is performed, as shown in FIG2G, to form an electrode layer 207. The electrode layer 207 fills the remaining portion of the trench 202 and covers the ferroelectric layer 205 located on the surface of the active region 2001.
[0080] In one example, the electrode layer 207 can be formed using various deposition methods commonly used in the art, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD). Exemplarily, the electrode layer 207 may be made of copper, tungsten, or doped polycrystalline silicon, or any other suitable material. Exemplarily, as shown in Figures 3 and 4, the electrode layer 207 may also extend to the isolation region 2002.
[0081] In one example, as shown in FIG2F, after forming the ferroelectric layer 205 and before forming the electrode layer 207, the step of forming an adhesion layer 206 is included. The adhesion layer 206 covers the ferroelectric layer 205, and the electrode layer 207 covers the adhesion layer 206. Exemplarily, the adhesion layer 206 is a metal layer with a suitable work function, and the material of the adhesion layer 206 includes, but is not limited to, titanium nitride, tantalum nitride, platinum, rubidium, etc. Exemplarily, as shown in FIG3, the adhesion layer 206 may also extend into the isolation region 2002.
[0082] Next, step S5 is executed, as shown in FIG2H, forming a source region 208 and a drain region 209 having a second conductivity type in the active region 2001. The source region 208 and the drain region 209 are located on both sides of the trench 202 along the first direction X. Exemplarily, the second conductivity type is a P-type or an N-type conductivity type, and the second conductivity type and the first conductivity type belong to different conductivity types. For example, the first conductivity type is an N-type conductivity type and the second conductivity type is a P-type conductivity type, or the first conductivity type is a P-type conductivity type and the second conductivity type is an N-type conductivity type. Exemplarily, both the source region 208 and the drain region 209 can be heavily doped regions, for example, both can be heavily doped N-type regions.
[0083] In one example, ion implantation can be performed on the surface of the active region 2001 to form a source region 208 and a drain region 209 extending from the surface of the substrate 200 into the substrate 200. Exemplarily, the ends of the source region 208 and the drain region 209 contact the ferroelectric layer 205; specifically, the ends of the source region 208 and the drain region 209 contact the ferroelectric layer 205 located on the surface of the active region 2001. Exemplarily, when an isolation dielectric layer 204 is formed, the ends of the source region 208 and the drain region 209 contact the isolation dielectric layer 204; specifically, the ends of the source region 208 and the drain region 209 contact the isolation dielectric layer 204 located on the surface of the active region 2001. Exemplarily, when a doped region 203 is formed, the ends of the source region 208 and the drain region 209 contact the doped region 203; specifically, the ends of the source region 208 and the drain region 209 contact the doped region 203 attached to the surface of the active region 2001.
[0084] In one example, as shown in Figures 3 and 4, the trench 202 penetrates the active region 2001 along the second direction Y and connects to the isolation regions 2002 located on both sides of the active region 2001 along the second direction Y, wherein the second direction Y is perpendicular to the first direction X. Exemplarily, the trench 202 penetrating the active region 2001 along the second direction Y effectively avoids channel loss and prevents the formation of conductive channels in areas not covered by the trench 202, thus preventing device failure. Exemplarily, when the trench 202 penetrates the active region 2001 along the second direction Y, the doped region 203 adheres to the bottom and sidewalls of the trench 202, including: the doped region 203 adheres to the bottom of the trench 202 within the active region 2001, the sidewalls within the active region 2001, and the sidewalls within the isolation regions 2002.
[0085] In one example, as shown in FIG2I, after forming a source region 208 and a drain region 209 having a second conductivity type in the active region 2001, the method of this application further includes: forming an interlayer dielectric layer 210; forming a first conductive plug 211, a second conductive plug 212, and a third conductive plug 213 penetrating the interlayer dielectric layer 210; and forming a first conductive layer 214, a second conductive layer 215, and a third conductive layer 216 on the interlayer dielectric layer 210. The interlayer dielectric layer 210 covers the surface of the substrate 200 and also covers the electrode layer 207. The bottom of the first conductive plug 211 is connected to the electrode layer 207, the bottom of the second conductive plug 212 is connected to the source region 208, and the bottom of the third conductive plug 213 is connected to the drain region 209. The first conductive layer 214 is electrically connected to the electrode layer 207 through the first conductive plug 211, the second conductive layer 215 is electrically connected to the source region 208 through the second conductive plug 212, and the third conductive layer 216 is electrically connected to the drain region 209 through the third conductive plug 213.
[0086] In one example, the interlayer dielectric layer 210 can be formed using various deposition methods commonly used in the art, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD). Exemplarily, the material of the interlayer dielectric layer 210 can be insulating materials such as silicon oxide, fluorocarbons, carbon-doped silicon oxide, or silicon carbonitride. This application is not limited to this. Taking silicon oxide as an example, the interlayer dielectric layer 210 can include a layer of doped or undoped silicon oxide, such as undoped silicon glass (USG), silicon phosphosilicate glass (PSG), or borosilicate glass (BPSG). Exemplarily, after forming the interlayer dielectric layer 210, the method further includes planarizing the interlayer dielectric layer 210. Exemplarily, non-limiting examples of this planarization method include mechanical planarization or chemical mechanical polishing planarization.
[0087] In one example, forming a first conductive plug 211, a second conductive plug 212, and a third conductive plug 213 penetrating the interlayer dielectric layer 210 includes: etching the interlayer dielectric layer 210 to form a through-hole penetrating the interlayer dielectric layer 210, and filling the through-hole with a conductive material to form the first conductive plug 211, the second conductive plug 212, and the third conductive plug 213. Exemplarily, the materials of the first conductive plug 211, the second conductive plug 212, and the third conductive plug 213 may include, but are not limited to, metals or alloys such as copper and aluminum.
[0088] In one example, various deposition methods commonly used in the art can be employed to form the first conductive layer 214, the second conductive layer 215, and the third conductive layer 216. For example, the first conductive layer 214 can be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD). The second conductive layer 215 can be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD). The third conductive layer 216 can be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD). Exemplarily, the materials of the first conductive layer 214, the second conductive layer 215, and the third conductive layer 216 can all include various conventional metals or alloys, and this application does not impose any limitations on this. For example, the first conductive layer 214 serves as a word line (WL) to lead out the electrode layer 207; the second conductive layer 215 serves as a source line (SL) to lead out the source region 208; and the third conductive layer 216 serves as a bit line (BL) to lead out the drain region 209.
[0089] In one example, the trench 202 of this application can increase the length of the channel between the source region 208 and the drain region 209 in the vertical direction, thereby improving the integration density of the device in the horizontal direction and effectively avoiding the short-channel effect and reducing the leakage current of the device. For example, when the electrode layer 207 is made of ferroelectric electrode material (e.g., copper, tungsten), the mismatch problem between traditional gate materials and ferroelectric materials can be effectively solved.
[0090] In one example, taking a write operation as an example, a bias voltage is applied to electrode layer 207 via WL. This bias voltage generates an electric field (a positive or negative bias voltage exceeding the coercive electric field of the ferroelectric material in ferroelectric dielectric layer 205 is applied to electrode layer 207, at which point BL and SL are at the same potential). The ferroelectric material in ferroelectric dielectric layer 205 possesses ferroelectric properties and forms different ferroelectric domains under positive and negative electric fields (i.e., the ferroelectric material has spontaneous polarization). These ferroelectric domains do not disappear when the external electric field is removed, thereby achieving non-volatile storage. The two different polarization states of ferroelectric dielectric layer 205 cause the transistor to generate different threshold voltages (i.e., the turn-on voltage of the channel between source region 208 and drain region 209). For example, taking a read operation as an example, a bias voltage is applied to electrode layer 207 via WL to control the channel's on / off state, and the drain current is measured (e.g., by measuring the drain current via BL) to complete the read operation.
[0091] This concludes the description of the key steps in the semiconductor device manufacturing method of this application. Other steps may also be included in the complete semiconductor device fabrication process, which will not be elaborated here. It is worth mentioning that the order of the above steps can be adjusted without conflict.
[0092] In summary, the semiconductor device manufacturing method of this application embodiment forms a trench in the active region 2001, and forms a ferroelectric dielectric layer and an electrode layer in the trench and on a portion of the surface of the active region 2001. By utilizing the spontaneous polarization characteristics of the ferroelectric dielectric layer and combining it with the reversal of the external electric field generated by the voltage applied to the electrode layer, the turn-on voltage difference of the channel between the source and drain regions is controlled, thereby achieving non-volatile storage and fast read / write operations. This is equivalent to integrating a ferroelectric capacitor into a transistor, thereby improving the integration density of the device.
[0093] Example 2
[0094] This application also provides a semiconductor device, which is prepared by the method described in the first embodiment above. Exemplarily, a semiconductor device according to an exemplary embodiment of this application will be described below with reference to Figures 2A-2I, Figure 3, and Figure 4. The semiconductor device of this application includes a substrate 200 having a first conductivity type, a trench 202, a ferroelectric layer 205, an electrode layer 207, and a source region 208 and a drain region 209 having a second conductivity type.
[0095] The substrate 200 includes an active region 2001.
[0096] The trench 202 is located in the active region 2001 and extends from the surface of the substrate 200 into the substrate 200.
[0097] The ferroelectric dielectric layer 205 covers the bottom and sidewalls of the trench 202 and covers part of the surface of the active region 2001 along the first direction X.
[0098] Electrode layer 207 fills the remaining portion of trench 202 and covers ferroelectric layer 205 located on the surface of active region 2001.
[0099] The source region 208 and the drain region 209 are located in the active region 2001 and are located on both sides of the trench 202 along the first direction X.
[0100] The semiconductor device can be any suitable type of device known to those skilled in the art. In this embodiment, the technical solution of the present invention is explained and illustrated mainly by taking the case of the semiconductor device being a ferroelectric memory as an example.
[0101] In one example, the first conductivity type is N-type conductivity type and the second conductivity type is P-type conductivity type, or the first conductivity type is P-type conductivity type and the second conductivity type is N-type conductivity type.
[0102] In one example, the trench 202 of this application can increase the length of the channel between the source region 208 and the drain region 209 in the vertical direction, thereby improving the integration density of the device in the horizontal direction and effectively avoiding the short-channel effect and reducing the leakage current of the device. For example, when the electrode layer 207 is made of ferroelectric electrode material (e.g., copper, tungsten), the mismatch problem between traditional gate materials and ferroelectric materials can be effectively solved.
[0103] In one example, as shown in Figures 3 and 4, the trench 202 penetrates the active region 2001 along the second direction Y and connects the isolation regions 2002 located on both sides of the active region 2001 along the second direction Y, wherein the second direction Y is perpendicular to the first direction X. Exemplarily, the trench 202 penetrating the active region 2001 along the second direction Y effectively avoids channel loss and prevents the formation of conductive channels in areas not covered by the trench 202, thus preventing device failure.
[0104] In one example, the substrate 200 further includes an isolation region 2002 surrounding the active region 2001, wherein a shallow trench isolation structure 201 is formed in the isolation region 2002. Exemplarily, as shown in FIG3, the ferroelectric layer 205 and the electrode layer 207 may also cover a portion of the surface of the isolation region 2002. Specifically, the ferroelectric layer 205 and the electrode layer 207 may also cover a portion of the surface of the shallow trench isolation structure 201 along the second direction Y.
[0105] In one example, as shown in FIG2I, the semiconductor device of this application further includes a doped region 203 having a first conductivity type. The doped region 203 is located in the substrate 200. The doped region 203 is attached to the bottom and sidewalls of the trench 202 and to a portion of the surface of the active region 2001 along the first direction X. The doping concentration of the doped region 203 is greater than or less than the doping concentration of the substrate 200, and the ends of the source region 208 and the drain region 209 contact the doped region 203 (as seen in FIG2H and FIG2I, the right end of the source region 208 and the left end of the drain region 209 contact the doped region 203 attached to the surface of the active region 2001). Exemplarily, the location of the doped region 203 is the location where the channel between the source region and the drain region is formed. By forming a doped region 203 with a doping concentration greater than or less than the doping concentration of the substrate 200 (here, the doping concentration of the substrate 200 is the doping concentration at the substrate 200 where the channel is originally formed), the external electric field strength required for channel conduction can be easily adjusted. For example, as shown in FIG3, the doped region 203 may also be attached to a portion of the surface of the isolation region 2002 along the second direction Y. Specifically, the doped region 203 may also be attached to a portion of the surface of the shallow trench isolation structure 201 along the second direction Y.
[0106] In one example, as shown in FIG2I, the semiconductor device of this application further includes an isolation dielectric layer 204. The isolation dielectric layer 204 covers the bottom and sidewalls of the trench 202 and covers a portion of the surface of the active region 2001 along a first direction X. A ferroelectric dielectric layer 205 covers the isolation dielectric layer 204. Exemplarily, the isolation dielectric layer 204 serves as an isolation layer and can be used to improve the interface states between the substrate 200 and the ferroelectric dielectric layer 205 to reduce defects and thus improve the reliability of the device. Exemplarily, the ends of the source region 208 and the drain region 209 contact the isolation dielectric layer 204. Exemplarily, as shown in FIG3, the isolation dielectric layer 204 may also cover a portion of the surface of the isolation region 2002 along a second direction Y. Specifically, the isolation dielectric layer 204 may also cover a portion of the surface of the shallow trench isolation structure 201 along the second direction Y. Exemplarily, the material of the isolation dielectric layer 204 includes silicon dioxide, silicon oxynitride, hafnium dioxide, or titanium oxide, or any other suitable material. For example, the thickness of the insulating dielectric layer 204 ranges from 1 angstrom to 100 angstroms, or it may be any other suitable thickness range.
[0107] In one example, as shown in FIG2I, the semiconductor device of this application further includes an adhesive layer 206. The adhesive layer 206 covers the ferroelectric dielectric layer 205, and the electrode layer 207 covers the adhesive layer 206. Exemplarily, the adhesive layer 206 is a metal layer with a suitable work function, and the material of the adhesive layer 206 includes, but is not limited to, titanium nitride, tantalum nitride, platinum, rubidium, etc.
[0108] In one example, as shown in FIG2I, the semiconductor device of this application further includes an interlayer dielectric layer 210, a first conductive plug 211, a second conductive plug 212, a third conductive plug 213, a first conductive layer 214, a second conductive layer 215, and a third conductive layer 216. The interlayer dielectric layer 210 covers the surface of the substrate 200. The first conductive plug 211, the second conductive plug 212, and the third conductive plug 213 penetrate the interlayer dielectric layer 210, wherein the bottom of the first conductive plug 211 is connected to the electrode layer 207, the bottom of the second conductive plug 212 is connected to the source region 208, and the bottom of the third conductive plug 213 is connected to the drain region 209. The first conductive layer 214, the second conductive layer 215, and the third conductive layer 216 are located on the interlayer dielectric layer 210. The first conductive layer 214 is electrically connected to the electrode layer 207 through the first conductive plug 211, the second conductive layer 215 is electrically connected to the source region 208 through the second conductive plug 212, and the third conductive layer 216 is electrically connected to the drain region 209 through the third conductive plug 213.
[0109] In one example, the first conductive layer 214 serves as a word line (WL) to bring out the electrode layer 207. The second conductive layer 215 serves as a source line (SL) to bring out the source region 208. The third conductive layer 216 serves as a bit line (BL) to bring out the drain region 209.
[0110] In one example, taking a write operation as an example, a bias voltage is applied to electrode layer 207 via WL. This bias voltage generates an electric field (a positive or negative bias voltage exceeding the coercive electric field of the ferroelectric material in ferroelectric dielectric layer 205 is applied to electrode layer 207, at which point BL and SL are at the same potential). The ferroelectric material in ferroelectric dielectric layer 205 possesses ferroelectric properties and forms different ferroelectric domains under positive and negative electric fields (i.e., the ferroelectric material has spontaneous polarization). These ferroelectric domains do not disappear when the external electric field is removed, thereby achieving non-volatile storage. The two different polarization states of ferroelectric dielectric layer 205 cause the transistor to generate different threshold voltages (i.e., the turn-on voltage of the channel between source region 208 and drain region 209). For example, taking a read operation as an example, a bias voltage is applied to electrode layer 207 via WL to control the channel's on / off state, and the drain current is measured (e.g., by measuring the drain current via BL) to complete the read operation.
[0111] This concludes the introduction to the structure of the semiconductor device of the present invention. The complete device may also include other components, which will not be described in detail here.
[0112] In summary, the semiconductor device of this application embodiment has a trench formed in the active region, and a ferroelectric dielectric layer and an electrode layer formed in the trench and on a portion of the surface of the active region. By utilizing the spontaneous polarization characteristics of the ferroelectric dielectric layer and combining it with the reversal of the external electric field generated by the voltage applied to the electrode layer, the difference in the turn-on voltage of the channel between the source and drain regions is controlled, thereby achieving non-volatile storage and fast read / write operations. This is equivalent to integrating a ferroelectric capacitor into a transistor, thereby improving the integration density of the device.
[0113] Although several embodiments have been described herein, it should be understood that many other modifications and embodiments will arise in the mind of those skilled in the art, all of which will fall within the spirit and scope of the concept disclosed herein. More specifically, various modifications and changes may be made in terms of the arrangement and / or components of the subject matter within the scope of this disclosure, the drawings, and the appended claims. In addition to modifications and changes in the components and / or arrangement, the use of alternative methods will also be obvious to those skilled in the art.
Claims
1. A method of manufacturing a semiconductor device, characterized by, include: A substrate having a first conductivity type is provided, the substrate including an active region; The active region is etched to form trenches in the active region; A ferroelectric dielectric layer is formed, which covers the bottom and sidewalls of the trench and a portion of the surface of the active region along a first direction; An electrode layer is formed, which fills the remaining portion of the trench and covers the ferroelectric layer located on the surface of the active region; A source region and a drain region having a second conductivity type are formed in the active region, and the source region and the drain region are respectively located on both sides of the trench along a first direction.
2. The manufacturing method according to claim 1, characterized by, The trench penetrates the active region along a second direction, which is perpendicular to the first direction.
3. The production method according to claim 1, characterized by After etching the active region to form a trench in the active region, the method further includes the step of forming a doped region having a first conductivity type in the substrate, the doped region being attached to the bottom and sidewalls of the trench and to a portion of the surface of the active region along the first direction, the doping concentration of the doped region being greater than or less than the doping concentration of the substrate, and the ends of the source and drain regions contacting the doped region.
4. The production method according to claim 1, characterized by After forming the trench and before forming the ferroelectric dielectric layer, the step further includes forming an isolation dielectric layer that covers the bottom and sidewalls of the trench and covers a portion of the surface of the active region along a first direction, the ferroelectric dielectric layer covering the isolation dielectric layer.
5. The manufacturing method according to claim 4, wherein The material of the isolation dielectric layer includes silicon dioxide, silicon oxynitride, hafnium dioxide or titanium oxide, and / or the thickness of the isolation dielectric layer ranges from 1 angstrom to 100 angstroms.
6. The production method according to claim 1, wherein After forming the ferroelectric dielectric layer and before forming the electrode layer, the step further includes forming an adhesion layer that covers the ferroelectric dielectric layer and the electrode layer that covers the adhesion layer.
7. The production method according to claim 1, wherein After forming a source region and a drain region having a second conductivity type in the active region, the method further includes: An interlayer dielectric layer is formed, which covers the surface of the substrate; A first conductive plug, a second conductive plug, and a third conductive plug are formed in the interlayer dielectric layer, wherein the bottom of the first conductive plug is connected to the electrode layer, the bottom of the second conductive plug is connected to the source region, and the bottom of the third conductive plug is connected to the drain region. A first conductive layer, a second conductive layer, and a third conductive layer are formed on the interlayer dielectric layer. The first conductive layer is electrically connected to the electrode layer through a first conductive plug, the second conductive layer is electrically connected to the source region through a second conductive plug, and the third conductive layer is electrically connected to the drain region through a third conductive plug.
8. The production method according to claim 1, wherein The thickness of the ferroelectric dielectric layer ranges from 30 angstroms to 150 angstroms.
9. The production method according to claim 1, wherein The substrate further includes an isolation region surrounding the active region, wherein a shallow trench isolation structure is formed in the isolation region, and the method further includes: Shallow trenches are formed by etching a certain depth from the surface of the substrate. A silicon oxide layer is formed within the shallow trench to form a shallow trench isolation structure.
10. A semiconductor device, characterized by comprising: include: A substrate having a first conductivity type, including an active region; A trench located in the active region and extending from the surface of the substrate into the substrate; A ferroelectric dielectric layer covers the bottom and sidewalls of the trench and a portion of the surface of the active region along a first direction; An electrode layer that fills the remaining portion of the trench and covers the ferroelectric dielectric layer located on the surface of the active region; A source region and a drain region having a second conductivity type are located in the active region and are respectively located on both sides of the trench along a first direction.
11. The semiconductor device of claim 10, wherein, Also includes: A doped region having a first conductivity type is located in the substrate, the doped region is attached to the bottom and sidewalls of the trench and to a portion of the surface of the active region along the first direction, the doping concentration of the doped region is greater than or less than the doping concentration of the substrate, and the ends of the source and drain regions are in contact with the doped region; and / or An isolation dielectric layer covers the bottom and sidewalls of the trench and a portion of the surface of the active region along a first direction; the ferroelectric dielectric layer covers the isolation dielectric layer. and / or An adhesive layer covers the ferroelectric dielectric layer, and the electrode layer covers the adhesive layer.
12. The semiconductor device of claim 10, wherein, Also includes: An interlayer dielectric layer covers the surface of the substrate; A first conductive plug, a second conductive plug, and a third conductive plug penetrate the interlayer dielectric layer, wherein the bottom of the first conductive plug is connected to the electrode layer, the bottom of the second conductive plug is connected to the source region, and the bottom of the third conductive plug is connected to the drain region. A first conductive layer, a second conductive layer, and a third conductive layer are located on the interlayer dielectric layer, wherein the first conductive layer is electrically connected to the electrode layer through the first conductive plug, the second conductive layer is electrically connected to the source region through the second conductive plug, and the third conductive layer is electrically connected to the drain region through the third conductive plug.
13. The semiconductor device of claim 11, wherein, The substrate further includes an isolation region surrounding the active region, wherein a shallow trench isolation structure is formed in the isolation region, and the doped region is attached to a portion of the surface of the shallow trench isolation structure along a second direction, the second direction being perpendicular to the first direction.
14. The semiconductor device of claim 10, wherein, The substrate further includes an isolation region surrounding the active region, wherein a shallow trench isolation structure is formed in the isolation region, and the ferroelectric layer covers a portion of the surface of the shallow trench isolation structure along a second direction, the second direction being perpendicular to the first direction.
15. The semiconductor device of claim 11, wherein, The substrate further includes an isolation region surrounding the active region, wherein a shallow trench isolation structure is formed in the isolation region, and the isolation dielectric layer covers a portion of the surface of the shallow trench isolation structure along a second direction, the second direction being perpendicular to the first direction.