Circuit arrangement for activating a half-bridge circuit
The integrated circuit with edge detection and sequential control signals addresses microcontroller failures in half-bridge circuits, ensuring reliable shutdown of gate drivers, enhancing reliability and robustness against voltage fluctuations.
Patent Information
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- SCHAEFFLER TECHNOLOGIES AG & CO KG
- Filing Date
- 2025-11-05
- Publication Date
- 2026-05-21
AI Technical Summary
Existing half-bridge circuits in power electronics, particularly in automotive applications, face reliability issues due to microcontroller failures from over- or undervoltage, leading to asynchronous interventions that can cause destructive short circuits in the current path, necessitating a reliable shutdown mechanism for high-side and low-side gate drivers.
A circuit arrangement with an integrated monitoring device and signal processing unit generates sequential shutdown/enable signals for high-side and low-side gate drivers, using edge detection and adjustable time delays to ensure controlled shutdown and enablement, independent of supply voltage fluctuations, and includes a self-test mechanism to verify functionality.
The solution provides enhanced reliability and robustness against voltage faults, ensuring safe and controlled shutdown of gate drivers, reducing failure rates and enabling precise time delays without additional testing effort.
Smart Images
Figure DE2025101024_21052026_PF_FP_ABST
Abstract
Description
[0001] 202400371
[0002] 1
[0003] Description
[0004] Circuit arrangement for controlling a half-bridge circuit
[0005] The present invention relates to a circuit arrangement for controlling a half-bridge circuit and to the use of such a circuit arrangement.
[0006] In the field of power electronics, for example in power converters (e.g.
[0007] DC / DC converters or DC / AC converters often use controllable half-bridge circuits with one or more half-bridges, each consisting of a series connection of two controllable semiconductor switches (high-side FET switch and low-side FET switch) supplied with a supply voltage, in order to provide a respective output voltage at an output node between the two semiconductor switches.
[0008] Such a half-bridge can be operated, for example, using PWM control (or another modulation method) to switch the two FET switches on and off in a complementary manner. When the half-bridge is supplied with a DC voltage applied to the series connection of the FET switches, an AC voltage is provided at the output node according to the control method (e.g., PWM control). With several half-bridges operated in parallel, the individual phase voltages and resulting phase currents required for a multi-phase (e.g., three-phase) AC machine can thus be generated, for example, in an inverter.
[0009] The complementary switching on and off of the two FET switches of a half-bridge, high-side FET switches, caused by the control signal, and
[0010] Lowside FET switch means that turning on one FET switch (e.g., highside FET switch) is accompanied by turning off the other FET switch (e.g., lowside FET switch), and vice versa.
[0011] To achieve the steepest possible edges of the output voltages during switching operations in the half-bridge circuit and thus reduce electrical losses, the high-side and low-side control signals are nowadays usually generated by a microcontroller, especially in the automotive sector, and output to the high-side and low-side gate drivers, which then convert them into 202400371
[0012] 2
[0013] generate sufficiently powerful gate drive signals that are applied to the gates (control terminals) of the FET switches.
[0014] However, if the functional range of the microcontroller or the control unit containing the microcontroller is exceeded, e.g. due to over- or undervoltage in the electrical supply of this unit, error-free control of the half-bridge circuit is no longer guaranteed and therefore, in such a fault case, an asynchronous intervention is carried out by the specially provided monitoring device, e.g., a so-called safety computer or "monitoring unit".
[0015] The monitoring device monitors the functionality of the control device intended for controlling the half-bridge circuit and is designed to, depending on a result of this monitoring and possibly further input variables, e.g. from a power supply device or e.g. from other monitoring devices, issue a digital signal.
[0016] To generate a shutdown / enable control signal for controlling the shutdown / enablement of the gate drivers. Therefore, if, for example, a fault event detected by the monitoring device occurs during operation of the half-bridge circuit, safety can be maintained by outputting a shutdown / enable control signal to shut down the gate drivers.
[0017] Upon detection of an error event, the gate drivers can be advantageously switched off by means of a corresponding shutdown / enable control signal (for shutdown), in order to prevent the
[0018] To turn off all the high-side FET switches and all the low-side FET switches, for example.
[0019] It is an object of the present invention to provide a circuit arrangement that enables reliable shutdown / release of high-side and low-side gate drivers, particularly in power electronics applications.
[0020] The problem is solved by the features of the independent patent claims. Advantageous embodiments are characterized in the dependent claims.
[0021] According to a first aspect, the task is solved by a circuit arrangement that includes a monitoring device for monitoring the functionality of a half-bridge circuit 202400371.
[0022] 3
[0023] the provided control device comprises, wherein the control device is configured to provide a high-side control signal for controlling a
[0024] The circuit is designed to generate a high-side gate driver signal for controlling at least one high-side FET switch of the half-bridge circuit and a low-side drive signal for controlling a low-side gate driver for controlling at least one low-side FET switch of the half-bridge circuit. The monitoring device is configured to generate a digital turn-off / enable control signal for controlling the turn-off / enable of the two gate drivers, depending on a result of the monitoring. The circuit arrangement further includes a signal processing device configured to generate a digital signal based on the turn-off / enable control signal.
[0025] To generate a high-side shutdown / enable signal for the high-side gate driver and a digital low-side shutdown / enable signal for the low-side gate driver, such that when the shutdown / enable control signal changes to shut down the gate drivers, the high-side shutdown / enable signal changes immediately and the
[0026] The lowside shutdown / enable signal changes only after a time delay, whereas when the shutdown / enable control signal changes to enable the gate drivers, the lowside shutdown / enable signal changes immediately and the highside shutdown / enable signal changes only after a time delay.
[0027] When controlling a three-phase machine, it may be desirable, for example, to switch off all high-side FET switches and switch on all low-side FET switches (to short-circuit the motor windings of the three-phase machine) in the event of a fault. To prevent, under all circumstances, a short circuit in the current path of a half-bridge during the gate driver switch-off process, which could be destructive, the circuit arrangement according to the invention allows the gate drivers to be switched off sequentially (one after the other) upon detection of a fault event, thus sequentially bringing the high-side FET switches and the low-side FET switches into their respective designated switching states. Accordingly, in the aforementioned example of controlling a three-phase machine, in the event of a fault, for example...First, all high-side FET switches are switched off, and after a short delay, all low-side FET switches are switched on. Based on this consideration for increasing operational reliability, the gate drivers (202400371) can also be used for the enable process.
[0028] 4
[0029] To sequentially (one after the other) enable the gate drivers in order to sequentially enable the controllability of the high-side FET switches and the low-side FET switches.
[0030] In at least one advantageous embodiment according to the first aspect, the circuit arrangement is designed as an integrated circuit. To implement the sequential shutdown / enabling of the high-side and low-side gate drivers, a discretely implemented delay circuit can be used to generate time-delayed signals for the shutdown / enabling of the high-side gate driver and the low-side gate driver, respectively, when the state of the shutdown / enabling control signal changes.
[0031] However, a disadvantage here is that, for example, due to the failure rate of externally interconnected individual components of the discretely implemented delay circuit, as well as due to unavoidable component tolerances, the delay circuit must be considered potentially unreliable. Furthermore, it is a disadvantage that monitoring or testing the functionality of the delay circuit to rule out latent faults would entail a relatively large effort. The integration of a shutdown / enabling mechanism, implemented particularly via edge detection, into the integrated circuit (e.g., [insert example here]) provided for in the invention addresses this issue.
[0032] By using a safety computer or "monitoring unit") with two separate shutdown / enabling control signals for high-side and low-side gate drivers, it is possible to eliminate the problems explained above or at least mitigate them considerably.
[0033] In at least one advantageous embodiment according to the first aspect, the integrated circuit is designed as a microcontroller component. In another embodiment of the invention, the integrated circuit is designed as an AS IC (application-specific integrated circuit) component.
[0034] Advantageously, the signal processing device integrated into the circuit according to the invention, and thus the elimination of a complex discrete delay circuit, can considerably increase the reliability during the sequential shutdown / enabling of the gate drivers. Furthermore, the invention enables (e.g., continuous) monitoring and / or (e.g., intermittent or as-needed) 202400371
[0035] 5
[0036] Testing the functionality of the signal processing device can be accomplished without significant additional effort.
[0037] In at least one advantageous embodiment according to the first aspect, the signal processing device includes an edge detection device for detecting rising edges and / or falling edges of the shutdown / enabling control signal. Regarding the specific implementation of the edge detection device, it is advantageous to draw on designs known in digital technology, and in particular digital signal processing technology.
[0038] In a further development of this embodiment, the edge detection device comprises a first edge detector for detecting rising edges and a second edge detector for detecting falling edges of the shutdown / enabling control signal. Designs for such selectively rising or falling edge-responsive detectors are well known in digital technology and can be advantageously employed in the invention.
[0039] In a further development, it is provided that the signal processing unit of the edge detection unit includes a signal delay unit downstream. This allows the time delays required by the invention to be achieved in a simple manner.
[0040] If the integrated circuit includes the aforementioned edge detection device with first and second edge detectors, then, for example, first and second signal delay elements can be provided downstream of these to generate the individual time delays. Designs for such signal delay elements are also known in digital technology and can be advantageously used in the invention. In this context, it should be noted that this also enables a very precise and reproducible specification of the time delays. Furthermore, it is possible to provide the two delays with different values and / or adjustability.
[0041] In view of the fact that the "delay functionality" of the signal processing device is independent of supply voltage fluctuations (which also affect the integrated circuit 202400371
[0042] 6
[0043] In one embodiment of the invention, it is advantageously provided that this functionality and / or the specification of the delays ("dead time" between the edges of the control signals) is implemented via an analog function in the signal processing unit, in order to ensure that the system (which must function reliably) can operate reliably. This means, for example, the use of at least one RC circuit to implement at least one of the delays, in a circuit design similar to the known discrete delay circuit, but with circuit components (resistor R and capacitor C) integrated into the circuit.
[0044] This is particularly advantageous because it enables or simplifies a design in which, for example, internal resets of an integrated circuit designed as an ASIC or microcontroller have no effect on the functionality of the sequential shutdown. Furthermore, using such an analog function as part of the signal processing unit makes it even more robust against supply voltage faults.
[0045] In one embodiment of a system that includes not only the integrated circuit with the monitoring device but also the (monitored) control device, the following functionality can be provided:
[0046] During commissioning of the control unit (e.g., startup of a microcontroller), the two shutdown / enable lines remain in the disabled state (for disabling the gate drivers) until the computer or the control unit's microcontroller is fully initialized. After activation of the monitoring function of the monitoring unit, the integrated circuit serving as an external "safety IC (monitoring unit)" first releases the shutdown signal for the low-side driver (enables the low-side driver), followed by the shutdown signal for the high-side driver (enables the
[0047] Lowside drivers). This prevents, for example, (PWM) errors, such as those caused by pin toggling, from energizing the output drivers during microcontroller startup and port initialization by the control device.
[0048] When the safety function in the safety IC shuts down (by outputting a corresponding shutdown / enable control signal), the sequence occurs in reverse order. This means that first the shutdown / enable line for the high-side driver is activated (switching off the high-side driver), and only after a delay is the shutdown of the low-side driver initiated. This disconnects the high-side FET switches from the DC link first, and only then does it trigger, for example, 202400371.
[0049] 7
[0050] When controlling 3-phase motors, the low-side FET switches create an active short circuit of the motor windings. In the application of controlling a half-bridge circuit of a DC / DC converter, the low-side FET switches can alternatively be switched to their off (high-impedance) state by switching off the low-side driver in the aforementioned last step.
[0051] In at least one advantageous embodiment according to the first aspect, the integrated circuit further comprises a self-test device for monitoring the functionality of the signal processing device. The self-test device can, for example, be configured to monitor the shutdown / enable control signal supplied to the signal processing device, as well as the high-side and
[0052] To subject lowside shutdown / enabling signals to evaluation. If the evaluation reveals a discrepancy between the evaluated signals, an error signal indicating this fault can be generated, for example.
[0053] According to a further aspect of the invention, the use of an integrated circuit of the type described herein for monitoring the functionality of a control device designed as a microcontroller for controlling a half-bridge circuit is proposed. Alternatively, the integrated circuit could be used to monitor a control device designed as an ASIC.
[0054] According to a further aspect of the invention, the use of an integrated circuit of the type described herein for monitoring the functionality of a control device provided for controlling a half-bridge circuit implemented in a power converter is proposed. The power converter can, for example, be an inverter or at least be operable as an inverter. Alternatively or additionally, the power converter can, for example, be a rectifier or at least be operable as a rectifier.
[0055] As already mentioned at the outset, the half-bridge circuit relevant to the use of the invention can have one or more (e.g., three) half-bridges (e.g., so-called B6 bridge), each consisting of a
[0056] Half-bridge supply voltage series connection of two controllable semiconductor switches, high-side FET switch and
[0057] Lowside FET switches are formed to be connected at an output node between the 202400371
[0058] 8
[0059] to provide each of the two semiconductor switches with its respective output voltage. Particularly in the automotive sector, this can involve the
[0060] The half-bridge supply voltage is a high voltage from the high-voltage electrical system of a vehicle, meaning voltages of more than 100 V or even more than 400 V, as is typical for electric vehicles, e.g., around 800 V to 1000 V. The half-bridge circuit can be controlled, for example, by means of PWM control or another modulation method, in order to effect complementary switching on and off of the two FET switches in each half-bridge during operation.
[0061] In particular, the invention may advantageously be used on board a vehicle, for example in connection with the control of an inverter by means of which a three-phase motor intended for driving the vehicle (e.g., electric vehicle or hybrid vehicle) is operated. The three-phase motor may, in particular, be a three-phase motor.
[0062] The invention is further described below with reference to exemplary embodiments and the accompanying drawings. These depict:
[0063] Fig. 1 shows a block diagram of a system with a half-bridge circuit and associated high-side and low-side gate drivers, a control device and a monitoring device according to an embodiment according to the invention.
[0064] Fig. 2 shows a representation of the time profiles of different signals in the system of Fig. 1, and
[0065] Fig. 3 shows a block diagram of a system with a half-bridge circuit and associated high-side and low-side gate drivers, a control device and a monitoring device according to an embodiment according to the invention.
[0066] Fig. 1 illustrates a system with a half-bridge circuit 3 and associated high-side and low-side gate drivers HSGD, LSGD, a control device 1 for controlling the gate drivers and an integrated 202400371
[0067] 9
[0068] Circuit 11 including a monitoring device 20 for monitoring the functionality of the control device 1.
[0069] In this example, the half-bridge circuit 3 forms an inverter, implemented with, for example, three half-bridges of the type shown in Figure 1, for generating three phase voltages and the resulting phase currents to power a three-phase AC machine (e.g., the drive motor of an electric or hybrid vehicle). Each half-bridge, as shown in Figure 1, consists of a series connection of two controllable semiconductor switches, supplied with a supply voltage (e.g., 800 V from a vehicle electrical system), a
[0070] A high-side FET switch (HST) and a low-side FET switch (LST) are formed to provide the respective output voltage (phase voltage) at a respective output node between the two switches HST and LST.
[0071] In the operation of the half-bridge circuit 3, the high-side FET switch HST and the low-side FET switch LST of each half-bridge are switched on and off in a complementary manner via the high-side gate driver HSGD and the low-side gate driver LSGD.
[0072] The control device 1 (e.g. "engine control unit" in a vehicle) can be designed as an ASIC or microcontroller component and serves to generate a high-side control signal HSpwm to control the high-side gate driver HSGD to control the high-side FET switches HST of the half-bridge circuit 3 and a low-side control signal LSpwm to control the low-side gate driver LSGD to control the low-side FET switches LST of the half-bridge circuit 3.
[0073] In this example, the control device 1 is configured for PWM control and includes a modulator 2 for generating the control signals. If the control device 1 is implemented by a microcontroller, the modulator 2 can represent a functional component of the control device (e.g., part of a control application running on the microcontroller).
[0074] The integrated circuit 11 can also be designed, for example, as an ASIC or microcontroller component and includes the monitoring device 20, which is configured to monitor the functionality of the control device 1 intended for controlling the half-bridge circuit 3. The specific method of this monitoring is shown in Fig. 1 by 202400371.
[0075] 10
[0076] A dotted line symbolizes numerous concepts known from the state of the art (e.g. "watchdog" etc.).
[0077] The monitoring device 20 is further configured to generate a digital shutdown / enable control signal DISset, depending on the result of the monitoring performed, to control the shutdown / enablement of the two gate drivers HSGD and LSGD. In this example, it is assumed that a high voltage in the digital signal DISset defines a logic high level (or logic 1) and is intended to "enable," whereas a low voltage defines a low level (or logic 0) and is intended to "shut down," for example, with a high voltage of more than 2.0 V and a low voltage of less than 0.8 V.
[0078] If the monitoring device 20 detects an error event based on the monitoring, the high-side gate driver LSGD and the low-side gate driver LSGD are sequentially switched off to prevent the
[0079] to bring the high-side FET switch HST and the low-side FET switch LST of the half-bridge circuit 3 into a controlled, sequential switching state intended for the event of a fault.
[0080] Conversely, for example after a proper completion of a start procedure of the control device 1 and the monitoring device 2 during commissioning of the system, the high-side gate driver LSGD and the low-side gate driver LSGD are sequentially enabled to allow the controlled sequential activation of the high-side FET switches HST and the low-side FET switches LST (using the high-side and low-side control signals HSpwm, LSpwm).
[0081] The deactivation / enabling of the gate drivers LSGD and HSGD is achieved by means of these control signals supplied for this purpose, namely a
[0082] Highside shutdown / enable signal HSdis for the highside gate driver HSGD and a lowside shutdown / enable signal LSdis for the
[0083] Lowside gate driver LSGD. In this example, it is assumed that for the digital signals HSdis and LSdis, a high voltage defines a logic high level (or logic 1) and causes the respective gate driver to be "enabled," whereas a low voltage defines a low level (or logic 0) and causes the respective gate driver to be "disabled." 202400371
[0084] 11
[0085] To implement the sequential shutdown / enabling of the high-side and low-side gate drivers HSGD and LSGD, a signal processing device 30, which has a discretely implemented delay circuit, is used, as shown in Fig. 1. The shutdown / enabling control signal DISset, output by the monitoring device 20, is input to this device, and it appropriately generates the signals HSdis (for the high-side gate driver HSGD) and LSdis (for the low-side gate driver LSGD).
[0086] Fig. 2 shows an example of a temporal progression of the
[0087] Switch-off / release control signal DISset and resulting time profiles of the signals HSdis and LSdis.
[0088] When the DISset signal changes from "0" to "1" (left in Fig. 2), in order to
[0089] To enable the gate driver, the signal LSdis changes immediately from "0" to "1" (enabling LSGD), whereas the signal HSdis only changes from "0" to "1" (enabling HSGD) after a time delay "Aten".
[0090] When the DISset signal changes from "1" to "0" (in Fig. 2 on the right) to switch off the gate drivers (i.e. to prevent PWM control and to bring HST, LST into defined switching states), then the HSdis signal immediately changes from "1" to "0" (switching off HSGD), whereas the LSdis signal only changes from "1" to "0" (switching off LSGD) after a time delay "Atdis".
[0091] Returning to Fig. 1, the delay circuit in the exemplary embodiment, as shown, comprises an RC network formed from a series connection of a resistor R and a capacitor C, a Schmitt trigger, an AND gate, and an OR gate. These components, interconnected as shown in Fig. 1, achieve the "delay functionality" shown in Fig. 2 when switching off and enabling the gate drivers HSGD and LSGD.
[0092] Unfortunately, reliability and accuracy (e.g., regarding the specified time delays "Aten" and "Atdis") cannot be guaranteed, especially over longer operating periods. 202400371
[0093] 12
[0094] An embodiment of an improved system with a configuration according to the invention is described below with reference to Fig. 3. The same reference numerals are used for components that act in the same way. Essentially, only the differences from the embodiment already described above with reference to Figs. 1 and 2 are discussed, and otherwise, reference is expressly made to the description of the preceding embodiment.
[0095] Fig. 3 shows a system with a half-bridge circuit 3 and associated high-side and low-side gate drivers HSGD, LSGD, and a control unit 1 for controlling the gate drivers HSGD, LSGD by means of high-side and low-side control signals HSpwm, LSpwm output by a modulator 2 of the control unit 1. These components of the system of Fig. 3 are configured, for example, as in the example of Fig. 1.
[0096] Furthermore, the system of Fig. 3, like the example of Fig.
[0097] 1 an integrated circuit 10 including a monitoring device 20 for monitoring the functionality of the control device 1 and for generating a digital shutdown / enable control signal DISset for controlling a shutdown / enable of the two gate drivers HSGD, LSGD.
[0098] In contrast to the example in Fig. 1, the integrated circuit 10 in Fig. 3 includes a signal processing device 30, which is configured to generate a digital high-side shutdown / enable signal HSdis for the monitoring device 20 within the integrated circuit, based on the shutdown / enable control signal DISset generated by the monitoring device 20.
[0099] Highside-gate driver HSGD and a digital
[0100] To generate a lowside shutdown / enable signal LSdis for the lowside gate driver LSGD. In this case, the integrated circuit 10 forms or comprises the circuit arrangement 5.
[0101] The signal processing unit 30 again provides the "delay functionality" already described with reference to Fig. 2 for switching off and enabling the gate drivers HSGD, LSGD, i.e., when the switch-off / enable control signal DISset changes to switch off the gate drivers HSGD, LSGD, the high-side switch-off / enable signal HSdis changes immediately and the low-side switch-off / enable signal LSdis only after a time delay "Atdis", whereas when the 202400371
[0102] 13
[0103] The shutdown / enabling control signal DISset enables the gate drivers HSGD and LSGD. The lowside shutdown / enabling signal LSdis changes immediately, while the highside shutdown / enabling signal HSdis changes only after a time delay "Aten".
[0104] The signal processing device 30 comprises an edge detection device 31, 32 comprising a first edge detector 31 for detecting rising edges of the signal DISset and a second edge detector 32 for detecting falling edges of the signal DISset. The two edge detectors 31, 32, connected in parallel in this example, are each followed by a first and second signal delay element 33, 34 (by means of which the individual time delays 'Aten' and 'Atdis' are defined or generated), as shown in Fig.3 signal paths are provided in parallel to each of the delay elements 33, 34 in order to output a total of four signals to a driver control 35, which mark, in a sense, the times at which the corresponding changes of the signals LSdis and HSdis are to take place when the signal DISset changes from "0" to "1" (to enable the gate drivers) and when the signal DISset changes from "1" to "0" (to disable the gate drivers).
[0105] With the method of defining the aforementioned time points (or generating the aforementioned four signals) provided here, by means of, for example, a digitally implemented combination of edge detection and signal delay, the required time delays "Aten" and "Atdis" or the resulting time profiles of the signals LSdis and HSdis can be provided very reliably, precisely, and reproducibly even over extended operating periods. In contrast to the illustrated embodiment, it is possible to make the two delays adjustable (e.g., depending on at least one operating parameter detected within the system). In a more advantageous embodiment, the delay functionality of the signal processing unit 30 or the aforementioned delay elements 33, 34 can be implemented via an analog function, e.g., using at least one RC circuit integrated into the circuit.
[0106] The driver control 35 is designed to control two downstream control signal drivers 36 based on the input signals (four in the example), and one (top in Fig. 3) control signal driver 36 to generate the signal HSdis 202400371
[0107] 14
[0108] and a (in Fig. 3 lower) control signal driver 36 for generating the signal LSdis.
[0109] The control signal drivers 36 are each formed as shown from a series connection of two controllable semiconductor switches, here FETs, supplied with a supply voltage VIO (e.g. 3.3 V), in order to generate at a respective output node between the two switches as a respective output signal of the signal HSdis or LSdis and output to the respective gate driver HSGD or LSGD.
[0110] An advantageous feature of the control signal drivers 36 is that the respective "highside" semiconductor switches are each connected to a so-called
[0111] A "back-to-back" arrangement of two simultaneously controlled FETs is formed to prevent damage to the integrated circuit 10 (in the example an ASIC component, alternatively e.g.) in the event of a fault where, for any reason, an impermissibly high voltage is present on one of the line paths carrying the HSdis and LSdis signals (switch-off / enable lines).
[0112] microcontroller).
[0113] Another advantageous feature of the integrated circuit 10 or the signal processing device 30 formed therein is that controllable "pull-down" devices 37, here FETs, are provided on the line paths carrying the signals HSdis and LSdis, by means of which, through appropriate control (e.g. in the event of a fault), the voltages or logic levels prevailing on these line paths can be actively pulled to "0" in order to switch off the gate drivers HSGD, LSGD.
[0114] Furthermore, in the integrated circuit 10, a status detection device 41 is provided on each of the line paths (switch-off / enable lines) carrying the HSdis and LSdis signals, as shown, for detecting the logic levels on these line paths. Each of these status detection devices 41 comprises a voltage divider formed from a series connection of resistors for dividing the voltage tapped on the respective path and a Schmitt trigger for generating the respective logic status signals LSstat or HSstat, which are output to a self-test device 40 within the integrated circuit 10. It should be noted that, due to this design of the status detection devices 41, their voltage dividers have an additional "passive pull-down" function, which (e.g., in the event of a failure of the 202400371)
[0115] 15
[0116] (The aforementioned "active" (controlled) pull-down semiconductor switches and / or failure of their control) also pull the voltages or logic levels present on the line paths to "0".
[0117] (Fail-safe behavior).
[0118] The self-test device 40 serves for internal monitoring of the functionality of the signal processing device 30 within the integrated circuit 10 and, in this example, is configured to monitor the shutdown / enable control signal DISset supplied to the signal processing device 30, as well as the high-side and
[0119] To subject the lowside shutdown / enable signals HSdis, LSdis to evaluation.
[0120] The example provides that, at least in certain operating situations, such as the commissioning and / or decommissioning of the monitoring device 20 (e.g., due to the commissioning and / or decommissioning of the control device 1 and thus half-bridge circuit 3), a self-test of the signal processing device 30 is performed by means of the self-test device 40. In particular, during a self-test, it may be provided that (e.g., with the power supply to the gate drivers switched off) the self-test device 40 generates a predefined test sequence of the signal DISset (e.g., with several transitions between "0" and "1") and outputs it to the signal processing device 30, and the self-test device 40 then evaluates the resulting status signals LSstat and HSstat to verify the correct function of the signal processing device 30.
[0121] In summary, the invention and the described embodiment enable a significantly enhanced benefit from an integrated circuit implementing the monitoring device of the type of interest here. Integrating a sequential control into an integrated circuit offers several advantages, such as increased robustness against voltage fluctuations and overvoltage. Active structures ensure that the off state (gate driver shutdown) is guaranteed even at very low supply voltages. Failure rates of an integrated analog function in the signal processing unit are significantly lower than in discrete circuit arrangements. Testing the function of the signal processing unit can be advantageously integrated into a standard automatic self-test (BIST), which is typically already implemented. Thus, 202400371
[0122] 16
[0123] For example, latent errors can be detected, and no additional test is necessary during control unit startup. If an analog function, such as one with at least one RC circuit, is provided for implementing the delays provided for in the invention, it should be considered that tolerances in a manufacturing process (e.g., silicon process) are then advantageously much lower than with external discrete circuits. 202400371
[0124] Reference symbol list
[0125] 1 Control unit
[0126] 2 Modulator
[0127] 3 half-bridge circuit
[0128] HST Highside FET Switch
[0129] LST Lowside FET Switch
[0130] HSpwm Highside Control Signal
[0131] HSGD Highside-Gate Driver
[0132] LSpwm Lowside Control Signal
[0133] LSGD Lowside Gate Driver
[0134] 5 Circuit arrangement
[0135] 10 integrated circuit
[0136] VIO supply voltage
[0137] 20 Monitoring device
[0138] DISset shutdown / enable control signal 30 Signal processing unit HSdis Highside shutdown / enable signal LSdis Lowside shutdown / enable signal 31 Edge detector (for rising edge) 32 Edge detector (for falling edge) 33 Signal delay stage
[0139] 34 Signal delay stage
[0140] Atdis delay (when shut down) Aten delay (wh when enabled)
[0141] 35 T driver control
[0142] 36 Control signal drivers
[0143] 37 Pull-down device
[0144] 40 Self-test kit
[0145] 41 Status recording device
[0146] HSstat Highside Status Signal
[0147] LSstat Lowside status signal
[0148] 100 delay circuit
Claims
202400371 18 Patent claims 1. Circuit arrangement (5) comprising a monitoring device (20) for monitoring the functionality of a control device (1) intended for controlling a half-bridge circuit (3), wherein the control device (1) is configured to provide a high-side control signal (HSpwm) for controlling a high-side gate driver (HSGD) for controlling at least one high-side FET switch (HST) of the half-bridge circuit (3) and a low-side control signal (LSpwm) for controlling a Lowside-gate driver (LSGD) for controlling at least one to generate the lowside FET switch (LST) of the half-bridge circuit (3), and wherein the monitoring device (20) is configured to generate a digital shutdown / enable control signal (DISset) depending on a result of the monitoring for controlling a shutdown / enable of the two gate drivers (HSGD, LSGD), wherein the circuit arrangement (5) further comprises a signal processing device (30) which is configured to perform, based on the Shutdown / Enable control signal (DISset) a digital To generate a high-side shutdown / enable signal (HSdis) for the high-side gate driver (HSGD) and a digital low-side shutdown / enable signal (LSdis) for the low-side gate driver (LSGD), such that when the shutdown / enable control signal (DISset) changes to shut down the gate drivers (HSGD, LSGD), the high-side shutdown / enable signal (HSdis) changes immediately and the low-side shutdown / enable signal (LSdis) changes only after a time delay (Atdis), whereas when the shutdown / enable control signal (DISset) changes to enable the gate drivers (HSGD, LSGD), the low-side shutdown / enable signal (LSdis) changes immediately and the high-side shutdown / enable signal (HSdis) changes only after a time delay (Aten).
2. Circuit arrangement (5) according to claim 1, wherein the circuit arrangement (5) is designed as an integrated circuit (10).
3. Circuit arrangement (5) according to claim 2, wherein the integrated circuit (10) is designed as an ASIC or microcontroller component. 202400371 19 4. Circuit arrangement (5) according to claim 2 or 3, wherein the signal processing device (30) has an edge detection device (31, 32) for detecting rising edges and / or falling edges of the disable / enable control signal (DISset).
5. Circuit arrangement (5) according to claim 4, wherein the edge detection device (31, 32) comprises a first edge detector (31) for detecting rising edges and a second edge detector (32) for detecting falling edges of the shutdown / enabling control signal (DISset).
6. Circuit arrangement (5) according to claim 4 or 5, wherein the signal processing device (30) of the edge detection device (31, 32) has a signal delay device (33, 34) connected downstream.
7. Circuit arrangement (5) according to one of the preceding claims 2 to 6, further comprising a self-test device (40) for monitoring the functionality of the signal processing device (30), wherein the self-test device (40) is configured to evaluate the shutdown / enable control signal (DISset) supplied to the signal processing device (30) and the high-side and low-side shutdown / enable signals (HSdis, LSdis) generated by the signal processing device (30).
8. Use of a circuit arrangement (5) according to one of the preceding claims 2 to 7 for monitoring the functionality of a control device (1) designed as a microcontroller for controlling a half-bridge circuit (3).
9. Use according to claim 8 on board a vehicle.