Semiconductor device and method for fabricating semiconductor device

Abstract

Provided is a semiconductor device that has a large on-state current. This semiconductor device includes a first conductive layer, a second conductive layer, a third conductive layer, an oxide layer, a semiconductor layer, a first insulating layer, and a second insulating layer. The first insulating layer is located on the first conductive layer. The second conductive layer is located on the first insulating layer. The oxide layer is located on the second conductive layer. The first insulating layer, second conductive layer, and oxide layer have an opening that reaches the first conductive layer. The semiconductor layer has a portion in contact with the first conductive layer, a portion in contact with a side surface of the opening in the first insulating layer, a portion in contact with a side surface of the opening in the second conductive layer, and a portion in contact with a top surface and side surface of the oxide layer. The second insulating layer is located on the semiconductor layer. The third conductive layer has a portion that faces the semiconductor layer with the second insulating layer interposed therebetween.

Description

Semiconductor device, method for manufacturing a semiconductor device

[0001] One aspect of the present invention relates to a transistor, a semiconductor device, a memory device, a display device, and an electronic device. Another aspect of the present invention relates to a method for manufacturing a transistor and a semiconductor device.

[0002] It should be noted that one aspect of the present invention is not limited to the above-mentioned technical field. Examples of technical fields of one aspect of the present invention include semiconductor devices, display devices, light-emitting devices, energy storage devices, memory devices, electronic devices, lighting devices, input devices (e.g., touch sensors), input / output devices (e.g., touch panels), methods for driving them, or methods for manufacturing them.

[0003] In this specification, a semiconductor device refers to a device that utilizes semiconductor properties, including circuits containing semiconductor elements (transistors, diodes, photodiodes, etc.), devices having such circuits, etc. It also refers to any device that can function by utilizing semiconductor properties. For example, integrated circuits, chips equipped with integrated circuits, and electronic components with chips housed in packages are examples of semiconductor devices. Furthermore, memory devices, display devices, light-emitting devices, lighting devices, and electronic devices are themselves semiconductor devices, and may each have a semiconductor device.

[0004] A technology for constructing transistors using semiconductor thin films formed on substrates with insulating surfaces is attracting attention. These transistors are widely applied in electronic devices such as integrated circuits (ICs) and display devices. While silicon-based semiconductor materials are widely known as semiconductor materials applicable to transistors, oxide semiconductors are also gaining attention as other materials.

[0005] Furthermore, transistors using oxide semiconductors are known to have extremely low leakage current in the non-conductive state. For example, Patent Document 1 discloses a low-power CPU (Central Processing Unit) that takes advantage of this low leakage current characteristic. Also, for example, Patent Document 2 discloses a memory device that can retain its contents for a long period of time by taking advantage of the low leakage current characteristic of transistors using oxide semiconductors.

[0006] Furthermore, examples of oxide semiconductors applicable to the active layer of a transistor include indium oxide and indium gallium zinc oxide. Non-patent document 1 discloses a thin-film transistor using polycrystalline indium hydride oxide formed by low-temperature solid-phase crystallization as the active layer.

[0007] Japanese Patent Publication No. 2012-257187 Japanese Patent Publication No. 2011-151383

[0008] Y. Magari et al., “High-mobility hydrogenerated polycrystalline In2O3 (In2O3:H)thin-film transmitters”, Nature Communications, 13, 1078 (2022). Takashi Koida, “High-mobility transparent conductive film”, National Institute of Advanced Industrial Science and Technology, AIST Photovoltaic Power Generation Research Results Presentation Meeting 2019, Internet <URL: https: / / unit.aist.go.jp / rpd-envene / PV / ja / results / 2019 / oral / T13.pdf>

[0009] One aspect of the present invention aims to provide a semiconductor device with a large on-current. Another aspect of the present invention aims to provide a semiconductor device with good electrical characteristics. Another aspect of the present invention aims to provide a highly reliable semiconductor device. Another aspect of the present invention aims to provide a semiconductor device that can be miniaturized or highly integrated. Another aspect of the present invention aims to provide a semiconductor device with low power consumption. Another aspect of the present invention aims to provide a memory device with a fast operating speed. Another aspect of the present invention aims to provide a method for manufacturing the above-mentioned semiconductor device.

[0010] Furthermore, the description of these problems does not preclude the existence of other problems. Moreover, one aspect of the present invention does not need to solve all of these problems. Other problems can be identified from the description in the specification, drawings, claims, etc.

[0011] One aspect of the present invention is a semiconductor device comprising a first conductive layer, a second conductive layer, a third conductive layer, an oxide layer, a semiconductor layer, a first insulating layer, and a second insulating layer, wherein the first insulating layer is located on the first conductive layer, the second conductive layer is located on the first insulating layer, the oxide layer is located on the second conductive layer, the first insulating layer, the second conductive layer, and the oxide layer each have an opening that reaches the first conductive layer, the semiconductor layer has a portion in contact with the first conductive layer, a portion in contact with the side surface of the opening in the first insulating layer, a portion in contact with the side surface of the opening in the second conductive layer, and a portion in contact with the top and side surfaces of the oxide layer, the second insulating layer is located on the semiconductor layer, and the third conductive layer has a portion facing the semiconductor layer via the second insulating layer.

[0012] In the above-described semiconductor device, it is preferable that the semiconductor layer contains indium and oxygen, and the oxide layer contains indium, gallium, and zinc.

[0013] In the above-described semiconductor device, it is preferable that there is a portion at the interface between the semiconductor layer and the second conductive layer in which the gallium concentration is 1.0 atomic% or less.

[0014] In the above-described semiconductor device, the oxide layer is preferably composed of In:Ga:Zn = 1:1:1 [atomic ratio] or a composition close to that, or In:Ga:Zn = 1:3:2 [atomic ratio] or a composition close to that.

[0015] In the semiconductor device described above, it is preferable that the oxide layer has a first crystal having a hexagonal or trigonal crystal structure, and the semiconductor layer has a second crystal having a cubic crystal structure.

[0016] In the semiconductor device described above, it is preferable that the <001> orientation of the first crystal is perpendicular or approximately perpendicular to the upper surface of the first insulating layer.

[0017] In the semiconductor device described above, it is preferable that the <111> orientation of the second crystal is parallel or approximately parallel to the depth direction of the opening.

[0018] In the semiconductor device described above, the second conductive layer comprises a fourth conductive layer and a fifth conductive layer, wherein the fifth conductive layer is located on the fourth conductive layer, the fourth conductive layer preferably contains tungsten, and the fifth conductive layer preferably contains indium, tin, and oxygen.

[0019] In the semiconductor device described above, it is preferable that the semiconductor layer has a portion that is in contact with the side surface of the opening of the fourth conductive layer.

[0020] In the semiconductor device described above, it is preferable that the semiconductor layer has a portion that is in contact with the side surface of the opening of the fifth conductive layer.

[0021] One aspect of the present invention is a method for manufacturing a semiconductor device, comprising: a first step of forming a first conductive layer, a first insulating layer, a second conductive layer, and an oxide layer in that order; a second step of forming a mask layer on the oxide layer; a third step of processing the oxide layer, the second conductive layer, and the first insulating layer using a dry etching method to form an opening that reaches the first conductive layer; a fourth step of covering the oxide layer with a part of the mask layer and performing a cleaning treatment; a fifth step of performing an ashing treatment using oxygen plasma; a sixth step of forming a first semiconductor layer on the oxide layer and on the opening; and a seventh step of forming a second insulating layer on the first semiconductor layer and a third conductive layer on the second insulating layer.

[0022] In the above-described method for manufacturing a semiconductor device, it is preferable to deposit the oxide layer using a sputtering method with a target containing indium, gallium, zinc, and oxygen.

[0023] In the above-described method for manufacturing a semiconductor device, the first semiconductor layer comprises a second semiconductor layer and a third semiconductor layer on the second semiconductor layer. Preferably, the second semiconductor layer is deposited using atomic layer deposition (ALD) with triethylindium as the precursor, and the third semiconductor layer is deposited using sputtering with a target containing indium, gallium, zinc, and oxygen.

[0024] In the above-described method for manufacturing semiconductor devices, it is preferable to use a cleaning solution containing hydrofluoric acid for the cleaning process.

[0025] According to one aspect of the present invention, a semiconductor device with a high on-current can be provided. According to one aspect of the present invention, a semiconductor device with good electrical characteristics can be provided. According to one aspect of the present invention, a highly reliable semiconductor device can be provided. According to one aspect of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided. According to one aspect of the present invention, a semiconductor device with low power consumption can be provided. According to one aspect of the present invention, a memory device with a high operating speed can be provided. According to one aspect of the present invention, a method for manufacturing the above-mentioned semiconductor device can be provided.

[0026] Furthermore, the description of these effects does not preclude the existence of other effects. Moreover, one aspect of the present invention does not need to possess all of these effects. Other effects can be extracted from descriptions in the specification, drawings, claims, etc.

[0027] Figure 1A is a plan view showing an example of a semiconductor device. Figures 1B and 1C are cross-sectional views showing an example of a semiconductor device. Figures 2A and 2B are cross-sectional views showing an example of a semiconductor device. Figure 3A is a cross-sectional view illustrating an indium oxide film. Figures 3B and 3C illustrate the carrier concentration dependence of hole mobility. Figures 4A, 4B, 4C, 4D, and 4E illustrate the crystal structure of a metal oxide. Figures 5A and 5B are cross-sectional views showing an example of a semiconductor device. Figures 6A and 6B are cross-sectional views showing an example of a semiconductor device. Figures 7A and 7B are cross-sectional views showing an example of a semiconductor device. Figure 8A is a plan view showing an example of a semiconductor device. Figures 8B and 8C are cross-sectional views showing an example of a semiconductor device. Figure 9A is a plan view showing an example of a semiconductor device. Figures 9B and 9C are cross-sectional views showing an example of a semiconductor device. Figure 10A is a plan view showing an example of a semiconductor device. Figures 10B and 10C are cross-sectional views showing an example of a semiconductor device. Figure 11A is a plan view showing an example of a memory device. Figures 11B and 11C are cross-sectional views showing an example of a memory device. Figure 12 is a cross-sectional view showing an example of a memory device. Figures 13A, 13B, and 13C are diagrams illustrating a method for manufacturing a semiconductor device. Figures 14A, 14B, and 14C are diagrams illustrating a method for manufacturing a semiconductor device. Figures 15A, 15B, and 15C are diagrams illustrating a method for manufacturing a semiconductor device. Figures 16A, 16B, and 16C are diagrams illustrating a method for manufacturing a semiconductor device. Figures 17A, 17B, and 17C are diagrams illustrating a method for manufacturing a semiconductor device. Figures 18A, 18B, and 18C are diagrams illustrating a method for manufacturing a semiconductor device. Figures 19A, 19B, and 19C are diagrams illustrating a method for manufacturing a semiconductor device. Figures 20A, 20B, and 20C are diagrams illustrating a method for manufacturing a semiconductor device. Figures 21A, 21B, and 21C are diagrams illustrating a method for manufacturing a semiconductor device. Figure 22 is a block diagram illustrating an example configuration of a semiconductor device. Figures 23A, 23B, 23C, 23D, 23E, 23F, 23G, and 23H illustrate examples of memory cell circuit configurations. Figures 24A and 24B are perspective views illustrating examples of semiconductor device configurations. Figure 25 is a block diagram illustrating a CPU.Figures 26A and 26B are perspective views of a semiconductor device. Figures 27A and 27B are perspective views of a semiconductor device. Figures 28A and 28B show an example of an electronic component. Figures 29A, 29B, and 29C show an example of a large-scale computer. Figure 29D shows an example of space equipment. Figure 29E shows an example of a storage system applicable to a data center. Figure 30 is a cross-sectional STEM image according to an embodiment. Figures 31A and 31B are cross-sectional STEM images according to an embodiment. Figure 32 shows the evaluation results of a transistor.

[0028] Embodiments will be described with reference to the drawings. However, it will be readily apparent to those skilled in the art that the present invention is not limited to the following description, and that its form and details can be modified in various ways without departing from the spirit and scope of the present invention. Accordingly, the present invention shall not be construed as being limited to the contents of the embodiments shown below.

[0029] In the invention described below, the same reference numerals are used in common across different drawings for identical parts or parts having similar functions, and repeated explanations are omitted. Furthermore, when referring to similar functions, the same hatching pattern may be used, and reference numerals may not be assigned.

[0030] Furthermore, for the sake of ease of understanding, the position, size, and scope of each component shown in the drawings may not represent their actual position, size, and scope. Therefore, the disclosed invention is not necessarily limited to the position, size, and scope disclosed in the drawings.

[0031] In this specification, the ordinal numbers "first" and "second" are used for convenience only and do not limit the number of components or the order of components (for example, process order or layering order). Furthermore, the ordinal numbers used for components in one part of this specification may not be the same as those used for the same components in other parts of this specification or in the claims.

[0032] Furthermore, a transistor is a type of semiconductor device that can perform functions such as amplifying current or voltage, and switching operations that control conduction or non-conductivity. Transistors as used herein include IGFETs (Insulated Gate Field Effect Transistors) and thin-film transistors (TFTs).

[0033] Furthermore, the terms "film" and "layer" can be interchanged depending on the context or situation. For example, the term "conductive layer" can be changed to "conductive film." Or, for example, the term "insulating film" can be changed to "insulating layer." Also, the term "conductor" can be interchanged with the terms "conductive layer" or "conductive film" depending on the context or situation. Similarly, the term "insulator" can be interchanged with the terms "insulating layer" or "insulating film" depending on the context or situation.

[0034] Furthermore, in this specification, "parallel" means a state in which two lines are set at an angle of -10 degrees or more and 10 degrees or less. Therefore, the case of -5 degrees or more and 5 degrees or less is also included. Furthermore, "approximately parallel" means a state in which two lines are set at an angle of -20 degrees or more and 20 degrees or less. Furthermore, "perpendicular" means a state in which two lines are set at an angle of 80 degrees or more and 100 degrees or less. Therefore, the case of 85 degrees or more and 95 degrees or less is also included. Furthermore, "approximately perpendicular" means a state in which two lines are set at an angle of 70 degrees or more and 110 degrees or less.

[0035] In this specification, when A is said to be perpendicular to the substrate surface or the surface to be formed, it means that the angle between the side surface of A and the top surface of the substrate surface or the surface to be formed is 80 degrees or more and 100 degrees or less. Furthermore, when A is said to be roughly perpendicular to the substrate surface or the surface to be formed, it means that the angle between the side surface of A and the top surface of the substrate surface or the surface to be formed is 70 degrees or more and 110 degrees or less. Note that the term "substrate surface" can be rephrased as the surface of the substrate.

[0036] In this specification, a tapered shape refers to a shape in which at least a portion of the side surface of a structure is inclined with respect to the substrate surface or the surface to be formed. For example, it is preferable to have a region in which the angle between the inclined side surface and the substrate surface or the surface to be formed (hereinafter sometimes referred to as the taper angle) is less than 90°. The side surface of the structure and the substrate surface do not necessarily have to be perfectly flat; they may have a curved shape or a shape with fine irregularities.

[0037] In this specification, transistors using an oxide semiconductor or metal oxide in the semiconductor layer, and transistors having an oxide semiconductor or metal oxide in the channel formation region, may be referred to as OS (Oxide Semiconductor) transistors. Furthermore, transistors having silicon in the channel formation region may be referred to as Si transistors.

[0038] Furthermore, the functions of "source" and "drain" may be reversed when transistors of different polarities are used, or when the direction of current changes during circuit operation. For this reason, in this specification, the terms "source" and "drain" may be used interchangeably.

[0039] (Embodiment 1) This embodiment describes a semiconductor device according to one aspect of the present invention. The semiconductor device according to one aspect of the present invention includes a transistor.

[0040] <Example of Semiconductor Device Configuration> An example of the configuration of a semiconductor device according to one embodiment of the present invention will be described using Figures 1A to 12. Note that some components may be omitted in the plan views and cross-sectional views shown below.

[0041] [Transistor 200A] Figures 1A to 1C show an example of a semiconductor device. Figure 1A is a plan view of a semiconductor device having transistor 200A. Figures 1B and 2A are cross-sectional views of the semiconductor device between the dashed-dotted lines A1 and A2 shown in Figure 1A. Figure 2A is an enlarged view of the semiconductor device shown in Figure 1B. Figure 1C is a cross-sectional view of the semiconductor device between the dashed-dotted lines A3 and A4 shown in Figure 1A. Figure 2B is a horizontal cross-sectional view of the semiconductor device between the dashed-dotted lines A5 and A6 shown in Figure 1B.

[0042] The semiconductor device includes an insulating layer 210, a transistor 200A, an insulating layer 280, an insulating layer 282, and an insulating layer 283. The transistor 200A includes a conductive layer 220 on the insulating layer 210, a conductive layer 240 on the insulating layer 280, an oxide layer 245 on the conductive layer 240, a semiconductor layer 230, an insulating layer 250 on the semiconductor layer 230, and a conductive layer 260 on the insulating layer 250. The insulating layer 280 is located on the insulating layer 210 and the conductive layer 220, the insulating layer 282 is located on the conductive layer 260 and the insulating layer 250, and the insulating layer 283 is located on the insulating layer 282. The insulating layers 210, 280, 282, and 283 may be considered as part of the components of the transistor 200A.

[0043] Figures 1B and 1C show an example in which the conductive layer 220 has a two-layer structure consisting of conductive layer 220_1 and conductive layer 220_2 on top of conductive layer 220_1, the conductive layer 240 has a two-layer structure consisting of conductive layer 240_1 and conductive layer 240_2 on top of conductive layer 240_1, the conductive layer 260 has a two-layer structure consisting of conductive layer 260_1 and conductive layer 260_2 on top of conductive layer 260_1, and the insulating layer 280 has a four-layer structure consisting of insulating layer 280_1, insulating layer 280_2, insulating layer 280_3, and insulating layer 280_4.

[0044] In transistor 200A, the conductive layer 260 functions as a gate electrode, the insulating layer 250 functions as a gate insulating layer, the conductive layer 220 functions as one of the source electrode and drain electrode, and the conductive layer 240 functions as the other of the source electrode and drain electrode. The semiconductor layer 230 has a channel formation region. The conductive layer 260 also has a region that functions as gate wiring.

[0045] As shown in Figures 1B and 1C, the insulating layer 280, the conductive layer 240, and the oxide layer 245 are provided with openings 290 that reach the conductive layer 220.

[0046] The opening 290 includes an opening in the insulating layer 280, an opening in the conductive layer 240, and an opening in the oxide layer 245. The shape and size of the opening 290 in plan view may differ for each layer. Furthermore, when the upper surface shape of the opening 290 is circular, the openings in each layer may be concentric, or they may not be concentric and their centers may be offset.

[0047] Each of the semiconductor layer 230, insulating layer 250, and conductive layer 260 is arranged such that at least a portion of them is located within the opening 290. Furthermore, the portions of the semiconductor layer 230, insulating layer 250, and conductive layer 260 that are located within the opening 290 are provided in a manner that reflects the shape of the opening 290.

[0048] The semiconductor layer 230 is provided so as to cover the bottom and sides of the opening 290. The semiconductor layer 230 also has a recess that reflects the shape of the opening 290. The semiconductor layer 230 has a portion that contacts the conductive layer 220, a portion that contacts the side surface of the insulating layer 280 in the opening 290, a portion that contacts the side surface of the conductive layer 240 in the opening 290, a portion that contacts the side surface of the oxide layer 245 in the opening 290, and a portion that contacts the upper surface of the oxide layer 245.

[0049] The insulating layer 250 is located on the semiconductor layer 230. The insulating layer 250 is also provided on the insulating layer 280 so as to cover the top and side surfaces of the semiconductor layer 230, the side surfaces of the conductive layer 240, and the side surfaces of the oxide layer 245. The insulating layer 250 also has recesses that reflect the shape of the recesses in the semiconductor layer 230.

[0050] The conductive layer 260 is provided so as to fill at least a portion of the recesses in the insulating layer 250. The conductive layer 260 also has a portion that faces the semiconductor layer 230 via the insulating layer 250.

[0051] The semiconductor layer 230 has a region that overlaps with the conductive layer 260 via the insulating layer 250. At least a portion of this region functions as the channel formation region of the transistor 200A. Of the region of the semiconductor layer 230 near the conductive layer 220 and the region of the semiconductor layer 230 near the conductive layer 240, one functions as the source region and the other functions as the drain region. In other words, the channel formation region is sandwiched between the source region and the drain region.

[0052] The semiconductor layer 230 is provided inside the opening 290. Furthermore, the transistor 200A has a configuration in which current flows vertically, as one of the source and drain electrodes (here, the conductive layer 220) is located downwards and the other (here, the conductive layer 240) is located upwards. In other words, a channel is formed along the side surface of the semiconductor layer 230 in the opening 290. As a result, the transistor 200A can reduce the occupied area compared to a planar transistor in which the channel formation region, source region, and drain region are located on the XY plane. Therefore, the semiconductor device can be highly integrated. Also, when a semiconductor device according to one aspect of the present invention is used as a memory device, the storage capacity per unit area can be increased. It should be noted that the transistor 200A can be said to have a channel length direction that has a component in the height direction (vertical direction), and therefore can be called a VFET (Vertical Field Effect Transistor), vertical transistor, vertical channel transistor, or vertical channel type transistor.

[0053] The semiconductor layer 230 is preferably an oxide semiconductor. Furthermore, the semiconductor layer 230 is preferably crystalline. The oxide layer 245 is preferably a metal oxide. Furthermore, the oxide layer 245 is preferably crystalline. By forming the semiconductor layer 230 such that at least a portion of it is located on the oxide layer 245, the crystallinity of the semiconductor layer 230 can be increased. The high crystallinity of the semiconductor layer 230 can improve the electrical characteristics and reliability of the semiconductor device.

[0054] The oxide layer 245 is often less conductive than the conductive layer 240. In this case, if the oxide layer 245 is formed between the semiconductor layer 230 and the side surface of the conductive layer 240 at the opening 290, the contact resistance between the semiconductor layer 230 and the conductive layer 240 may increase. Therefore, it is preferable that the oxide layer 245 does not come into contact with the side surface of the conductive layer 240 at the opening 290. In other words, it is preferable that the oxide layer 245 is not formed between the semiconductor layer 230 and the side surface of the conductive layer 240 at the opening 290. As described above, in the configuration of a semiconductor device in one aspect of the present invention, the semiconductor layer 230 can be provided so as to come into contact with the side surface of the conductive layer 240 at the opening 290. The contact area between the semiconductor layer 230 and the conductive layer 240 can be increased, and the contact resistance between the semiconductor layer 230 and the conductive layer 240 can be reduced. This makes it possible to increase the on-current of the semiconductor device.

[0055] Figure 1C shows a configuration in which the edges of the conductive layer 240, the oxide layer 245, and the semiconductor layer 230 coincide or substantially coincide outside the opening 290. The conductive layer 240, the oxide layer 245, and the semiconductor layer 230 can be manufactured by processing using the same mask. Therefore, this is preferable because it reduces the number of masks required to manufacture the semiconductor device. However, the present invention is not limited to this. For example, in the X or Y direction, one of the edges of the semiconductor layer 230, the oxide layer 245, the conductive layer 240_1, and the conductive layer 240_2 may be located inward or outward compared to the others.

[0056] Furthermore, the transistor 200A is provided at the intersection of a conductive layer 260 extending in the X direction and a conductive layer 240 extending in the Y direction. The diameter of the opening 290 can be made smaller than the width of the short side of both the conductive layer 240 and the conductive layer 260. Thus, the transistor 200A can be said to have a structure that enables high integration and miniaturization.

[0057] As shown in Figure 2B, by forming the opening 290 so that it is circular in plan view, the semiconductor layer 230, the insulating layer 250, and the conductive layer 260 are arranged concentrically. Therefore, the side surface of the conductive layer 260 in the opening 290, which is located at the center of the opening 290, faces the side surface of the semiconductor layer 230 via the insulating layer 250. In other words, in plan view, the entire perimeter of the semiconductor layer 230 becomes the channel formation region. At this time, for example, the channel width of the transistor 200A is determined by the length of the outer perimeter of the semiconductor layer 230. That is, the channel width of the transistor 200A can be said to be determined by the width of the opening 290 (or the diameter if the opening 290 is circular in plan view). Figures 2A and 2B show the width D of the opening 290, and Figure 2B shows the channel width W of the transistor 200A.

[0058] Furthermore, by arranging the semiconductor layer 230, the insulating layer 250, and the conductive layer 260 in a concentric manner, the distance between the conductive layer 260 and the semiconductor layer 230 becomes approximately uniform, so that the gate electric field can be applied to the semiconductor layer 230 in an approximately uniform manner.

[0059] By increasing the width D of the aperture 290, the channel width per unit area can be increased, and the on-current can be increased. On the other hand, the area occupied by the transistor 200A, for example, the area of ​​the transistor 200A in a plan view, is roughly determined according to the width of the aperture 290. By decreasing the width D of the aperture 290, the area occupied by the transistor 200A can be reduced, and the semiconductor device can be highly integrated.

[0060] The width D of the opening 290 may vary in the depth direction. Here, in particular, the shortest distance between the two sides of the conductive layer 240 on the opening side in a cross-sectional view is used as the width D. In other words, the minimum width of the opening in the conductive layer 240 is used as the width D of the opening 290. Alternatively, the width of the opening at the highest position, the width of the opening at the lowest position, the width of the opening at the midpoint between these, or the average of these three widths may be used as the width D. Here, an example is shown in which the width D of the opening 290 is determined using the width of the opening in the conductive layer 240, but the method of determining the width D is not particularly limited. For example, the shortest distance between the two sides of the insulating layer 280 on the opening side can be used as the width D. Alternatively, the width of the opening at the highest position, the width of the opening at the lowest position, the width of the opening at the midpoint between these, or the average of these three widths may be used as the width D of the opening 290.

[0061] The width D of the opening 290 is determined by the thickness of the semiconductor layer 230, the insulating layer 250, and the conductive layer 260 provided within the opening 290. The width D of the opening 290 is preferably, for example, 5 nm to 100 nm, more preferably 10 nm to 60 nm, more preferably 20 nm to 50 nm, more preferably 20 nm to 40 nm, and still more preferably 20 nm to 30 nm. When the opening 290 is circular in plan view, the width D of the opening 290 corresponds to the diameter of the opening 290, and the channel width W can be calculated as "D × π".

[0062] In this embodiment, an example is shown in which the opening 290 is circular in plan view. By making it circular, the processing accuracy when forming the opening can be improved, and a fine-sized opening can be formed. However, the present invention is not limited to this. In plan view, the opening 290 can be, for example, a circular or elliptical or other approximately circular shape, a triangle, a quadrilateral (including rectangles, rhombuses, and squares), a pentagon, or a polygon with rounded corners, or a polygon with rounded corners. Note that the circular shape is not limited to a perfect circle. Furthermore, the polygon may be either a concave polygon (a polygon in which at least one interior angle exceeds 180 degrees) or a convex polygon (a polygon in which all interior angles are 180 degrees or less).

[0063] The channel length of transistor 200A is the distance between the source region and the drain region. In other words, the channel length of transistor 200A is determined by the thickness of the insulating layer 280 on the conductive layer 220. Therefore, the channel length of transistor 200A does not affect the area occupied by transistor 200A, for example, the area of ​​transistor 200A in a plan view. In Figure 2A, the channel length L of transistor 200A is shown by a dashed double arrow. The channel length L can be considered as the distance between the edge of the region where the semiconductor layer 230 and the conductive layer 220 are in contact and the edge of the region where the semiconductor layer 230 and the conductive layer 240 are in contact in a cross-sectional view. In this case, the channel length L corresponds to the length of the side surface of the insulating layer 280 on the opening 290 side in a cross-sectional view.

[0064] The channel length of transistor 200A can be, for example, 500 nm or less, typically 1 nm to 300 nm, preferably 5 nm to 100 nm. Furthermore, transistor 200A can be fabricated with an extremely fine structure, with a channel length of 1 nm to 10 nm. This improves productivity and yield in processes such as the formation of the insulating layer 280 and the formation of the opening 290 into the insulating layer 280. Additionally, the on-current of transistor 200A increases, improving the frequency characteristics.

[0065] The channel length L of transistor 200A is preferably at least smaller than the channel width W of transistor 200A. The channel length L of transistor 200A is preferably 0.1 times or more and 0.99 times or less than or equal to the channel width W of transistor 200A, and more preferably 0.5 times or more and 0.8 times or less. By adopting such a configuration, a transistor with good electrical characteristics and high reliability can be realized.

[0066] A transistor according to one aspect of the present invention has a semiconductor layer 230 including a channel-forming region, which contains a metal oxide (also called an oxide semiconductor) that functions as a semiconductor. In other words, this transistor can be called an OS transistor. In this specification, a semiconductor layer having an oxide semiconductor can be referred to as an oxide semiconductor layer. Furthermore, since the semiconductor layer 230 has a metal oxide, the semiconductor layer 230 can be referred to as a metal oxide layer.

[0067] OS transistors have oxygen vacancies (V) in the channel formation region of an oxide semiconductor. Ｏ The presence of oxygen vacancies and impurities can easily lead to fluctuations in electrical properties and reduced reliability. Therefore, it is preferable that oxygen vacancies and impurities be reduced as much as possible in the channel formation region of an oxide semiconductor. In other words, it is preferable that the channel formation region in an oxide semiconductor has a reduced carrier concentration and is i-type (intrinsic) or substantially i-type.

[0068] Furthermore, if an excessive amount of oxygen is supplied to the semiconductor layer 230, electron traps caused by this oxygen are formed in the insulating layer 250. As a result, the OS transistor becomes more susceptible to positive drift degradation in the +GBT (Gate Bias-Temperature) stress test. In other words, the amount of positive drift degradation in the +GBT stress test increases.

[0069] Therefore, in a semiconductor device according to one aspect of the present invention, it is preferable that the impurity concentration in the semiconductor layer 230 is low. It is also preferable that an appropriate amount of oxygen is supplied to the semiconductor layer 230. Furthermore, it is preferable to reduce the amount of excess oxygen in the semiconductor layer 230.

[0070] The semiconductor layer 230 contains indium and oxygen. For example, it is preferable that the semiconductor layer 230 has an indium oxide film. The higher the ratio of the number of indium atoms to the sum of the number of atoms of all metal elements contained in the metal oxide, the higher the field-effect mobility of the transistor can be. Therefore, by using indium oxide in the semiconductor layer 230, the transistor can obtain a large on-current and high frequency characteristics.

[0071] Furthermore, it is preferable that the indium oxide film is crystalline. For example, it is preferable that the indium oxide film has crystal grains. Examples of films having crystal grains include single-crystal films, polycrystalline films, or amorphous films containing crystal grains. A polycrystalline film is composed of two or more crystal grains, while a single-crystal film can be considered to be composed of one crystal grain. In polycrystalline films, crystal grain boundaries (also called grain boundaries) can be observed, whereas in single-crystal films, crystal grain boundaries cannot be observed.

[0072] Furthermore, unlike polycrystalline films, single-crystal films do not exhibit grain boundaries in the channel formation region. Impurities that inhibit carrier flow (typically insulating impurities, insulating oxides, etc.) tend to segregate at grain boundaries. Therefore, when grain boundaries are present in the channel formation region, variations in transistor characteristics become large. On the other hand, in a single-crystal film according to one aspect of the present invention, since no grain boundaries are observed in the channel formation region, it exhibits the excellent effect of suppressing variations in transistor characteristics caused by such grain boundaries.

[0073] Furthermore, in this specification, a semiconductor layer in which no grain boundaries are observed in the channel-forming region, a semiconductor layer in which the channel-forming region is contained within a single crystal grain, or a semiconductor layer in which the crystal axis directions are the same in at least two regions within the channel-forming region can be called a single-crystal film. Alternatively, a semiconductor layer in which at least one crystal orientation is oriented in one direction in the channel-forming region can be called a single-crystal film.

[0074] The channel-forming region refers to a region within a semiconductor layer that overlaps with (or faces) the gate electrode via the gate insulating layer, and is located between the region in contact with the source electrode and the region in contact with the drain electrode. Furthermore, a semiconductor layer in which no grain boundaries are observed in the region between the source electrode and the drain electrode, a semiconductor layer in which the region between the source electrode and the drain electrode is contained within a single crystal grain, or a semiconductor layer in which at least two regions located between the source electrode and the drain electrode have the same crystal axis direction can also be called a single-crystal film. Alternatively, a semiconductor layer in which at least one crystal orientation is oriented in one direction in the region between the source electrode and the drain electrode can also be called a single-crystal film.

[0075] Furthermore, in the channel formation region, the current path is the shortest distance between the source electrode and the drain electrode. Therefore, the crystal grains, grain boundaries, crystal axes, and crystal orientations in the channel formation region, or the region located between the region in contact with the source electrode and the region in contact with the drain electrode, can be confirmed by cross-sectional observation including the semiconductor layer, source electrode, and drain electrode.

[0076] The crystallinity of the semiconductor layer 230 can be analyzed, for example, by X-ray diffraction (XRD), transmission electron microscopy (TEM), or electron diffraction (ED). Alternatively, a combination of these methods may be used for analysis.

[0077] Crystal grains can be identified, for example, using high-resolution transmission electron microscope (TEM) images. Furthermore, crystal grain boundaries can sometimes be identified, for example, using high-resolution TEM images. In other words, crystal grains and crystal grain boundaries can sometimes be observed in high-resolution TEM images of crystalline films. The overall magnification when acquiring TEM images is preferably 2 million times or more, and more preferably 4 million times or more.

[0078] The indium oxide film is more preferably a single-crystal film. Since a single-crystal film does not have grain boundaries, carrier scattering at grain boundaries can be suppressed, enabling the realization of transistors with high field-effect mobility. Furthermore, highly reliable transistors can be realized.

[0079] The indium oxide film may be a polycrystalline film or an amorphous film containing crystal grains. In this case, it is preferable that no crystal grain boundaries are observed or that there are few grain boundary components in the channel formation region. For example, by having one crystal grain located in the channel formation region, it is possible to create a configuration in which no crystal grain boundaries are observed in the channel formation region. Even with such a configuration, the same effects as the configuration in which the indium oxide film is a single crystal film can be achieved.

[0080] Furthermore, two or more crystal grains can be located in the channel-forming region. For example, when a first crystal grain and a second crystal grain are located in the channel-forming region, it is preferable that the crystal orientation of the first crystal grain and the crystal orientation of the second crystal grain coincide or approximately coincide. When the crystal orientations of the first and second crystal grains coincide or approximately coincide, a grain boundary may not be observed at the boundary between the first and second crystal grains. By having the crystal orientations of the first and second crystal grains coincide or approximately coincide, the formation of a grain boundary between the first and second crystal grains can be suppressed. Therefore, even in such a configuration, the same effects as in a configuration where the indium oxide film is a single crystal film can be achieved. Note that the coincidence or approximately coincidence of the crystal orientations of the first and second crystal grains can sometimes be confirmed, for example, by a high-resolution TEM image. Specifically, this can be confirmed in high-resolution TEM images by observing that the lattice patterns of the first crystal grain and the second crystal grain are continuously connected at the boundary between the first and second crystal grains.

[0081] In this specification, a grain boundary refers to, for example, the boundary between adjacent crystal grains with different crystal orientations. Therefore, in this specification, the boundary between adjacent crystal grains with the same crystal orientation is not included in the definition of a grain boundary. For example, even if a boundary is observed between two crystal grains in a high-resolution TEM image, if the crystal orientations of those two crystal grains are the same or nearly the same, the boundary may not be called a grain boundary.

[0082] The degree of polycrystalline nature of an indium oxide film can be evaluated by the grain size. The grain size can be calculated, for example, by determining the area of ​​the grain and then determining the diameter of a circle corresponding to that area. This diameter is sometimes referred to as the area-circle equivalent diameter.

[0083] Furthermore, the degree of polycrystalline nature of an indium oxide film can also be evaluated by the length of the grain boundaries. The length of the grain boundaries can be calculated, for example, by extracting a field of view of a specific area from a TEM image of the film acquired at a total magnification where the grain boundaries can be observed, and summing the lengths of the grain boundaries observed in that field of view. An indium oxide film with a grain boundary length of 0 nm can be considered a single-crystal film. Also, a longer grain boundary length indicates a higher proportion of grain boundary components.

[0084] The extended grain boundary length in the indium oxide film is preferably 0 nm to 1500 nm, more preferably 0 nm to 1000 nm, and even more preferably 0 nm to 800 nm. By having an indium oxide film with an extended grain boundary length within the above range in the semiconductor layer 230, a configuration can be achieved in which no crystal grain boundaries are observed or where there are few grain boundary components in the channel formation region. Unless otherwise specified in this specification, the field of view used to calculate the extended grain boundary length is 90 nm square.

[0085] The thickness of the semiconductor layer 230 is more preferably 2 nm to 50 nm, more preferably 2.5 nm to 30 nm, more preferably 2.5 nm to 20 nm, more preferably 5 nm to 20 nm, and even more preferably 5 nm to 10 nm. The semiconductor layer 230 only needs to have regions with the above-mentioned thickness in at least a portion of it. For example, the channel formation region of the semiconductor layer 230 only needs to have regions with the above-mentioned thickness. Increasing the thickness of the semiconductor layer 230 makes it possible to increase the on-current of the transistor. On the other hand, if the thickness of the semiconductor layer 230 is made too thick, the extension length of the grain boundaries increases, and the on-current of the transistor may decrease due to the influence of carrier scattering at the grain boundaries. Furthermore, by making the thickness of the semiconductor layer 230 thinner, it is possible to suppress the decrease in the threshold voltage and make it possible to create a normally-off transistor. On the other hand, if the thickness of the semiconductor layer 230 is made too thin, the crystallinity of the semiconductor layer 230 will vary within the substrate surface, which may cause variations in the electrical characteristics of the transistor. Therefore, by setting the thickness of the semiconductor layer 230 within the above range, the crystallinity of the semiconductor layer 230 can be increased. By increasing the crystallinity of the semiconductor layer 230, the semiconductor layer 230 can have crystalline grains.

[0086] Furthermore, when a metal oxide contains indium and zinc, it may have a CAAC (c-axis aligned crystal) structure. The CAAC structure has fewer grain boundaries in the a-b plane than the polycrystalline structure. Examples of metal oxides containing indium and zinc include indium zinc oxide (In-Zn oxide, also known as IZO®) and indium gallium zinc oxide (In-Ga-Zn oxide, also written as IGZO).

[0087] In a crystalline oxide semiconductor layer, an indium oxide film is a film in which one or both of hydrogen and oxygen move more easily compared to, for example, an IGZO film. Therefore, it can be said that an indium oxide film is a film in which one or both of hydrogen and oxygen are more easily supplied and one or both of hydrogen and oxygen are more easily discharged compared to, for example, an IGZO film. Note that it can be said that an indium oxide film is a film having high permeability to one or both of hydrogen and oxygen. In other words, it can be said that an indium oxide film is a film having low barrier properties to one or both of hydrogen and oxygen compared to, for example, an IGZO film.

[0088] In a heat treatment where the heating temperature of the indium oxide film is 400 °C and the treatment time is 8 hours, for example, oxygen permeates at 1 cm ３ per 1×10 ２０ atoms or more and 2×10 ２１ atoms or less, preferably 2×10 ３ atoms or more and 1×10 ２０ atoms or less per 1 cm. It is preferable that the indium oxide film has the property of permeating. Also, by a heat treatment where the heating temperature of the indium oxide film is 400 °C and the treatment time is 8 hours, for example, oxygen diffuses through the crystal grains at 1 cm ２１ per 1×10 ３ atoms or more and 2×10 ２０ atoms or less, preferably 2×10 ２１ atoms or more and 1×10 ３ atoms or less per 1 cm. It is preferable that the indium oxide film has the property of oxygen diffusing within the crystal grains. ２０ ２１ Ｏ By the diffusion of oxygen in the indium oxide film through the crystal grains and grain boundaries, V existing in the crystal grains or grain boundaries

[0089] can be reduced. Therefore, the electrical characteristics and reliability of the transistor can be improved. Ｏ can be reduced. Therefore, the electrical characteristics and reliability of the transistor can be improved.

[0090] Furthermore, the permeability of the membrane to oxygen and hydrogen can be evaluated using a calculation method such as Nudged Elastic Band (NEB). Specifically, it can be evaluated by calculating the migration barriers for oxygen and hydrogen atoms using the NEB method. The smaller the value of the migration barrier, the easier it is for those atoms to move (permeate).

[0091] An example of the calculation results is shown in Table 1. ２ O ３ The first figure is a crystal model of indium oxide, and the second figure, IGZO, shown in Table 1, is a crystal model of In-Ga-Zn oxide. Note that the excess oxygen shown in Table 1 refers to oxygen not located at oxygen sites in the crystal lattice, or oxygen located between lattice spaces.

[0092]

[0093] Table 1 shows that the transport barriers for oxygen, hydrogen, and excess oxygen are large in the In-Ga-Zn oxide crystal model and small in the indium oxide crystal model. This suggests that oxygen and hydrogen move more easily (permeate more easily) in indium oxide compared to In-Ga-Zn oxide. Furthermore, it is suggested that the indium oxide film has higher permeability to oxygen and hydrogen atoms than the In-Ga-Zn oxide film. Therefore, it is inferred that the indium oxide film is a film that easily supplies hydrogen and oxygen and easily releases hydrogen and oxygen. In addition, the V generated in the +GBT test Ｏ It is expected that this will fill the gaps with oxygen, which could lead to the realization of highly reliable transistors.

[0094] Therefore, as shown in Figure 3A, the indium oxide film (InO Ｘ Oxygen (O) diffusing into the indium oxide film passes through the indium oxide film and oxygen molecules (O) ２ It is released as water molecules (H) by reacting with hydrogen contained in the membrane. ２In some cases, oxygen may be released as (O). Also, if oxygen vacancies (Vo) exist in the film, diffusing oxygen atoms will fill the vacancies. Indium oxide films allow oxygen to diffuse easily, so they can be said to fill oxygen vacancies more easily than IGZO films. Thus, indium oxide films reduce oxygen vacancies in the film more easily than IGZO films, and by applying such indium oxide films to transistors, it is possible to realize transistors that exhibit extremely high reliability.

[0095] Furthermore, as shown in Figure 3A, the indium oxide film diffuses hydrogen. Hydrogen diffusing into the indium oxide film from the outside permeates the film and forms hydrogen molecules (H ２ It is released as ) or, as mentioned above, it is released as water molecules by reacting with oxygen contained in the membrane.

[0096] It is preferable that the content of the first element in the semiconductor layer 230 be low. Furthermore, it is preferable that the concentration of the first element in the semiconductor layer 230 be low. In particular, it is preferable that the concentration of the first element in the channel formation region be low. Here, the first element is at least one of boron, carbon, aluminum, silicon, zinc, and gallium. That is, in the semiconductor layer 230, it is preferable that the concentration of any one of boron, carbon, aluminum, silicon, zinc, and gallium be low, more preferably that the concentration of two selected from boron, carbon, aluminum, silicon, zinc, and gallium be low, and even more preferably that the concentrations of all of boron, carbon, aluminum, silicon, zinc, and gallium be low. The concentration of the first element in the semiconductor layer 230 is preferably, for example, 1 atomic% or less, more preferably 0.1 atomic% or less, and even more preferably 0.01 atomic% (100 ppm) or less. Furthermore, the preferred concentration of the first element in the semiconductor layer 230 can also be said to be the preferred concentration of the first element in the channel formation region.

[0097] Furthermore, as will be described later, by using a precursor that has undergone one or more distillations, it is possible to set the concentration of the first element in the semiconductor layer 230 to 0.01 atomic% (100 ppm) or less, 0.0001% (1 ppm) or less, 0.00001% (0.1 ppm or 100 ppb) or less, or 0.0000001% (0.001 ppm or 1 ppb) or less. In other words, the indium content (purity) excluding oxygen in the semiconductor layer 230 can be set to 99.99 atomic% or more (4N), 99.9999 atomic% or more (6N), 99.99999 atomic% or more (7N), or 99.9999999 atomic% or more (9N), making it possible to form a semiconductor layer 230 with a purity comparable to that of silicon used in the semiconductor layer (10N).

[0098] By lowering the concentrations of boron, carbon, aluminum, and silicon in the semiconductor layer 230, the crystallinity of the semiconductor layer 230 can be improved.

[0099] When the semiconductor layer 230 contains gallium atoms, these gallium atoms bond with excess oxygen atoms to form a Ga-O structure. The Ga-O structure functions as an acceptor that traps electrons. Therefore, in a transistor having a semiconductor layer 230 containing gallium atoms and excess oxygen atoms, the fluctuation in the threshold voltage in the PBTS (Positive Bias Temperature Stress) test becomes large. Thus, by lowering the concentration of gallium in the semiconductor layer 230, the fluctuation in the threshold voltage in the PBTS test can be reduced. This results in a transistor with high reliability against positive bias application. The same thing can happen when the semiconductor layer 230 contains zinc atoms as when it contains gallium atoms.

[0100] Furthermore, compared to indium atoms, aluminum, gallium, and zinc atoms have stronger bonding forces with oxygen atoms. Therefore, by lowering the concentrations of aluminum, gallium, and zinc in the indium oxide film, it is possible to suppress the decrease in oxygen permeability.

[0101] Furthermore, impurities such as the first element contained in the indium oxide film can act as crystal nuclei. By reducing impurities in the indium oxide film as much as possible, the number of crystal nuclei can be reduced, which promotes the formation of larger crystal grains, as will be described later.

[0102] Furthermore, if the indium oxide film is a polycrystalline film, the first element segregates at the grain boundaries, forming an oxide containing the first element. Since this oxide is an insulator, it may cause a decrease in the transistor's on-current or field-effect mobility. By reducing the amount of the first element in the indium oxide film as much as possible, the transistor's on-current or field-effect mobility can be increased.

[0103] Furthermore, impurities in the indium oxide film can be reduced to suppress impurity scattering. Therefore, a transistor with high field-effect mobility can be realized. For example, by setting the concentration of the first element in the semiconductor layer 230 to the above preferred range, the field-effect mobility of the transistor can be increased to 50 cm⁻¹. ２ / (V·s) or more, preferably 100 cm ２ / (V·s) or more, more preferably 150 cm ２ / (V·s) or more, more preferably 200 cm ２ / (V·s) or more, more preferably 250 cm ２ It can be set to (V・s) or more.

[0104] Here, we will explain the carrier concentration dependence of the hole (Hall) mobility of indium oxide, silicon, and IGZO. Figure 3B shows silicon (Si) and indium oxide (InO2). Ｘ Figure 3C is a schematic diagram of the carrier concentration dependence of hole mobility with respect to IGZO.

[0105] First, as indicated by the arrows in Figure 3C, IGZO tends to exhibit higher hole mobility as the carrier concentration increases. On the other hand, as indicated by the arrows in Figure 3B, indium oxide tends to exhibit higher hole mobility as the carrier concentration decreases (see Non-Patent Literature 2). This trend is similar to that of silicon, where the lower the concentration of dopants (impurities) in the material, the less impurity scattering occurs and the higher the hole mobility. In other words, the higher the purity and intrinsic nature of indium oxide, the higher its hole mobility. From these results, it can be said that indium oxide, unlike IGZO, is a material with physical properties similar to silicon. Note that the properties of indium oxide shown in Figure 3B are assumed to be those of a single crystal. Therefore, when indium oxide is not a single crystal (for example, polycrystalline), the properties may differ from those shown in Figure 3B.

[0106] In Figure 3B, the low carrier concentration range R1 exhibits extremely high hole mobility, making it a suitable carrier concentration range for, for example, the channel formation region of a transistor. For example, in the case of indium oxide, the range R1 has a carrier concentration of 1 × 10⁻⁶. １５ cm −３ This range includes, for example, 1 × 10 １４ cm −３ The above is 1 x 10 １８ cm −３ The range is as follows: By sufficiently reducing the carrier concentration, the hole mobility value can be increased to 270 cm⁻¹. ２ It can be expected to be raised to the level of / (V・s).

[0107] Furthermore, in indium oxide, the region where the carrier concentration is within the range R1 may contain elements that lower the carrier concentration. Examples of elements that lower the carrier concentration include magnesium, calcium, cadmium, and copper. By substituting these elements for indium, the carrier concentration can be lowered. Other elements that lower the carrier concentration include nitrogen, phosphorus, arsenic, and antimony. For example, by substituting nitrogen, phosphorus, arsenic, or antimony for oxygen, the carrier concentration can be lowered.

[0108] On the other hand, the range R2 with high carrier concentration has low electrical resistance and can be said to be a suitable range of carrier concentration for applications such as the source and drain regions of a transistor, or resistors, or transparent conductive films. Range R2 is when the carrier concentration value is 1 × 10⁻⁶ ２０ cm −３ This range includes, for example, 1 × 10 １９ cm −３ The above is 1 x 10 ２２ cm −３ The range is as follows: By making the carrier concentration sufficiently high, the resistivity can be increased to 1 × 10⁻⁶. −４ It is expected that the level can be reduced to below Ω·cm.

[0109] In the case of indium oxide, the region where the carrier concentration is in the range R2 may contain elements that increase the carrier concentration. For example, it is preferable to include elements common to the source and drain electrodes of the transistor. Examples of elements that increase the carrier concentration include titanium, tantalum, tungsten, molybdenum, tin, silicon, germanium, zirconium, hafnium, and boron. In particular, it is more preferable to use elements whose oxides are conductive or semiconducting. As for the supply method of elements that increase the carrier concentration, a method of forming a film containing the element and diffusing it, ion implantation, ion doping, plasma immersion ion implantation, or plasma treatment can be used. In this specification, unless otherwise specified, the presence or absence of mass separation is not limited. For example, in this specification, a method of supplying ions by mass separation is called ion implantation, and a method of supplying ions without mass separation is called ion doping.

[0110] In this way, indium oxide uses regions with low carrier concentrations for the transistor's channel formation region and regions with high carrier concentrations for the transistor's source and drain regions. In other words, indium oxide can be said to be an oxide in which valence electron control is possible. In contrast, with IGZO, strain can form in the source and drain regions due to stress on the electrodes in contact with IGZO, and n-type regions may be formed. On the other hand, unlike IGZO, indium oxide allows for valence electron control, so it does not require strain to form in the film as in IGZO. Less strain in the film is expected to improve reliability. For example, by creating regions with carrier concentrations in the range R1 and range R2 shown in Figure 3B within the indium oxide film, a so-called n-i-n junction (a junction between an n-type region, an i-type region, and an n-type region) can be created. Valence electron control in silicon transistors is generally known. On the other hand, valence electron control in indium oxide transistors is a novel technological concept that would not normally be conceived.

[0111] For example, by adding an atom that can become a cation with a valency of 4 or higher to indium oxide, the atom substitutes for an indium atom, resulting in one or more electrons remaining, and no energy levels are formed within the band restriction, thus forming an n-type system. Examples of such atoms include tin, antimony, germanium, and titanium. In other words, by adding such an atom to indium oxide, the carrier concentration in the added region increases, and that region can be used as a source region or a drain region.

[0112] The concentration of the first element can be determined by, for example, inductively coupled plasma mass spectrometry (ICP-MS), X-ray photoelectron spectroscopy (XPS), secondary ion mass spectrometry (SIMS), time-of-flight secondary ion mass spectrometry (ToF-SIMS), and Auger electron spectroscopy (AES). It can be evaluated using methods such as spectroscopy, energy-dispersive X-ray spectroscopy (EDX), or inductively coupled radio-frequency plasma emission spectroscopy (ICP-AES).

[0113] Hydrogen contained in oxide semiconductors can react with oxygen bonded to metal atoms to form water, potentially creating oxygen vacancies. Consequently, electrical properties may fluctuate, leading to reduced reliability. On the other hand, hydrogen present at grain boundaries can terminate dangling bonds, improving the electrical properties and reliability of the transistor. Therefore, while it is preferable to reduce the hydrogen concentration in the indium oxide film, it may be higher than the concentration of the first element in some cases.

[0114] The band gap of indium oxide is between 2.5 eV and 3.7 eV. By using indium oxide, which has a larger band gap than silicon, in the semiconductor layer 230, the off-current of the transistor can be reduced, and the power consumption of the semiconductor device can be significantly reduced.

[0115] Transistors using indium oxide films are storage-type transistors that use electrons as majority carriers. Assuming that the carrier relaxation time is constant, the smaller the effective mass of electrons (carriers), the higher the electron mobility. In other words, by using indium oxide, which has a small effective mass of electrons, in a transistor, the on-current or field-effect mobility of the transistor can be increased.

[0116] Here, single crystal indium oxide (here, In ２ O ３ The effective masses of electrons (m) are shown in Table 2 for single-crystal In-Ga-Zn oxide (IGZO in this case) and single-crystal silicon (Si). ＊ ｅ ) and the effective mass of the hole (m ＊ ｈ This value is calculated by first-principles electronic state calculations.

[0117] The above first-principles electronic state calculations utilize the Quantum ESPRESSO package, which is based on density functional theory (DFT) using plane wave basis and pseudopotentials. The exchange-correlation functional is GGA / PBE (Generalized-Gradient-Approxification / Perdew-Burke-Ernzerhof). An ultrasoft pseudopotential is used. The wave function cutoff energy is set to 100 Ry, and the electron density cutoff energy is set to 900 Ry. Spin polarization is assumed to be absent.

[0118] First, a calculation to optimize the structure (also called a structural optimization calculation) is performed, followed by an SCF (Self Consistent Field) calculation, and then a band calculation. The E-k dispersion curve can be obtained through the band calculation. Next, the effective mass of electrons and the effective mass of holes are calculated by fitting the band edges in the E-k dispersion curve with a quadratic function.

[0119]

[0120] As shown in Table 2, the effective electron mass of indium oxide is small. Therefore, by using indium oxide, which has a small effective electron mass, in the semiconductor layer 230, it is possible to realize transistors with a large on-current, high field-effect mobility, and high frequency characteristics (also called f-characteristics). Furthermore, the effective electron mass of indium oxide has the characteristic of being almost independent of the crystal orientation. In addition, the effective electron mass of indium oxide is smaller than, for example, the effective electron mass of silicon. Therefore, from the viewpoint of the effective electron mass, the f-characteristics of a transistor using indium oxide in the channel formation region will be higher than that of a Si transistor.

[0121] As shown in Table 2, the effective hole mass of indium oxide is large. Therefore, by using indium oxide, which has a large effective hole mass, in the semiconductor layer 230, a transistor with an extremely low off-current can be realized. Furthermore, the effective hole mass of indium oxide is larger than, for example, the effective hole mass of silicon. Specifically, the effective hole mass of indium oxide is about 20 times heavier than, for example, the effective hole mass of silicon. Therefore, from the viewpoint of effective hole mass, the off-current of a transistor using indium oxide in the channel formation region is significantly smaller than the off-current of a Si transistor. As shown in Table 2, the off-current I of a transistor using indium oxide in the channel formation region ｏｆｆ This is the off-current I of the Si transistor. ｏｆｆ This is 10 orders of magnitude smaller. Table 2 also shows typical band gap (Eg) values ​​for each material. Note that 3.028 eV in Table 2 is a typical Eg for In-Ga-Zn oxide films deposited using the ALD method, and 3.14 eV in Table 2 is a typical Eg for In-Ga-Zn oxide films deposited using the sputtering method.

[0122] In a transistor using indium oxide as the semiconductor layer 230, the off-current value at room temperature (25°C) per 1 μm channel width is 1 × 10⁻¹⁶ −１７ A / μm or less, preferably 1 × 10 −１８ A / μm or less, more preferably 1 × 10 −１９It is possible to reduce the A / μm or less. Also, the off-current value at 85°C per 1 μm of channel width is 1 × 10⁻¹⁶ −１６ A / μm or less, preferably 1 × 10 −１７ A / μm or less, more preferably 1 × 10 −１８ It is possible to reduce the A / μm level to less than or equal to 1 / μm.

[0123] Furthermore, miniaturizing the OS transistor can improve its high-frequency characteristics. For example, the transistor's cutoff frequency (fT) can be improved. Specifically, the transistor's cutoff frequency can be set to 50 GHz or higher, preferably 100 GHz or higher, and more preferably 150 GHz or higher, under room temperature (25°C) conditions.

[0124] Furthermore, by reducing the grain boundaries in the indium oxide, carrier scattering at the grain boundaries is suppressed, making it easier to apply the gate electric field to the conductive layer 260. Also, by reducing the grain boundaries in the indium oxide, the incorporation of impurities into the indium oxide via the grain boundaries is suppressed, thereby reducing impurities in the indium oxide film. As a result, the on-current of the transistor can be improved and the subthreshold swing value (S value) of the transistor can be reduced. Specifically, the S value of the transistor can be set to 60 mV / dec. to 120 mV / dec., preferably 60 mV / dec. to 100 mV / dec., and more preferably 60 mV / dec. to 80 mV / dec. The S value refers to the change in gate voltage when the drain current is changed by one order of magnitude while the drain voltage is constant in the subthreshold region.

[0125] The semiconductor layer 230 is preferably formed using the ALD method. By using the ALD method, which deposits atoms individually during film formation, rather than the sputtering method, which impacts the surface to be formed with particles, the formation of crystal nuclei in the film can be suppressed. For example, a first precursor and a first oxidizing agent can be used to form the semiconductor layer 230. The first precursor preferably contains indium. In this case, an indium oxide film is formed as the semiconductor layer 230. When the first precursor contains indium, the thermal ALD method can be used as the ALD method.

[0126] Indium-containing precursors that can be used include trimethylindium, triethylindium, ethyldimethylindium, tris(1-methylethyl)indium, tris(2,2,6,6-tetramethyl-3,5-heptanedionic acid)indium, cyclopentadienylindium, indium(III) acetylacetonate, (3-(dimethylamino)propyl)dimethylindium, (diethylphosphino)dimethylindium, chlorodimethylindium, bromodimethylindium, and dimethyl(2-propanolat)indium.

[0127] Furthermore, inorganic precursors that do not contain hydrocarbons may be used as indium precursors. Examples of indium-containing inorganic precursors include halogenated indium compounds such as trifluoroindium (indium(III) fluoride), indium trichloride (indium(III) chloride), indium tribromide (indium(III) bromide), and indium triiodide (indium(III) iodide). Indium trichloride has a decomposition temperature of approximately 500°C to 700°C. Therefore, by using indium trichloride, film deposition by the ALD method can be performed while heating the substrate at approximately 400°C to 600°C, for example, at 500°C.

[0128] In the method for forming the semiconductor layer 230, it is preferable to use a precursor with a low impurity concentration, i.e., a high purity precursor. For example, by using a precursor with a purity of 3N (99.9%) or higher, preferably 4N (99.99%) or higher, more preferably 5N (99.999%) or higher, and even more preferably 6N (99.9999%) or higher, the amount of impurities in the semiconductor layer 230 can be reduced.

[0129] The gallium content and aluminum content of the indium-containing precursor are preferably 1000 ppm or less, more preferably 500 ppm or less, even more preferably 100 ppm or less, even more preferably 50 ppm or less, even more preferably 10 ppm or less, and even more preferably 1 ppm or less. By using a precursor with a low gallium content, the gallium concentration in the semiconductor layer 230 can be reduced, thereby improving the reliability of the transistor. Furthermore, by using a precursor with a low aluminum content, the aluminum concentration in the semiconductor layer 230 can be reduced, thereby improving the crystallinity of the semiconductor layer 230.

[0130] Furthermore, it is preferable to use a precursor that has been purified by two or more distillations (also called rectification or precision distillation) as the precursor used in this embodiment. Using such a precursor makes it easier to form a metal oxide film with fewer impurities, which is preferable. Performing distillation multiple times is preferable because it can further suppress the retention of impurities in the precursor that originate from the starting materials used in the manufacture of the precursor. However, the present invention is not limited to the above, and a precursor purified by one distillation, i.e., simple distillation, may also be used. Using simple distillation is preferable because it can reduce manufacturing costs. By performing distillation one or more times, the aluminum content of the indium-containing precursor can be set to 100 ppm or less, 1 ppm or less, or 1 ppb (0.001 ppm) or less.

[0131] As the first oxidizing agent, ozone (O ３ ), oxygen (O ２ ), water (H ２ O), hydrogen peroxide (H ２ O ２) and the like can be used. Preferably, the first oxidizing agent contains at least one of ozone and oxygen. By using ozone, oxygen, etc., which do not contain hydrogen, as the first oxidizing agent, the amount of hydrogen mixed into the semiconductor layer 230 can be reduced.

[0132] Unless otherwise specified in this specification, when ozone, oxygen, or water are used as oxidizing agents, these shall include not only gaseous or molecular states, but also plasma states, radical states, or ionic states.

[0133] The pulse time for introducing the first oxidizing agent is preferably 0.1 seconds to 30 seconds, more preferably 0.3 seconds to 15 seconds, and even more preferably 0.3 seconds to 10 seconds. By shortening the pulse time for introducing the first oxidizing agent and reducing the amount of the first oxidizing agent introduced, more hydrogen contained in the first precursor remains in the film. By leaving more hydrogen in the film, the formation of crystal nuclei is suppressed, and some of the crystal nuclei in the film are eliminated, resulting in a small number of crystal nuclei in the film.

[0134] Here, the substrate heating temperature when introducing the first precursor into the reaction chamber is preferably a temperature corresponding to the decomposition temperature of the first precursor. In the case of a thermal ALD method using triethylindium as the indium-containing precursor, for example, the substrate heating temperature can be 100°C to 350°C, preferably 150°C to 300°C. When an oxide layer 245, which will be described later, is provided, the substrate heating temperature can be room temperature (25°C) to 300°C, preferably room temperature to 200°C, and more preferably room temperature to 150°C.

[0135] After providing the oxide layer 245 described later, the semiconductor layer 230 can be formed by the ALD method, which may allow for the formation of a crystalline semiconductor layer 230 during the semiconductor layer formation process. For example, by setting the substrate heating temperature during film formation by the ALD method to a range of 100°C to 300°C, or 150°C to 250°C, a crystalline semiconductor layer 230 can be formed during film formation.

[0136] The semiconductor layer 230 can also be deposited using sputtering, chemical vapor deposition (CVD), molecular beam epitaxy (MBE), or pulsed laser deposition (PLD).

[0137] To improve the crystallinity of the semiconductor layer 230, it is preferable to provide an oxide layer 245 on the conductive layer 240. The oxide layer 245 functions as a seed or nucleus for improving the crystallinity of the semiconductor layer 230. Therefore, the oxide layer 245 can be called a seed layer, seed crystal, crystal nucleus, etc. By providing the oxide layer 245, a highly crystalline semiconductor layer 230 can be formed at any location (for example, the upper surface of the insulating layer 280 or the side surface of the insulating layer 280).

[0138] To enhance the crystallinity of the semiconductor layer 230, it is preferable to use In-Ga-Zn oxide as the oxide layer 245. The semiconductor layer 230 can be heteroepitaxially grown with the oxide layer 245 as a nucleus, thereby enhancing the crystallinity of the semiconductor layer 230. In this case, the orientation of the first crystal of the oxide layer 245 and the orientation of the second crystal of the semiconductor layer 230 coincide or substantially coincide.

[0139] Indium oxide crystals have a cubic crystal structure (Bixbite type). Therefore, the oxide layer 245 can be an oxide layer 245 having a first crystal whose crystal structure is hexagonal or trigonal. In this case, by forming the oxide layer 245 such that the <001> orientation of the first crystal is perpendicular or approximately perpendicular to the substrate surface or the surface to be formed, a semiconductor layer 230 can be formed having a second crystal whose <111> orientation is parallel or approximately parallel to the <001> orientation of the first crystal.

[0140] Alternatively, the oxide layer 245 can be an oxide layer 245 having a first crystal having a cubic crystal structure. In this case, by forming the oxide layer 245 such that the <111> orientation of the first crystal is perpendicular or approximately perpendicular to the substrate surface or the surface to be formed, a semiconductor layer 230 can be formed on the oxide layer 245 with a crystal orientation <111> perpendicular or approximately perpendicular to the substrate surface or the surface to be formed.

[0141] In this specification, space groups are expressed using international notation (or Hermann-Mauguin notation) in short notation. Crystal planes and crystal orientations are expressed using Miller indices. In crystallography, space groups, crystal planes, and crystal orientations are expressed by superscripting numbers, but in this specification, due to formatting constraints, a minus sign (-) may be placed before the number instead of a superscript. Individual orientations within a crystal are represented by [ ], collective orientations representing all equivalent orientations are represented by < >, individual crystal planes are represented by ( ), and collective planes with equivalent symmetry are represented by {}.

[0142] In this specification, unless otherwise specified, the crystal orientation of a crystal refers to the orientation relative to the surface of the substrate. However, the crystal orientation of a crystal may also refer to the orientation relative to the surface on which the film or layer containing the crystal is formed.

[0143] Specifically, the oxide layer 245 can be indium oxide, zinc oxide, indium gallium oxide (also written as In-Ga oxide), indium tin oxide (also written as In-Sn oxide, ITO), indium tungsten oxide (also written as In-W oxide), In-Zn oxide, gallium zinc oxide (also written as Ga-Zn oxide, GZO), aluminum zinc oxide (also written as Al-Zn oxide, AZO), indium aluminum zinc oxide (also written as In-Al-Zn oxide, IAZO), In-Ga-Zn oxide, or indium tin zinc oxide (also written as In-Sn-Zn oxide). It is preferable to use In-Ga-Zn oxide as the oxide layer 245. In this case, the oxide layer 245 contains indium, gallium, zinc, and oxygen. Specifically, it is preferable to have a composition of In:Ga:Zn = 1:1:1 [atomic ratio] or close to that, or a composition of In:Ga:Zn = 1:3:2 [atomic ratio] or close to that.

[0144] In-Ga-Zn oxides and In-Sn-Zn oxides, etc., tend to have a CAAC structure. When an oxide having a CAAC structure is used for the oxide layer 245, the c-axis of the first crystal is perpendicular or approximately perpendicular to the substrate surface or the surface on which the oxide layer 245 is formed. In other words, the <001> orientation of the first crystal is perpendicular or approximately perpendicular to the substrate surface or the surface on which the oxide layer 245 is formed. Therefore, by using an oxide that tends to have a CAAC structure for the oxide layer 245, the controllability of the orientation of the first crystal can be improved. The above structure can be understood as a structure in which a semiconductor layer 230 having a cubic crystal structure is formed on an oxide layer 245 having a crystal with a CAAC structure. That is, it can also be considered as a layered structure fabricated using heteroepitaxial growth technology or a technology similar to heteroepitaxial growth.

[0145] Here, the crystal structures of metal oxides are shown in Figures 4A to 4E. Figure 4A is a view of the crystal structure of In-Ga-Zn oxide with a composition of In:Ga:Zn = 1:1:1 [atomic ratio], viewed from a direction perpendicular to the c-axis. Figure 4B is a view of the plane indicated by the dashed line in Figure 4A, viewed from the c-axis direction. Figure 4C is a view of the plane indicated by the dashed line in Figure 4A, viewed from the c-axis direction. Figure 4D is a view of the plane indicated by the double-dotted line in Figure 4A, viewed from the c-axis direction. In Figures 4A, 4C, and 4D, Mx represents a Ga atom or a Zn atom. Note that in Figure 4A, the plane indicated by the dashed line, the plane indicated by the dashed line, and the plane indicated by the double-dotted line are sometimes collectively called the c-plane. Figure 4E is a view of the crystal structure of indium oxide, viewed from a direction perpendicular to the (111) plane.

[0146] The interatomic distance between metal atoms on the c-plane (indicated by double arrows in Figures 4B to 4D) is said to be 0.330 nm. Furthermore, the In-In distance on the (111) plane (indicated by double arrows in Figure 4E) is said to be 0.334 nm and 0.385 nm. This indicates that the arrangement of metal atoms is similar between the c-plane of the CAAC structure and the (111) plane of indium oxide. Therefore, oxides that readily possess a CAAC structure can be suitably used as the oxide layer 245.

[0147] Furthermore, it is preferable that the difference (also called lattice mismatch) between the lattice constant or unit cell vector length of the first crystal and the lattice constant or unit cell vector length of the second crystal is small. By using an oxide that reduces lattice mismatch in the oxide layer 245, the crystallinity of the semiconductor layer 230 can be improved.

[0148] One method for evaluating the degree of lattice mismatch is to use the lattice mismatch value shown below. The lattice mismatch Δa [%] of the crystals of the forming film (in this case, the indium oxide film) relative to the crystals of the film being formed is calculated using the following formula (1). Hereafter, the lattice mismatch Δa of the crystals of the forming film relative to the crystals of the film being formed may simply be referred to as the lattice mismatch Δa of the forming film relative to the film being formed.

[0149]

[0150] In formula (1), L １ L is the lattice constant or unit cell vector length of the crystal of the formed film. ２ This is the lattice constant or the length of the unit cell vector of the crystal of the film to be formed.

[0151] The lattice mismatch Δa of the second crystal with respect to the first crystal is preferably -10% or more and 10% or less, more preferably -5% or more and 5%, and even more preferably -3% or more and 3% or less. By using a material for the oxide layer 245 that has a small lattice mismatch with respect to the semiconductor layer 230, the crystallinity of the semiconductor layer 230 can be improved.

[0152] The oxide layer 245 may also use an oxide having a second crystal with a cubic crystal structure. Since the first crystal has the same crystal structure as the second crystal, the semiconductor layer 230 can be epitaxially grown using the oxide layer 245 as a seed or nucleus, thereby increasing the crystallinity of the semiconductor layer 230. Note that crystals of oxides containing group 3 elements in the periodic table tend to have a cubic crystal structure. Furthermore, the group 3 elements in such crystals mainly exist as trivalent cations. Therefore, it is preferable that the oxide layer 245 contains at least one element that can become a trivalent cation. Preferred elements that can become trivalent cations in the oxide layer 245 include scandium, yttrium, cerium, gadolinium, erbium, or ytterbium.

[0153] As the oxide layer 245, for example, an oxide containing one or both of yttrium and zirconium, erbium oxide, etc., can be used. Examples of oxides containing one or both of yttrium and zirconium include yttrium oxide, zirconium oxide, yttrium zirconium oxide, etc.

[0154] It is preferable that the oxide layer 245 has a thin film thickness. For example, it is preferable that the film thickness of the oxide layer 245 is thinner than the film thickness of the semiconductor layer 230. Specifically, it is preferable that the oxide layer 245 has a region in which the film thickness is 0.1 nm or more and less than 2 nm, and it is more preferable that it has a region in which the film thickness is 0.5 nm or more and less than 2 nm. By making the film thickness of the oxide layer 245 thin, the step difference that occurs between the oxide layer 245 and the insulating layer 280 is reduced. Therefore, the coverage of the semiconductor layer 230 is improved and defects such as porosity can be reduced. Furthermore, it is possible to promote crystal growth of the semiconductor layer 230. Furthermore, even if the oxide layer 245 has insulating properties, the conductive layer 240 and the semiconductor layer 230 can come into contact, and an increase in contact resistance can be suppressed.

[0155] The method for forming the oxide layer 245 is not particularly limited. For example, the oxide layer 245 can be formed by forming a film that will become the oxide layer 245 and then processing the film. The film can be formed using methods such as sputtering, CVD, vacuum deposition, PLD, or ALD.

[0156] The oxide layer 245 is preferably formed using a sputtering method. By using a sputtering method, the crystallinity of the oxide layer 245 can be improved.

[0157] By increasing the crystallinity of the oxide layer 245, the crystallinity of the semiconductor layer 230 on the oxide layer 245 can also be increased. An example of the crystal structure of the semiconductor layer 230 will be explained using Figures 5A and 5B. Figure 5A is an enlarged view of the region Q1 enclosed by the dashed line shown in Figure 2A. Figure 5B is an enlarged view of the region Q2 enclosed by the dashed line shown in Figure 2A. For example, by providing the oxide layer 245 such that the crystal structure is hexagonal or trigonal and has a first crystal whose <001> orientation is perpendicular or approximately perpendicular to the substrate surface or the surface to be formed, the <111> orientation of the crystal located between the bottom surface of the conductive layer 220_2 and the insulating layer 250 and the <111> orientation of the crystal located between the side surface of the recess in the conductive layer 220_2 and the insulating layer 250 coincide or approximately coincide (see Figure 5A). Similarly, by providing the oxide layer 245 such that it has a first crystal whose crystal structure is hexagonal or trigonal and whose <001> orientation is perpendicular or approximately perpendicular to the substrate surface or the surface to be formed, the <111> orientation of the crystal located on the oxide layer 245 and the <111> orientation of the crystal located between the side surface of the opening 290 of the conductive layer 240_2 and the insulating layer 250 coincide or approximately coincide (see Figure 5B). In other words, the <111> orientation of the crystal that the semiconductor layer 230 has within the opening 290 can be said to be parallel or approximately parallel to the depth direction of the opening 290. As shown in Figures 5A and 5B, the crystallinity of the semiconductor layer 230 can be increased even within the opening 290.

[0158] The semiconductor layer 230 may have crystals in the <111> orientation, and the oxide layer 245 may have crystals in the <001> orientation. Furthermore, by having at least a portion of the semiconductor layer 230 located on the oxide layer 245, the crystallinity of the semiconductor layer 230 can be increased. The high crystallinity of the semiconductor layer 230 can improve the electrical characteristics and reliability of the transistor 200A.

[0159] Although the semiconductor layer 230 has been shown as a single-layer structure, it is not limited to this and can also be a multilayer structure. Figure 6A shows an example in which the semiconductor layer 230 has a two-layer multilayer structure. Note that in Figure 6A, the detailed structure of the insulating layer 280 is omitted to avoid making the drawing complicated. As shown in Figure 6A, the semiconductor layer 230 can have a two-layer structure consisting of semiconductor layer 230_1 and semiconductor layer 230_2 on top of semiconductor layer 230_1. In this case, it is preferable to use a metal oxide (typically indium oxide) applicable to the semiconductor layer 230 as described above for semiconductor layer 230_1, and a metal oxide whose lower end of the conduction band is located on the vacuum level side of the lower end of the conduction band of semiconductor layer 230_1 for semiconductor layer 230_2. In this case, semiconductor layer 230_1 can mainly function as a current path (channel). That is, semiconductor layer 230_1 has a channel-forming region on the surface on the semiconductor layer 230_2 side and in its vicinity.

[0160] By using the above configuration, the number of carriers trapped at and near the interface of the semiconductor layer 230_1 can be reduced. In addition, the channel can be moved away from the surface of the insulating layer 250, reducing the effects of surface scattering. As a result, the field-effect mobility of the transistor can be increased.

[0161] As metal oxides applicable to semiconductor layer 230_2, for example, In-Ga oxide, In-Zn oxide, ITO, indium titanium oxide (also written as In-Ti oxide), indium tungsten oxide (also written as In-W oxide), In-Al-Zn oxide, In-Ga-Zn oxide, In-Sn-Zn oxide, indium titanium zinc oxide (also written as In-Ti-Zn oxide), indium tin oxide containing silicon oxide (also called ITSO), etc. can be used. Alternatively, zinc oxide, Al-Zn oxide, aluminum tin oxide (also written as Al-Sn oxide), etc. can be used.

[0162] The In-Zn oxide used in the semiconductor layer 230_2 can specifically have a composition of In:Zn = 1:1 [atomic ratio] or close to it, In:Zn = 2:1 [atomic ratio] or close to it, or In:Zn = 4:1 [atomic ratio] or close to it. Furthermore, the IGZO used in the semiconductor layer 230_2 can specifically have a composition of In:Ga:Zn = 1:1:1 [atomic ratio] or close to it, In:Ga:Zn = 1:3:2 [atomic ratio] or close to it, or In:Ga:Zn = 1:3:4 [atomic ratio] or close to it. Note that "close to" compositions include a range of ±30% of the desired atomic ratio.

[0163] The crystallinity of the metal oxide in the semiconductor layer 230_2 is not particularly limited. For example, the semiconductor layer 230_2 may include one or more amorphous semiconductors (semiconductors having an amorphous structure), single-crystal semiconductors (semiconductors having a single-crystal structure), or semiconductors having crystalline properties other than single crystals (microcrystalline semiconductors, polycrystalline semiconductors, or semiconductors having crystalline regions in part).

[0164] When the semiconductor layer 230 has a multilayer structure, the semiconductor layer 230 can also be formed using, for example, sputtering and ALD methods. For example, as shown in Figure 6A, when the semiconductor layer 230 has a two-layer structure consisting of semiconductor layer 230_1 and semiconductor layer 230_2, it is possible to deposit semiconductor layer 230_1 using the ALD method and semiconductor layer 230_2 using the sputtering method. Since the ALD method is a film deposition method with superior coverage compared to the sputtering method, the coverage of the semiconductor layer 230 can be improved by depositing semiconductor layer 230_1 using the ALD method. In addition, damage to the substrate (here, the conductive layer 220 or oxide layer 245) can be reduced, the formation of a mixed layer at the interface between the substrate and the semiconductor layer 230 can be suppressed, and crystallinity can be increased. Furthermore, productivity can be increased by depositing semiconductor layer 230_2 using the sputtering method.

[0165] Alternatively, the semiconductor layer 230_1 may be deposited by sputtering and the semiconductor layer 230_2 may be deposited by ALD. Even if pinholes or stepped defects are formed in the semiconductor layer 230_1 deposited by sputtering, the overlapping portions can be covered with the semiconductor layer 230_2 deposited by the ALD method, which has good coverage.

[0166] Figures 6B and 7A are examples of cross-sectional views of a semiconductor device, enlarged from the region D1 shown in Figure 6A. As shown in Figure 6B, the semiconductor layer 230 may have different film thicknesses T1 in the portion where the upper surface of the oxide layer 245 is the surface to be formed, and different film thicknesses T2 in the portion where the side surface of the opening 290 is the surface to be formed. For example, when a portion of the semiconductor layer 230 is formed by sputtering, the semiconductor layer 230 may have different film thicknesses T1 and T2. For example, as shown in Figure 6B, the ratio of film thickness T2 to film thickness T1 may be less than 1, less than 0.8, or less than 0.5.

[0167] For example, when a semiconductor layer 230_2 is deposited by sputtering, the semiconductor layer 230_2 is formed so as to be in contact with the upper surface of the semiconductor layer 230_1 and the side surface of the semiconductor layer 230_1 at the opening 290 (see Figure 6B). In this case, the thickness of the semiconductor layer 230_2 formed on the side surface of the semiconductor layer 230_1 at the opening 290 is smaller than the thickness of the semiconductor layer 230_2 formed on the upper surface of the semiconductor layer 230_1, so the thickness T2 is smaller than the thickness T1.

[0168] Furthermore, depending on the thickness of the semiconductor layer 230_2, the semiconductor layer 230_2 may be formed on the upper surface of the semiconductor layer 230_1, but not on the side surface of the semiconductor layer 230_1 at the opening 290 (see Figure 7A). In this case, the distance between the channel formation region of the semiconductor layer 230_1 and the conductive layer 260 becomes smaller, allowing the gate electric field to be effectively applied to the semiconductor layer 230. Also, above the conductive layer 240, the physical distance between the conductive layer 260 and the conductive layer 240 can be increased by the thickness of the semiconductor layer 230_2, thereby reducing the parasitic capacitance between the conductive layer 260 and the conductive layer 240.

[0169] Furthermore, semiconductor layers 230_1 and 230_2 can also be formed by the ALD method. For example, Figure 7B shows a cross-sectional view of a semiconductor device, enlarged from region D1 in Figure 6A. Semiconductor layer 230_2 is formed so as to be in contact with the upper surface of semiconductor layer 230_1 and the side surface of semiconductor layer 230_1 at the opening 290. In this case, the film thickness T1 is approximately the same as the film thickness T2.

[0170] Since the insulating layer 210 functions as an interlayer film, it is preferable to use a material with a low dielectric constant. For example, silicon oxide or silicon oxynitride can be used. By using a material with a low dielectric constant for the interlayer film, parasitic capacitance between wiring can be reduced.

[0171] The insulating layer 210 preferably has hydrogen barrier properties. For example, silicon nitride can be used. By having the insulating layer 210, which is provided below the semiconductor layer 230, have hydrogen barrier properties, the diffusion of hydrogen from below the transistor 200A to the semiconductor layer 230 can be suppressed.

[0172] Furthermore, it is preferable that the insulating layer 210 has the function of capturing or fixing hydrogen. For example, aluminum oxide, hafnium oxide, hafnium zirconium oxide, or hafnium silicate can be used. By having the function of capturing or fixing hydrogen in the insulating layer 210, hydrogen in the semiconductor layer 230 can diffuse into the insulating layer 210 via the conductive layer 220, and the hydrogen can be captured or fixed. Therefore, the hydrogen concentration in the semiconductor layer 230 can be reduced.

[0173] Furthermore, it is preferable that the concentration of impurities such as hydrogen or water in the insulating layer 210 is reduced. This makes it possible to suppress the incorporation of impurities such as hydrogen or water into the channel formation region of the semiconductor layer 230.

[0174] Furthermore, the insulating layer 210 can have a laminated structure of two or more layers. For example, the insulating layer 210 can have a two-layer structure consisting of a first insulating layer and a second insulating layer on the first insulating layer. In this case, it is preferable that, for example, the first insulating layer has barrier properties against hydrogen, and the second insulating layer has a function of capturing or fixing hydrogen. Specifically, it is preferable to use silicon nitride as the first insulating layer and aluminum oxide, hafnium oxide, hafnium zirconium oxide, or hafnium silicate as the second insulating layer.

[0175] The insulating layer 250 preferably has the function of supplying oxygen to the semiconductor layer 230. The insulating layer 250 preferably has a region containing oxygen that is desorbed by heating (hereinafter sometimes referred to as excess oxygen). By the insulating layer having a region containing excess oxygen coming into contact with the semiconductor layer 230, oxygen can be supplied to the semiconductor layer 230. The oxygen supplied to the semiconductor layer 230 repairs oxygen vacancies and can reduce the amount of oxygen vacancies in the semiconductor layer 230. Examples of insulating materials that readily form regions containing excess oxygen include silicon oxide, silicon oxynitride, and silicon oxide with vacancies. Examples of insulating layers that readily form regions containing excess oxygen include silicon oxide films, silicon oxynitride films, and silicon oxide films with vacancies.

[0176] Furthermore, it is preferable that the insulating layer 250 has the function of capturing or fixing oxygen (also known as gettering). As mentioned above, the indium oxide film is a film to which oxygen easily moves. Therefore, by having the function of capturing or fixing oxygen in the insulating layer 250, an excess amount of oxygen in the semiconductor layer 230 can diffuse into the insulating layer 250 and capture or fix the oxygen. Thus, the OS transistor can suppress positive drift degradation in the +GBT stress test caused by the oxygen. Examples of insulating materials having the function of capturing or fixing oxygen include aluminum oxide, hafnium oxide, hafnium zirconium oxide, and oxides containing hafnium and silicon (hafnium silicate).

[0177] Furthermore, aluminum oxide, hafnium oxide, hafnium zirconium oxide, and hafnium silicate have the function of capturing or fixing hydrogen. As mentioned above, the indium oxide film is a film to which hydrogen easily moves. Therefore, because the insulating layer 250 has the function of capturing or fixing hydrogen, hydrogen in the semiconductor layer 230 can diffuse into the insulating layer 250 and be captured or fixed therein. Consequently, the hydrogen concentration in the semiconductor layer 230 (especially the hydrogen concentration in the channel formation region) can be reduced.

[0178] Furthermore, the insulating layer 250 can be made into a laminated structure of two or more layers. In this case, it is preferable that the insulating layer 250 is formed from two or more types of films. By making the insulating layer 250 from two or more types of films, multiple functions can be imparted to the insulating layer 250. Examples of functions that the insulating layer 250 may have include the function of extracting excess oxygen from the semiconductor layer 230, the function of extracting hydrogen from the semiconductor layer 230, and the function of suppressing the diffusion of hydrogen into the semiconductor layer 230.

[0179] Figure 7B shows an example where the insulating layer 250 has a four-layer structure consisting of insulating layer 250_1, insulating layer 250_2 on insulating layer 250_1, insulating layer 250_3 on insulating layer 250_2, and insulating layer 250_4 on insulating layer 250_3. In this case, insulating layer 250_1 is in contact with semiconductor layer 230_2.

[0180] As the insulating layer 250_1, any material applicable to the insulating layer 250 described above can be used. For example, if the insulating layer 250_1 has an insulating layer that has the function of capturing or fixing oxygen, the excess amount of oxygen in the semiconductor layer 230 can be reduced. In addition, an insulating layer that has the function of capturing or fixing oxygen may also have the function of capturing or fixing hydrogen, so the hydrogen concentration in the semiconductor layer 230 may be reduced. Therefore, a highly reliable transistor can be realized.

[0181] Furthermore, a material with a high dielectric constant (high-k) can be used for the insulating layer 250_1. An example of a high-k material is an oxide containing either or both aluminum and hafnium. By using a high-k material as the insulating layer 250_1, it becomes possible to reduce the gate potential applied during transistor operation while maintaining the physical thickness of the gate insulator. Additionally, it becomes possible to thin the equivalent oxide thickness (EOT) of the insulator that functions as a gate insulator.

[0182] Therefore, it is preferable to use an oxide containing one or both of aluminum and hafnium as the insulating layer 250_1, and it is more preferable to use an oxide having an amorphous structure and containing one or both of aluminum and hafnium. Aluminum oxide is preferable because an amorphous film can be formed relatively easily using the ALD method. Aluminum oxide can be suitably used as the insulating layer 250_1 because it has the function of capturing or fixing oxygen and hydrogen. Alternatively, hafnium oxide can be suitably used as the insulating layer 250_1 because it has a high function of capturing or fixing oxygen and hydrogen.

[0183] Furthermore, it is preferable to use an insulating material with a high dielectric strength as the insulating layer 250_2. This can reduce the leakage current of the transistor. For example, it is preferable that the insulating layer 250_2 has a silicon oxide film or a silicon oxynitride film. Also, the silicon oxide film or silicon oxynitride film is a film with high hydrogen permeability. Therefore, the insulating layer 250 may have a three-layer structure consisting of insulating layer 250_2, insulating layer 250_1 on insulating layer 250_2, and insulating layer 250_4 on insulating layer 250_1. With such a configuration, hydrogen in the semiconductor layer 230 can diffuse to the insulating layer 250_1 via the insulating layer 250_2, and the hydrogen can be captured or fixed. Therefore, the hydrogen concentration in the semiconductor layer 230 can be reduced.

[0184] The insulating layer 250_4 preferably has barrier properties against hydrogen. This configuration suppresses the diffusion of hydrogen into the semiconductor layer 230. Furthermore, the insulating layer 250_4 preferably has barrier properties against oxygen. The insulating layer 250_4 is provided between the channel-forming region of the semiconductor layer 230 and the conductive layer 260. This configuration suppresses the diffusion of oxygen contained in the channel-forming region of the semiconductor layer 230 into the conductive layer 260, preventing the formation of oxygen vacancies in the channel-forming region of the semiconductor layer 230. It also suppresses the diffusion of oxygen contained in the semiconductor layer 230 into the conductive layer 260, preventing the conductive layer 260 from oxidizing. The insulating layer 250_4 preferably has less oxygen permeability than the insulating layer 250_2. Furthermore, the insulating layer 250_4 preferably has a function to suppress the diffusion of hydrogen. This prevents impurities such as hydrogen contained in the conductive layer 260 from diffusing into the semiconductor layer 230. For example, silicon nitride is preferably used as the insulating layer 250_4.

[0185] Alternatively, a structure may be provided in which an insulating layer 250_3 is placed on top of the insulating layer 250_2. As the insulating layer 250_3, an insulating material applicable to the insulating layer 250_1 can be used. For example, by providing an insulating layer 250_3 having the function of capturing or fixing hydrogen between the insulating layer 250_4 and the insulating layer 250_2, hydrogen contained in the insulating layer 250_2 can be captured or fixed.

[0186] Preferably, the insulating layer 250 has a four-layer structure in which an aluminum oxide film, a silicon oxide film, a hafnium oxide film, and a silicon nitride film are stacked in that order from the semiconductor layer 230 side. With this configuration, hydrogen in the semiconductor layer 230 diffuses into insulating layer 250_1 or insulating layer 250_3, and the hydrogen can be captured or fixed there. Therefore, the hydrogen concentration in the semiconductor layer 230 can be reduced.

[0187] The insulating layer 250 is preferably a thin film. For example, by setting the thickness of the insulating layer 250 to 1 nm or more and 20 nm or less, preferably 3 nm or more and 10 nm or less, the S value of the transistor can be reduced. The S value refers to the amount of change in gate voltage when the drain current is changed by one order of magnitude while the drain voltage is constant in the subthreshold region.

[0188] Furthermore, the film thickness of each layer constituting the insulating layer 250 is preferably 0.1 nm to 20 nm, more preferably 0.1 nm to 10 nm, more preferably 0.1 nm to 5.0 nm, more preferably 0.5 nm to 5.0 nm, more preferably 1.0 nm to less than 5.0 nm, and even more preferably 1.0 nm to 3.0 nm. Note that each layer constituting the insulating layer 250 only needs to have a region with the above-mentioned film thickness in at least a portion of it.

[0189] Typically, the film thicknesses of insulating layers 250_1, 250_2, 250_3, and 250_4 are set to 1 nm, 2 nm, 2 nm, and 1 nm, respectively. This configuration allows for good electrical characteristics even when the transistor is miniaturized or highly integrated.

[0190] In addition, the insulating layer 250 has a four-layer structure, and the insulating layer 250_4 may be omitted. For example, insulating layer 250_1 can be an insulating layer having the function of capturing or fixing oxygen, insulating layer 250_2 can be an insulating layer having a low dielectric constant, and insulating layer 250_3 can be an insulating layer having the function of capturing or fixing hydrogen. Specifically, the insulating layer 250 can be a three-layer structure in which an aluminum oxide film, a silicon oxide film, and a hafnium oxide film are stacked in that order from the semiconductor layer 230 side.

[0191] Furthermore, the insulating layer 250 can have a three-layer structure in which a hafnium oxide film, a silicon oxide film, and a silicon nitride film are stacked in that order from the semiconductor layer 230 side. The thicknesses of the hafnium oxide film, silicon oxide film, and silicon nitride film are 2 nm, 2 nm, and 1 nm, respectively. With this configuration, excess oxygen in the semiconductor layer 230 can be discharged to the insulating layer 250, reducing the amount of excess oxygen in the semiconductor layer 230. In addition, hydrogen in the semiconductor layer 230 can be captured or fixed. Therefore, the electrical characteristics and reliability of the transistor 200A can be improved.

[0192] To make the thickness of insulating layers 250_1 to 250_4 as described above, it is preferable to use the ALD method for film formation. Furthermore, to form insulating layers 250_1 to 250_4 with good coverage within the opening 290, it is preferable to use the ALD method for film formation.

[0193] Furthermore, in forming the insulating layer 250 having a laminated structure of multiple insulating films, it is preferable to use the ALD process two or more times. For example, it is preferable that two or more of the multiple insulating films of the insulating layer 250 are formed using the ALD process. By forming at least two or more insulating films using the ALD process, the coverage and uniformity of the film thickness of the insulating layer 250 can be improved. In addition, productivity can be increased by continuously forming, for example, two or more insulating films using the ALD process.

[0194] Although the above describes a configuration in which the insulating layer 250 has a three-layer or four-layer structure, the present invention is not limited thereto. The insulating layer 250 can have at least one of insulating layers 250_1 to 250_4. By configuring the insulating layer 250 with one, two, or three layers from insulating layers 250_1 to 250_4, the manufacturing process of semiconductor devices can be simplified and productivity can be improved.

[0195] As shown in Figure 1B, the insulating layer 280 can have a four-layer structure consisting of insulating layer 280_1, insulating layer 280_2 on insulating layer 280_1, insulating layer 280_3 on insulating layer 280_2, and insulating layer 280_4 on insulating layer 280_3.

[0196] Since the insulating layer 280_3 functions as an interlayer film, it is preferable to use a material with a low dielectric constant. By using a material with a low dielectric constant for the interlayer film, parasitic capacitance between wirings can be reduced. For example, silicon oxide or silicon oxynitride can be used as the insulating layer 280_3.

[0197] By using silicon oxide, which has a low coefficient of thermal expansion, for the insulating layer 280_3 that is provided before the formation of the semiconductor layer 230, it is possible to promote the crystal growth of indium oxide formed by the ALD method inside the opening 290 of the insulating layer 280_3.

[0198] It is preferable that the concentration of impurities such as hydrogen or water in the insulating layer 280_3 is reduced. This makes it possible to suppress the incorporation of impurities such as hydrogen or water into the channel formation region of the semiconductor layer 230.

[0199] It is preferable to use oxygen barrier insulating layers as insulating layers 280_1, 280_2, and 280_4. This suppresses oxidation of conductive layers 220 and 240, thereby suppressing increased resistance. The upper surface of insulating layer 280_2 may be planarized by a planarization treatment such as the CMP method to improve flatness. For example, it is preferable to use silicon nitride or aluminum oxide as insulating layers 280_1, 280_2, and 280_4.

[0200] Furthermore, the insulating layer 280 can have a three-layer structure. Figures 8A to 8C show modified examples of the semiconductor device shown in Figures 1A to 1C. Figure 8A corresponds to the plan view of the semiconductor device in Figure 1A. Figures 8B and 8C correspond to the cross-sectional views of the semiconductor device in Figures 1B and 1C. Specifically, Figure 8B differs from the cross-sectional view of the semiconductor device shown in Figure 1B in that it does not have the insulating layer 280_2.

[0201] For example, as shown in Figure 8B, the insulating layer 280 can have a three-layer structure consisting of insulating layer 280_1, insulating layer 280_3 on insulating layer 280_1, and insulating layer 280_4 on insulating layer 280_3. The upper surface of insulating layer 280_3 may be planarized by a planarization treatment using the CMP method or the like to improve flatness. In this case, it is preferable to use a material with a low dielectric constant as insulating layer 280_3, and to use oxygen barrier insulating layers as insulating layer 280_1 and insulating layer 280_4. This suppresses oxidation of the conductive layer 220 and conductive layer 240, thereby suppressing increased resistance. For example, it is preferable to use silicon nitride or aluminum oxide as insulating layer 280_1 and insulating layer 280_4, and silicon oxide as insulating layer 280_3. Furthermore, insulating layer 280_1, insulating layer 280_2, and insulating layer 280_4 may each be a laminated structure of two or more layers.

[0202] In the above, the present invention has described a configuration in which the insulating layer 280 has a three-layer or four-layer structure, but the present invention is not limited thereto. The insulating layer 280 can also have a single-layer structure, a two-layer structure, or a laminated structure of five or more layers. An example in which the insulating layer 280 has a single-layer structure is shown in Figure 9B. Figures 9A to 9C are modified examples of the semiconductor device shown in Figures 1A to 1C. Specifically, these differ from the semiconductor device shown in Figure 1B and the like in that the conductive layer 220, conductive layer 240, conductive layer 260, and insulating layer 280 have a single-layer structure.

[0203] The insulating layer 280 shown in Figure 9B functions as an interlayer film, so it is preferable to use a material with a low dielectric constant. For example, silicon oxide or silicon oxynitride can be used as the insulating layer 280. By making the insulating layer 280 a single-layer structure, the manufacturing process of the semiconductor device can be simplified and productivity can be improved.

[0204] Since the conductive layer 220 and the conductive layer 240 are in contact with the semiconductor layer 230, it is preferable to use conductive materials that are resistant to oxidation, conductive materials that maintain low electrical resistance even when oxidized, conductive metal oxides (also called oxide conductors), or conductive materials that have the function of suppressing oxygen diffusion. Examples of such conductive materials include conductive materials containing nitrogen and conductive materials containing oxygen. This makes it possible to suppress a decrease in the conductivity of the conductive layer 220 and the conductive layer 240.

[0205] As shown in Figure 1B, the conductive layer 220 has a recess that overlaps with the opening 290. Specifically, the recess is provided in the conductive layer 220_2 at the position overlapping with the opening 290. By having the recess in the conductive layer 220_2, the height of the lower surface of the insulating layer 250 and the lower surface of the conductive layer 260 within the opening 290 can be made lower than the height of the upper surface of the conductive layer 220_2 that is in contact with the insulating layer 280, compared to the case where the recess is not present. Here, the height of each surface can be determined with reference to the surface on which the transistor is formed. Here, the upper surface of the insulating layer 210 is used as the reference. The surface used as the reference is not limited to the surface on which the transistor is formed. For example, the upper surface of the substrate on which the transistor or semiconductor device is provided may be used as the reference.

[0206] As shown in Figure 1B, the semiconductor layer 230 is in contact with the bottom and side surfaces of the recesses of the conductive layer 220_2. The presence of recesses in the conductive layer 220_2 increases the contact area between the semiconductor layer 230 and the conductive layer 220_2. Therefore, the contact resistance between the semiconductor layer 230 and the conductive layer 220_2 can be reduced.

[0207] The recess in the conductive layer 220_2 may have a curved portion, as shown in Figure 1B. Because the recess has a curved portion, the portions of the semiconductor layer 230, insulating layer 250, etc., provided on the recess may also have a curved portion. In other words, these portions may have a curved or concave surface in cross-sectional view. Furthermore, these portions may not have corners (right angles or acute angles) in cross-sectional view. This reduces electric field concentration on the insulating layer 250 near the recess, improves the dielectric breakdown voltage of the transistor 200A, and suppresses electrostatic discharge breakdown of the transistor 200A. Therefore, the reliability of the semiconductor device can be improved.

[0208] By using an oxygen-containing conductive material as the conductive layer 220 and conductive layer 240, conductivity can be maintained even if the conductive layer 220 and conductive layer 240 absorb oxygen. Furthermore, even when an oxygen-containing insulator such as hafnium oxide is used as the insulating layer 210, the conductive layer 220 can maintain conductivity, which is preferable. For example, it is preferable to use ITO, ITSO, In-Zn oxide, etc., as the conductive layer 220 and conductive layer 240, respectively.

[0209] When the conductive layer 220 and the conductive layer 240 each have a laminated structure, by using an oxygen-containing conductive material in the layer with the largest contact area with the semiconductor layer 230, the contact resistance between the conductive layer 220 and the semiconductor layer 230, and between the conductive layer 240 and the semiconductor layer 230, can be reduced.

[0210] As shown in Figure 1B, the conductive layer 220 has a two-layer structure consisting of conductive layer 220_1 and conductive layer 220_2 on conductive layer 220_1. In this case, it is preferable to use an oxygen-containing conductive material as conductive layer 220_2 and a material with higher conductivity than conductive layer 220_2 as conductive layer 220_1. Specifically, it is preferable to use an oxide conductor (e.g., ITO, ITSO, or In-Zn oxide) as conductive layer 220_2 and tungsten as conductive layer 220_1. Alternatively, ruthenium, titanium nitride, or tantalum nitride may be used as conductive layer 220_1. By using an oxide conductor as the conductive layer 220_2 that mainly contacts the semiconductor layer 230, the contact resistance between the semiconductor layer 230 and the conductive layer can be reduced. Furthermore, by using a material with higher conductivity than the oxide conductor in the layer constituting conductive layer 220_1, the conductivity of conductive layer 220_1 can be increased.

[0211] Furthermore, the conductive layer 220_1 can also have a two-layer structure consisting of a first conductive layer and a second conductive layer on the first conductive layer. In other words, the conductive layer 220 can also have a three-layer structure. In this case, for example, it is preferable to use a first conductive layer on the insulating layer 210 that is made of a conductive material that is resistant to oxidation or a conductive material that has the function of suppressing oxygen diffusion, a second conductive layer on the first conductive layer that is made of a highly conductive material, and a conductive material containing oxygen (more preferably an oxide conductor) as the conductive layer 220_2 on the second conductive layer. Specifically, it is preferable to use titanium nitride as the first conductive layer, tungsten as the second conductive layer, and an oxide conductor (for example, ITO, ITSO, or In-Zn oxide) as the conductive layer 220_2. In this case, the titanium nitride film is in contact with the insulating layer 210, and the oxide conductive film is in contact with the semiconductor layer 230. In addition, the oxide conductor is used in the layer closest to the channel formation region of the semiconductor layer 230. Compared to tungsten, oxide conductors have lower contact resistance with the semiconductor layer 230, which can shorten the current path between the source and drain, and in some cases increase the on-current of the transistor 200A. With this structure, conductivity can be maintained even when the conductive layer 220 is in contact with the semiconductor layer 230. Furthermore, when an oxide insulating layer is used for the insulating layer 210, excessive oxidation of the conductive layer 220 by the insulating layer 210 can be suppressed. In addition, by using a metal material with higher conductivity than oxide conductors and titanium nitride (tungsten in this case) as the second conductive layer, the conductivity of the conductive layer 220 can be increased.

[0212] Although the above describes a configuration in which the conductive layer 220 has a two-layer or three-layer structure, the present invention is not limited to these. An example of a single-layer structure for the conductive layer 220 is shown in Figure 9B. For example, it is preferable to use tungsten for the conductive layer 220. By making the conductive layer 220 a single-layer structure, the manufacturing process of the semiconductor device can be simplified and productivity can be improved.

[0213] The conductive layer 240 shown in Figure 1B has a two-layer structure consisting of conductive layer 240_1 and conductive layer 240_2 on conductive layer 240_1. In this case, it is preferable to use an oxygen-containing conductive material as conductive layer 240_2 and a material with higher conductivity than conductive layer 240_2 as conductive layer 240_1. Specifically, it is preferable to use an oxide conductor (e.g., ITO, ITSO, or In-Zn oxide) as conductive layer 240_2 and tungsten as conductive layer 240_1. Alternatively, ruthenium, titanium nitride, or tantalum nitride may be used as conductive layer 240_1. By using an oxide conductor as the conductive layer 240_2 that mainly contacts the semiconductor layer 230, the contact resistance between the semiconductor layer 230 and the conductive layer can be reduced. Furthermore, by using a material with higher conductivity than the oxide conductor in the layer constituting conductive layer 240_1, the conductivity of conductive layer 240_1 can be increased.

[0214] For example, it is possible to use indium oxide as the semiconductor layer 230, IGZO as the oxide layer 245, tungsten as the conductive layer 240_1, and ITO as the conductive layer 240_2.

[0215] In addition, it is preferable that the oxide layer 245 does not come into contact with the side surfaces of the openings 290 of the conductive layers 240_1 and 240_2. In other words, it is preferable that the oxide layer 245 is not formed between the semiconductor layer 230 and the side surfaces of the openings 290 of the conductive layers 240_1 and 240_2.

[0216] Because the oxide layer 245 is not formed between the semiconductor layer 230 and the side surface of the conductive layer 240_2 on the side facing the opening 290, the semiconductor layer 230 and the side surface of the conductive layer 240_2 on the side facing the opening 290 can be in contact. Since the conductive layer 240_2 is an oxide conductor, the contact resistance between the semiconductor layer 230 and the conductive layer 240_2 can be reduced. Similarly, the semiconductor layer 230 and the side surface of the conductive layer 240_1 on the side facing the opening 290 can also be in contact. By the semiconductor layer 230 and the side surface of the conductive layer 240_1 on the side facing the opening 290, the contact area between the semiconductor layer 230 and the side surface of the conductive layer 240 on the side facing the opening 290 can be increased. In this way, by the side surfaces of the conductive layer 240_1 and the conductive layer 240_2 on the side facing the opening 290 being in contact with the semiconductor layer 230, the contact area of ​​the conductive layer 240 can be further increased. Therefore, the conductive layer 240 can reduce the contact resistance between itself and the semiconductor layer 230, thereby increasing the on-current of the transistor 200A.

[0217] At the interface between the side surface of the conductive layer 240 and the semiconductor layer 230 in the opening 290, it is preferable that the components contained in the oxide layer 245 are below the detection limit. For example, it is preferable that the concentration of gallium be 1.0 atomic% or less. The composition can be quantified using XPS, EDX, SIMS, ICP-MS, ICP-AES, etc. By reducing the concentration of the components of the oxide layer 245 at the interface, the contact area between the conductive layer 240_2 and the semiconductor layer 230 can be increased. Therefore, the contact resistance between the conductive layer 240 and the semiconductor layer 230 can be reduced.

[0218] Furthermore, it is also possible to use an oxygen-containing conductive material as conductive layer 240_1 and a material with higher conductivity than conductive layer 240_1 as conductive layer 240_2. In this case, an oxide conductor is used in the conductive layer 240 that is closest to the channel formation region of the semiconductor layer 230. Therefore, the current path between the source and drain can be shortened, and the on-current of transistor 200A can be increased in some cases.

[0219] Although the above description describes a configuration in which the conductive layer 240 has a two-layer structure, the present invention is not limited to this. The conductive layer 240 can also have a single-layer structure or a laminated structure of three or more layers. An example of a single-layer conductive layer 240 is shown in Figure 9B. For example, it is preferable to use tungsten for the conductive layer 240. By making the conductive layer 240 a single-layer structure, the manufacturing process of semiconductor devices can be simplified and productivity can be improved.

[0220] The conductive layer 260 shown in Figure 1B has a two-layer structure consisting of conductive layer 260_1 and conductive layer 260_2 on conductive layer 260_1. In this case, it is preferable to use titanium nitride as conductive layer 260_1 and tungsten as conductive layer 260_2. Alternatively, it is preferable to use tantalum nitride as conductive layer 260_1 and copper as conductive layer 260_2. By using such a configuration, the conductivity of the conductive layer 260 can be increased.

[0221] Furthermore, the conductive layer 260 may have a laminated structure of three or more layers. For example, the conductive layer 260 may have a three-layer structure consisting of a tantalum nitride film, a titanium nitride film on the tantalum nitride film, and a tungsten film on the titanium nitride film.

[0222] Although the above describes a configuration in which the conductive layer 260 has a two-layer or three-layer structure, the present invention is not limited to these. An example of a single-layer structure for the conductive layer 260 is shown in Figure 9B. For example, it is preferable to use tungsten for the conductive layer 260. By using a single-layer structure, the manufacturing process of the semiconductor device can be simplified and productivity can be improved.

[0223] As shown in Figure 1B, an insulating layer 282 may be provided on the transistor 200A, and an insulating layer 283 may be provided on the insulating layer 282. Specifically, an insulating layer 282 may be provided on the conductive layer 260 and on the insulating layer 250.

[0224] It is preferable to use a hydrogen barrier insulating layer for the insulating layer 282. For example, it is possible to use silicon nitride oxide and silicon nitride, or both, for the insulating layer 282. The insulating layer 282 can be formed by a film deposition method such as sputtering, ALD, or CVD. With such a configuration, the diffusion of hydrogen from above the transistor 200A to the semiconductor layer 230 can be suppressed.

[0225] It is preferable to use a film deposited by a sputtering method that does not use hydrogen as the deposition gas for the insulating layer 283. The insulating layer 283 can be deposited by sputtering, CVD, or ALD. For example, silicon nitride, silicon oxide, silicon nitride oxide, silicon oxynitride, etc. can be used for the insulating layer 283. After the insulating layer 283 is deposited, a planarization treatment such as the CMP method can be used.

[0226] In transistor 200A, both conductive layer 260_1 and conductive layer 260_2 are located within the opening 290. Depending on the width of the opening 290, and the thicknesses of the semiconductor layer 230, insulating layer 250, and conductive layer 260_1, conductive layer 260_1 may be located within the opening 290, while conductive layer 260_2 may be located in a position overlapping the opening 290.

[0227] Within the opening 290, it is preferable that the side surfaces of the oxide layer 245, the conductive layer 240, and the insulating layer 280 coincide or approximately coincide. With this configuration, the opening 290 can be formed in the conductive layer 240 and the insulating layer 280 simultaneously. Furthermore, the thickness distribution of the semiconductor layer 230 and the like, provided inside the opening 290, can be made uniform. In addition, it is possible to suppress the separation of the semiconductor layer 230 and the like due to steps or other differences between the conductive layer 240 and the insulating layer 280.

[0228] However, the present invention is not limited to the above configuration. The example shows the case where the side surface of the insulating layer 280 in the opening 290 is perpendicular or approximately perpendicular to the substrate surface or the surface to be formed, but it may also be tapered.

[0229] For example, within the opening 290, the side surface of the conductive layer 240 and the side surface of the insulating layer 280 may be discontinuous. Also, within the opening 290, the inclination of the side surface of the conductive layer 240 and the inclination of the side surface of the insulating layer 280 may be different from each other. In this case, a part of the side surface of the opening 290 will have a tapered shape.

[0230] Furthermore, as shown in Figure 7B, the side surface of the conductive layer 240 within the opening 290 may be tapered. Alternatively, the side surfaces of the conductive layer 240 and the insulating layer 280 within the opening 290 may each be tapered.

[0231] By tapering the side surface of the opening 290, the coverage of the semiconductor layer 230, the insulating layer 250, etc., is improved, and defects such as porosity can be reduced. When tapering the side surface of the opening 290, for example, the tapered angle of the side surface of the conductive layer 240 within the opening 290 and the tapered angle of the side surface of the insulating layer 280 within the opening 290 are preferably 45 degrees or more and less than 90 degrees. Specifically, a tapered angle of 80 degrees or more and less than 90 degrees is preferable because it enables miniaturization or high integration of the semiconductor device. Alternatively, a tapered angle of 45 degrees or more and less than 80 degrees, or 50 degrees or more and 75 degrees or less is preferable because it improves the coverage of the film formed within the opening 290.

[0232] Furthermore, for example, it is preferable that the taper angle of the side surface of the conductive layer 240 within the opening 290 is smaller than the taper angle of the side surface of the insulating layer 280 within the opening 290. By adopting such a configuration, the coverage of the semiconductor layer 230, etc., on the side surface of the conductive layer 240 within the opening 290 is improved, and defects such as porosity can be reduced. Also, if the insulating layer 280 has a laminated structure, the inclination of the side surfaces of each layer within the opening 290 may be different. Similarly, if the conductive layer 240 has a laminated structure, the inclination of the side surfaces of each layer within the opening 290 may be different.

[0233] In the following section, using Figures 10A to 10C, we will describe an example of a transistor configuration that differs in some aspects from transistor 200A. Note that we will omit explanations of parts that overlap with the above, and will only provide detailed explanations of the differences. Furthermore, even if components differ in position or shape, if their function is the same, they may be given the same reference numeral and their explanation may be omitted.

[0234] [Transistor 200B] Figure 10A is a plan view of a semiconductor device having transistor 200B. Figure 10B is a cross-sectional view between the dashed lines A1 and A2 shown in Figure 10A. Figure 10C is a cross-sectional view between the dashed lines A3 and A4 shown in Figure 10A. Note that the cross-sectional view between the dashed lines A5 and A6 shown in Figures 10B and 10C can be found in Figure 2B.

[0235] The semiconductor device shown in Figures 10A to 10C differs from the semiconductor device shown in Figures 1A to 1C in that it has a conductive layer 265, an insulating layer 284, and an insulating layer 285. Also, to avoid making the drawings complicated, some components (for example, the insulating layer 280) may be omitted.

[0236] In transistor 200B, the laminated structure from the conductive layer 220 to the insulating layer 250 is the same as that of transistor 200A described above, so a detailed explanation is omitted.

[0237] As shown in Figures 10B and 10C, the insulating layer 284 is provided so as to be located on the insulating layer 250. In addition, the insulating layer 284 has an opening 270 that reaches the insulating layer 250, located at a position that overlaps with the opening 290.

[0238] The conductive layer 260 is provided to fill the openings 290 and 270. The conductive layer 260 is provided on the insulating layer 250 and is in contact with the insulating layer 250 within the opening 270. The conductive layer 260 has a portion that faces the semiconductor layer 230 via the insulating layer 250 within the opening 290 and a portion that is located within the opening 270.

[0239] Figures 10B and 10C show an example in which both conductive layer 260_1 and conductive layer 260_2 are provided within the opening 290. Note that if the width of opening 290 and opening 270 are small, only conductive layer 260_1 may be provided within opening 290, and both conductive layer 260_1 and conductive layer 260_2 may be provided within opening 270. Also, only conductive layer 260_1 may be provided within opening 270.

[0240] The smaller the width of the opening 270 is than the width D of the opening 290, the greater the physical distance between the conductive layer 240 and the conductive layer 260 can be, and the smaller the parasitic capacitance that occurs between the conductive layer 240 and the conductive layer 260 can be, which is preferable. For example, the width of the opening 270 is preferably less than or equal to the width of the opening 290.

[0241] The conductive layer 265 is provided on the conductive layer 260 and is in contact with the upper surface of the conductive layer 260. It can also be said that the conductive layer 260 and the conductive layer 265 are connected to each other. The conductive layer 265 may be considered a component of the transistor 200B. The height of the upper surface of the conductive layer 260 and the height of the upper surface of the insulating layer 285 are the same or approximately the same.

[0242] The conductive layer 265 functions as gate wiring. The conductive layer 265 can be made from materials applicable to the conductive layer 260. For example, the conductive layer 265 can be made from high-melting-point materials such as tungsten or molybdenum, which offer both heat resistance and conductivity. Alternatively, low-resistance conductive materials such as aluminum or copper can be used. Using low-resistance conductive materials can reduce wiring resistance.

[0243] The portion of the conductive layer 265 that does not overlap with the opening 290 is mainly located on the insulating layer 285. Therefore, the conductive layer 265 overlaps with the conductive layer 240 and the oxide layer 245 mainly via the insulating layers 284 and 285. This increases the physical distance between the conductive layer 265 and the conductive layer 240, and reduces the parasitic capacitance that occurs between the conductive layer 265 and the conductive layer 240. Note that the conductive layer 240 and the conductive layer 265 may have portions that overlap without the insulating layer 285.

[0244] Transistor 200B has a configuration that reduces parasitic capacitance between the source electrode, the other drain electrode, and the gate wiring. Therefore, the frequency characteristics of a circuit using this transistor can be improved.

[0245] In this embodiment, an example is shown in which the opening 270 is circular in plan view, but the present invention is not limited to this. The shapes applicable to the opening 270 are the same as the shapes applicable to the opening 290 described above.

[0246] Furthermore, the width of the opening 270 may vary in the depth direction. In particular, the maximum width of the opening 270 provided in the insulating layer 284 in a cross-sectional view is used as the width of the opening 270.

[0247] The insulating layer 284 preferably has the function of capturing or fixing hydrogen. With this configuration, the diffusion of hydrogen from above the insulating layer 284 to the semiconductor layer 230 is suppressed, and hydrogen contained in the semiconductor layer 230 can be captured or fixed. Therefore, the hydrogen concentration in the semiconductor layer 230 can be reduced. As the insulating layer 284, aluminum oxide, hafnium oxide, hafnium zirconium oxide, or hafnium silicate can be used.

[0248] Furthermore, the insulating layer 284 can be used as a barrier insulating layer against hydrogen. This suppresses the diffusion of hydrogen from above the insulating layer 284 into the semiconductor layer 230. Both silicon nitride and silicon nitride oxide have the characteristic of being impermeable to oxygen and hydrogen, and are therefore suitable for use in the insulating layer 284.

[0249] When the insulating layer 284 has a silicon nitride film, it is preferable that the silicon nitride film be deposited by sputtering. Since sputtering does not require the use of hydrogen-containing molecules in the deposition gas, the hydrogen concentration in the insulating layer 284 can be reduced. Furthermore, by depositing the insulating layer 284 by sputtering, a high-density silicon nitride film can be formed.

[0250] Furthermore, the insulating layer 284 may have a laminated structure consisting of an insulating layer having the function of capturing or fixing hydrogen and a barrier insulating layer against hydrogen. For example, the insulating layer 284 may have a laminated film of an aluminum oxide film and a silicon nitride film on the aluminum oxide film.

[0251] Since the insulating layer 285 functions as an interlayer film, it is preferable to use a material with a low dielectric constant, as described above. For example, it is preferable that the insulating layer 285 has a silicon oxide film.

[0252] <Example of Memory Device Configuration 1> The configuration of a memory device having memory cells will be explained using Figures 11A to 11C. Figure 11A is a plan view of a memory device having memory cells 150. Figure 11B is a cross-sectional view between the dashed lines A1 and A2 shown in Figure 11A. Figure 11C is a cross-sectional view between the dashed lines A3 and A4 shown in Figure 11A.

[0253] The memory device shown in Figures 11A to 11C comprises an insulating layer 140 on a substrate (not shown), a conductive layer 110 on the insulating layer 140, a memory cell 150 on the conductive layer 110, an insulating layer 180 on the conductive layer 110, and an insulating layer 280 on the insulating layer 180. The insulating layer 140 and the insulating layer 180 function as interlayer films. The conductive layer 110 functions as wiring.

[0254] The memory cell 150 includes a capacitive element 100 on a conductive layer 110 and a transistor 200 on the capacitive element 100.

[0255] The capacitive element 100 includes a conductive layer 115 on a conductive layer 110, an insulating layer 130 on the conductive layer 115, and a conductive layer 220_1 on the insulating layer 130. The conductive layer 220_1 functions as one of a pair of electrodes (sometimes called the upper electrode), the conductive layer 115 functions as the other of a pair of electrodes (sometimes called the lower electrode), and the insulating layer 130 functions as a dielectric. In other words, the capacitive element 100 constitutes a MIM (Metal-Insulator-Metal) capacitance. Note that the conductive layer 220_2 provided on the conductive layer 220_1 can also be considered as part of the upper electrode of the capacitive element 100.

[0256] As shown in Figures 11B and 11C, the insulating layer 180 is provided with an opening 190 that reaches the conductive layer 110. At least a portion of the conductive layer 115 is located within the opening 190. The conductive layer 115 has a region within the opening 190 that is in contact with the upper surface of the conductive layer 110, a region within the opening 190 that is in contact with the side surface of the insulating layer 180, and a region that is in contact with at least a portion of the upper surface of the insulating layer 180. At least a portion of the insulating layer 130 is located within the opening 190. At least a portion of the conductive layer 220_1 is located within the opening 190. It is preferable that the conductive layer 220_1 is provided so as to fill the opening 190, as shown in Figures 11B and 11C. It is preferable that the films provided inside the opening 190 are formed using the ALD method. This results in good coverage of the films. For example, the conductive layer 115, the insulating layer 130, and the conductive layer 220_1 are preferably formed using the ALD method.

[0257] The capacitive element 100 is configured such that the upper electrode and lower electrode face each other with a dielectric in between, not only on the bottom surface but also on the sides, within the opening 190, allowing for a large capacitance per unit area. Therefore, the deeper the opening 190, the larger the capacitance of the capacitive element 100 can be. By increasing the capacitance per unit area of ​​the capacitive element 100 in this way, the read operation of the memory device can be made more stable. Furthermore, miniaturization or high integration of the memory device can be promoted.

[0258] Figures 11B and 11C show an example where the side surface of the opening 190 is perpendicular to the upper surface of the conductive layer 110, and the opening 190 is circular in plan view. This configuration makes it possible to miniaturize or highly integrate the memory device.

[0259] A conductive layer 115 and an insulating layer 130 are laminated along the side surface of the opening 190 and the upper surface of the conductive layer 110. Furthermore, a conductive layer 220_1 is provided on the insulating layer 130 so as to fill the opening 190. A capacitive element 100 having such a configuration may be called a trench-type capacitor or trench capacitor.

[0260] The conductive layer 110 functions as a wiring CAL, as described later, and can be provided in a strip shape, for example. A strip shape refers to a shape having a region extending in a certain direction (for example, the X direction, Y direction, or Z direction).

[0261] The conductive layer 110 can be formed as a single layer or in a laminated form using the conductive material described in the [conductive layer] of this embodiment. For example, a highly conductive material such as tungsten can be used as the conductive layer 110. By using a highly conductive material, the conductivity of the conductive layer 110 can be improved, allowing it to function sufficiently as a wiring CAL.

[0262] The conductive layer 115 is preferably made of a conductive material that is resistant to oxidation, or a conductive material that has the function of suppressing oxygen diffusion, and is used in a single layer or laminate. For example, titanium nitride or ITSO may be used. Alternatively, for example, a structure in which titanium nitride is laminated on tungsten may be used. Alternatively, for example, a structure in which tungsten is laminated on a first titanium nitride, and a second titanium nitride is laminated on the tungsten may be used. By using such a structure, if an oxide is used for the insulating layer 130, oxidation of the conductive layer 110 by the insulating layer 130 can be suppressed. Also, if an oxide is used for the insulating layer 180, oxidation of the conductive layer 110 by the insulating layer 180 can be suppressed.

[0263] The insulating layer 130 is provided so as to be in contact with the upper and side surfaces of the conductive layer 115. In other words, it is preferable that the insulating layer 130 is structured to cover the side edges of the conductive layer 110. This prevents the conductive layer 115 and the conductive layer 220_1 from short-circuiting.

[0264] Furthermore, the side edges of the insulating layer 130 and the conductive layer 115 may be aligned or approximately aligned. By adopting such a structure, the insulating layer 130 and the conductive layer 115 can be formed using the same mask, thereby simplifying the manufacturing process of the memory device.

[0265] It is preferable to use a high-k material as the insulating layer 130. By using a high-k material as the insulating layer 130, the insulating layer 130 can be made thick enough to suppress leakage current, while also ensuring sufficient capacitance of the capacitive element 100.

[0266] Furthermore, the insulating layer 130 is preferably made by laminating insulating layers made of high-k material, and it is preferable to use a laminated structure of a high-k material and a material with a higher dielectric strength than the high-k material. For example, as the insulating layer 130, an insulating film laminated in the order of zirconium oxide, aluminum oxide, and zirconium oxide can be used. Alternatively, for example, an insulating film laminated in the order of zirconium oxide, aluminum oxide, zirconium oxide, and aluminum oxide can be used. Alternatively, for example, an insulating film laminated in the order of hafnium zirconium oxide, aluminum oxide, hafnium zirconium oxide, and aluminum oxide can be used. By laminating insulating layers with relatively high dielectric strength, such as aluminum oxide, the dielectric strength is improved, and electrostatic discharge breakdown of the capacitive element 100 can be suppressed.

[0267] Furthermore, a material capable of ferroelectricity may be used as the insulating layer 130. For details on materials capable of ferroelectricity, please refer to the description in this embodiment.

[0268] Metal oxides containing one or both of hafnium and zirconium are preferable as insulating layers 130 because they can possess ferroelectric properties even in thin films of a few nanometers. The thickness of the insulating layer 130 is preferably 100 nm or less, more preferably 50 nm or less, even more preferably 20 nm or less, and even more preferably 10 nm or less (typically 2 nm to 9 nm). Furthermore, for example, it is preferable to have a thickness of 8 nm to 12 nm. By using a ferroelectric layer that can be made into a thin film, the capacitive element 100 can be combined with semiconductor elements such as miniaturized transistors to form a semiconductor device.

[0269] Furthermore, metal oxides containing either or both hafnium and zirconium are preferable as insulating layers 130 because they can exhibit ferroelectric properties even over minute areas. For example, the area (occupied area) of the ferroelectric layer in a plan view is 100 μm². ２ Below, 10μm ２ Below, 1μm ２ The following, or 0.1 μm ２ Even if the following is true, it can still possess ferroelectric properties. Also, 10,000 nm ２ The following, or 1000 nm ２ Even in the following cases, ferroelectric properties may be present. By using a ferroelectric layer with a small area, the occupied area of ​​the capacitive element 100 can be reduced.

[0270] Ferroelectric materials are insulators that exhibit internal polarization when an external electric field is applied, and this polarization remains even when the electric field is removed. Therefore, non-volatile memory elements can be formed using capacitive elements (sometimes referred to as ferroelectric capacitors) that utilize this material as a dielectric. Non-volatile memory elements using ferroelectric capacitors are sometimes called FeRAM (Ferroelectric Random Access Memory) or ferroelectric memory. For example, a ferroelectric memory has a transistor and a ferroelectric capacitor, with one of the transistor's sources and drains connected to one terminal of the ferroelectric capacitor. Therefore, when a ferroelectric capacitor is used as the capacitive element 100, the memory device shown in this embodiment functions as a ferroelectric memory.

[0271] The conductive layer 220_1 is provided in contact with a portion of the upper surface of the insulating layer 130. Preferably, the side edge of the conductive layer 220_1 is located inside the side edge of the conductive layer 115 in both the X and Y directions. However, in a structure in which the insulating layer 130 covers the side edge of the conductive layer 115, the side edge of the conductive layer 220_1 may be located outside the side edge of the conductive layer 115.

[0272] Since the insulating layer 180 functions as an interlayer film, it is preferable that it has a low dielectric constant. By using a material with a low dielectric constant as the interlayer film, parasitic capacitance between wiring can be reduced.

[0273] Although Figures 11B and 11C show the insulating layer 180 as a single layer, the present invention is not limited to this. The insulating layer 180 may also have a laminated structure of two or more layers.

[0274] A detailed explanation of transistor 200 is omitted here, as it can be found in the description of this embodiment (transistor 200A shown in Figure 1A). Furthermore, the transistors in the memory cell 150 are not limited to transistor 200A, and any of the transistors exemplified in this embodiment can be used. In addition, transistors with a planar structure, a GAA (Gate All Around) structure, or an LGAA (Lateral Gate All Around) structure can also be used.

[0275] As shown in Figures 11A to 11C, the transistor 200 is provided so as to overlap with the capacitive element 100. Furthermore, the opening 290, through which part of the transistor 200's structure is provided, has a region that overlaps with the opening 190, through which part of the capacitive element 100's structure is provided. In particular, the conductive layer 220 functions as both the source electrode and the drain electrode of the transistor 200, and as the upper electrode of the capacitive element 100; therefore, the transistor 200 and the capacitive element 100 share a portion of their structure. This configuration allows the transistor 200 and the capacitive element 100 to be provided without significantly increasing the occupied area in a plan view. This reduces the occupied area of ​​the memory cell 150, allowing for a higher density arrangement of the memory cell 150 and thus increasing the storage capacity of the memory device. In other words, the memory device can be highly integrated. Figures 11B and 11C show an example where the width of the opening 190 is smaller than the width of the opening 290. The relative sizes of the widths of the opening 190 and 290 are not particularly limited. From the viewpoint of miniaturization, it is preferable that the width of the opening 190 is the same as or smaller than the width of the opening 290.

[0276] Furthermore, by positioning the transistor 200 above the capacitive element 100, the transistor 200 is not affected by the heat treatment during the manufacturing of the capacitive element 100. Therefore, in the transistor 200, fluctuations in the threshold voltage, deterioration of electrical characteristics such as an increase in parasitic resistance, and an increase in variations in electrical characteristics due to the deterioration of electrical characteristics can be suppressed.

[0277] A memory device can also be manufactured in which the transistor 200B described in this embodiment is used as the transistor 200 in the memory cell 150.

[0278] Figure 23A shows the circuit diagram of the memory device shown in this embodiment. As shown in Figure 23A, the configuration shown in Figures 11A to 11C functions as a memory cell. The memory cell 951 has a transistor M1 and a capacitive element CA. Here, transistor M1 corresponds to transistor 200, and capacitive element CA corresponds to capacitive element 100.

[0279] One of the source and drain of transistor M1 is connected to one of the pair of electrodes of the capacitive element CA. The other of the source and drain of transistor M1 is connected to wiring BIL. The gate of transistor M1 is connected to wiring WOL. The other of the pair of electrodes of the capacitive element CA is connected to wiring CAL.

[0280] Here, wiring BIL corresponds to conductive layer 240, wiring WOL corresponds to conductive layer 260, and wiring CAL corresponds to conductive layer 110. As shown in Figures 11A to 11C, it is preferable that conductive layer 260 extends in the X direction and conductive layer 240 extends in the Y direction. With this configuration, wiring BIL and wiring WOL are provided intersecting each other. Also, in Figure 11A, wiring CAL (conductive layer 110) is provided parallel to wiring WOL (conductive layer 260). However, the present invention is not limited to this. Wiring CAL may, for example, be provided parallel to wiring BIL (conductive layer 240).

[0281] <Example of Memory Device Configuration 2> The memory cell 150 having a transistor 200 and a capacitive element 100, as shown in this embodiment, can be used as a memory cell of a memory device. The transistor 200 is an OS transistor. Because the transistor 200 has a small off-current, using it in a memory device makes it possible to retain the stored contents for a long period of time. In other words, refresh operations are not required, or the frequency of refresh operations is extremely low, so the power consumption of the memory device can be significantly reduced. In addition, because the transistor 200 has a high frequency characteristic, reading and writing to the memory device can be performed at high speed.

[0282] Figure 12 shows an example of a cross-sectional configuration of a memory device in which layers containing memory cells are stacked on a layer on which a drive circuit including a sense amplifier is provided.

[0283] In Figure 12, a memory cell 150 (transistor 200 and capacitive element 100) is provided above the transistor 300.

[0284] Transistor 300 is one of the transistors in the sense amplifier.

[0285] For details regarding the memory cell 150 shown in Figure 12, please refer to the description of the memory cell 150 in <Example of Memory Device Configuration 1>.

[0286] As shown in Figure 12, by configuring the sense amplifier to overlap with the memory cell 150, the bit line can be shortened. This reduces the bit line capacity and enables high-speed operation of the memory device.

[0287] The memory device shown in Figure 12 can correspond to the semiconductor device 900 described in Embodiment 2. Specifically, transistor 300 corresponds to the transistor in sense amplifier 927 of semiconductor device 900. Also, memory cell 150 corresponds to memory cell 950.

[0288] The transistor 300 is provided on a substrate 311 and includes a conductive layer 316 that functions as a gate, an insulating layer 315 that functions as a gate insulating layer, a semiconductor region 313 that is part of the substrate 311, and low-resistance regions 314a and 314b that function as a source region or drain region. The transistor 300 may be either a p-channel or an n-channel type. The substrate 311 preferably contains a silicon-based semiconductor, and more specifically, it preferably contains single-crystal silicon.

[0289] Furthermore, the substrate 311 can also be a structure in which a single-crystal oxide semiconductor film (typically an indium oxide film) is provided on a stabilized zirconia substrate. As described in this embodiment, the indium oxide film formed on the stabilized zirconia substrate has a single crystal structure. By using a portion of the indium oxide film as a semiconductor region 313, the field-effect mobility of the transistor 300 can be increased. In addition, the reliability of the transistor 300 can be improved.

[0290] In Figure 12, the transistor 300 has a convex shape in the semiconductor region 313 (part of the substrate 311) where the channel is formed. Furthermore, a conductive layer 316 covers the side and top surfaces of the semiconductor region 313 via an insulating layer 315. The conductive layer 316 may be made of a material that adjusts the work function. Such a transistor 300 is also called a FIN-type transistor because it utilizes the convex portion of the semiconductor substrate. It may also have an insulating layer in contact with the upper part of the convex portion, functioning as a mask for forming the convex portion. While this example shows the formation of the convex portion by processing a part of the semiconductor substrate, a semiconductor film with a convex shape may also be formed by processing an SOI substrate.

[0291] Note that the transistor 300 shown in Figure 12 is just one example, and its structure is not limited to that; an appropriate transistor can be used depending on the circuit configuration or driving method. Furthermore, in the configuration shown in Figure 12, the transistor 300 is a P-channel silicon transistor (PMOS), and the transistor 200 is an N-channel indium oxide transistor (NMOS), and a CMOS (Complementary Metal Oxide Semiconductor) type circuit can be constructed using both transistor 300 and transistor 200.

[0292] A wiring layer containing interlayer films, wiring, and plugs may be provided between each structure. Furthermore, multiple wiring layers may be provided depending on the design. Here, conductive layers functioning as plugs or wiring may be grouped together and assigned the same reference numeral. Also, in this specification, the wiring and the plug connected to the wiring may be a single integrated unit. That is, a portion of the conductive layer may function as wiring, and a portion of the conductive layer may function as a plug.

[0293] For example, on the transistor 300, insulating layers 320, 322, 324, and 326 are sequentially stacked as interlayer films. Furthermore, a conductive layer 328 is embedded in insulating layers 320 and 322, and a conductive layer 330 is embedded in insulating layers 324 and 326. The conductive layers 328 and 330 function as plugs or wiring.

[0294] Furthermore, the insulating layer, which functions as an interlayer film, may also function as a planarizing film that covers the uneven shape beneath it. For example, the upper surface of the insulating layer 322 may be planarized by a planarizing treatment using the CMP method or the like to improve its flatness.

[0295] A wiring layer may be provided on the insulating layer 326 and the conductive layer 330. For example, in Figure 12, insulating layers 350, 352, and 354 are stacked in order. A conductive layer 356 is formed on insulating layers 350, 352, and 354. The conductive layer 356 functions as a plug or wiring.

[0296] The insulating layers 352 and 354, which function as interlayer films, can be the insulating layers described above that can be used in semiconductor devices or memory devices.

[0297] For conductive layers that function as plugs or wiring, such as conductive layer 328, conductive layer 330, and conductive layer 356, conductive materials applicable to conductive layer 240 can be used. It is preferable to use high-melting-point materials such as tungsten or molybdenum that provide both heat resistance and conductivity, and tungsten is preferred. Alternatively, it is preferable to form them with low-resistance conductive materials such as aluminum or copper. Using low-resistance conductive materials can reduce wiring resistance.

[0298] The conductive layer 240 of the transistor 200 is connected to a low-resistance region 314b that functions as the source region or drain region of the transistor 300 via conductive layers 643, 642, 644, 645, 646, 356, 330, and 328.

[0299] The conductive layer 643 is embedded in the insulating layer 280. The conductive layer 642 is provided on the insulating layer 130 and embedded in the insulating layer 280. The conductive layer 642 can be manufactured from the same material and using the same process as the conductive layer 220. The conductive layer 644 is embedded in the insulating layer 180 and the insulating layer 130. The conductive layer 645 is embedded in the insulating layer 180. The conductive layer 645 can be manufactured from the same material and using the same process as the conductive layer 110. The conductive layer 646 is embedded in the insulating layer 648. The transistor 300 and the conductive layer 110 are insulated by the insulating layer 648.

[0300] This embodiment can be combined with other embodiments as appropriate. Furthermore, if multiple configuration examples are shown within a single embodiment in this specification, these configuration examples can be combined as appropriate.

[0301] <Materials for the semiconductor device> Hereinafter, materials that can be used in the semiconductor device of the present embodiment will be described. Note that each layer constituting the semiconductor device of the present embodiment may have a single-layer structure or a stacked structure.

[0302] [Oxide semiconductor layer] For the oxide semiconductor layer that can be used as the semiconductor layer of the transistor according to one aspect of the present invention, reference can be made to the content described in <Configuration example of semiconductor device>.

[0303] The carrier concentration in the channel formation region is 1×10 １９ cm −３ less than, 1×10 １８ cm −３ less than, 5×10 １７ cm −３ less than, 1×10 １７ cm −３ less than, 1×10 １６ cm −３ less than, 1×10 １５ cm −３ less than, 1×10 １４ cm −３ less than, 1×10 １３ cm −３ less than, 1×10 １２ cm −３ less than, 1×10 １１ cm −３ less than, or 1×10 １０ cm −３ less than is preferable. Also, the lower limit value of the carrier concentration in the channel formation region is not particularly limited. For example, it can be 1×10 −７ cm −３ can be set.

[0304] As described above, in an OS transistor, if oxygen vacancies (V Ｏ ) and impurities are present in the channel formation region in the oxide semiconductor, the electrical characteristics are likely to fluctuate and the reliability may deteriorate. Therefore, in order to stabilize the electrical characteristics of the OS transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. Also, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to reduce the impurity concentration in the adjacent film. Examples of impurities include hydrogen, carbon, and nitrogen.

[0305] In an oxide semiconductor, when nitrogen is contained, electrons as carriers are generated, the carrier concentration increases, and it tends to become n-type. As a result, a transistor using an oxide semiconductor containing nitrogen tends to be normally on. Or, in an oxide semiconductor, when nitrogen is contained, trap levels may be formed. As a result, the electrical characteristics of the transistor may become unstable. Therefore, the nitrogen concentration in the channel formation region of the oxide semiconductor obtained by SIMS is 1×10 ２０ atoms / cm ３ or less, preferably 5×10 １９ atoms / cm ３ or less, more preferably 1×10 １９ atoms / cm ３ or less, more preferably 5×10 １８ atoms / cm ３ or less, more preferably 1×10 １８ atoms / cm ３ or less, still more preferably 5×10 １７ atoms / cm ３ or less.

[0306] Further, hydrogen contained in the oxide semiconductor may react with oxygen bonded to metal atoms to form water, thereby forming oxygen vacancies. When hydrogen enters the oxygen vacancies, electrons as carriers may be generated. Also, a part of hydrogen may bond with oxygen bonded to metal atoms to generate electrons as carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen tends to be normally on. Therefore, it is preferable that hydrogen in the channel formation region of the oxide semiconductor is reduced as much as possible. Specifically, the hydrogen concentration in the channel formation region of the oxide semiconductor obtained by SIMS is less than 1×10 ２０ atoms / cm ３ preferably less than 5×10 １９ atoms / cm ３ more preferably less than 1×10 １９ atoms / cm ３ more preferably less than 5×10 １８ atoms / cm ３Less than, more preferably 1 × 10 １８ atoms / cm ３ Less than 1 × 10 １７ atoms / cm ３ It shall be less than 1 × 10⁻⁶. There are no particular limitations on the lower limit of hydrogen concentration in the channel formation region of oxide semiconductors, but for example, 1 × 10⁻⁶ １６ atoms / cm ３ This can be done.

[0307] Furthermore, if alkali metals or alkaline earth metals are present in the oxide semiconductor, defect levels may form, potentially leading to unstable electrical properties of the transistor. For this reason, the concentration of alkali metals or alkaline earth metals in the channel formation region of the oxide semiconductor obtained by SIMS is set to 1 × 10⁻⁶. １８ atoms / cm ３ The following is preferably 2 × 10 １６ atoms / cm ３ Do the following:

[0308] By using an oxide semiconductor with sufficiently reduced impurities in the channel formation region of a transistor, stable electrical characteristics can be imparted.

[0309] [Insulating Layers] For the insulating layers of the semiconductor device (insulating layer 210, insulating layer 250, insulating layer 280, insulating layer 282, insulating layer 283, insulating layer 284, insulating layer 285, etc.), it is preferable to use inorganic insulating films. Examples of inorganic insulating films include oxide insulating films, nitride insulating films, oxidative nitride insulating films, and nitride oxide insulating films. Examples of oxide insulating films include silicon oxide films, aluminum oxide films, magnesium oxide films, gallium oxide films, germanium oxide films, yttrium oxide films, zirconium oxide films, lanthanum oxide films, neodymium oxide films, hafnium oxide films, tantalum oxide films, cerium oxide films, gallium zinc oxide films, and hafnium aluminate films. Examples of nitride insulating films include silicon nitride films and aluminum nitride films. Examples of oxidative nitride insulating films include silicon oxidative nitride films, aluminum oxidative nitride films, gallium oxidative nitride films, yttrium oxidative nitride films, and hafnium oxidative nitride films. Examples of nitride oxide insulating films include silicon nitride films and aluminum nitride films. Furthermore, organic insulating films may be used for the insulating layer of semiconductor devices.

[0310] For example, as transistors become smaller and more integrated, thinning of the gate insulating layer can lead to problems such as leakage current. By using a high-k material for the gate insulating layer, it becomes possible to lower the voltage during transistor operation while maintaining the physical film thickness. It also becomes possible to thin the equivalent oxide thickness (EOT) of the gate insulating layer. On the other hand, by using a material with a low relative permittivity for the insulating layer that functions as an interlayer film, parasitic capacitance between wiring can be reduced. Therefore, it is preferable to select the material according to the function of the insulating layer. It should be noted that materials with a low relative permittivity are also materials with high dielectric strength.

[0311] Examples of materials with a high dielectric constant include aluminum oxide, gallium oxide, hafnium oxide, tantalum oxide, zirconium oxide, hafnium-zirconium oxide, oxides containing aluminum and hafnium, oxides containing aluminum and hafnium, oxides containing silicon and hafnium, oxides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0312] Examples of materials with low dielectric constant include inorganic insulating materials such as silicon oxide, silicon oxide-nitride, and silicon nitride-oxide, as well as resins such as polyester, polyolefin, polyamide (nylon and aramid, etc.), polyimide, polycarbonate, and acrylic resin. Other inorganic insulating materials with low dielectric constant include, for example, silicon oxide containing fluorine, silicon oxide containing carbon, and silicon oxide containing carbon and nitrogen. Also, for example, silicon oxide having vacancies can be used. These silicon oxides may contain nitrogen.

[0313] Furthermore, a ferroelectric material may be used for the insulating layer of the semiconductor device. Preferably, an oxide containing one or both hafnium and zirconium is used as the ferroelectric material. Examples of such oxides include metal oxides such as hafnium oxide, zirconium oxide, and hafnium-zirconium oxide. Alternatively, a material may be used in which element J1 (where element J1 is one or more selected from the other of hafnium and zirconium, silicon, aluminum, gadolinium, yttrium, lanthanum, and strontium, etc.) is added to a metal oxide containing either hafnium or zirconium as the ferroelectric material.

[0314] Furthermore, by adding a Group 3 element from the periodic table to an oxide containing one or both hafnium and zirconium, the oxygen vacancy concentration in the oxide increases, making it easier to form crystals with an orthorhombic crystal structure. This is preferable because it increases the proportion of crystals with an orthorhombic crystal structure and thus increases the amount of remanent polarization. On the other hand, if too much Group 3 element is added, the crystallinity of the oxide may decrease, making it difficult to exhibit ferroelectric properties. Therefore, the content of Group 3 elements in an oxide containing one or both hafnium and zirconium is preferably 0.1 atomic% to 10 atomic%, more preferably 0.1 atomic% to 5 atomic%, and even more preferably 0.1 atomic% to 3 atomic%. Here, the content of Group 3 elements refers to the ratio of the number of Group 3 elements to the sum of the number of atoms of all metal elements contained in the layer. The Group 3 element is preferably one or more selected from scandium, lanthanum, and yttrium, and more preferably one or both of lanthanum and yttrium.

[0315] Furthermore, a material that may possess ferroelectric properties is a metal nitride having at least one of elements M1 and M2, and nitrogen. Here, element M1 is one or more selected from aluminum, gallium, and indium, etc. Element M2 is one or more selected from boron, scandium, yttrium, lanthanum, cerium, neodymium, europium, titanium, zirconium, hafnium, vanadium, niobium, tantalum, and chromium, etc. Another material that may possess ferroelectric properties is a material in which element M3 is added to the above metal nitride. Element M3 is one or more selected from magnesium, calcium, strontium, zinc, and cadmium, etc.

[0316] Furthermore, SrTaO is an example of a material that may possess ferroelectric properties. ２ N and BaTaO ２ Perovskite-type oxynitrides such as N, and GaFeO with a κ-alumina structure. ３ These are some examples. In addition, lead titanate (PbTiO) is a material that can possess ferroelectric properties.Ｘ ), or piezoelectric ceramics having a perovskite structure such as barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), bismuth ferrite (BFO), or barium titanate may be used.

[0317] While the above explanation uses metal oxides and metal nitrides as examples, it is not limited to these. For example, metal oxynitrides obtained by adding nitrogen to the aforementioned metal oxides, or metal nitrogen oxides obtained by adding oxygen to the aforementioned metal nitrides, may be used.

[0318] Furthermore, as a material that may possess ferroelectricity, for example, a mixture or compound consisting of multiple materials selected from the materials listed above can be used. Alternatively, a laminated structure consisting of multiple materials selected from the materials listed above can be used. Incidentally, the crystal structure (properties) of the materials listed above may change not only depending on the film deposition conditions but also on various processes, so in this specification, materials that exhibit ferroelectricity are not only called ferroelectrics, but also materials that may possess ferroelectricity.

[0319] In this specification, a layered structure of a material capable of ferroelectricity may be referred to as a ferroelectric layer, a metal oxide film, or a metal nitride film. Furthermore, a device having such a ferroelectric layer, metal oxide film, or metal nitride film may be referred to as a ferroelectric device in this specification.

[0320] The ferroelectric layer is preferably composed of crystals having an orthorhombic crystal structure, as this exhibits ferroelectric properties. The crystal structure of the crystals included in the ferroelectric layer may be one or more selected from tetragonal, orthorhombic, monoclinic, and hexagonal systems. Furthermore, the ferroelectric layer may have an amorphous structure. In this case, the ferroelectric layer may have a composite structure comprising both an amorphous and a crystalline structure.

[0321] Metal oxides containing either or both hafnium and zirconium are insulating materials that have the function of capturing or fixing hydrogen. Therefore, by using a metal oxide containing either or both hafnium and zirconium in at least a portion of the gate insulating layer, hydrogen contained in the oxide semiconductor layer can be captured or fixed, thereby reducing the hydrogen concentration in the oxide semiconductor layer. Furthermore, a transistor having such a gate insulating layer can function as an FeFET (Ferroelectric Field Effect Transistor).

[0322] Furthermore, the electrical properties of a transistor using a metal oxide can be stabilized by surrounding it with an insulating layer that has the function of suppressing the permeation of impurities and oxygen. As an insulating layer that has the function of suppressing the permeation of impurities and oxygen, for example, an insulating layer containing one or more selected from boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum can be used in a single layer or multilayer configuration. Specifically, as the material for the insulating layer that has the function of suppressing the permeation of impurities and oxygen, metal oxides such as aluminum oxide, magnesium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide, nitrides such as aluminum nitride or silicon nitride, and nitride oxides such as silicon nitride can be used.

[0323] Specifically, materials for insulating layers that have the function of suppressing the permeation of impurities such as water and hydrogen, and oxygen, include metal oxides such as aluminum oxide, magnesium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, and oxides containing aluminum and hafnium (hafnium aluminate). Also, nitrides such as aluminum nitride and silicon nitride are mentioned. Furthermore, nitride oxides such as silicon nitride are mentioned. Additionally, gallium oxide is mentioned as a material for insulating layers that has the function of suppressing oxygen permeation.

[0324] Furthermore, insulating layers that are in contact with the oxide semiconductor layer, such as gate insulating layers, or insulating layers provided near the oxide semiconductor layer, are preferably insulating layers that have regions containing excess oxygen. For example, by having an insulating layer with regions containing excess oxygen in contact with or near the oxide semiconductor layer, the oxygen vacancies in the oxide semiconductor layer can be reduced. For insulating layers that easily form regions containing excess oxygen, refer to the description in <Examples of Semiconductor Device Configurations>.

[0325] It is preferable to use a hydrogen barrier insulating layer for the insulating layer in contact with the oxide semiconductor layer, or an insulating layer provided near the oxide semiconductor layer. The hydrogen barrier properties of this insulating layer suppress the diffusion of hydrogen into the oxide semiconductor layer. A hydrogen barrier insulating layer can also be described as an insulating layer that has the function of suppressing hydrogen diffusion.

[0326] Examples of insulating materials having the function of capturing or fixing hydrogen include metal oxides such as hafnium oxides, magnesium oxides, aluminum oxides, aluminum and hafnium oxides (hafnium aluminate), and hafnium silicate. Furthermore, these metal oxides may also contain zirconium, for example, hafnium and zirconium oxides.

[0327] An insulating layer having the function of capturing or fixing hydrogen preferably has an amorphous structure. In metal oxides having an amorphous structure, some oxygen atoms have dangling bonds, thus having a high ability to capture or fix hydrogen. Therefore, by having an amorphous structure in the insulating layer, the function of capturing or fixing hydrogen can be enhanced.

[0328] By making the insulating layer amorphous, the formation of grain boundaries can be suppressed. Suppressing the formation of grain boundaries improves the flatness of the insulating layer. This makes the thickness distribution of the insulating layer more uniform, reducing areas with extremely thin thickness, and thus improving the dielectric strength of the insulating layer. Furthermore, the thickness distribution of the film provided on the insulating layer can be made more uniform. In addition, by suppressing the formation of grain boundaries in the insulating layer, leakage current caused by defect levels at the grain boundaries can be reduced. Therefore, the insulating layer can function as an insulating film with low leakage current.

[0329] Furthermore, the function of capturing or fixing a corresponding substance can also be described as the property of making the corresponding substance difficult to diffuse. Therefore, the function of capturing or fixing a corresponding substance can be rephrased as barrier properties.

[0330] In this specification, the term "barrier insulating layer" refers to an insulating layer that possesses barrier properties. Furthermore, "barrier property" refers to the property of making it difficult for the corresponding substance to diffuse (also referred to as the property of making it difficult for the corresponding substance to permeate, the property of having low permeability to the corresponding substance, or the function of suppressing the diffusion of the corresponding substance). When hydrogen is described as a corresponding substance, it refers to, for example, a hydrogen atom, a hydrogen molecule, and water molecules and OH groups. − This refers to at least one substance that is bonded with hydrogen, such as [substance name]. Furthermore, when an impurity is described as a corresponding substance, unless otherwise specified, it refers to an impurity in the channel-forming region or semiconductor layer, such as a hydrogen atom, hydrogen molecule, water molecule, nitrogen atom, nitrogen molecule, nitrogen oxide molecule (N ２ O, NO, and NO ２This refers to at least one of the following: (etc.), and copper atoms, etc. Furthermore, when oxygen is described as a corresponding substance, it refers to at least one of the following: for example, an oxygen atom and an oxygen molecule, etc.

[0331] Examples of materials for the barrier insulating layer against hydrogen include aluminum oxide, magnesium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium (hafnium aluminate), oxides containing hafnium and zirconium (hafnium zirconium oxide), silicon nitride, or silicon nitride oxide.

[0332] The inorganic insulating layers listed as having the function of capturing or fixing hydrogen, and the function of suppressing hydrogen diffusion, also possess barrier properties against oxygen. Examples of materials for the oxygen barrier insulating layer include oxides containing one or both of aluminum and hafnium, magnesium oxide, zinc gallium oxide, silicon nitride, and silicon nitride oxide. Examples of oxides containing one or both of aluminum and hafnium include aluminum oxide, hafnium oxide, oxides containing aluminum and hafnium (hafnium aluminate), and hafnium silicate.

[0333] [Substrate] As a substrate for forming a transistor, for example, an insulating substrate, a semiconductor substrate, or a conductive substrate can be used. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (such as yttria-stabilized zirconia substrates), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. Furthermore, there are semiconductor substrates having insulating regions within the aforementioned semiconductor substrates, such as SOI (Silicon On Insulator) substrates. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, or conductive resin substrates. Alternatively, there are substrates having metal nitrides or metal oxides. Furthermore, there are substrates on which a conductor or semiconductor is provided on an insulating substrate, substrates on which a conductor or insulator is provided on a semiconductor substrate, and substrates on which a semiconductor or insulator is provided on a conductive substrate. Alternatively, substrates with elements mounted on them may be used. Examples of elements mounted on the substrate include capacitive elements, resistive elements, switch elements, light-emitting elements, or memory elements.

[0334] [Conductive Layers] The conductive layers (conductive layer 220, conductive layer 240, conductive layer 260, conductive layer 265, etc.) of the semiconductor device are preferably made of metal elements selected from aluminum, chromium, copper, silver, gold, platinum, zinc, tantalum, nickel, titanium, iron, cobalt, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, palladium, iridium, strontium, and lanthanum, respectively, or alloys composed of the aforementioned metal elements, or alloys combining the aforementioned metal elements. As alloys composed of the aforementioned metal elements, nitrides of the alloy or oxides of the alloy may be used. For example, it is preferable to use tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. Alternatively, semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements like phosphorus, or silicides such as nickel silicide may be used.

[0335] Furthermore, conductive materials containing nitrogen, such as nitrides containing tantalum, nitrides containing titanium, nitrides containing molybdenum, nitrides containing tungsten, nitrides containing ruthenium, nitrides containing tantalum and aluminum, or nitrides containing titanium and aluminum; conductive materials containing oxygen, such as oxides containing ruthenium oxide, strontium and ruthenium, or oxides containing lanthanum and nickel; and materials containing metallic elements such as titanium, tantalum, or ruthenium are preferred because they are conductive materials that are resistant to oxidation, conductive materials that have the function of suppressing oxygen diffusion, or materials that maintain conductivity even when absorbing oxygen. Examples of conductive materials containing oxygen include indium oxide containing tungsten oxide, indium oxide containing titanium oxide, ITO, indium tin oxide containing titanium oxide, ITSO, In-Zn oxide, and indium zinc oxide containing tungsten oxide. In this specification, conductive films formed using conductive materials containing oxygen are sometimes referred to as oxide conductive films.

[0336] Furthermore, multiple conductive layers formed from the above materials may be used in a laminated structure. For example, a laminated structure may be formed by combining the aforementioned metal element material with an oxygen-containing conductive material. Alternatively, a laminated structure may be formed by combining the aforementioned metal element material with a nitrogen-containing conductive material. Alternatively, a laminated structure may be formed by combining the aforementioned metal element material with an oxygen-containing conductive material and a nitrogen-containing conductive material.

[0337] Furthermore, when using a metal oxide for the channel formation region of a transistor, it is preferable to use a laminated structure for the conductive layer that functions as the gate electrode, which combines the aforementioned metal element material with an oxygen-containing conductive material. In this case, it is preferable to provide the oxygen-containing conductive material on the channel formation region side. By providing the oxygen-containing conductive material on the channel formation region side, oxygen detached from the conductive material is more easily supplied to the channel formation region.

[0338] The above describes the materials that can be used in the semiconductor device of this embodiment.

[0339] <Example of Manufacturing Method> Below, an example of a method for manufacturing a semiconductor device according to one aspect of the present invention will be described using Figures 13A to 21C. In the drawings showing an example of a method for manufacturing a semiconductor device, (A) in each figure shows a plan view. (B) in each figure is a cross-sectional view between the dashed lines A1 and A2 shown in (A) of each figure. (C) in each figure is a cross-sectional view between the dashed lines B1 and B2 shown in (A) of each figure.

[0340] Thin films (insulating films, semiconductor films, conductive films, etc.) that constitute semiconductor devices can be formed using sputtering, CVD, vacuum deposition, PLD, ALD, and other methods. CVD methods include plasma enhanced CVD (PECVD), thermal CVD, and photo CVD. Other methods include metal-organic CVD (MOCVD) and metal CVD.

[0341] Furthermore, thin films (insulating films, semiconductor films, conductive films, etc.) that constitute semiconductor devices can be formed by methods such as spin coating, dip coating, spray coating, inkjet printing, dispensing, screen printing, offset printing, slit coating, roll coating, and curtain coating.

[0342] Furthermore, the thin films constituting the semiconductor device can be processed using photolithography or other methods. Alternatively, the thin films may be processed by nanoimprint lithography, lift-off lithography, or other methods. In addition, island-shaped thin films may be directly formed using a film deposition method employing a shielding mask such as a metal mask.

[0343] There are two main methods of photolithography. One method involves forming a resist mask on the thin film to be processed, then processing the thin film by etching or other means, and removing the resist mask. The other method involves forming a photosensitive thin film, then exposing and developing it to process the thin film into the desired shape.

[0344] Etching can be performed using methods such as dry etching or wet etching.

[0345] First, an insulating layer 210 is formed on a substrate (not shown) (Figures 13A to 13C). For the insulating layer 210, an inorganic insulating film such as silicon oxide, silicon nitride, silicon oxynitride, or silicon oxide nitride can be used. For forming the insulating layer 210, for example, sputtering, CVD, or ALD can be used. If the upper surface of the insulating layer 210 is not flat, a planarization treatment may be performed after the insulating layer 210 is formed so that the upper surface of the insulating layer 210 becomes flat. For the planarization treatment, for example, the CMP (Chemical Mechanical Polishing) method can be used.

[0346] Next, films that will become conductive layers 220 (conductive layer 220_1, conductive layer 220_2) are deposited on the insulating layer 210. The conductive layers 220 are formed by processing the films that will become conductive layers 220. Sputtering, metal CVD, MOCVD, ALD, etc. can be used to deposit the conductive layers 220. For example, as conductive layers 220, tungsten deposited by metal CVD can be used as conductive layer 220_1, and a conductive oxide film deposited by sputtering can be used as conductive layer 220_2. Alternatively, as conductive layers 220, for example, tungsten deposited by sputtering can be used as conductive layer 220_1, and a conductive oxide film deposited by sputtering can be used as conductive layer 220_2. ITO, ITSO, etc. can be used as conductive oxide films. Dry etching is preferably used to process the conductive layers 220. For example, a mask (not shown) is formed on the film that will become the conductive layer 220 in the region that will become the conductive layer 220, and the film that will become the conductive layer 220 in the regions where the mask is not formed is removed by etching. It is preferable to use anisotropic dry etching for this etching process. After the etching process, the mask is removed. Figure 13B shows an example in which the side surface of the conductive layer 220 at the opening 290 is perpendicular to the surface to be formed, but depending on the etching conditions, the side surface of the conductive layer 220 at the opening 290 may have a tapered shape that is inclined with respect to the surface to be formed.

[0347] Next, an insulating layer 280_1 is formed on the conductive layer 220, covering the conductive layer 220. The insulating layer 280_1 can be formed by a film formation method such as ALD, sputtering, or CVD. For example, silicon nitride formed by the ALD method can be used for the insulating layer 280_1. It is preferable to use an insulating film that has the function of capturing or fixing hydrogen, an insulating film that has the function of suppressing the permeation of impurities such as water and hydrogen and oxygen, an insulating film that has barrier properties against hydrogen, or an insulating film that has barrier properties against oxygen for the insulating layer 280_1.

[0348] Next, an insulating layer 280_2 is formed on the insulating layer 280_1. The insulating layer 280_2 can be formed by a film formation method such as sputtering, ALD, or CVD. For example, silicon nitride formed by sputtering can be used for the insulating layer 280_2. It is preferable to use an insulating film that has the function of capturing or fixing hydrogen, an insulating film that has the function of suppressing the permeation of impurities such as water and hydrogen and oxygen, an insulating film that has barrier properties against hydrogen, or an insulating film that has barrier properties against oxygen for the insulating layer 280_2. It is also preferable to perform a planarization treatment on the insulating layer 280_2. For example, the CMP method can be used for the planarization treatment.

[0349] Next, an insulating layer 280_3 is formed on the insulating layer 280_2. The insulating layer 280_3 can be silicon nitride, silicon oxide, silicon nitride oxide, silicon oxynitride, or silicon oxynitride, which are formed by sputtering, CVD, or ALD. For example, silicon oxide formed by sputtering can be used for the insulating layer 280_3. It is preferable to use a film formed by sputtering that does not use hydrogen as the deposition gas for the insulating layer 280_3. It is also preferable to perform a heat treatment after the deposition of the insulating layer 280_3 to reduce the amount of hydrogen in the insulating layer 280_3.

[0350] The heat treatment should be carried out at a temperature of 250°C to 650°C, preferably 300°C to 500°C, and more preferably 320°C to 450°C. The heat treatment should be carried out in an atmosphere of nitrogen gas or an inert gas, or in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, when heat treatment is carried out in a mixed atmosphere of nitrogen gas and oxygen gas, the oxygen gas should be about 20%. The heat treatment may also be carried out under reduced pressure. Alternatively, the heat treatment may be carried out in an atmosphere of nitrogen gas or an inert gas, and then in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to replenish the desorbed oxygen. By performing the heat treatment as described above, impurities such as water and hydrogen contained in the insulating layer 280_3, etc., can be reduced before the deposition of the oxide semiconductor film that will become the semiconductor layer.

[0351] Furthermore, it is preferable that the gas used in the above heat treatment is highly purified. For example, the amount of water contained in the gas used in the above heat treatment can be 1 ppb or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less. By performing the heat treatment using a highly purified gas, it is possible to prevent as much as possible from moisture or other substances being incorporated into the insulating layer 280_3, etc.

[0352] There are no special limitations on the equipment used for heat treatment; it may be an equipment that heats the workpiece by heat conduction or thermal radiation from a heat source such as a resistance heating element. For example, an electric furnace or an RTA (Rapid Thermal Anneal) equipment such as an LRTA (Lamp Rapid Thermal Anneal) or GRTA (Gas Rapid Thermal Anneal) equipment can be used. An LRTA equipment is an equipment that heats the workpiece by radiation of light (electromagnetic waves) emitted from a lamp such as a halogen lamp, metal halide lamp, xenon arc lamp, carbon arc lamp, high-pressure sodium lamp, or high-pressure mercury lamp. A GRTA equipment is an equipment that performs heat treatment using high-temperature gas.

[0353] Furthermore, a process to supply oxygen to the insulating layer 280_3 can also be performed. Oxygen is supplied to the insulating layer 280_3, and the heat applied after the formation of the semiconductor layer 230 can supply oxygen from the insulating layer 280_3 to the semiconductor layer 230.

[0354] Examples of processes for supplying oxygen include heating in an oxygen-containing atmosphere, or plasma treatment (including microwave plasma treatment) in an oxygen-containing atmosphere. Alternatively, oxygen may be supplied to the insulating layer 280_3 by forming an oxide film (preferably a metal oxide film) in an oxygen-containing atmosphere using a sputtering method. It is preferable to remove the formed oxide film immediately. The oxygen-containing atmosphere may be oxygen gas (O ２ ) as well as ozone (O ３ ) or nitrous oxide (N ２ The atmosphere includes gases containing oxygen-containing compounds such as O). Furthermore, the substrate temperature during plasma treatment shall be between room temperature (25°C) and 450°C.

[0355] Next, an insulating layer 280_4 is formed on the insulating layer 280_3. The insulating layer 280_4 can be formed by a film formation method such as sputtering, ALD, or CVD. For example, silicon nitride formed by sputtering can be used for the insulating layer 280_4. It is preferable to use an insulating film having the function of capturing or fixing hydrogen, an insulating film having the function of suppressing the permeation of impurities such as water and hydrogen and oxygen, an insulating film having barrier properties against hydrogen, or an insulating film having barrier properties against oxygen for the insulating layer 280_1.

[0356] Next, conductive films 240f (conductive film 240_1f, conductive film 240_2f), which will become conductive layers 240 (conductive layer 240_1, conductive layer 240_2), are deposited on the insulating layer 280_4. Sputtering, metal CVD, MOCVD, ALD, etc., can be used to deposit the conductive films 240f. For example, tungsten deposited by sputtering as conductive film 240_1f, and a conductive oxide deposited by sputtering as conductive film 240_2f can be used. ITO, ITSO, etc., can be used as conductive oxide films.

[0357] Next, as shown in Figures 14A to 14C, an oxide film 245f, which will become the oxide layer 245, is deposited on the conductive film 240_2f. The oxide film 245f can be a film containing crystals that will serve as nuclei for crystallizing the semiconductor film 230f that will be deposited later. Therefore, the oxide layer 245 can be called a seed crystal layer or seed layer. The method for depositing the oxide layer 245 is not particularly limited. For example, it can be formed using a sputtering method or an ALD method. It is preferable to use a metal oxide or an oxide semiconductor for the oxide film 245f. It is more preferable to use a target containing indium, gallium, zinc, and oxygen and deposit the oxide film 245f by sputtering.

[0358] The oxide film 245f is preferably thin. For example, the thickness of the oxide film 245f is preferably thinner than the thickness of the semiconductor layer 230. Specifically, the oxide film 245f preferably has a region with a thickness of 0.1 nm or more and less than 2 nm, and more preferably has a region with a thickness of 0.5 nm or more and less than 2 nm. The oxide film 245f may be in the form of a film or granules.

[0359] It is preferable to deposit the oxide film 245f, the conductive film 240_2f, and the conductive film 240_1f continuously without exposure to the atmosphere. For example, a multi-chamber type deposition apparatus can be used. This makes it possible to suppress the incorporation of impurities during the deposition of the oxide film 245f, the conductive film 240_2f, and the conductive film 240_1f.

[0360] Next, as shown in Figures 15A to 16C, the opening 290 is formed using lithography. First, as shown in Figures 15A to 15C, a mask layer 400 is formed on the oxide film 245f in the region other than the region that will become the opening 290.

[0361] In lithography, the resist is first exposed through a mask. Next, the exposed area is removed or left intact using a developer to form a resist mask. Then, by etching through this resist mask, conductors, semiconductors, or insulators can be processed into the desired shape. For example, a resist mask can be formed by exposing the resist using KrF excimer laser light, ArF excimer laser light, EUV (Extreme Ultraviolet) light, etc. Alternatively, immersion technology may be used, in which a liquid (e.g., water) is filled between the substrate and the projection lens for exposure. In addition, an electron beam or ion beam may be used instead of the aforementioned light. When using an electron beam or ion beam, a mask may not be necessary in some cases.

[0362] Alternatively, a configuration may be used in which an SOC (Spin On Carbon) film and an SOG (Spin On Glass) film are deposited between the workpiece and the resist mask. By using the SOC film and SOG film as masks, the durability of the mask pattern can be improved. For example, lithography can be performed by depositing the SOC film, SOG film, and resist mask in that order on the workpiece.

[0363] Next, as shown in Figures 16A to 16C, the oxide film 245f, conductive film 240_2f, conductive film 240_1f, insulating layer 280_4, insulating layer 280_3, insulating layer 280_2, insulating layer 280_1, and a portion of the conductive layer 220_2 are removed by etching. It is preferable to use anisotropic dry etching for this etching process. It is preferable to make the conductive layer 220_2 in the region that will become the opening 290 into a recessed shape. Note that a portion of the mask layer 400 may be removed by the etching process.

[0364] Next, the oxide film 245f is covered with at least a portion of the mask layer 400, and a cleaning process is performed to remove impurities and other contaminants attached to the transistor 200A. By covering the oxide film 245f with the mask layer 400, the cleaning process can be performed without damaging the oxide film 245f. Cleaning methods include wet cleaning using a cleaning solution (which can also be called wet etching), plasma treatment using plasma, and cleaning by heat treatment, and these cleaning methods may be combined as appropriate.

[0365] Wet cleaning may be performed using an aqueous solution obtained by diluting one or more of oxalic acid, phosphoric acid, and hydrofluoric acid with carbonated water or distilled water. Alternatively, wet cleaning may be performed using an aqueous solution obtained by diluting ammonia water with carbonated water or distilled water. Alternatively, wet cleaning may be performed using distilled water or carbonated water, etc. Alternatively, ultrasonic cleaning may be performed using these aqueous solutions, distilled water, or carbonated water. Alternatively, these cleaning methods may be combined as appropriate.

[0366] In this specification, an aqueous solution obtained by diluting hydrofluoric acid with pure water may be referred to as diluted hydrofluoric acid. The concentration and temperature of the aqueous solution are adjusted as appropriate depending on the impurities to be removed and the configuration of the semiconductor device to be cleaned. The hydrofluoric acid concentration of the diluted hydrofluoric acid is preferably 0.01 ppm to 100 ppm, and more preferably 0.1 ppm to 10 ppm.

[0367] The cleaning process preferably involves megasonic cleaning using hydrofluoric acid and pure water. More preferably, megasonic cleaning using hydrofluoric acid and pure water, as well as carbonated water cleaning, are used.

[0368] By performing the cleaning process described above, impurities adhering to the surface of the opening 290 or diffused into its interior can be removed. It is also possible to perform the same cleaning process under the same conditions as above after etching the conductive film 240_2f.

[0369] Next, as shown in Figures 17A to 17C, a dry etching treatment such as an ashing treatment using oxygen plasma (hereinafter sometimes referred to as oxygen plasma treatment) is performed to remove the mask layer 400. The mask layer 400 may also be removed by wet etching treatment, not just dry etching treatment. Furthermore, wet etching treatment may be performed after dry etching treatment. Furthermore, dry etching treatment may be performed after wet etching treatment.

[0370] Next, as shown in Figures 18A to 18C, a semiconductor film 230f is formed. The semiconductor film 230f is formed to cover at least a portion of the conductive layer 220, the insulating layer 280, the conductive film 240f, and the oxide film 245f. It is more preferable that the semiconductor film 230f is formed to cover the oxide film 245f. Within the opening 290, the semiconductor film 230f has regions in contact with the side surface of the oxide film 245f, regions in contact with the side surface of the conductive layer 240_1, regions in contact with the side surface of the conductive layer 240_2, regions in contact with the side surface of the insulating layer 280_4, regions in contact with the side surface of the insulating layer 280_3, regions in contact with the side surface of the insulating layer 280_2, regions in contact with the side surface of the insulating layer 280_1, and regions in contact with the conductive layer 220_2. The semiconductor film 230f can be formed by a film formation method such as ALD or sputtering. For the semiconductor film 230f, it is preferable to use, for example, indium oxide. The semiconductor film 230f may also be in a laminated structure. For example, in the case of a two-layer laminated structure, an indium oxide film is deposited as the first layer on the side in contact with the oxide film 245f using the ALD method with triethylindium as the precursor. Furthermore, as the second layer, an IGZO film is deposited on the first layer using the sputtering method with a target containing indium, gallium, zinc, and oxygen.

[0371] In the present invention, when an oxide film 245f is formed after an opening 290 is formed in the insulating layer 280 and the conductive film 240f, the oxide film 245f is formed on the side of the conductive film 240f facing the opening 290, which can make it difficult for the semiconductor film 230f to come into contact with that side. This may increase the contact resistance between the semiconductor layer 230 and the conductive layer 240. On the other hand, as described above, in the method for manufacturing a semiconductor device according to one aspect of the present invention, an oxide film 245f is formed on the conductive film 240f, and then an opening 290 is provided in the insulating layer 280, the conductive film 240f, and the oxide film 245f. Subsequently, by forming the semiconductor film 230f, the semiconductor film 230f can be provided in contact with the side of the conductive film 240f facing the opening 290. By having the semiconductor film 230f and the side of the conductive film 240f facing the opening 290 come into contact, the contact area between the semiconductor layer 230 and the conductive layer 240 can be increased. By increasing the contact area between the semiconductor layer 230 and the conductive layer 240, the contact resistance between the semiconductor layer 230 and the conductive layer 240 can be reduced. This allows for an increase in the on-current of the semiconductor device.

[0372] Furthermore, it is preferable that the indium oxide used in the semiconductor film 230f is highly purified. Specifically, the Al concentration in the indium oxide film is 3.0 × 10⁻⁶. １５ atoms / cm ３ The following is preferable. Also, the Ga concentration in the indium oxide film is 4.0 × 10⁻⁶. １５ atoms / cm ３ The following is preferable:

[0373] The film thickness of the semiconductor film 230f is preferably 1 nm or more and 50 nm or less, more preferably 2.5 nm or more and 30 nm or less, still more preferably 2.5 nm or more and 20 nm or less, still more preferably 5 nm or more and 20 nm or less, and even more preferably 5 nm or more and 10 nm or less. Note that the semiconductor film 230f only needs to have a film thickness region as described above at least partially. For example, it is sufficient if the semiconductor film 230f has a film thickness region as described above in the channel formation region. By setting the film thickness of the semiconductor film 230f within the above range, the crystallinity of the semiconductor film 230f can be enhanced. By enhancing the crystallinity of the semiconductor film 230f, the semiconductor film 230f can have crystal grains.

[0374] Note that it is preferable to perform a process for enhancing the crystallinity of the semiconductor film 230f after forming the semiconductor film 230f. Examples of the process for enhancing the crystallinity of the semiconductor film 230f include heat treatment, plasma treatment, microwave (typically 2.45 GHz) treatment, microwave plasma treatment, and light (e.g., ultraviolet light) irradiation treatment. Note that a plurality of these processes may be performed simultaneously or sequentially. For example, heat treatment and microwave plasma treatment can be performed simultaneously. Alternatively, microwave plasma treatment can be performed after heat treatment.

[0375] Also, it is more preferable to perform the process for enhancing the crystallinity of the semiconductor film 230f a plurality of times. For example, when the semiconductor film 230f is formed by the ALD method, it is preferable to perform microwave plasma treatment every time one atomic layer is formed. Alternatively, performing a process for enhancing crystallinity every time a semiconductor film 230f having a film thickness within a predetermined range is formed can enhance productivity and is preferable. Specifically, it is preferable to form a first metal oxide film of 1 nm or more and 10 nm or less, perform a first microwave plasma treatment, then form a second metal oxide film of 1 nm or more and 10 nm or less, and perform a second microwave plasma treatment.

[0376] Also, the process of enhancing the crystallinity of the semiconductor film 230f may be performed after the formation of the semiconductor film 230f. Specifically, this process may be directly performed on the semiconductor film 230f after film formation, or may be performed through other films such as an insulating film formed on the semiconductor film 230f. For example, microwave plasma treatment is performed after the formation of the semiconductor film 230f, or after forming an insulating film (e.g., silicon nitride film, silicon oxide film, aluminum oxide film, etc.) on the semiconductor film 230f, heat treatment or microwave plasma treatment may be performed on the semiconductor film 230f through the insulating film.

[0377] The process of enhancing the crystallinity of the semiconductor film 230f can also serve as a process for removing impurities contained in the semiconductor film 230f. For example, carbon, hydrogen, nitrogen, etc. contained in the semiconductor film 230f can be preferably removed. Or, by performing the process of enhancing the crystallinity of the semiconductor film 230f in an oxygen gas atmosphere, oxygen vacancies in the semiconductor film 230f can be reduced.

[0378] In order to enhance the crystallinity of the semiconductor film 230f, it is preferable that at least a part of the semiconductor film 230f is located on the oxide film 245f. When performing the above cleaning process, by protecting the oxide film 245f with the mask layer 400, the oxide film 245f is not removed, so that the semiconductor film 230f can be formed on the oxide film 245f. Using the oxide film 245f as a seed or nucleus, the crystallinity of the semiconductor film 230f can be enhanced. By enhancing the crystallinity of the semiconductor film 230f, a transistor with good reliability can be realized.

[0379] Also, since the indium oxide film that can be used for the semiconductor film 230f is a film in which one or both of hydrogen and oxygen move easily, it can be said that excessive oxygen or excessive hydrogen that can become carriers or fixed charges in the semiconductor layer 230 is difficult to accumulate by performing heat treatment, so that a transistor with good electrical characteristics and reliability can be obtained.

[0380] Furthermore, it is preferable that the gas used in the above heat treatment is highly purified. By performing the heat treatment using a highly purified gas, it is possible to prevent moisture and other substances from being incorporated into the semiconductor film 230f as much as possible. Alternatively, impurities such as carbon and hydrogen can be reduced from the semiconductor film 230f, thereby increasing its purity.

[0381] The semiconductor film 230f can be formed, for example, by a sputtering method using a metal oxide target.

[0382] It is preferable that the semiconductor film 230f be a dense film with as few defects as possible. Furthermore, it is preferable that the semiconductor film 230f is a high-purity film with as few impurities as possible, such as hydrogen and water. In particular, it is preferable to use a crystalline semiconductor film 230f.

[0383] Furthermore, when depositing the semiconductor film 230f, oxygen gas may be mixed with an inert gas (for example, helium gas, argon gas, xenon gas, etc.). The higher the proportion of oxygen gas in the total deposition gas when depositing the semiconductor film 230f (hereinafter also referred to as the oxygen flow rate ratio), the higher the crystallinity of the semiconductor film 230f can be, and a highly reliable transistor can be realized. On the other hand, the lower the oxygen flow rate ratio, the lower the crystallinity of the semiconductor film 230f, and a transistor with a higher on-current can be made.

[0384] When forming a semiconductor film 230f, the higher the substrate temperature, the higher the crystallinity and the denser the semiconductor film 230f can be formed. On the other hand, the lower the substrate temperature, the lower the crystallinity and the higher the electrical conductivity of the semiconductor film 230f can be formed.

[0385] When using the ALD method, it is preferable to use a film deposition method such as the thermal ALD method or PEALD. The thermal ALD method is preferred because it exhibits extremely high step coverage. The PEALD method is also preferred because, in addition to exhibiting high step coverage, it allows for low-temperature film deposition.

[0386] In the ALD method, films of any composition can be deposited by using multiple different types of precursors. When multiple different types of precursors are introduced, films of any composition can be deposited by controlling the number of cycles for each precursor.

[0387] For example, when a metal oxide is used for the semiconductor film 230f, the film can be formed by the ALD method using a precursor containing the constituent metal elements and an oxidizing agent.

[0388] For example, when forming an In-Ga-Zn oxide film, three precursors—one containing indium, one containing gallium, and one containing zinc—can be used, along with ozone, oxygen, water, or other oxidizing agents. Alternatively, two precursors—one containing indium, and two containing gallium and zinc—can be used, along with ozone, oxygen, water, or other oxidizing agents.

[0389] For example, when forming an indium oxide film, an indium-containing precursor and oxidizing agents such as ozone, oxygen, or water can be used.

[0390] Indium-containing precursors that can be used include trimethylindium, triethylindium, ethyldimethylindium, tris(1-methylethyl)indium, tris(2,2,6,6-tetramethyl-3,5-heptanedionic acid)indium, cyclopentadienylindium, indium(III) acetylacetonate, (3-(dimethylamino)propyl)dimethylindium, (diethylphosphino)dimethylindium, chlorodimethylindium, bromodimethylindium, and dimethyl(2-propanolat)indium.

[0391] Furthermore, gallium-containing precursors such as trimethylgallium, triethylgallium, tris(dimethylamide)gallium(III), gallium(III) acetylacetonate, tris(2,2,6,6-tetramethyl-3,5-heptanedionic acid)gallium, dimethylchlorogallium, diethylchlorogallium, and gallium(III) chloride can be used.

[0392] Furthermore, zinc-containing precursors such as dimethylzinc, diethylzinc, bis(2,2,6,6-tetramethyl-3,5-heptanedionic acid) zinc, and zinc chloride can be used.

[0393] For example, ozone, oxygen, and water can be used as oxidizing agents.

[0394] Methods for controlling the composition of the resulting film include adjusting the flow rate ratio of the source gases, the duration of the source gas flow, and the order in which the source gases are flowed. By adjusting these factors, it is also possible to deposit films with continuously changing compositions. Furthermore, it becomes possible to deposit two or more films with different compositions in succession.

[0395] For example, indium oxide deposited by the ALD method used for semiconductor film 230f can be deposited using triethylindium (TEI) as an indium precursor and ozone and oxygen as oxidizing agents. In this case, it is preferable that the time for introducing the mixed gas of ozone and oxygen as oxidizing agents during one cycle is 9 seconds.

[0396] It is preferable to perform a heat treatment after the formation of the semiconductor film 230f. The heat treatment is preferably performed at a temperature of 250°C to 650°C, preferably 400°C to 600°C. The heat treatment is performed in an atmosphere of nitrogen gas or an inert gas, or in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, when performing the heat treatment in a mixed atmosphere of nitrogen gas and oxygen gas, the oxygen gas can be set to about 20%. The heat treatment may also be performed under reduced pressure. Alternatively, after heat treatment in an atmosphere of nitrogen gas or an inert gas, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to replenish the desorbed oxygen.

[0397] Furthermore, it is preferable that the gas used in the above heat treatment is highly purified. For example, the amount of water contained in the gas used in the above heat treatment can be 1 ppb or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less. By performing the heat treatment using a highly purified gas, it is possible to prevent as much as possible from the incorporation of water and other substances into the semiconductor film 230f, etc.

[0398] Although the drawing shows the semiconductor film 230f as a single layer, it may also be a multilayer structure. For example, it can be a two-layer structure formed by the ALD method, a three-layer structure formed by the ALD method, a two-layer structure in which the first layer is formed by the ALD method and the second layer by the sputtering method, or a three-layer structure in which the first layer is formed by the ALD method, the second layer by the sputtering method and the third layer by either the ALD method or the sputtering method. It is also possible to have a three-layer structure in which the first and second layers are formed by the ALD method and the third layer by the sputtering method. Forming the first layer by the ALD method is preferable because it can suppress mixing, but it can also be formed by the sputtering method. For example, it is possible to have a two-layer structure in which the first layer is formed by the sputtering method and the second layer by the ALD method. The semiconductor film 230f may also be a multilayer structure of four or more layers.

[0399] Next, as shown in Figures 19A to 19C, the semiconductor layer 230, oxide layer 245, conductive layer 240_2, and conductive layer 240_1 are formed by removing a portion of the semiconductor film 230f, oxide film 245f, conductive film 240_2f, and conductive film 240_1f. For example, a mask (not shown) is formed on the semiconductor film 230f, and the semiconductor film 230f, oxide film 245f, conductive film 240_2f, and conductive film 240_1f in the areas where the mask is not formed are removed by etching. It is preferable to use anisotropic dry etching for this etching process. After the etching process, the mask is removed. In Figures 19A to 19C, an example is shown in which the semiconductor film 230f, oxide film 245f, conductive film 240_2f, and conductive film 240_1f are etched using the same mask pattern. By forming the semiconductor film 230f, oxide film 245f, conductive film 240_2f, and conductive film 240_1f with the same mask pattern, the number of exposures can be reduced, improving productivity. On the other hand, the semiconductor film 230f, oxide film 245f, conductive film 240_2f, and conductive film 240_1f can also be etched with different mask patterns. In this case, the degree of freedom in layout design can be improved. Figures 19B and 19C show an example where the sides of the semiconductor layer 230, oxide layer 245, conductive film 240_2f, and conductive film 240_1f at the opening 290 are perpendicular to the surface to be formed. However, depending on the etching conditions, the sides of the semiconductor layer 230, oxide layer 245, conductive layer 240_2, and conductive layer 240_1 at the opening 290 may have a tapered shape that is inclined with respect to the surface to be formed.

[0400] Next, as shown in Figures 20A to 20C, an insulating layer 250 is formed to cover the semiconductor layer 230. Typically, the insulating layer 250 is preferably formed using the ALD method, which provides higher step coverage than other film deposition methods.

[0401] Next, a conductive film 260_1f, which will become the conductive layer 260_1, is formed on the insulating layer 250. A conductive film 260_2f, which will become the conductive layer 260_2, is formed on the conductive film 260_1f. The conductive films 260_1f and 260_2f are preferably formed using methods such as metal CVD, MOCVD, ALD, or sputtering. For example, titanium nitride deposited by metal CVD can be used as the conductive film 260_1f, and tungsten deposited by metal CVD can be used as the conductive film 260_2f.

[0402] Next, as shown in Figures 21A to 21C, it is preferable to use a dry etching method for processing the conductive films 260_1f and 260_2f. For example, a mask (not shown) is formed on the conductive film 260_2f in the region that will become the conductive layer 260_2, and the conductive films 260_2f and 260_1f in the regions where the mask is not formed are removed by etching. It is preferable to use anisotropic dry etching for this etching process. After the etching process, the mask is removed.

[0403] Next, an insulating layer 282 is formed on the insulating layer 250 and the conductive layer 260. The insulating layer 282 can be formed by a film deposition method such as sputtering, ALD, or CVD. For example, silicon nitride deposited by the ALD method can be used for the insulating layer 282. It is preferable to use an insulating film that has the function of capturing or fixing hydrogen, an insulating film that has the function of suppressing the permeation of impurities such as water and hydrogen and oxygen, an insulating film that has barrier properties against hydrogen, or an insulating film that has barrier properties against oxygen for the insulating layer 282.

[0404] Next, an insulating layer 283 is formed on the insulating layer 282. The insulating layer 283 is formed by a sputtering method, a CVD method, or an ALD method. For example, silicon nitride, silicon oxide, silicon oxynitride, silicon nitride oxide, etc. can be used for the insulating layer 283. For the insulating layer 283, for example, silicon oxide formed by a sputtering method can be used. The insulating layer 283 preferably uses a film formed by a sputtering method that does not contain hydrogen in the film-forming gas. After forming the insulating layer 283, the insulating layer 283 is planarized by performing a planarization process. As the planarization process, for example, a CMP method can be used.

[0405] Through the above steps, the semiconductor device illustrated in FIGS. 1A to 1C can be manufactured. By using such a manufacturing method, a semiconductor device with a large on-current can be provided. Or, a semiconductor device with good electrical characteristics can be provided. Or, a highly reliable semiconductor device can be provided. Or, a semiconductor device capable of miniaturization or high integration can be provided. Or, a semiconductor device with low power consumption can be provided.

[0406] This embodiment can be appropriately combined with other embodiments. Also, in this specification, when a plurality of configuration examples are shown in one embodiment, the configuration examples can be appropriately combined.

[0407] (Embodiment 2) In this embodiment, a semiconductor device 900 according to an aspect of the present invention will be described. The semiconductor device 900 can function as a storage device.

[0408] FIG. 22 shows a block diagram showing a configuration example of the semiconductor device 900. The semiconductor device 900 shown in FIG. 22 includes a drive circuit 910 and a memory array 920. The memory array 920 includes one or more memory cells 950. FIG. 22 shows an example in which the memory array 920 has a plurality of memory cells 950 arranged in a matrix.

[0409] A storage device (such as the memory cell 150) can be applied to the memory cell 950.

[0410] The drive circuit 910 includes a PSW 931 (power switch), a PSW 932, and a peripheral circuit 915. The peripheral circuit 915 includes a peripheral circuit 911, a control circuit 912, and a voltage generation circuit 928.

[0411] In the semiconductor device 900, each circuit, each signal, and each voltage can be appropriately selected or omitted as needed. Alternatively, other circuits or other signals may be added. Signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are external input signals, and signal RDA is an external output signal. Signal CLK is a clock signal.

[0412] Furthermore, signals BW, CE, and GW are control signals. Signal CE is the chip enable signal, signal GW is the global write enable signal, and signal BW is the byte write enable signal. Signal ADDR is the address signal. Signal WDA is the write data signal, and signal RDA is the read data signal. Signals PON1 and PON2 are power gating control signals. Signals PON1 and PON2 may be generated by the control circuit 912.

[0413] The control circuit 912 is a logic circuit that has the function of controlling the overall operation of the semiconductor device 900. For example, the control circuit 912 performs logical operations on signals CE, GW, and BW to determine the operating mode of the semiconductor device 900 (e.g., write operation, read operation). Alternatively, the control circuit 912 generates control signals for the peripheral circuit 911 so that this operating mode is executed.

[0414] The voltage generation circuit 928 has the function of generating a negative voltage. The signal WAKE has the function of controlling the input of the signal CLK to the voltage generation circuit 928. For example, when a high-level signal is given as the signal WAKE, the signal CLK is input to the voltage generation circuit 928, and the voltage generation circuit 928 generates a negative voltage.

[0415] The peripheral circuit 911 is a circuit for writing and reading data to and from the memory cell 950. The peripheral circuit 911 includes a row decoder 941, a column decoder 942, a row driver 923, a column driver 924, an input circuit 925, an output circuit 926, and a sense amplifier 927.

[0416] The row decoder 941 and column decoder 942 have the function of decoding the ADDR signal. The row decoder 941 is a circuit for specifying the row to access, and the column decoder 942 is a circuit for specifying the column to access. The row driver 923 has the function of selecting the row specified by the row decoder 941. The column driver 924 has the function of writing data to the memory cell 950, reading data from the memory cell 950, and holding the read data.

[0417] The input circuit 925 has the function of holding the signal WDA. The data held by the input circuit 925 is output to the column driver 924. The output data of the input circuit 925 is the data (Din) to be written to the memory cell 950. The data (Dout) read by the column driver 924 from the memory cell 950 is output to the output circuit 926. The output circuit 926 has the function of holding Dout. The output circuit 926 also has the function of outputting Dout to the outside of the semiconductor device 900. The data output from the output circuit 926 is the signal RDA.

[0418] PSW931 provides V to peripheral circuit 915 ＤＤ It has the function of controlling the supply. PSW932 has the function of V to line driver 923 ＨＭ It has a function to control the supply. Here, the high power supply potential of the semiconductor device 900 is V ＤＤ Therefore, the low power supply potential is GND (ground potential). Also, V ＨＭ This is a high power supply potential used to raise the word line to a high level, V ＤＤ It is higher than that. The on / off state of PSW931 is controlled by signal PON1, and the on / off state of PSW932 is controlled by signal PON2. In Figure 22, in peripheral circuit 915, V ＤＤThe number of power domains supplied is set to one, but it can be multiple. In this case, a power switch should be provided for each power domain.

[0419] Using Figures 23A to 23H, other examples of memory cell configurations applicable to the memory cell 950 will be described.

[0420] In the following, when two components are described as being connected, this includes being connected via a circuit element (such as a transistor, switch, diode, or resistor). An electrical connection means that an electric current can flow between two components. Furthermore, when two components are connected via a switch or transistor, an electric current can flow when these are in the ON state, and therefore this is also considered an electrical connection.

[0421] [DOSRAM] Figure 23A shows an example of the circuit configuration of a memory cell of a DRAM (Dynamic Random Access Memory). In this specification and elsewhere, a DRAM using an OS transistor is called a DOSRAM (Dynamic Oxide Semiconductor Random Access Memory). The memory cell 951 has a transistor M1 and a capacitive element CA.

[0422] Transistor M1 may have a front gate (sometimes simply called a gate) and a back gate. In this case, the back gate may be connected to a wire to which a constant potential or signal is supplied, or the front gate and back gate may be connected.

[0423] The first terminal of transistor M1 is connected to the first terminal of capacitive element CA, the second terminal of transistor M1 is connected to wiring BIL, and the gate of transistor M1 is connected to wiring WOL. The second terminal of capacitive element CA is connected to wiring CAL.

[0424] Wiring BIL functions as a bit line, and wiring WOL functions as a word line. Wiring CAL functions as wiring for applying a predetermined potential to the second terminal of the capacitive element CA. When writing and reading data, it is preferable to apply a low-level potential (sometimes called a reference potential) to wiring CAL.

[0425] Data writing and reading are performed by applying a high-level potential to the wiring WOL, turning on transistor M1, and creating a conductive state (a state in which current can flow) between the wiring BIL and the first terminal of the capacitive element CA.

[0426] Furthermore, the memory cells that can be used in memory cell 950 are not limited to memory cell 951, and the circuit configuration can be changed. For example, a configuration in which one wiring BIL is provided in common for two or more memory cells may be used. Alternatively, for example, the configuration of memory cell 952 as shown in Figure 23B may be used. Memory cell 952 is an example in which there is no capacitive element CA and wiring CAL. The first terminal of transistor M1 is electrically floating.

[0427] In the memory cell 952, the potential written via transistor M1 is held in the capacitance (also called parasitic capacitance) between the first terminal and the gate, indicated by the dashed line. This configuration significantly simplifies the structure of the memory cell.

[0428] Furthermore, it is preferable to use an OS transistor as transistor M1. OS transistors have the characteristic of having an extremely low off-current. By using an OS transistor as transistor M1, the leakage current of transistor M1 can be made very small. In other words, the written data can be held by transistor M1 for a long time, so the frequency of memory cell refresh can be reduced. Alternatively, the refresh operation of the memory cell can be made unnecessary. In addition, because the leakage current is very small, multi-level data or analog data can be held in memory cells 951 and 952.

[0429] In particular, it is preferable to use the OS transistor described in Embodiment 1 as transistor M1. The OS transistor has the characteristic of having a high on-current. By using the OS transistor as transistor M1, the processing speed of transistor M1 can be improved, and thus a memory device with a high operating speed can be provided.

[0430] [NOSRAM] Figure 23C shows an example of a circuit configuration for a gain cell type memory cell with two transistors and one capacitance element. The memory cell 953 has a transistor M2, a transistor M3, and a capacitance element CB. In this specification and elsewhere, a memory device having a gain cell type memory cell using an OS transistor for transistor M2 is called NOSRAM (Nonvolatil Oxide Semiconductor RAM).

[0431] The first terminal of transistor M2 is connected to the first terminal of capacitive element CB, the second terminal of transistor M2 is connected to wiring WBL, and the gate of transistor M2 is connected to wiring WOL. The second terminal of capacitive element CB is connected to wiring CAL. The first terminal of transistor M3 is connected to wiring RBL, the second terminal of transistor M3 is connected to wiring SL, and the gate of transistor M3 is connected to the first terminal of capacitive element CB.

[0432] Wiring WBL functions as a write bit line, wiring RBL functions as a read bit line, and wiring WOL functions as a word line. Wiring CAL functions as wiring for applying a predetermined potential to the second terminal of the capacitive element CB. When writing data, during data retention, and when reading data, it is preferable to apply a low-level potential (sometimes called a reference potential) to wiring CAL.

[0433] Data writing is performed by applying a high-level potential to the wiring WOL, turning on transistor M2, and creating a conductive state between the wiring WBL and the first terminal of the capacitive element CB. Specifically, when transistor M2 is ON, a potential corresponding to the information to be recorded in the wiring WBL is applied, and this potential is written to the first terminal of the capacitive element CB and the gate of transistor M3. Subsequently, a low-level potential is applied to the wiring WOL, turning off transistor M2, thereby maintaining the potential of the first terminal of the capacitive element CB and the potential of the gate of transistor M3.

[0434] Data is read by applying a predetermined potential to the wiring SL. The current flowing between the source and drain of transistor M3, and the potential of the first terminal of transistor M3, are determined by the potential of the gate and the potential of the second terminal of transistor M3. Therefore, by reading the potential of the wiring RBL connected to the first terminal of transistor M3, the potential held at the first terminal of the capacitive element CB (or the gate of transistor M3) can be read. In other words, the information written to this memory cell can be read from the potential held at the first terminal of the capacitive element CB (or the gate of transistor M3).

[0435] Alternatively, for example, the wiring WBL and wiring RBL may be combined into a single wiring BIL. An example of the circuit configuration of such a memory cell is shown in Figure 23D. Memory cell 954 is configured such that the wiring WBL and wiring RBL of memory cell 953 are combined into a single wiring BIL, and the second terminal of transistor M2 and the first terminal of transistor M3 are connected to the wiring BIL. In other words, memory cell 954 is configured to operate with the write bit line and the read bit line as a single wiring BIL.

[0436] The memory cell 955 shown in Figure 23E is an example where the capacitive element CB and wiring CAL in memory cell 953 are omitted. Similarly, the memory cell 956 shown in Figure 23F is an example where the capacitive element CB and wiring CAL in memory cell 954 are omitted. By using such a configuration, the integration density of memory cells can be increased.

[0437] Furthermore, it is preferable to use an OS transistor for at least transistor M2. In particular, it is preferable to use OS transistors for transistors M2 and M3. By using an OS transistor as transistor M2, the written data can be held by transistor M2 for a long time, thereby reducing the frequency of memory cell refresh. Alternatively, it may be possible to eliminate the need for memory cell refresh operations. In addition, because the leakage current is very small, multi-level data or analog data can be held in memory cells 953 to 956.

[0438] In particular, it is preferable to use the OS transistors described in Embodiment 1 for transistors M2 and M3. Since the OS transistors have the characteristic of having a high on-current, the processing speed of transistor M2 can be improved, and a memory device with a high operating speed can be provided.

[0439] Memory cells 953 to 956, which use an OS transistor as transistor M2, represent one form of NOSRAM.

[0440] Furthermore, a Si transistor may be used as transistor M3. Si transistors can increase field-effect mobility and can also be made into p-channel transistors, thus increasing the flexibility of circuit design.

[0441] Figure 23G also shows a gain cell type memory cell 957 with three transistors and one capacitance element. The memory cell 957 has transistors M4 to M6 and a capacitance element CC.

[0442] The first terminal of transistor M4 is connected to the first terminal of capacitive element CC, the second terminal of transistor M4 is connected to wiring BIL, and the gate of transistor M4 is connected to wiring WOL. The second terminal of capacitive element CC is connected to the first terminal of transistor M5 and to wiring GNDL. The second terminal of transistor M5 is connected to the first terminal of transistor M6, and the gate of transistor M5 is connected to the first terminal of capacitive element CC. The second terminal of transistor M6 is connected to wiring BIL, and the gate of transistor M6 is connected to wiring RWL.

[0443] Wiring BIL functions as a bit line, wiring WOL functions as a write word line, and wiring RWL functions as a read word line. Wiring GNDL is a wire that provides a low level potential.

[0444] Data writing is performed by applying a high-level potential to the wiring WOL, turning on transistor M4, and creating a conductive state between the wiring BIL and the first terminal of the capacitive element CC. Specifically, when transistor M4 is ON, a potential corresponding to the information to be recorded in wiring BIL is applied, and this potential is written to the first terminal of the capacitive element CC and the gate of transistor M5. Subsequently, a low-level potential is applied to the wiring WOL, turning off transistor M4, thereby maintaining the potential of the first terminal of the capacitive element CC and the potential of the gate of transistor M5.

[0445] Data is read by precharging the wiring BIL to a predetermined potential, then electrically freezing the wiring BIL, and applying a high-level potential to the wiring RWL. As the wiring RWL reaches a high-level potential, transistor M6 turns ON, and the wiring BIL and the second terminal of transistor M5 become conductive. At this time, the potential of the wiring BIL is applied to the second terminal of transistor M5, but the potential of the second terminal of transistor M5 and the potential of the wiring BIL change depending on the potential held at the first terminal of the capacitive element CC (or the gate of transistor M5). By reading the potential of the wiring BIL, the potential held at the first terminal of the capacitive element CC (or the gate of transistor M5) can be read. In other words, the information written to this memory cell can be read from the potential held at the first terminal of the capacitive element CC (or the gate of transistor M5).

[0446] Furthermore, it is preferable to use an OS transistor for at least transistor M4.

[0447] Note that Si transistors may be used as transistors M5 and M6. As mentioned above, Si transistors may have higher field-effect mobility than OS transistors depending on the crystal state of the silicon used in the semiconductor layer.

[0448] [OS-SRAM] Figure 23H shows an example of SRAM (Static Random Access Memory) using an OS transistor. In this specification and elsewhere, SRAM using an OS transistor is called OS-SRAM (Oxide Semiconductor-SRAM). Note that the memory cell 958 shown in Figure 23H is a memory cell of a backup-capable SRAM.

[0449] The memory cell 958 includes transistors M7 to M10, transistors MS1 to MS4, and capacitive elements CD1 and CD2. Transistors MS1 and MS2 are p-channel transistors, while transistors MS3 and MS4 are n-channel transistors.

[0450] The first terminal of transistor M7 is connected to wiring BIL, and the second terminal of transistor M7 is connected to the first terminal of transistor MS1, the first terminal of transistor MS3, the gate of transistor MS2, the gate of transistor MS4, and the first terminal of transistor M10. The gate of transistor M7 is connected to wiring WOL. The first terminal of transistor M8 is connected to wiring BILB, and the second terminal of transistor M8 is connected to the first terminal of transistor MS2, the first terminal of transistor MS4, the gate of transistor MS1, the gate of transistor MS3, and the first terminal of transistor M9. The gate of transistor M8 is connected to wiring WOL.

[0451] The second terminal of transistor MS1 is connected to wiring VDL. The second terminal of transistor MS2 is connected to wiring VDL. The second terminal of transistor MS3 is connected to wiring GNDL. The second terminal of transistor MS4 is connected to wiring GNDL.

[0452] The second terminal of transistor M9 is connected to the first terminal of capacitive element CD1, and the gate of transistor M9 is connected to wiring BRL. The second terminal of transistor M10 is connected to the first terminal of capacitive element CD2, and the gate of transistor M10 is connected to wiring BRL.

[0453] The second terminal of capacitive element CD1 is connected to wiring GNDL, and the second terminal of capacitive element CD2 is connected to wiring GNDL.

[0454] Wires BIL and BILB function as bit lines, wire WOL functions as a word line, and wire BRL controls the on and off states of transistors M9 and M10.

[0455] Wiring VDL is a wiring that provides a high-level potential, and wiring GNDL is a wiring that provides a low-level potential.

[0456] Data is written by applying a high-level potential to the wiring WOL and also to the wiring BRL. Specifically, when transistor M10 is ON, a potential corresponding to the information to be recorded in wiring BIL is applied, and this potential is written to the second terminal side of transistor M10.

[0457] Incidentally, since the memory cell 958 is configured as an inverter loop by transistors MS1 to MS2, an inverted signal of the data signal corresponding to the potential is input to the second terminal side of transistor M8. Because transistor M8 is ON, the wiring BILB outputs an inverted signal of the potential applied to wiring BIL, i.e., the signal input to wiring BIL. Also, because transistors M9 and M10 are ON, the potential of the second terminal of transistor M7 and the potential of the second terminal of transistor M8 are held at the first terminal of capacitive element CD2 and the first terminal of capacitive element CD1, respectively. Subsequently, by applying a low-level potential to wiring WOL and wiring BRL, and turning off transistors M7 to M10, the potentials of the first terminal of capacitive element CD1 and the first terminal of capacitive element CD2 are maintained.

[0458] The data reading process is described below. First, wiring BIL and wiring BILB are precharged to a predetermined potential. Next, a high-level potential is applied to wiring WOL and wiring BRL. At this time, the potential of the first terminal of capacitive element CD1 is refreshed by the inverter loop of memory cell 958 and output to wiring BILB. Also, the potential of the first terminal of capacitive element CD2 is refreshed by the inverter loop of memory cell 958 and output to wiring BIL. In wiring BIL and wiring BILB, the potential changes from the precharged potential to the potential of the first terminal of capacitive element CD2 and the potential of the first terminal of capacitive element CD1, respectively. Therefore, the potential held in the memory cell can be read from the potential of wiring BIL or wiring BILB.

[0459] Furthermore, it is preferable to use OS transistors as transistors M7 to M10. This allows the written data to be retained for a long time by transistors M7 to M10, thereby reducing the frequency of memory cell refreshes. Alternatively, it may eliminate the need for memory cell refresh operations altogether. Or, it may provide a storage device with a high operating speed.

[0460] It is preferable to use the OS transistors described in Embodiment 1 as transistors M7 to M10. The OS transistors have the characteristic of having a high on-current. By using these OS transistors as transistors M7 to M10, the processing speed of transistors M7 to M10 can be improved, and thus a memory device with a high operating speed can be provided.

[0461] Furthermore, Si transistors may be used as transistors MS1 to MS4.

[0462] The drive circuit 910 and memory array 920 of the semiconductor device 900 may be provided on the same plane. Alternatively, as shown in Figure 24A, the drive circuit 910 and memory array 920 may be stacked on top of each other. By stacking the drive circuit 910 and memory array 920, the signal propagation distance can be shortened. Furthermore, as shown in Figure 24B, multiple memory arrays 920 may be stacked on top of the drive circuit 910.

[0463] Next, an example of a processing unit that can be equipped with the above-mentioned memory device and other semiconductor devices will be described.

[0464] Figure 25 shows a block diagram of the arithmetic unit 960. The arithmetic unit 960 shown in Figure 25 can be applied to a CPU, for example. The arithmetic unit 960 can also be applied to processors such as GPUs (Graphics Processing Units), TPUs (Tensor Processing Units), and NPUs (Neural Processing Units) that have a large number of processor cores (tens to hundreds) capable of parallel processing, more so than a CPU.

[0465] The arithmetic unit 960 shown in Figure 25 has an ALU 962 (ALU: Arithmetic logic unit, arithmetic circuit), an ALU controller 962c, an instruction decoder 963, an interrupt controller 964, a timing controller 965, a register 966, a register controller 967, a bus interface 968, a cache 969, and a cache interface 969i on a substrate 961. The substrate 961 can be a semiconductor substrate, an SOI substrate, a glass substrate, etc. It may also have a rewritable ROM and a ROM interface. In addition, the cache 969 and the cache interface 969i may be provided on a separate chip.

[0466] The cache 969 is connected to the main memory located on a separate chip via a cache interface 969i. The cache interface 969i has the function of supplying a portion of the data held in the main memory to the cache 969. The cache interface 969i also has the function of outputting a portion of the data held in the cache 969 to the ALU 962 or register 966, etc., via the bus interface 968.

[0467] As will be described later, a memory array 920 can be stacked on the arithmetic unit 960. The memory array 920 can be used as a cache. In this case, the cache interface 969i may have the function of supplying data held in the memory array 920 to the cache 969. In this case, it is preferable that a drive circuit 910 is included in part of the cache interface 969i.

[0468] Alternatively, the cache 969 can be omitted, and only the memory array 920 can be used as the cache.

[0469] The arithmetic unit 960 shown in Figure 25 is merely a simplified example of its configuration, and actual arithmetic units 960 have a wide variety of configurations depending on their application. For example, it is preferable to have a so-called multi-core configuration in which the configuration including the arithmetic unit 960 shown in Figure 25 is considered one core, and multiple such cores are included, with each core operating in parallel. The more cores there are, the higher the computational performance can be. While a larger number of cores is preferable, it is preferable to have, for example, two, preferably four, more preferably eight, even more preferably twelve, and even more preferably sixteen or more cores. Furthermore, in cases where very high computational performance is required, such as for server applications, it is preferable to have a multi-core configuration with 16 or more, preferably 32 or more, and even more preferably 64 or more cores. In addition, the number of bits that the arithmetic unit 960 can handle in its internal arithmetic circuitry, data bus, etc., can be, for example, 8 bits, 16 bits, 32 bits, 64 bits, etc.

[0470] Instructions input to the arithmetic unit 960 via the bus interface 968 are input to the instruction decoder 963, decoded, and then input to the ALU controller 962c, interrupt controller 964, register controller 967, and timing controller 965.

[0471] The ALU controller 962c, interrupt controller 964, register controller 967, and timing controller 965 perform various controls based on the decoded instructions. Specifically, the ALU controller 962c generates signals to control the operation of the ALU 962. The interrupt controller 964 processes interrupt requests from external input / output devices and peripheral circuits during program execution of the arithmetic unit 960, based on their priority, mask status, etc. The register controller 967 generates the address of register 966 and reads and writes to register 966 according to the state of the arithmetic unit 960.

[0472] Furthermore, the timing controller 965 generates signals that control the timing of the operation of the ALU 962, ALU controller 962c, instruction decoder 963, interrupt controller 964, and register controller 967. For example, the timing controller 965 includes an internal clock generation unit that generates an internal clock signal based on a reference clock signal, and supplies the internal clock signal to the various circuits mentioned above.

[0473] In the arithmetic unit 960 shown in Figure 25, the register controller 967 selects a data retention operation in register 966 according to instructions from ALU 962. That is, it selects whether to retain data in the memory cell of register 966 using a flip-flop or using a capacitive element. If data retention using a flip-flop is selected, power potential is supplied to the memory cell in register 966. If data retention using a capacitive element is selected, data is rewritten to the capacitive element, and the supply of power potential to the memory cell in register 966 can be stopped.

[0474] The memory array 920 and the arithmetic unit 960 can be mounted on top of each other. Figures 26A and 26B show perspective views of the semiconductor device 970A. The semiconductor device 970A has a layer 930 on which memory arrays are provided on the arithmetic unit 960. The layer 930 is provided with memory arrays 920L1, 920L2, and 920L3. The arithmetic unit 960 and each memory array have overlapping regions. To make the configuration of the semiconductor device 970A easier to understand, Figure 26B shows the arithmetic unit 960 and layer 930 separately.

[0475] By stacking the layer 930 containing the memory array and the arithmetic unit 960, the connection distance between them can be shortened. Therefore, the communication speed between them can be increased. In addition, power consumption can be reduced due to the short connection distance.

[0476] As a method for stacking the layer 930 having the memory array and the arithmetic unit 960, one may use a method in which the layer 930 having the memory array is directly stacked on the arithmetic unit 960 (also called monolithic stacking), or one may use a method in which the arithmetic unit 960 and the layer 930 are formed on different substrates, the two substrates are bonded together, and they are connected using through-via or conductive film bonding technology (such as Cu-Cu bonding). The former does not require consideration of positional misalignment during bonding, so not only can the chip size be reduced, but manufacturing costs can also be reduced.

[0477] Here, the arithmetic unit 960 does not have a cache 969, and the memory arrays 920L1, 920L2, and 920L3 provided in layer 930 can each be used as caches. In this case, for example, memory array 920L1 can be used as an L1 cache (also called a level 1 cache), memory array 920L2 can be used as an L2 cache (also called a level 2 cache), and memory array 920L3 can be used as an L3 cache (also called a level 3 cache). Of the three memory arrays, memory array 920L3 has the largest capacity and the lowest access frequency. Also, memory array 920L1 has the smallest capacity and the highest access frequency.

[0478] Furthermore, when the cache 969 provided in the arithmetic unit 960 is used as the L1 cache, each memory array provided in layer 930 can be used as a lower-level cache or main memory, respectively. Main memory has a larger capacity than cache and is accessed less frequently.

[0479] Furthermore, as shown in Figure 26B, drive circuits 910L1, 910L2, and 910L3 are provided. Drive circuit 910L1 is connected to memory array 920L1 via connecting electrode 940L1. Similarly, drive circuit 910L2 is connected to memory array 920L2 via connecting electrode 940L2, and drive circuit 910L3 is connected to memory array 920L3 via connecting electrode 940L3.

[0480] Note that while this example shows three memory arrays functioning as a cache, it is also possible to use one or two, or even four or more.

[0481] When the memory array 920L1 is used as a cache, the drive circuit 910L1 may function as part of the cache interface 969i, or the drive circuit 910L1 may be configured to be connected to the cache interface 969i. Similarly, the drive circuits 910L2 and 910L3 may also function as part of the cache interface 969i, or be configured to be connected to it.

[0482] Whether the memory array 920 functions as a cache or as main memory is determined by the control circuit 912 of each drive circuit 910. Based on signals supplied from the arithmetic unit 960, the control circuit 912 can make some of the multiple memory cells 950 of the semiconductor device 900 function as RAM.

[0483] The semiconductor device 900 can have some of its multiple memory cells 950 function as a cache and the other part function as main memory. In other words, the semiconductor device 900 can have both cache and main memory functions. A semiconductor device 900 according to one aspect of the present invention can function as a universal memory, for example.

[0484] Alternatively, a layer 930 having a single memory array 920 may be superimposed on the arithmetic unit 960. Figure 27A shows a perspective view of the semiconductor device 970B.

[0485] In the semiconductor device 970B, a single memory array 920 can be divided into multiple areas, each used for a different function. Figure 27A shows an example where area L1 is used as the L1 cache, area L2 as the L2 cache, and area L3 as the L3 cache.

[0486] Furthermore, in the semiconductor device 970B, the capacities of each of the regions L1 to L3 can be changed according to the situation. For example, if it is desired to increase the capacity of the L1 cache, this can be achieved by increasing the area of ​​region L1. By adopting such a configuration, the efficiency of arithmetic processing can be improved, and the processing speed can be increased.

[0487] Furthermore, multiple memory arrays may be stacked. Figure 27B shows a perspective view of the semiconductor device 970C.

[0488] The semiconductor device 970C has a layer 930L1 with a memory array 920L1, a layer 930L2 with a memory array 920L2 on top of it, and a layer 930L3 with a memory array 920L3 on top of that. The memory array 920L1, which is physically closest to the arithmetic unit 960, can be used as the upper cache, and the memory array 920L3, which is furthest away, can be used as the lower cache or main memory. By using this configuration, the capacity of each memory array can be increased, thereby improving processing power.

[0489] This embodiment can be combined with other embodiments as appropriate. Furthermore, if multiple configuration examples are shown within a single embodiment in this specification, these configuration examples can be combined as appropriate.

[0490] (Embodiment 3) In this embodiment, an application example of a semiconductor device according to one aspect of the present invention will be described with reference to Figures 28A to 29E.

[0491] A semiconductor device according to one aspect of the present invention can be used, for example, in electronic components, large computers, space equipment, data centers (also referred to as DCs), and various electronic devices. By using a semiconductor device according to one aspect of the present invention, lower power consumption and higher performance can be achieved in electronic components, large computers, space equipment, data centers, and various electronic devices.

[0492] Furthermore, a display device having a semiconductor device according to one aspect of the present invention can be used in the display units of various electronic devices. A display device having a semiconductor device according to one aspect of the present invention can be easily made higher resolution and higher definition.

[0493] Examples of electronic devices include television sets, desktop or laptop computers, computer monitors, digital signage, and large game machines such as pachinko machines, as well as other electronic devices with relatively large screens, digital cameras, digital video cameras, digital photo frames, mobile phones, portable game consoles, personal digital assistants, and audio playback devices.

[0494] In particular, a display device according to one aspect of the present invention can be used suitably in electronic devices having a relatively small display area because it can increase the resolution. Examples of such electronic devices include wristwatch-type and bracelet-type information terminals (wearable devices), as well as wearable devices that can be worn on the head, such as VR devices such as head-mounted displays, AR devices such as glasses, and mixed reality (MR) devices.

[0495] A display device according to one aspect of the present invention preferably has an extremely high resolution such as HD (1280 x 720 pixels), FHD (1920 x 1080 pixels), WQHD (2560 x 1440 pixels), WQXGA (2560 x 1600 pixels), 4K (3840 x 2160 pixels), or 8K (7680 x 4320 pixels). In particular, a resolution of 4K, 8K, or higher is preferred. Furthermore, the pixel density (detail) of the display device according to one aspect of the present invention is preferably 100 ppi or more, 300 ppi or more, 500 ppi or more, 1000 ppi or more, 2000 ppi or more, 3000 ppi or more, 5000 ppi or more, or 7000 ppi or more. By using a display device having one or both of these high resolutions and high detail, it is possible to further enhance the sense of presence and depth. Furthermore, there are no particular limitations on the aspect ratio of the display device according to one embodiment of the present invention. For example, the display device can support various aspect ratios such as 1:1 (square), 4:3, 16:9, or 16:10.

[0496] The electronic device of this embodiment may have sensors (including those with the function of detecting, detecting, or measuring force, displacement, position, velocity, acceleration, angular velocity, rotational speed, distance, light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared radiation).

[0497] The electronic device of this embodiment can have a variety of functions. For example, it can have a function to display various information (still images, videos, or text images, etc.) on the display unit, a touch panel function, a function to display a calendar, date or time, a function to execute various software (programs), a wireless communication function, a function to read programs or data recorded on a recording medium, and so on.

[0498] [Electronic Components] Figure 28A shows a perspective view of a substrate (mounted substrate 989) on which electronic components 980 are mounted. The electronic component 980 shown in Figure 28A has a semiconductor device 981 inside a mold 984. Some details are omitted in Figure 28A to show the inside of the electronic component 980. The electronic component 980 has a land 985 on the outside of the mold 984. The land 985 is connected to an electrode pad 986, and the electrode pad 986 is connected to the semiconductor device 981 via a wire 987. The electronic component 980 is mounted on a printed circuit board 988, for example. Multiple such electronic components are combined and connected on the printed circuit board 988 to complete the mounted substrate 989.

[0499] Furthermore, the semiconductor device 981 has a drive circuit layer 982 and a storage layer 983. The storage layer 983 has a configuration in which multiple memory cell arrays are stacked. The configuration in which the drive circuit layer 982 and the storage layer 983 are stacked can be a monolithic stack configuration. In a monolithic stack configuration, the layers can be connected without using through-electrode technologies such as TSV (Through Silicon Via) and bonding technologies such as Cu-Cu direct bonding. By monolithically stacking the drive circuit layer 982 and the storage layer 983, for example, a so-called on-chip memory configuration can be achieved in which memory is directly formed on the processor. By using an on-chip memory configuration, it is possible to speed up the operation of the interface portion between the processor and the memory.

[0500] Furthermore, by using an on-chip memory configuration, the size of connection wiring can be reduced compared to technologies using through-hole electrodes such as TSVs, making it possible to increase the number of connection pins. Increasing the number of connection pins enables parallel operation, which in turn improves the memory bandwidth (also called memory bandwidth).

[0501] Furthermore, it is preferable to form the multiple memory cell arrays of the memory layer 983 using OS transistors and to stack these multiple memory cell arrays monolithically. By configuring the multiple memory cell arrays in a monolithic stack, it is possible to improve either or both of the memory bandwidth and / or memory access latency. Bandwidth is the amount of data transferred per unit time, and access latency is the time from access to the start of data exchange. In the case of a configuration using Si transistors in the memory layer 983, it is difficult to create a monolithic stack configuration compared to OS transistors. Therefore, in a monolithic stack configuration, OS transistors can be said to have a superior structure compared to Si transistors.

[0502] The semiconductor device 981 may also be referred to as a die. In this specification, a die refers to a chip piece obtained in the semiconductor chip manufacturing process by forming a circuit pattern on, for example, a disc-shaped substrate (also called a wafer) and cutting it into cubes. Examples of semiconductor materials that can be used for dies include silicon (Si), silicon carbide (SiC), or gallium nitride (GaN). For example, a die obtained from a silicon substrate (also called a silicon wafer) is sometimes called a silicon die.

[0503] Next, a perspective view of the electronic component 990 is shown in Figure 28B. The electronic component 990 is an example of a SiP (System in Package) or MCM (Multi-Chip Module). The electronic component 990 has an interposer 991 provided on a package substrate 992 (printed circuit board), and a semiconductor device 994 and a plurality of semiconductor devices 981 are provided on the interposer 991.

[0504] Electronic component 990 shows an example where semiconductor device 981 is used as a high-bandwidth memory (HBM). Furthermore, semiconductor device 994 can be used in integrated circuits such as CPUs, GPUs, or FPGAs (Field Programmable Gate Arrays).

[0505] The package substrate 992 can be, for example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate. The interposer 991 can be, for example, a silicon interposer or a resin interposer.

[0506] The interposer 991 has multiple wirings and functions to connect multiple integrated circuits with different terminal pitches. The multiple wirings are provided in a single layer or multiple layers. The interposer 991 also has the function of connecting integrated circuits provided on the interposer 991 to electrodes provided on the package substrate 992. For these reasons, the interposer is sometimes called a "redistribution substrate" or "intermediate substrate". In addition, through electrodes may be provided on the interposer 991, and these through electrodes may be used to connect the integrated circuits and the package substrate 992. Furthermore, in silicon interposers, TSVs can also be used as through electrodes.

[0507] In HBMs, many connections are necessary to achieve a wide memory bandwidth. Therefore, the interposer on which the HBM is mounted requires fine and high-density wiring. For this reason, it is preferable to use a silicon interposer for mounting the HBM.

[0508] Furthermore, in SiP and MCM using silicon interposers, reliability degradation due to differences in expansion coefficients between the integrated circuit and the interposer is less likely to occur. In addition, because silicon interposers have high surface flatness, connection failures between the integrated circuit and the silicon interposer are less likely to occur. In particular, in 2.5D packages (2.5-dimensional packaging) where multiple integrated circuits are arranged side by side on the interposer, it is preferable to use a silicon interposer.

[0509] On the other hand, when connecting multiple integrated circuits with different terminal pitches using silicon interposers and TSVs, space is required, such as the width of the terminal pitch. Therefore, when attempting to reduce the size of the electronic component 990, the width of the terminal pitch becomes a problem, and it may become difficult to provide the many wires necessary to achieve a wide memory bandwidth. For this reason, as mentioned above, a monolithic stacked configuration using OS transistors is preferable. A composite structure combining a memory cell array stacked using TSVs and a monolithic stacked memory cell array may also be used.

[0510] Alternatively, a heat sink (heat dissipation plate) may be provided on top of the electronic component 990. If a heat sink is provided, it is preferable to align the heights of the integrated circuits provided on the interposer 991. For example, in the electronic component 990 shown in this embodiment, it is preferable to align the heights of the semiconductor device 981 and the semiconductor device 994.

[0511] To mount the electronic component 990 onto another substrate, electrodes 993 may be provided at the bottom of the package substrate 992. Figure 28B shows an example in which the electrodes 993 are formed with solder balls. By providing solder balls in a matrix at the bottom of the package substrate 992, BGA (Ball Grid Array) mounting can be achieved. Alternatively, the electrodes 993 may be formed with conductive pins. By providing conductive pins in a matrix at the bottom of the package substrate 992, PGA (Pin Grid Array) mounting can be achieved.

[0512] The electronic component 990 can be mounted on other boards using various mounting methods, not limited to BGA and PGA. Examples of mounting methods include SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ (Quad Flat J-leaded package), and QFN (Quad Flat Non-leaded package).

[0513] [Large-scale computer] Next, a perspective view of the large-scale computer 5600 is shown in Figure 29A. The large-scale computer 5600 shown in Figure 29A has multiple rack-mount type computers 5620 housed in rack 5610. The large-scale computer 5600 may also be called a supercomputer.

[0514] The computer 5620 can have the configuration shown in the perspective view in Figure 29B, for example. In Figure 29B, the computer 5620 has a motherboard 5630, which has multiple slots 5631 and multiple connection terminals. A PC card 5621 is inserted into a slot 5631. In addition, the PC card 5621 has connection terminals 5623, 5624, and 5625, which are each connected to the motherboard 5630.

[0515] The PC card 5621 shown in Figure 29C is an example of a processing board equipped with a CPU, GPU, storage device, etc. The PC card 5621 has a board 5622. The board 5622 also has connection terminals 5623, 5624, 5625, semiconductor device 5626, semiconductor device 5627, semiconductor device 5628, and connection terminal 5629. Although Figure 29C shows semiconductor devices other than semiconductor devices 5626, 5627, and 5628, you can refer to the descriptions of semiconductor devices 5626, 5627, and 5628 below for details on these semiconductor devices.

[0516] The connector 5629 has a shape that allows it to be inserted into the slot 5631 of the motherboard 5630, and functions as an interface for connecting the PC card 5621 and the motherboard 5630. Examples of standards for the connector 5629 include PCIe.

[0517] Terminals 5623, 5624, and 5625 can serve as interfaces for, for example, power supply and signal input to the PC card 5621. They can also serve as interfaces for, for example, outputting signals calculated by the PC card 5621. Examples of standards for terminals 5623, 5624, and 5625 include USB (Universal Serial Bus), SATA (Serial ATA), and SCSI (Small Computer System Interface). When outputting video signals from terminals 5623, 5624, and 5625, examples of standards include HDMI (registered trademark).

[0518] The semiconductor device 5626 has terminals (not shown) for inputting and outputting signals, and the semiconductor device 5626 and the board 5622 can be connected by inserting these terminals into sockets (not shown) provided on the board 5622.

[0519] The semiconductor device 5627 has multiple terminals, and the semiconductor device 5627 and the board 5622 can be connected by soldering these terminals to the wiring provided on the board 5622, for example, using a reflow soldering method. Examples of semiconductor devices 5627 include FPGAs, GPUs, and CPUs. For example, an electronic component 990 can be used as the semiconductor device 5627.

[0520] The semiconductor device 5628 has multiple terminals, and the semiconductor device 5628 and the board 5622 can be connected by soldering these terminals to the wiring provided on the board 5622, for example, using a reflow soldering method. Examples of the semiconductor device 5628 include a memory device. For example, an electronic component 990 can be used as the semiconductor device 5628.

[0521] The 5600 mainframe computer can also function as a parallel computer. By using the 5600 mainframe computer as a parallel computer, it is possible to perform large-scale calculations necessary for, for example, artificial intelligence training and inference.

[0522] [Space Equipment] A semiconductor device according to one aspect of the present invention can be suitably used in space equipment.

[0523] One embodiment of the present invention includes an OS transistor. Compared to Si transistors, OS transistors exhibit smaller fluctuations in electrical properties due to radiation exposure. In other words, they have high resistance to radiation, making them highly reliable and suitable for use in environments where radiation may be incident. For example, OS transistors are suitable for use in outer space. Specifically, OS transistors can be used as transistors constituting semiconductor devices installed in space shuttles, artificial satellites, or space probes. Examples of radiation include X-rays and neutrons. Outer space refers, for example, to an altitude of 100 km or higher, but outer space as described herein may include one or more of the thermosphere, mesosphere, and stratosphere.

[0524] Figure 29D shows an example of space equipment, specifically a satellite 6800. The satellite 6800 comprises a body 6801, a solar panel 6802, an antenna 6803, a secondary battery 6805, and a control device 6807. In Figure 29D, a planet 6804 is shown as an example in outer space.

[0525] Furthermore, although not shown in Figure 29D, a battery management system (also known as a BMS) or a battery control circuit may be provided with the secondary battery 6805. Using an OS transistor in the aforementioned battery management system or battery control circuit is preferable because it consumes little power and has high reliability even in outer space.

[0526] Furthermore, outer space is an environment with radiation levels more than 100 times higher than those on Earth. Examples of radiation include electromagnetic waves (electromagnetic radiation) such as X-rays and gamma rays, as well as particle radiation such as alpha rays, beta rays, neutron rays, proton rays, heavy ion rays, and meson rays.

[0527] When sunlight shines on the solar panel 6802, the power necessary for the satellite 6800 to operate is generated. However, if, for example, the solar panel is not exposed to sunlight, or if the amount of sunlight hitting the solar panel is low, the amount of power generated will decrease. Therefore, there is a possibility that the power necessary for the satellite 6800 to operate may not be generated. To operate the satellite 6800 even under conditions of low power generation, it is advisable to equip the satellite 6800 with a secondary battery 6805. Note that solar panels are sometimes called solar cell modules.

[0528] The satellite 6800 can generate a signal. This signal is transmitted via antenna 6803, and can be received by, for example, a receiver on the ground or another satellite. By receiving the signal transmitted by satellite 6800, the position of the receiver that received the signal can be measured. Thus, satellite 6800 can constitute a satellite positioning system.

[0529] Furthermore, the control device 6807 has the function of controlling the artificial satellite 6800. The control device 6807 is configured using, for example, one or more selected from a CPU, a GPU, and a memory device. It is preferable to use a semiconductor device including an OS transistor, which is one embodiment of the present invention, for the control device 6807.

[0530] Furthermore, the satellite 6800 can be configured to include sensors. For example, by configuring it to include a visible light sensor, the satellite 6800 can have the function of detecting sunlight reflected off objects on the ground. Alternatively, by configuring it to include a thermal infrared sensor, the satellite 6800 can have the function of detecting thermal infrared radiation emitted from the Earth's surface. Thus, the satellite 6800 can function, for example, as an Earth observation satellite.

[0531] In this embodiment, an artificial satellite was used as an example of space equipment, but the invention is not limited to this. For example, a semiconductor device according to one aspect of the present invention can be suitably used in space equipment such as spacecraft, space capsules, and space probes.

[0532] This embodiment can be combined with other embodiments as appropriate. Furthermore, if multiple configuration examples are shown within a single embodiment in this specification, these configuration examples can be combined as appropriate.

[0533] As explained above, OS transistors have superior advantages compared to Si transistors, such as the ability to achieve a wider memory bandwidth and higher radiation resistance.

[0534] [Data Center] One embodiment of the present invention is suitably used in storage systems applied to data centers, for example. Data centers are required to manage data over the long term, such as by ensuring the immutability of the data. Managing data over the long term requires the installation of storage and servers to store vast amounts of data, securing a stable power supply to hold the data, or securing cooling equipment required for data storage, which necessitates the construction of larger buildings.

[0535] By using a semiconductor device according to one aspect of the present invention in a storage system applied to a data center, it is possible to reduce the power required for data retention and miniaturize the semiconductor device that holds the data. Therefore, it is possible to miniaturize the storage system, the power supply for data retention, and the cooling equipment. This, in turn, contributes to space savings in the data center.

[0536] Furthermore, because the semiconductor device according to one aspect of the present invention has low power consumption, heat generation from the circuit can be reduced. Therefore, adverse effects on the circuit itself, peripheral circuits, and modules due to such heat generation can be reduced. In addition, by using the semiconductor device according to one aspect of the present invention, a data center that operates stably even in high-temperature environments can be realized. Therefore, the reliability of the data center can be improved.

[0537] Figure 29E shows a storage system applicable to a data center. The storage system 7010 shown in Figure 29E has multiple servers 7001sb as hosts 7001 (indicated as Host Computer) and multiple storage devices 7003md as storage 7003 (indicated as Storage). The host 7001 and storage 7003 are connected via a storage area network 7004 (SAN: Storage Area Network) and a storage control circuit 7002 (indicated as Storage Controller).

[0538] Host 7001 corresponds to a computer that accesses data stored in storage 7003. The hosts 7001 may be connected to each other via a network.

[0539] Although storage 7003 uses flash memory to shorten data access speed, that is, the time required for data storage and retrieval, this time is significantly longer than the time required for DRAM, which can be used as cache memory within the storage. In storage systems, cache memory is usually provided within the storage to shorten the time required for data storage and retrieval in order to solve the problem of the long access speed of storage 7003.

[0540] The aforementioned cache memory is used within the storage control circuit 7002 and storage 7003. Data exchanged between the host 7001 and storage 7003 is stored in the cache memory within the storage control circuit 7002 and storage 7003, and then output to the host 7001 or storage 7003.

[0541] By using OS transistors as the transistors for storing the aforementioned cache memory data, and configuring them to maintain a potential corresponding to the data, the frequency of refresh can be reduced, thereby lowering power consumption. Furthermore, miniaturization is possible by stacking the memory cell arrays.

[0542] In this example, a sample containing an indium oxide film was prepared, and its cross-sectional observation and electrical properties were evaluated.

[0543] A transistor 200A with the configuration shown in Figure 1 was fabricated using the process shown in Figures 13 to 21.

[0544] First, an insulating layer 210, with a silicon nitride film having a thickness of 60 nm on the top surface, was deposited on a substrate (not shown). Next, a conductive film to become conductive layer 220_1 and a conductive film to become conductive layer 220_2 were deposited sequentially on the insulating layer 210. For conductive layer 220_1, a titanium nitride film with a thickness of 5 nm was deposited using the CVD method, and a tungsten film with a thickness of 40 nm was deposited on the titanium nitride film using the CVD method. For conductive layer 220_2, an ITO film with a thickness of 20 nm was deposited using the sputtering method. Subsequently, conductive layers 220_1 and 220_2 were formed by processing these conductive films.

[0545] Next, insulating layers 280 (insulating layers 280_1 to 280_4) were formed on the conductive layer 220_2. As insulating layer 280_1, a silicon nitride film with a thickness of 5 nm was deposited using the ALD method.

[0546] Next, a silicon nitride film with a thickness of 90 nm was deposited as insulating layer 280_2 using the sputtering method. Subsequently, a silicon oxide film with a thickness of 120 nm was deposited as a sacrificial layer using the sputtering method. Then, using the silicon oxide film as a sacrificial layer, the silicon nitride film was subjected to CMP treatment to flatten the upper surface of the silicon nitride film deposited by sputtering. The CMP treatment was performed so that the thickness of the flattened silicon nitride film was 10 nm.

[0547] Next, a silicon oxide film with a thickness of 80 nm was deposited as insulating layer 280_3 using the sputtering method. Then, a silicon nitride film with a thickness of 10 nm was deposited as insulating layer 280_4 using the sputtering method. Insulating layer 280 was formed to have a thickness of 105 nm. In other words, insulating layer 280 was formed so that the shortest distance between conductive layer 220_2 and the conductive film 240_1f to be formed next was 105 nm.

[0548] Next, a conductive film 240_1f, which will become conductive layer 240_1, and a conductive film 240_2f, which will become conductive layer 240_2, were sequentially deposited on the insulating layer 280. A tungsten film with a thickness of 15 nm was deposited as conductive film 240_1f using the sputtering method. An ITO film with a thickness of 10 nm was deposited as conductive film 240_2f using the sputtering method.

[0549] Next, an oxide film 245f, which will become the oxide layer 245, was deposited on the conductive film 240_2f. The oxide film 245f with a thickness of 2 nm was deposited using the sputtering method. For the oxide film 245f, an oxide target with a composition of In:Ga:Zn = 1:3:2 [atomic ratio] was used. Ar gas 163 sccm, O ２ A gas of 42 sccm was used, the pressure was set to 1.0 Pa, the distance between electrodes was set to 145 mm, the substrate temperature was set to 250°C, and 1000 W was supplied from an RF power supply.

[0550] Next, the oxide film 245f and the conductive film 240_2f were processed using lithography to form the opening 290. In the lithography method, a mask layer 400 was used, which consisted of a SOC (spin-on-carbon) film, an SOG (spin-on-grass) film, and a resist mask in that order. The opening 290 was formed by dry etching. In addition, a portion of the mask layer 400 was removed by dry etching.

[0551] The opening 290 was formed to reach the conductive layer 220_2. The opening 290 was formed to have a circular shape with a diameter of 60 nm in a plan view.

[0552] Next, with the oxide film 245f covered with the mask layer 400, megasonic cleaning was performed using hydrofluoric acid and pure water. The cleaning was carried out at a discharge rate of 20 ml / min of hydrofluoric acid and a frequency of 1.5 MHz. Note that the above cleaning treatment was performed after processing the conductive film 240_2f.

[0553] Next, the remaining SOC layer and residual polymer were removed by ashing using oxygen plasma. The ashing was performed for 60 seconds. ２A gas of 200 sccm was used, the pressure was set to 0.67 Pa, and the substrate temperature was set to 40°C. 2000 W was supplied from the RF power supply, and 50 W was applied to the bias potential.

[0554] Next, a semiconductor film 230f, which will become the semiconductor layer 230, was formed in a two-layer structure to cover the opening 290. As the first semiconductor film, an indium oxide film with a thickness of 5 nm was deposited using the ALD method. The indium oxide film was deposited using triethylindium as the precursor and ozone as the oxidizing agent, with an introduction time of 9 seconds per cycle and a substrate temperature of 200°C. As the second semiconductor film, an IGZO film with a thickness of 5 nm was deposited using the sputtering method. The IGZO film was deposited using an oxide target with an In:Ga:Zn ratio of 1:1:1.2 [atomic ratio].

[0555] Next, the semiconductor film 230f, the oxide film 245f, and the conductive films 240_1f and 240_2f were processed. By processing the semiconductor film 230f, a semiconductor layer 230 was formed having a region in contact with the conductive layer 220, a region in contact with the oxide layer 245, and a region in contact with the conductive layer 240. By processing the oxide film 245f, an oxide layer 245 was formed so as to be located between the semiconductor layer 230 and the conductive layer 240. By processing the conductive film 240f, a conductive layer 240 was formed so as to be located between the insulating layer 280 and the oxide layer 245.

[0556] Next, an insulating layer 250 was formed on the semiconductor layer 230. As the insulating layer 250, an aluminum oxide film with a thickness of 1 nm, a silicon oxide film with a thickness of 2 nm, a hafnium oxide film with a thickness of 2 nm, and a silicon nitride film with a thickness of 1 nm were sequentially deposited by the ALD method.

[0557] Next, conductive layers 260 (conductive layer 260_1 and conductive layer 260_2) were formed on the insulating layer 250. Conductive film 260_1f, which will become conductive layer 260_1, and conductive film 260_2f, which will become conductive layer 260_2, were deposited in sequence. For conductive film 260_1f, a titanium nitride film with a thickness of 5 nm was deposited using the CVD method. For conductive film 260_2f, a tungsten film with a thickness of 20 nm was deposited using the CVD method. Subsequently, conductive layers 260_1 and 260_2 were formed by processing conductive films 260_1f and 260_2f. As a result, a transistor with a channel length of 105 nm and a channel width of 60 nmφ was formed.

[0558] [Cross-sectional observation, elemental analysis] Cross-sectional STEM images were taken and elemental analysis was performed on the prepared samples. For cross-sectional STEM image acquisition, the prepared samples were thinned using a focused ion beam (FIB). Spherical aberration corrector function was used for observation of the cross-sectional STEM images. Cross-sectional STEM images were taken using a JEOL Ltd. atomic resolution analytical electron microscope JEM-ARM200F with an acceleration voltage of 200 kV. Elemental analysis was performed using energy-dispersive X-ray spectroscopy (EDX), and EDX mapping was acquired.

[0559] Cross-sectional STEM images of the fabricated sample are shown in Figures 30 to 31B. Figure 30 is a cross-sectional STEM image (TE image) of the sample, and Figure 31A is a cross-sectional STEM image (ZC image) of region D1 shown in Figure 30, magnified. Figure 31B is an EDX-Mapping image showing the Ga distribution of the cross-sectional STEM image shown in Figure 31A. From Figure 30, it was confirmed that the target sample was fabricated. As shown in Figures 31A and 31B, the oxide layer 245 can be seen on the upper surface of the conductive layer 240. In addition, the Ga peak was 1.0 atomic% or less at the interface between the side surface of the conductive layer 240 and the semiconductor layer 230. From Figures 31A and 31B, the oxide layer 245 is not present at the interface between the side surface of the conductive layer 240 and the semiconductor layer 230. From this, it was confirmed that the reduction in the contact area between the conductive layer 240 and the semiconductor layer 230 was suppressed. Therefore, it is expected that the contact resistance between the conductive layer 240 and the semiconductor layer 230 can be lowered, and the on-current of the semiconductor device can be increased.

[0560] [Evaluation of Transistor Electrical Characteristics] The Id-Vg characteristics of the nine transistors contained in the sample prepared in this example were measured.

[0561] In the measurement, the drain voltage Vd was set to 1.2V or 0.1V, and the gate voltage was swept from -4V to +4V in 0.1V steps. The measurement temperature was room temperature. Figure 32 shows the Id-Vg characteristics of the transistor. In Figure 32, the first vertical axis (left vertical axis) represents the drain current Id [A], and the second vertical axis (right vertical axis) represents the field effect mobility μFE [cm]. ２ The horizontal axis represents the gate voltage Vg [V], with the horizontal axis representing Vd = Vs. Figure 32 shows the Id-Vg curves and field-effect mobility for Vd = 0.1V and Vd = 1.2V, respectively.

[0562] As shown in Figure 32, the transistors included in the sample were confirmed to exhibit good electrical characteristics. Specifically, the transistors included in the sample had a median field-effect mobility of 45.0 cm⁻¹. ２The median on-current was 73.6 μA, the median S value was 84.3 mV / dec., the threshold voltage (Vth) was -0.56 V, and the standard deviation of the threshold voltage was 83 mV. The on-current is the value of the drain current Id at Vg = Vth + 2.5 V. The threshold voltage was calculated using the constant current method. The constant current method is a method in which Id is normalized from the Id-Vg characteristic result so that L / W = 1, and Vth is taken as the value of Vg when a constant current flows.

[0563] As shown in Figure 32, the on-current of the transistor showed a good value. One reason for this is that, as shown in Figure 31, there is no oxide layer 245 between the semiconductor layer 230 and the conductive layer 240. This suggests that the contact area between the conductive layer 240 and the semiconductor layer 230 could be increased, and the conductive layer 240 was able to lower the contact resistance between itself and the semiconductor layer 230. By using such a transistor, it was possible to fabricate a semiconductor device with a large on-current.

[0564] 100: Capacitive element, 110: Conductive layer, 115: Conductive layer, 130: Insulating layer, 140: Insulating layer, 150: Memory cell, 180: Insulating layer, 190: Aperture, 200: Transistor, 200A: Transistor, 200B: Transistor, 210: Insulating layer, 220: Conductive layer, 220_1: Conductive layer, 220_2: Conductive layer, 230: Semiconductor layer, 230_1: Semiconductor layer, 230_2: Semiconductor layer, 230f: Semiconductor film, 240: Conductive layer, 240_1: Conductive layer, 240_1f: Conductive film, 240_2: Conductive layer, 240_2f: Conductive film, 240f: Conductive film, 245: Oxide layer, 245f: Oxide film, 250: Insulating layer, 250_1: Insulating layer, 250_2: Insulating layer, 250_3: Insulating layer, 250_4: Insulating layer, 260: Conductive layer, 260_1: Conductive layer, 260_1f: Conductive film, 260_2: Conductive layer, 260_2f: Conductive film, 265: Conductive layer, 270: Aperture, 280: Insulating layer, 280_1: Insulating layer, 280_2: Insulating layer, 280_3: Insulating layer, 280_4: Insulating layer, 282: Insulating layer, 283: Insulating layer, 284: Insulating layer, 285: Insulating layer, 290: Aperture, 300: Transistor, 311: Substrate, 313: Semiconductor region, 314a: Low resistor 314b: Low-resistance region, 315: Insulating layer, 316: Conductive layer, 320: Insulating layer, 322: Insulating layer, 324: Insulating layer, 326: Insulating layer, 328: Conductive layer, 330: Conductive layer, 350: Insulating layer, 352: Insulating layer, 354: Insulating layer, 356: Conductive layer, 400: Mask layer, 642: Conductive layer, 643: Conductive layer, 644: Conductive layer, 645: Conductive layer, 646: Conductive layer, 648: Insulating layer, 900: Semiconductor device, 910: Drive circuit, 911: Peripheral circuit, 912: Control circuit, 915: Peripheral circuit, 920: Memory array, 923: Row driver, 924: Column driver B, 925: Input circuit, 926: Output circuit, 927: Sense amplifier, 928: Voltage generation circuit, 930: Layer, 931: PSW, 932: PSW, 941: Row decoder, 942: Column decoder, 950: Memory cell, 951: Memory cell, 952: Memory cell, 953: Memory cell, 954: Memory cell, 955: Memory cell, 956: Memory cell, 957: Memory cell, 958: Memory cell, 960: Arithmetic unit, 961: Circuit board, 962: ALU, 962c: ALU controller, 963: Instruction decoder, 964: Interrupt controller,965: Timing controller, 966: Register, 967: Register controller, 968: Bus interface, 969: Cache, 969i: Cache interface, 970A: Semiconductor device, 970B: Semiconductor device, 970C: Semiconductor device, 980: Electronic component, 981: Semiconductor device, 982: Drive circuit layer, 983: Memory layer, 984: Mold, 985: Land, 986: Electrode pad, 987: Wire, 988: Printed circuit board, 989: Mounted circuit board, 990: Electronic component, 991: Interposer, 992: Package substrate, 993: Electrode, 994: Semiconductor device, 5600: Mainframe computer, 56 10: Rack, 5620: Computer, 5621: PC Card, 5622: Board, 5623: Connector, 5624: Connector, 5625: Connector, 5626: Semiconductor device, 5627: Semiconductor device, 5628: Semiconductor device, 5629: Connector, 5630: Motherboard, 5631: Slot, 6800: Satellite, 6801: Aircraft, 6802: Solar Panel, 6803: Antenna, 6804: Planet, 6805: Rechargeable Battery, 6807: Control Device, 7001: Host, 7001sb: Server, 7002: Storage Control Circuit, 7003: Storage, 7003md: Memory Device, 7010: Storage System

Claims

1. A semiconductor device comprising: a first conductive layer, a second conductive layer, a third conductive layer, an oxide layer, a semiconductor layer, a first insulating layer, and a second insulating layer, wherein the first insulating layer is located on the first conductive layer, the second conductive layer is located on the first insulating layer, the oxide layer is located on the second conductive layer, the first insulating layer, the second conductive layer, and the oxide layer each have an opening that reaches the first conductive layer, the semiconductor layer has a portion in contact with the first conductive layer, a portion in contact with the side surface of the opening of the first insulating layer, a portion in contact with the side surface of the opening of the second conductive layer, and a portion in contact with the top and side surfaces of the oxide layer, the second insulating layer is located on the semiconductor layer, and the third conductive layer has a portion facing the semiconductor layer via the second insulating layer.

2. The semiconductor device according to claim 1, wherein the semiconductor layer comprises indium and oxygen, and the oxide layer comprises indium, gallium and zinc.

3. The semiconductor device according to claim 2, wherein the gallium concentration at the interface between the semiconductor layer and the second conductive layer is 1.0 atomic% or less in a portion of the interface.

4. The semiconductor device according to claim 2, wherein the oxide layer has a composition of In:Ga:Zn = 1:1:1 [atomic ratio] or close to that, or a composition of In:Ga:Zn = 1:3:2 [atomic ratio] or close to that.

5. The semiconductor device according to claim 2, wherein the oxide layer has a first crystal having a hexagonal or trigonal crystal structure, and the semiconductor layer has a second crystal having a cubic crystal structure.

6. The semiconductor device according to claim 5, wherein the <001> orientation of the first crystal is perpendicular or substantially perpendicular to the upper surface of the first insulating layer.

7. The semiconductor device according to claim 5, wherein the <111> orientation of the second crystal is parallel or substantially parallel to the depth direction of the opening.

8. A semiconductor device according to any one of claims 1 to 7, wherein the second conductive layer comprises a fourth conductive layer and a fifth conductive layer, the fifth conductive layer is located on the fourth conductive layer, the fourth conductive layer contains tungsten, and the fifth conductive layer contains indium, tin, and oxygen.

9. The semiconductor device according to claim 8, wherein the semiconductor layer has a portion that is in contact with the side surface of the opening of the fourth conductive layer.

10. The semiconductor device according to claim 8, wherein the semiconductor layer has a portion that is in contact with the side surface of the opening of the fifth conductive layer.

11. A method for manufacturing a semiconductor device, comprising: a first step of depositing a first conductive layer, a first insulating layer, a second conductive layer, and an oxide layer in that order; a second step of forming a mask layer on the oxide layer; a third step of processing the oxide layer, the second conductive layer, and the first insulating layer using a dry etching method to form an opening that reaches the first conductive layer; a fourth step of covering the oxide layer with a part of the mask layer and performing a cleaning treatment; a fifth step of performing an ashing treatment using oxygen plasma; a sixth step of depositing a first semiconductor layer on the oxide layer and on the opening; and a seventh step of depositing a second insulating layer on the first semiconductor layer and a third conductive layer on the second insulating layer.

12. A method for manufacturing a semiconductor device according to claim 11, wherein the oxide layer is formed by sputtering using a target containing indium, gallium, zinc, and oxygen.

13. A method for manufacturing a semiconductor device according to claim 11 or claim 12, wherein the first semiconductor layer comprises a second semiconductor layer and a third semiconductor layer on the second semiconductor layer, the second semiconductor layer is formed by the ALD method using triethylindium as a precursor, and the third semiconductor layer is formed by the sputtering method using a target containing indium, gallium, zinc, and oxygen.

14. A method for manufacturing a semiconductor device according to claim 11, wherein the cleaning process uses a cleaning solution containing hydrofluoric acid.

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