Semiconductor device and production method for semiconductor device

Abstract

A semiconductor device according to the present invention includes a plurality of lower layer conductive patterns that are formed above a substrate, a lower layer insulating film that fills the spaces between the plurality of lower layer conductive patterns such that upper portions of the lower layer conductive patterns protrude, an intermediate insulating film that is self-aligned with the lower layer insulating film at a film thickness that protrudes from the lower layer conductive patterns, a plurality of upper layer conductive patterns that are joined to the plurality of lower layer conductive patterns in the spaces in the intermediate insulating film so as to protrude from the intermediate insulating film, and an upper layer insulating film that is provided above the intermediate insulating film so as to fill the spaces between the plurality of upper layer conductive patterns.

Description

Semiconductor device and method of manufacturing the same

[0001] The present invention relates to a semiconductor device and a method of manufacturing the same.

[0002] As a technology related to semiconductor devices, Patent Document 1 below describes, referring to FIG. 1, "On a lower insulating layer 320, a plurality of first wirings 420 are arranged. Each first wiring 420 is connected to a gate electrode 240 or the like via a contact plug 410. Further, on each first wiring 420, a first via 440 is arranged. The bottom surface of the first via 440 is in contact with the upper surface of the first wiring 420. On the lower insulating layer 320, a first insulating layer 330 is arranged. The first insulating layer 330 is in contact with at least the upper surface of the first wiring 420 and the side surface of the first via 440.... The first wiring 420, the first via 440, and the first insulating layer 330 form one first wiring layer 30." Further, FIG. 1 of Patent Document 1 below shows a state in which the upper surface of the first via 440 and the upper surface of the first insulating layer 330 are arranged on the same plane.

[0003] U.S. Patent No. 8,722,532

[0004] By the way, in conductive patterns such as wirings and vias, an electric field is likely to concentrate at convex corners of the pattern shape. Therefore, in the configuration in which the upper surface of the first via, which is a conductive pattern, and the upper surface of the first insulating layer are arranged on the same plane as shown in Patent Document 1, there is room for improvement in terms of improving the breakdown voltage characteristics.

[0005] Accordingly, an object of the present invention is to provide a semiconductor device and a method of manufacturing the same that can improve the breakdown voltage characteristics between conductive patterns.

[0006] To achieve this objective, the present invention provides a semiconductor device comprising: a plurality of lower conductive patterns formed on the upper surface of a substrate; a lower insulating film that fills the spaces between the plurality of lower conductive patterns with the upper parts of the plurality of lower conductive patterns protruding; an intermediate insulating film that is provided with a thickness protruding from the lower conductive patterns and is self-aligned with the lower insulating film; a plurality of upper conductive patterns that are bonded to the plurality of lower conductive patterns between the intermediate insulating films with a thickness protruding from the intermediate insulating film; and an upper insulating film provided above the intermediate insulating film that fills the spaces between the plurality of upper conductive patterns.

[0007] The present invention also relates to a method for manufacturing a semiconductor device, comprising the steps of: forming a plurality of lower conductive patterns and a lower insulating film that fills the spaces between the plurality of lower conductive patterns on a substrate; etching back the lower insulating film to cause the upper parts of the lower conductive patterns to protrude from the lower insulating film; forming an intermediate insulating film with a thickness that protrudes from the lower conductive patterns in a self-aligned manner with respect to the lower insulating film; and forming a plurality of upper conductive patterns that are bonded to the plurality of lower conductive patterns between the intermediate insulating films, and an upper insulating film that fills the spaces between the plurality of upper conductive patterns, on top of the intermediate insulating film.

[0008] The present invention provides a semiconductor device and a method for manufacturing a semiconductor device that can improve the withstand voltage characteristics between adjacent conductive patterns.

[0009] This is a cross-sectional view of the main part of the semiconductor device of the first embodiment in the X direction. This is a cross-sectional view of the main part of the semiconductor device of the first embodiment in the Y direction. This is a process diagram (1) showing the manufacturing method of the semiconductor device of the first embodiment. This is a process diagram (2) showing the manufacturing method of the semiconductor device of the first embodiment. This is a process diagram (3) showing the manufacturing method of the semiconductor device of the first embodiment. This is a process diagram (4) showing the manufacturing method of the semiconductor device of the first embodiment. This is a process diagram (5) showing the manufacturing method of the semiconductor device of the first embodiment. This is a graph schematically showing the dielectric breakdown voltage of the insulating material. This is a cross-sectional view of the main part of the semiconductor device of the second embodiment in the X direction. This is a cross-sectional view of the main part of the semiconductor device of the second embodiment in the Y direction. This is a process diagram (1) showing the manufacturing method of the semiconductor device of the second embodiment. This is a process diagram (2) showing the manufacturing method of the semiconductor device of the second embodiment. This is a process diagram (3) showing the manufacturing method of the semiconductor device of the second embodiment. This is a process diagram (4) showing the manufacturing method of the semiconductor device of the second embodiment. This is a cross-sectional view of the main part of the semiconductor device of the third embodiment in the X direction. This is a cross-sectional view of the main part of the semiconductor device of the third embodiment in the Y direction.

[0010] Hereinafter, embodiments of the semiconductor device and the method for manufacturing the semiconductor device of the present invention will be described in detail with reference to the drawings. In each embodiment, common components are denoted by the same reference numerals, and redundant descriptions are omitted.

[0011] <First Embodiment> <Configuration of Semiconductor Device 1 of the First Embodiment> Figure 1 is a cross-sectional view of the main part of the semiconductor device 1 of the first embodiment in the X direction. Figure 2 is a cross-sectional view of the main part of the semiconductor device 1 of the first embodiment in the Y direction, and is a cross-sectional view taken along line A-A in Figure 1. The semiconductor device 1 shown in these figures is constructed by applying damascene technology, and comprises a plurality of lower conductive patterns 10 and a plurality of upper conductive patterns 20 provided above them on one main surface of a substrate (not shown) on which elements such as transistors are formed. Furthermore, the semiconductor device 1 has a lower insulating film 100, an intermediate insulating film 200, an upper barrier insulating film 300', and an upper insulating film 300 provided in this order on one main surface of a substrate (not shown here) with the lower conductive patterns 10 and upper conductive patterns 20 embedded in it. These configurations will be described below.

[0012] [Lower Conductive Pattern 10] The lower conductive pattern 10 is a copper (Cu) pattern formed by applying the damascene method. The lower conductive pattern 10 consists of lower vias (not shown in the illustration here) and lower wiring M1 arranged on the lower vias and connected to the lower vias. The lower vias may be contact plugs connected to semiconductor elements. The lower vias and lower wiring M1 may also be integrally formed by applying the dual damascene method. Since the lower wiring M1 constituting the lower conductive pattern 10 is a pattern formed by applying the damascene method (including the dual damascene method), it has the largest line width [w1] at the top.

[0013] The upper part of the lower conductive pattern 10 (in this case, the upper part of the lower wiring M1) is provided protruding from the lower insulating film 100, which will be described later. The lower conductive pattern 10 may also have a cap layer M1a on its surface. The cap layer M1a is a metal layer that prevents oxidation of the copper (Cu) constituting the lower wiring M1, and is made of, for example, cobalt (Co).

[0014] [Upper Conductive Pattern 20] The upper conductive pattern 20 is a copper (Cu) pattern formed by applying the damascene method. The upper conductive pattern 20 is a pattern provided in a state where it is joined to the lower conductive pattern 10, and consists of an upper via V2 and an upper wiring M2 that is placed on the upper via V2 and formed integrally with the upper via V2. Since the upper wiring M2 that constitutes the upper conductive pattern 20 is a pattern formed by applying the damascene method, it has the largest line width [w2] at the top.

[0015] The upper conductive pattern 20 described above is provided by joining it to a plurality of lower conductive patterns 10 between the intermediate insulating films 200, which will be described later. More specifically, the lower part of the upper conductive pattern 20, in this case the lower part of the upper via V2, is provided by joining it to a plurality of lower conductive patterns 10 between the intermediate insulating films 200. Also, the upper part of the upper conductive pattern 20, the upper part of the upper via V2 and the upper wiring M2 protrude from the intermediate insulating film 200 and are embedded in the surface layer of the upper insulating film 300, which will be described later. In addition, similar to the lower conductive pattern 10, the upper conductive pattern 20 may have a cap layer M2a on its surface.

[0016] [Lower insulating film 100] The lower insulating film 100 is provided with a thickness that fills the space between the lower conductive patterns 10 with the upper parts of the lower conductive patterns 10 protruding, and in this case, it has a thickness that allows the upper parts of the lower wiring M1 in the lower conductive patterns 10 to protrude. It is preferable that such a lower insulating film 100 is made of a low dielectric constant material such as silicon hydride carbonate (hereinafter referred to as SiCOH) containing Si, C, O, and H. This makes it possible to reduce parasitic capacitance generated between adjacent lower conductive patterns 10.

[0017] [Intermediate insulating film 200] The intermediate insulating film 200 is a film selectively grown on the exposed surface of the lower insulating film 100. It is not positioned on the upper part of the lower conductive pattern 10, but is characterized by being self-aligned only on the lower insulating film 100 that is exposed from the lower conductive pattern 10. This intermediate insulating film 200 protrudes above the lower conductive pattern 10 and has a thickness that covers the lower conductive pattern 10 and the upper conductive pattern 20 from the upper part of the lower conductive pattern 10 to the lower part of the upper conductive pattern 20. Furthermore, the upper and lower interfaces 200a and 200b of the intermediate insulating film 200 are positioned at a height of 1 nm or more away from the upper surface of the lower conductive pattern 10. In other words, the intermediate insulating film 200 covers the interface between the upper via V2 and the lower wiring M1 (specifically, around the interface in the height direction of the semiconductor device 1) in a configuration comprising a plurality of wirings including a lower wiring M1 and an upper wiring M2, an upper via V2 electrically connected to at least one of these plurality of wirings, and an upper wiring M2 electrically connected to the lower wiring M1 via the upper via V2. Here, the intermediate insulating film 200 is an example of a "first insulating layer". The upper via V2 is an example of a "via".

[0018] Such an intermediate insulating film 200 is made of at least one aluminum-based material selected from the group consisting of aluminum oxide (AlOx) and aluminum nitride (AlNx), or at least one silicon-based material selected from the group consisting of silicon nitride (SiN), silicon carbonitride (SiCN), and silicon hydride carbonate (SiCOH). Alternatively, both the lower insulating film 100 and the intermediate insulating film 200 may be made of SiCOH.

[0019] Furthermore, it is preferable that the intermediate insulating film 200 be made of a material with a higher film density than the lower insulating film 100 among these insulating materials. For example, if the lower insulating film 100 is made of SiCOH, it is preferable that the intermediate insulating film 200 be made of aluminum oxide (AlOx), aluminum nitride (AlNx), silicon nitride (SiN), silicon carbonitride (SiCN), etc. This makes it possible to ensure the breakdown voltage between the lower conductive patterns 10, between the upper conductive patterns 20, and between the lower conductive patterns 10 and the upper conductive patterns 20.

[0020] Furthermore, it is preferable that the intermediate insulating film 200 is made of a material that has etching resistance in the etching of the upper barrier insulating film 300' and the upper insulating film 300, which will be described later. For example, when the upper barrier insulating film 300' and the upper insulating film 300 are made of silicon-based materials, it is preferable that the intermediate insulating film 200 is made of aluminum oxide (AlOx) or aluminum nitride (AlNx).

[0021] [Upper barrier insulating film 300'] The upper barrier insulating film 300' covers the intermediate insulating film 200 and the lower conductive pattern 10, and is provided to fill the spaces between the multiple upper conductive patterns 20. This upper barrier insulating film 300' is a layer for preventing oxidation of the metal (copper) constituting the upper conductive pattern 20 on the cap layer M1a made of Co, and is the base layer for the upper insulating film 300 which will be described next. Such an upper barrier insulating film 300' is made of a material with a high film density, such as SiCN. Furthermore, it is preferable that the upper barrier insulating film 300' is made of a material with a higher etching selectivity than the intermediate insulating film 200. This makes it possible to bond the upper conductive pattern 20 to the lower conductive pattern 10 exposed between the intermediate insulating films 200 with good positional accuracy, as will be described in the semiconductor device manufacturing method described later.

[0022] [Upper insulating film 300] The upper insulating film 300 is provided on the upper barrier insulating film 300' to fill the spaces between the multiple upper conductive patterns 20. It is preferable that such an upper insulating film 300 is made of a low dielectric constant material such as SiCOH. This reduces parasitic capacitance that occurs between adjacent upper conductive patterns 20.

[0023] <Method of Manufacturing Semiconductor Device 1 of the First Embodiment> Figures 3 to 7 are process diagrams (1) to (5) showing the method of manufacturing the semiconductor device of the first embodiment, and are drawings corresponding to the cross-sectional view in the X direction of Figure 1. The method of manufacturing the semiconductor device of the first embodiment will be described below based on these figures.

[0024] First, as shown in Figure 3, a plurality of lower conductive patterns 10 and a lower insulating film 100 that fills the spaces between the plurality of lower conductive patterns 10 are formed on top of the substrate (not shown here) by applying the damascene method.

[0025] In this process, for example, a lower insulating film 100 made of SiCOH is deposited on the substrate, and trenches 100a for lower wiring are patterned in this lower insulating film 100. Then, a barrier metal and a copper seed layer (not shown here) are deposited in this order to cover the inner walls of the trenches 100a, and a copper film is deposited on the lower insulating film 100 to fill the inside of the trenches 100a. Next, the copper film, barrier metal, and copper seed layer are chemically mechanically polished (CMP) until the lower insulating film 100 is exposed, thereby forming the lower wiring M1 which will become the lower conductive pattern 10. After that, if necessary, a Co film is selectively deposited on the copper lower wiring M1 to form a lower wiring M1 having a Co cap layer M1a.

[0026] Next, as shown in Figure 4, the upper part of the lower wiring M1 is made to protrude from the lower insulating film 100 by etch-back the lower insulating film 100. In this case, if the lower insulating film 100 is made of SiCOH, the lower insulating film 100 is etch-back by dry etching using fluorocarbon gas. The exposed height [h] of the lower wiring M1 from the lower insulating film 100 is set to 1 nm or more.

[0027] Next, as shown in Figure 5, an intermediate insulating film 200 is formed with a thickness that protrudes from the lower conductive pattern 10, in a self-aligned manner with respect to the lower insulating film 100. In this process, first, a SAM (self-assembled monolayer), which is not shown here, is formed to selectively cover the exposed surface of the lower wiring M1. Then, the intermediate insulating film 200 is selectively formed on the exposed surface of the lower insulating film 100. The intermediate insulating film 200 formed here is, for example, an aluminum oxide (AlOx) film, but AlN, iCOH, SiCN, and SiN can also be selectively grown in the same way. The thickness [t] of the intermediate insulating film 200 is set to 2 nm or more, thereby moving the upper surface 10a of the lower conductive pattern 10 at least 1 nm away from the upper and lower interfaces 200a and 200b of the intermediate insulating film 200, and suppressing dielectric breakdown between the lower conductive patterns 10 via the interfaces 200a and 200b.

[0028] Next, as shown in Figure 6, an upper barrier insulating film 300' made of, for example, SiCN is deposited on the entire upper surface of the intermediate insulating film 200 and the lower conductive pattern 10, and then an upper insulating film 300 made of SiCOH is deposited on the upper barrier insulating film 300'.

[0029] Next, as shown in Figure 7, via holes 300a for upper vias and trenches 300b for upper wiring are formed in the upper insulating film 300, the upper barrier insulating film 300', and the intermediate insulating film 200. First, a resist pattern for vias (not shown) is used as a mask to etch the upper insulating film 300, the upper barrier insulating film 300', and the intermediate insulating film 200 to form via holes 300a that reach the lower conductive pattern 10. Then, a resist pattern for wiring (not shown) is used as a mask to etch the upper insulating film 300 to form trenches 300b that communicate with the via holes 300a.

[0030] In the formation of the trench 300b, a via fan 301 is formed when the upper shoulder portion of the via hole 300a exposed on the bottom surface of the trench 300b is deformed by the concentration of etchant. Therefore, by constructing the intermediate insulating film 200 using a material with a low etching selectivity ratio compared to the upper barrier insulating film 300' and the upper insulating film 300, the intermediate insulating film 200 can act as an etching stopper to prevent the expansion of the via fan 301.

[0031] After the above steps, a barrier metal and a copper seed layer (not shown in the illustration) are deposited in this order to cover the inner walls of the via holes 300a and trenches 300b, and then a copper film is deposited on the lower insulating film 100 to fill the inside of the via holes 300a and trenches 300b. Next, the copper film, barrier metal, and copper seed layer are chemically and mechanically polished until the upper insulating film 300 is exposed. This forms an upper conductive pattern 20 having upper wiring M2 and upper vias V2 made of copper, as shown in Figures 1 and 2. After that, if necessary, a Co film is selectively deposited on the upper wiring M2 made of copper to obtain a semiconductor device 1 with upper wiring M2 having a cap layer M2a made of Co.

[0032] Furthermore, if an even higher conductive pattern is to be formed on top of the upper conductive pattern 20, the upper conductive pattern 20 can be replaced with the lower conductive pattern 10, and the process described using Figure 4, and the subsequent processes, can be repeated.

[0033] <Effects of the First Embodiment> The semiconductor device 1 of the first embodiment described above has a configuration in which the convex corners at the top of the lower conductive pattern 10, where the electric field is easily concentrated and the pattern width [w1] is at its maximum, resulting in a narrow gap between adjacent patterns, are positioned at an intermediate position in the film thickness direction of the intermediate insulating film 200. Therefore, dielectric breakdown between adjacent lower conductive patterns 10 and between upper conductive patterns 20 connected to them can be prevented via the interface of the insulating film, and the breakdown characteristics between the lower conductive patterns 10 and the upper conductive patterns 20 can be improved.

[0034] Furthermore, by using a film with a higher density than the lower insulating film 100, the upper barrier insulating film 300', and the upper insulating film 300 as the intermediate insulating film 200, it is possible to more effectively prevent dielectric breakdown between the lower conductive patterns 10 and the upper conductive patterns 20. Figure 8 is a graph showing the dielectric breakdown voltage of the insulating material. The insulating material is, for example, SiCOH (film density 1-2 g / cm³), which is a constituent material of the lower insulating film 100 and the upper insulating film 300. ３ ) and AlOx (film density 2.8-3.2 g / cm³), which is a constituent material of the intermediate insulating film 200. ３ As shown in Figure 8, AlOx, which has a high film density, has a higher dielectric breakdown voltage than SiCOH, which has a low film density. This shows that using a material with a high film density as the intermediate insulating film 200 enhances the effect of preventing dielectric breakdown between the lower conductive patterns 10.

[0035] Furthermore, by using a film as the intermediate insulating film 200 that is resistant to etching of the upper barrier insulating film 300' and the upper insulating film 300, the expansion of the via fan 301 can be prevented, as explained with reference to Figure 7. This allows for a wider distance [l] between the upper conductive pattern 20 and the adjacent lower conductive pattern 10 in the via chamfer 301 portion, as indicated by the arrows in Figure 1, thereby improving the breakdown voltage characteristics between them.

[0036] Furthermore, in the formation of the via holes 300a as explained with reference to Figure 7, by etching the upper barrier insulating film 300' using the intermediate insulating film 200 as an etching stopper, it becomes possible to form the via holes 300a in a self-aligned manner in the arrangement direction of the lower wiring M1. As a result, misalignment of the upper conductive pattern 20 with respect to the lower conductive pattern 10 is prevented, and the breakdown voltage characteristics between the lower conductive pattern 10 and the upper conductive pattern 20 can be improved.

[0037] ≪Second Embodiment≫ <Configuration of the Semiconductor Device of the Second Embodiment> Figure 9 is a cross-sectional view of the main part of the semiconductor device 2 of the second embodiment in the X direction. Figure 10 is a cross-sectional view of the main part of the semiconductor device 2 of the second embodiment in the Y direction, and is a cross-sectional view taken along line A-A in Figure 9. The semiconductor device 2 shown in these figures is constructed by applying subtractive technology, and comprises a plurality of lower conductive patterns 10' and a plurality of upper conductive patterns 20' provided above them on one main surface of a substrate (not shown) on which elements such as transistors are formed. Furthermore, the semiconductor device 2 has a lower insulating film 100, an intermediate insulating film 200, and an upper insulating film 300 provided in this order on one main surface of a substrate (not shown here), with the lower conductive patterns 10' and upper conductive patterns 20' embedded within it.

[0038] [Lower Conductive Pattern 10'] The lower conductive pattern 10' is a pattern formed by applying subtractive technology. The lower conductive pattern 10' consists of lower wiring M1 and lower vias V1 arranged on and connected to the lower wiring M1. The lower wiring M1 and the lower vias V1 may be integrally formed. Since the lower conductive pattern 10' is a pattern formed by applying subtractive technology, it has a shape in which the line width gradually increases towards the bottom.

[0039] The upper part of the lower conductive pattern 10' described above (in this case, the upper part of the lower via V1) is provided protruding from the lower insulating film 100, which will be described later.

[0040] Furthermore, if the semiconductor device 2 has a wiring pitch of 20 nm or less, the lower conductive pattern 10' is constructed using a post-Cu material whose mean free path of electrons is smaller than that of copper (Cu), in order to suppress wiring resistance. Examples of such materials include single-component metal materials such as ruthenium (Ru), cobalt (Co), molybdenum (Mo), tungsten (W), rhodium (Rh), and iridium (Ir), as well as multi-component metal materials such as NiAl.

[0041] [Upper conductive pattern 20'] The upper conductive pattern 20' is a pattern formed by applying subtractive technology. The upper conductive pattern 20' is a pattern provided in a state of being joined to the lower conductive pattern 10', and is composed of an upper wiring M2 and an upper via V2 disposed on the upper wiring M2 and connected to the upper wiring M2. The upper wiring M2 and the upper via V2 may be integrally formed. Since the upper conductive pattern 20' is a pattern formed by applying subtractive technology, it has a shape in which the line width gradually expands toward the lower part.

[0042] The upper conductive pattern 20' as described above is provided by being joined to the lower conductive pattern 10 between the intermediate insulating films 200 to be described later. Also, at the upper part of the upper conductive pattern 20', here, the upper part of the upper wiring M2 and the upper via V2 protrude from the intermediate insulating film 200 and are embedded in the surface layer of the upper insulating film 300 to be described later. When the semiconductor device 2 has a wiring pitch of 20 nm or less, the upper conductive pattern 20' is configured using a post-Cu material, similar to the lower conductive pattern 10'.

[0043] [Lower insulating film 100] The lower insulating film 100 is provided with a thickness that fills the space between the lower conductive patterns 10' in a state of protruding above the lower conductive patterns 10'. Here, it has a thickness that protrudes above the lower via V1 in the lower conductive pattern 10'. Such a lower insulating film 100 is preferably composed of a low dielectric constant material such as SiCOH. Thus, it is possible to reduce the parasitic capacitance generated between adjacent lower conductive patterns 10', which is the same as in the first embodiment.

[0044] [Intermediate insulating film 200] The intermediate insulating film 200 is a film selectively grown on the exposed surface of the lower insulating film 100, and is characterized in that it is not placed on the upper part of the lower conductive pattern 10', but is self-aligned and provided only on the lower insulating film 100 that is exposed from the lower conductive pattern 10'. This intermediate insulating film 200 protrudes from the lower conductive pattern 10' and has a thickness that covers the lower conductive pattern 10' and the upper conductive pattern 20' from the upper part of the lower conductive pattern 10' to the lower part of the upper conductive pattern 20'. Furthermore, the upper and lower interfaces 200a and 200b of the intermediate insulating film 200 are located at a height of 1 nm or more away from the upper surface 10a of the lower conductive pattern 10'. In other words, the intermediate insulating film 200 covers the interface between the lower via V1 and the lower wiring M1 (specifically, around the interface in the height direction of the semiconductor device 1) in a configuration comprising a plurality of wirings including a lower wiring M1 and an upper wiring M2, a lower via V1 electrically connected to at least one of these plurality of wirings, and an upper wiring M2 electrically connected to the lower wiring M1 via the lower via V1. Here, the intermediate insulating film 200 is an example of a "first insulating layer". The lower via V1 is an example of a "via".

[0045] Such an intermediate insulating film 200 is the same as that of the first embodiment and consists of an insulating material such as aluminum oxide (AlOx), aluminum nitride (AlNx), silicon nitride (SiN), silicon carbonitride (SiCN), and SiCOH. Alternatively, both the lower insulating film 100 and the intermediate insulating film 200 may be made of SiCOH.

[0046] Furthermore, it is preferable that the intermediate insulating film 200 be made of a material with a higher film density than the lower insulating film 100 among these insulating materials. This makes it possible to ensure the breakdown voltage between the lower conductive patterns 10, between the upper conductive patterns 20, and between the lower conductive patterns 10 and the upper conductive patterns 20, as in the first embodiment.

[0047] [Upper Insulating Film 300] The upper insulating film 300 is provided so as to embed between a plurality of upper conductive patterns 20' on the intermediate insulating film 200. Such an upper insulating film 300 is preferably formed using a low dielectric constant material such as SiCOH. This can reduce the parasitic capacitance generated between adjacent upper conductive patterns 20', which is the same as in the first embodiment.

[0048] <Manufacturing Method of Semiconductor Device 2 of Second Embodiment>FIGS. 11 to 14 are process diagrams (Part 1) to (Part 4) showing the manufacturing method of the semiconductor device 2 of the second embodiment, and are drawings corresponding to the cross-sectional view in the X direction of FIG. 9. Hereinafter, the manufacturing method of the semiconductor device 2 of the second embodiment will be described based on these drawings.

[0049] First, as shown in FIG. 11, above a substrate not shown here, a lower wiring M1 serving as a lower conductive pattern 10' and a lower via V1 above it are formed by applying the subtractive method.

[0050] At this time, for example, a post-Cu material film such as Ru or Mo is formed on the substrate, and the post-Cu material film is patterned into the shape of the lower wiring M1 by reactive ion etching (RIE) using a resist pattern for wiring as a mask. Then, the upper part of the lower wiring shape made of the post-Cu material film is patterned into the shape of the lower via V1 by RIE using a resist pattern for via as a mask. Thereby, a lower conductive pattern 10' composed of the lower wiring M1 and the lower via V1 above it is formed.

[0051] Next, a lower insulating film 100 made of SiCOH, which is a low dielectric constant film with good gap filling characteristics, is formed so as to embed the lower conductive pattern 10'. Then, by CMP of the lower insulating film 100, the upper surface of the lower conductive pattern 10' is exposed.

[0052] Next, as shown in Figure 12, the upper part of the lower via V1 is exposed from the lower insulating film 100 by etch-back of the lower insulating film 100. In this case, if the lower insulating film 100 is made of SiCOH, the lower insulating film 100 is etch-back by dry etching using fluorocarbon gas. The exposure height [h] of the lower via V1 from the lower insulating film 100 is set to 1 nm or more.

[0053] Next, as shown in Figure 13, an intermediate insulating film 200 is formed with a thickness that protrudes from the lower conductive pattern 10', self-aligned with the lower insulating film 100. The formation of the intermediate insulating film 200 is carried out in the same manner as the procedure described with reference to Figure 5 in the first embodiment. Specifically, first, a SAM (self-assembled monolayer), which is not shown here, is formed to cover the exposed surface of the lower via V1. Then, the intermediate insulating film 200 is selectively formed on the exposed surface of the lower insulating film 100. The intermediate insulating film 200 formed here is, for example, an aluminum oxide (AlOx) film, but AlN, iCOH, SiCN, and SiN can also be selectively grown in the same manner. Furthermore, the film thickness [t] of the intermediate insulating film 200 is set to 2 nm or more, thereby keeping the upper surface 10a of the lower conductive pattern 10' at least 1 nm away from the upper and lower interfaces 200a and 200b of the intermediate insulating film 200, and suppressing dielectric breakdown between the lower conductive patterns 10' via the interfaces 200a and 200b.

[0054] Next, as shown in Figure 14, an upper conductive pattern 20' consisting of upper wiring M2 and upper vias V2 above it is formed on the upper part of the intermediate insulating film 200 and the lower conductive pattern 10' by applying the same subtractive method as in the formation of the lower conductive pattern 10'. In this process, the upper conductive pattern 20' consisting of upper wiring M2 and upper vias V2 above it is formed by pattern etching the post Cu material film using the intermediate insulating film 200 as an etching stopper.

[0055] After the above steps, with the upper conductive pattern 20' embedded, an upper insulating film 300 made of SiCOH, a low dielectric constant film with good gap-fill characteristics, is formed. Then, the surface of the upper conductive pattern 20' is exposed by CMP of the upper insulating film 300. This yields the semiconductor device 2 shown in Figures 9 and 10.

[0056] Furthermore, if an even higher conductive pattern is to be formed on top of the upper conductive pattern 20', the process described using Figure 12 and the subsequent processes can be repeated by replacing the upper conductive pattern 20' with the lower conductive pattern 10'.

[0057] <Effects of the Second Embodiment> The semiconductor device 2 of the second embodiment described above has a configuration in which the convex corner portion at the top of the lower conductive pattern 10', where the electric field tends to concentrate, is positioned at an intermediate position in the thickness direction of the intermediate insulating film 200. Therefore, dielectric breakdown between adjacent lower conductive patterns 10' can be prevented through the interface of the insulating film, and the breakdown voltage characteristics between the lower conductive patterns 10' can be improved.

[0058] Furthermore, the upper conductive pattern 20' is patterned on an intermediate insulating film 200 located above the upper surface 10a of the lower conductive pattern 10'. Therefore, compared to the case where the upper conductive pattern 20' is patterned at the same height as the upper surface 10a of the lower conductive pattern 10', the maximum line width [w2] of the upper conductive pattern 20' can be reduced. As a result, it becomes possible to widen the spacing between adjacent upper conductive patterns 20', thereby improving the breakdown voltage characteristics between the upper conductive patterns 20'.

[0059] <Third Embodiment> <Configuration of the Semiconductor Device of the Third Embodiment> Figure 15 is a cross-sectional view of the main part of the semiconductor device 3 of the third embodiment in the X direction. Figure 16 is a cross-sectional view of the main part of the semiconductor device 3 of the third embodiment in the Y direction, and is a cross-sectional view taken along line A-A in Figure 15. The semiconductor device 3 shown in these figures is a modified version of the semiconductor device 2 of the second embodiment, and the configuration of the lower conductive pattern 10" and the upper conductive pattern 20" differs from that of the semiconductor device 2 of the second embodiment. The other configurations are the same as in the second embodiment, so their explanation is omitted here.

[0060] [Underlayer conductive pattern 10''] The underlayer conductive pattern 10'' is a pattern formed by applying subtractive technology. The underlayer conductive pattern 10'' consists of an underlayer wiring M1, an underlayer via V1 placed on the underlayer wiring M1 and connected to the underlayer wiring M1, and a via cap layer V1a on the underlayer via V1. The underlayer wiring M1 and the underlayer via V1 may be integrally formed from molybdenum (Mo), a post-Cu material.

[0061] The via cap layer V1a is a layer provided to prevent oxidation of the lower via V1, and is composed of a post-Cu material that is less susceptible to oxidation than molybdenum (Mo) which constitutes the lower via V1 (for example, ruthenium (Ru)).

[0062] [Upper conductive pattern 20''] The upper conductive pattern 20'' is a pattern formed by applying subtractive technology. The upper conductive pattern 20'' consists of an upper wiring M2, an upper via V2 placed on the upper wiring M2 and connected to the upper wiring M2, and a via cap layer V2a of the upper via V2. The upper wiring M2 and the upper via V2 may be integrally formed from molybdenum (Mo), a post-Cu material.

[0063] The via cap layer V2a is a layer provided to prevent oxidation of the upper via V2, and is composed of a cap material (for example, ruthenium (Ru)) that is less susceptible to oxidation compared to molybdenum (Mo), which constitutes the upper via V2, among the post-Cu materials.

[0064] <Method for Manufacturing a Semiconductor Device of the Third Embodiment> The manufacturing of the semiconductor device 3 of the third embodiment described above can be achieved by adding a step of forming a film of a material (for example, ruthenium (Ru)) that will become the via cap layers V1a and V2a to the manufacturing of the semiconductor device of the second embodiment.

[0065] In other words, when forming the lower wiring M1 which will become the lower conductive pattern 10'', the lower via V1 above it, and the via cap layer V1a by the subtractive method, first a post Cu material film such as molybdenum (Mo) is deposited, and then an oxidation-resistant cap material film such as ruthenium (Ru) is deposited. After that, the cap material film and the post Cu material film are patterned to the shape of the lower wiring M1 using a resist pattern for wiring as a mask with a RIE. Then, the upper part of the lower wiring shape consisting of the cap material film and the post Cu material film is patterned to the shape of the via cap layer V1a and the lower via V1 using a resist pattern for vias with a RIE. This forms the lower conductive pattern 10'' consisting of the lower wiring M1 and the lower via V1 and via cap layer V1a above it.

[0066] Next, a lower insulating film 100 made of SiCOH, a low dielectric constant film with good gap sill properties, is deposited to embed the lower conductive pattern 10''. Then, the surface of the lower conductive pattern 10'' is exposed by CMP of the lower insulating film 100. Subsequently, the upper parts of the via cap layer V1a and lower via V1 are exposed from the lower insulating film 100 by etch-back of the lower insulating film 100. In this case, if the lower insulating film 100 is made of SiCOH, the lower insulating film 100 is etch-back by dry etching using fluorocarbon gas. The exposure height [h] of the lower via V1 and via cap layer V1a from the lower insulating film 100 is set to 1 nm or more.

[0067] Next, similar to the second embodiment, an intermediate insulating film 200 is formed on the exposed surface of the lower insulating film 100 by self-alignment technology.

[0068] Next, an upper conductive pattern 20" consisting of an upper wiring M2 and an upper via V2 and via cap layer V2a above it is formed on the upper part of the intermediate insulating film 200 by a subtractive method similar to that used for the lower conductive pattern 10". Subsequently, similar to the second embodiment, an upper insulating film 300 made of SiCOH, a low dielectric constant film with good gap sill characteristics, is deposited to embed the upper conductive pattern 20", and then the surface of the upper conductive pattern 20" is exposed by CMP of the upper insulating film 300. This gives rise to the semiconductor device 3.

[0069] <Effects of the Third Embodiment> In the semiconductor device 3 of the third embodiment described above, the uppermost parts of the lower conductive pattern 10" and the upper conductive pattern 20" are composed of via cap layers V1a and V2a that are resistant to oxidation. This makes it possible to further improve reliability by reducing the resistance of the lower conductive pattern 10" and the upper conductive pattern 20" and preventing oxidation, in addition to the effects of the second embodiment.

[0070] 1, 2, 3... Semiconductor equipment 10, 10', 10"... Lower conductive pattern 10a... Top surface (lower conductive pattern) 20, 20', 20"... Upper conductive pattern 100... Lower insulating film 100a... Trench 200... Intermediate insulating film 200a, 200b... Interface 300... Upper insulating film 300'... Upper barrier insulating film 300a... Via hole 300b... Trench 301... Via fan M1... Lower wiring M2... Upper wiring M1a, M2a... Cap layer V1... Lower via V2... Upper via V1a, V2a... Via cap layer

Claims

1. A semiconductor device comprising: a plurality of lower conductive patterns formed on the upper part of a substrate; a lower insulating film that fills the spaces between the plurality of lower conductive patterns with the upper parts of the plurality of lower conductive patterns protruding; an intermediate insulating film that is provided with a thickness that protrudes from the lower conductive patterns and is self-aligned with the lower insulating film; a plurality of upper conductive patterns that protrude from the intermediate insulating film and are bonded to the plurality of lower conductive patterns between the intermediate insulating films; and an upper insulating film provided above the intermediate insulating film that fills the spaces between the plurality of upper conductive patterns.

2. The semiconductor device according to claim 1, wherein the intermediate insulating film is made of at least one aluminum-based material selected from the group consisting of aluminum oxide and aluminum nitride, or at least one silicon-based material selected from the group consisting of silicon nitride, silicon carbonitride, and silicon hydride carbonate.

3. The semiconductor device according to claim 1, wherein the intermediate insulating film is denser than the lower insulating film.

4. The semiconductor device according to claim 3, wherein the intermediate insulating film is composed of aluminum oxide or aluminum nitride.

5. The semiconductor device according to claim 1, wherein the upper and lower interfaces of the intermediate insulating film are arranged at a height of 1 nm or more away from the upper surface of the lower conductive pattern.

6. The semiconductor device according to claim 1, wherein the lower conductive pattern and the uppermost part of the upper conductive pattern are composed of an anti-oxidation cap layer.

7. The semiconductor device according to claim 1, wherein the upper conductive pattern is composed of vias arranged to bond to the lower conductive pattern between the intermediate insulating films and wiring embedded in the surface layer of the upper insulating film above the vias, and the intermediate insulating film is made of a material resistant to etching of the upper insulating film.

8. The semiconductor device according to claim 2, wherein the upper conductive pattern is composed of vias arranged to bond to the lower conductive pattern between the intermediate insulating films, and wiring embedded in the surface layer of the upper insulating film above the vias, and further comprising a barrier insulating film that is denser than the lower insulating film, covering the intermediate insulating film and the surface of the lower conductive pattern to which the vias are not connected, below the upper insulating film.

9. The semiconductor device according to claim 1, wherein the lower conductive pattern is composed of vias arranged to bond to the upper conductive pattern between the intermediate insulating films and wiring embedded in the lower insulating film below the vias, and the vias have a tapered shape with increasing line width towards the bottom.

10. The semiconductor device according to claim 1, wherein the plurality of lower conductive patterns and the upper conductive patterns are formed of a post-Cu material having a mean free path of electrons smaller than that of copper.

11. The semiconductor device according to claim 9 or 10, wherein the lower conductive pattern further comprises a cap layer disposed between the via and the upper conductive pattern.

12. A semiconductor device comprising: a plurality of wirings; vias electrically connected to at least one lower wiring among the plurality of wirings; upper wiring electrically connected to at least one lower wiring via the vias; and a first insulating layer covering the interface between the vias and the at least one lower wiring.

13. A method for manufacturing a semiconductor device, comprising the steps of: forming a plurality of lower conductive patterns and a lower insulating film that fills the spaces between the plurality of lower conductive patterns on a substrate; etching back the lower insulating film to cause the upper parts of the lower conductive patterns to protrude from the lower insulating film; forming an intermediate insulating film with a thickness that protrudes from the lower conductive patterns in a self-aligned manner with respect to the lower insulating film; and forming a plurality of upper conductive patterns that are bonded to the plurality of lower conductive patterns between the intermediate insulating films and an upper insulating film that fills the spaces between the plurality of upper conductive patterns on top of the intermediate insulating film.

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