Semiconductor device comprising self-aligned openings and manufacturing method therefor
By forming signal lines with insulating spacers and using a photoresist pattern as a mask, the alignment margin of openings in vertical channel transistors is enhanced, ensuring precise opening formation and maintaining device performance.
Patent Information
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- INDUSTRY UNIVERSITY COOPERATION FOUNDATION HANYANG UNIVERSITY
- Filing Date
- 2025-11-13
- Publication Date
- 2026-05-21
AI Technical Summary
The alignment margin during the formation of openings that penetrate an upper electrode and expose a lower electrode in vertical channel thin-film transistors is prone to errors, affecting device performance.
A method involving the formation of first and second signal lines with insulating spacers on both sides, followed by the creation of an opening using a photoresist pattern as a mask, ensures self-alignment of the opening with the signal lines, enhancing alignment precision.
The method improves the alignment margin of the opening, allowing for increased allowable alignment errors without compromising device performance.
Smart Images
Figure KR2025018673_21052026_PF_FP_ABST
Abstract
Description
Semiconductor device including self-aligned openings and method for manufacturing the same
[0001] The present invention relates to a semiconductor device, and more specifically, to a semiconductor device having an opening formed therein.
[0002] As for the silicon film used as a semiconductor film for thin-film transistors, either an amorphous silicon film or a polycrystalline silicon film is used depending on the purpose. For example, in the case of transistors included in large display devices, it is preferable to use an amorphous silicon film, which can form relatively uniform characteristics even when formed over a large area. On the other hand, in the case of devices including driving circuits, it is preferable to use a polycrystalline silicon film, which can exhibit high field-effect mobility. As a method for forming the polycrystalline silicon film, methods are known to involve high-temperature heat treatment of the amorphous silicon film or treatment with laser light.
[0003] Vertical channel thin-film transistors are being developed to improve the integration density of such thin-film transistors. Corresponding structures include the Channel-All-Around (CAA) structure, in which the channel surrounds the device, and the Gate-All-Around (GAA) structure, in which the gate surrounds the device.
[0004] In such vertical channel thin-film transistors, an opening is formed within the intersection region between the lower and upper electrodes, penetrating the upper electrode and exposing the lower electrode; however, if an alignment error exceeding the alignment margin occurs during the formation of this opening, the performance of the device may deteriorate.
[0005] The problem that the present invention aims to solve is to provide a method that can improve the alignment margin of an opening that penetrates an upper electrode and exposes a lower electrode.
[0006] The technical problems of the present invention are not limited to those mentioned above, and other unmentioned technical problems will be clearly understood by those skilled in the art from the description below.
[0007] To achieve the above objective, one aspect of the present invention provides a method for manufacturing a semiconductor device. First, a first signal line extending in a first direction and first insulating patterns disposed on both sides thereof are formed on a substrate. Here, the upper surface of the first signal line is lower than the upper surface of the first insulating patterns, so that the sidewalls of the first insulating patterns are exposed on both sides of the first signal line. First insulating spacers are formed on the sidewalls of the first insulating patterns exposed on both sides of the first signal line. On the substrate on which the first insulating spacers are formed, a first interlayer insulating film covering the first signal line, the first insulating patterns, and the first insulating spacers is formed. On the first interlayer insulating film, a second signal line extending in a second direction intersecting the first signal line and second insulating patterns disposed on both sides thereof are formed. Here, the upper surface of the second signal line is lower than the upper surface of the second insulation patterns, so that the sidewalls of the second insulation patterns are exposed on both sides of the second signal line. Second insulation spacers are formed on the sidewalls of the second insulation patterns exposed on both sides of the second signal line. A second interlayer insulating film covering the second signal line, the second insulation patterns, and the second insulation spacers is formed on the substrate on which the second insulation spacers are formed. An opening is formed within the second interlayer insulating film that penetrates the region where the second signal line intersects the first signal line and exposes the first signal line within the bottom.
[0008] The step of forming the first signal line and the first insulation patterns disposed on both sides thereof may include forming the first signal line and the first insulation patterns such that the upper surface of the first signal line and the upper surface of the first insulation patterns are at the same level, and then recessing the first signal line.
[0009] The step of forming the second signal line and the second insulation patterns disposed on both sides thereof may include forming the second signal line and the second insulation patterns such that the upper surface of the second signal line and the upper surface of the second insulation patterns are at the same level, and then recessing the second signal line.
[0010] The first insulating patterns, the first insulating spacers, the second insulating patterns, and the second insulating spacers are silicon nitride films, and the first interlayer insulating film and the second interlayer insulating film may be silicon oxide films.
[0011] The above opening can be formed by forming a photoresist pattern having a hole above the area where the second signal line intersects the first signal line on the second interlayer insulating film, and etching the second interlayer insulating film, the second signal line, and the first interlayer insulating film in sequence using the photoresist pattern as a mask. When etching the second interlayer insulating film, the second insulating spacers remain, and the second insulating spacers can act as an etching mask during the process of etching the second signal line located below them. When etching the first interlayer insulating film, the first insulating spacers may remain.
[0012] The first insulating spacers, the first interlayer insulating film, the second signal lines, and the second interlayer insulating film may be exposed sequentially from bottom to top within the side walls on both sides in the second direction of the opening. The first interlayer insulating film, the second signal lines, the second insulating spacers, and the second interlayer insulating film may be exposed sequentially from bottom to top within the side walls on both sides in the first direction of the opening.
[0013] In one example, the method further includes the step of forming a gate insulating film covering the sidewall of the opening, wherein a portion of a first signal line that is not covered by the gate insulating film may be exposed within the bottom of the opening. A channel layer may be formed on the first signal line exposed within the bottom of the opening and on the gate insulating film. An electrode pattern connected to the channel layer may be formed. The first signal line may be a first source / drain electrode, the second signal line may be a gate electrode, and the electrode pattern may be a second source / drain electrode.
[0014] In another example, a channel layer covering the bottom and sidewalls of the opening may be formed. A gate insulating film may be formed on the channel layer. An electrode pattern may be formed on the gate insulating film. The first signal line may be a first source / drain electrode, the second signal line may be a second source / drain electrode, and the electrode pattern may be a gate electrode.
[0015] In another example, an electrode pattern covering the bottom and side walls of the opening can be formed. The electrode pattern may be a via electrode.
[0016] To achieve the above objective, another aspect of the present invention provides a semiconductor device. The semiconductor device comprises a first signal line extending in a first direction on a substrate and first insulating patterns disposed on both sides thereof. Here, the upper surface of the first signal line is lower than the upper surface of the first insulating patterns, so that the sidewalls of the first insulating patterns are exposed on both sides of the first signal line. First insulating spacers are disposed on the sidewalls of the first insulating patterns exposed on both sides of the first signal line. The first signal line, the first insulating patterns, and the first insulating spacers are covered by a first interlayer insulating film. A second signal line extending in a second direction intersecting the first signal line and second insulating patterns are disposed on both sides thereof on the first interlayer insulating film. Here, the upper surface of the second signal line is lower than the upper surface of the second insulating patterns, so that the sidewalls of the second insulating patterns are exposed on both sides of the second signal line. Second insulating spacers are respectively disposed on the sidewalls of the second insulating patterns exposed on both sides of the second signal line. The second interlayer insulating film covers the second signal line, the second insulating patterns, and the second insulating spacers. An opening is disposed within the second interlayer insulating film that penetrates the area where the second signal line intersects the first signal line and exposes the first signal line within the bottom.
[0017] The first insulating patterns, the first insulating spacers, the second insulating patterns, and the second insulating spacers are silicon nitride films, and the first interlayer insulating film and the second interlayer insulating film may be silicon oxide films.
[0018] The first insulating spacers, the first interlayer insulating film, the second signal lines, and the second interlayer insulating film may be exposed sequentially from bottom to top within the side walls on both sides in the second direction of the opening, and the first interlayer insulating film, the second signal lines, the second insulating spacers, and the second interlayer insulating film may be exposed sequentially from bottom to top within the side walls on both sides in the first direction of the opening.
[0019] In one example, a gate insulating film may cover the sidewall of the opening. Here, a portion of a first signal line that is not covered by the gate insulating film may be exposed within the bottom of the opening. A channel layer may be disposed on the first signal line exposed within the bottom of the opening and on the gate insulating film. An electrode pattern may be connected to the channel layer. The first signal line may be a first source / drain electrode, the second signal line may be a gate electrode, and the electrode pattern may be a second source / drain electrode.
[0020] In another example, the bottom and sidewalls of the opening may be covered by a channel layer. A gate insulating film may be disposed on the channel layer. An electrode pattern may be disposed on the gate insulating film. The first signal line may be a first source / drain electrode, the second signal line may be a second source / drain electrode, and the electrode pattern may be a gate electrode.
[0021] In another example, the bottom and side walls of the opening may be covered with an electrode pattern. The electrode pattern may be a via electrode.
[0022] In a semiconductor device according to embodiments of the present invention, the opening can be self-aligned with the first signal line and the second signal line by means of the first insulating spacers and the second insulating spacers. As a result, the alignment margin when forming the opening can be improved.
[0023] However, the effects of the present invention are not limited to those mentioned above, and other unmentioned effects will be clearly understood by those skilled in the art from the description below.
[0024] FIG. 1 is a layout diagram showing a state in which an opening is formed in which a first signal line and a second signal line are respectively exposed on the bottom and the side face during a method for manufacturing a semiconductor device according to one embodiment of the present invention.
[0025] FIGS. 2a, FIGS. 3a, FIGS. 4a, FIGS. 5a, FIGS. 6a, FIGS. 7a, FIGS. 8a, FIGS. 9a, and FIGS. 10a are perspective views showing a method for forming an opening shown in FIG. 1 in process steps.
[0026] FIGS. 2b, FIGS. 3b, FIGS. 4b, FIGS. 5b, FIGS. 6b, FIGS. 7b, FIGS. 8b, FIGS. 9b, and FIGS. 10b are cross-sectional views taken according to process steps along the cutting line II′ of FIGS. 1, corresponding to the cross-sectional views taken along the cutting line II′ of FIGS. 2a, FIGS. 3a, FIGS. 4a, FIGS. 5a, FIGS. 6a, FIGS. 7a, FIGS. 8a, FIGS. 9a, and FIGS. 10a, respectively.
[0027] FIGS. 2c, FIGS. 3c, FIGS. 4c, FIGS. 5c, FIGS. 6c, FIGS. 7c, FIGS. 8c, FIGS. 9c, and FIGS. 10c are cross-sectional views taken at each process step along the cutting line Ⅱ-Ⅱ′ of FIGS. 1, and correspond to the cross-sectional views taken along the cutting line Ⅱ-Ⅱ′ of FIGS. 2a, FIGS. 3a, FIGS. 4a, FIGS. 5a, FIGS. 6a, FIGS. 7a, FIGS. 8a, FIGS. 9a, and FIGS. 10a, respectively.
[0028] FIG. 11 is a layout diagram showing a vertical channel transistor as an example of a semiconductor device including the opening shown in FIG. 1.
[0029] FIG. 12a is a perspective view of the vertical channel transistor shown in FIG. 11, showing the process after forming the opening shown in FIG. 11a.
[0030] FIG. 12b is a cross-sectional view taken along the cutting line II′ of FIG. 11 and FIG. 12a, and FIG. 12c is a cross-sectional view taken along the cutting line II-II′ of FIG. 11 and FIG. 12a.
[0031] FIG. 13 is a layout diagram showing a vertical channel transistor as another example of a semiconductor device including the opening shown in FIG. 1.
[0032] FIG. 14a is a perspective view of the vertical channel transistor shown in FIG. 13, showing the process after forming the opening shown in FIG. 11a.
[0033] FIG. 14b is a cross-sectional view taken along the cutting line II′ of FIG. 13 and FIG. 14a, and FIG. 14c is a cross-sectional view taken along the cutting line II-II′ of FIG. 13 and FIG. 14a.
[0034] FIG. 15 is a layout diagram showing another example of a semiconductor device including the opening shown in FIG. 1.
[0035] [Correction pursuant to Rule 91 25.11.2025] FIG. 16a is a cross-sectional view taken along the cutting line II′ of FIG. 15, and FIG. 16b is a cross-sectional view taken along the cutting line II-II′ of FIG. 15.
[0036] Hereinafter, preferred embodiments according to the present invention will be described in more detail with reference to the accompanying drawings in order to explain the present invention more specifically. However, the present invention is not limited to the embodiments described herein and may be embodied in other forms. In the drawings, where a layer is referred to as being "on" another layer or substrate, it may be formed directly on the other layer or substrate, or a third layer may be interposed between them. In these embodiments, "first," "second," or "third" are not intended to impose any limitations on the components, but should be understood merely as terms to distinguish the components.
[0037]
[0038] FIG. 1 is a layout diagram showing a state in which an opening is formed in which a first signal line and a second signal line are respectively exposed on the bottom and the side face during a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 2a, FIG. 3a, FIG. 4a, FIG. 5a, FIG. 6a, FIG. 7a, FIG. 8a, FIG. 9a, and FIG. 10a are perspective views showing a method for forming the opening shown in FIG. 1 in a process step. FIG. 2b, FIG. 3b, FIG. 4b, FIG. 5b, FIG. 6b, FIG. 7b, FIG. 8b, FIG. 9b, and FIG. 10b are cross-sectional views taken in a process step along the cutting line II′ of FIG. 1, corresponding to the cross-sectional views taken along the cutting line II′ of FIG. 2a, FIG. 3a, FIG. 4a, FIG. 5a, FIG. 6a, FIG. 7a, FIG. 8a, FIG. 9a, and FIG. 10a, respectively. FIGS. 2c, FIGS. 3c, FIGS. 4c, FIGS. 5c, FIGS. 6c, FIGS. 7c, FIGS. 8c, FIGS. 9c, and FIGS. 10c are cross-sectional views taken at each process step along the cutting line Ⅱ-Ⅱ′ of FIGS. 1, and correspond to the cross-sectional views taken along the cutting line Ⅱ-Ⅱ′ of FIGS. 2a, FIGS. 3a, FIGS. 4a, FIGS. 5a, FIGS. 6a, FIGS. 7a, FIGS. 8a, FIGS. 9a, and FIGS. 10a, respectively.
[0039] Referring to FIG. 1, FIG. 2a, FIG. 2b, and FIG. 2c, a substrate (100) may be provided. The substrate (100) may be a semiconductor substrate such as a silicon substrate or a GaAs substrate, an insulating substrate such as a glass substrate or sapphire, or a polymer substrate.
[0040] A base insulating film (110) may be disposed on a substrate (100). The base insulating film (110) may be a silicon oxide film, a silicon nitride film, or a silicon oxynitride film, but is not limited thereto. In one example, the substrate (100) may be a silicon substrate, and the base insulating film (110) may be a silicon oxide film. Additionally, other components may be disposed within the base insulating film (110).
[0041] A first signal line (130) extending in a first direction, specifically in the Y-axis direction, and first insulation patterns (123) disposed on both sides thereof can be formed on a base insulating film (110). In one example, when multiple first signal lines (130) are formed, multiple first insulation patterns (123) extending in the Y-axis direction can be formed between adjacent parallel first signal lines (130). In this case, the first insulation patterns (123) and the first signal lines (130) can be alternately arranged in the X-axis direction. The upper surface of the first signal lines (130) and the upper surface of the first insulation patterns (123) may have the same level.
[0042] In one example, a first insulating layer is formed on a base insulating film (110), and then patterned to form first insulating patterns (123) that are parallel to each other and extend in the Y-axis direction, and a first conductive layer is formed on top of the first insulating patterns (123), and the formed first conductive layer is polished until the surface of the first insulating patterns (123) is exposed to form first signal lines (130) located between the first insulating patterns (123) that are adjacent to each other. In another example, a first conductive layer is formed on a base insulating film (110), and then patterned to form first signal lines (130) that are parallel to each other and extend in the Y-axis direction, and then a first insulating layer is formed on top of the first insulating layer, and the formed first insulating layer is polished until the surface of the first signal lines (130) is exposed to form first insulating patterns (123) located between the first signal lines (130) that are adjacent to each other. Here, polishing can be chemical mechanical polishing (CMP).
[0043] The first insulating layer and the first insulating patterns (123) formed therefrom may be a silicon oxide film, a silicon nitride film, or a silicon oxynitride film, but are not limited thereto. In one example, the first insulating layer and the first insulating patterns (123) may be a silicon nitride film.
[0044] The first conductive layer and the first signal lines (130) formed therefrom may include a conductive metal such as platinum (Pt), ruthenium (Ru), iridium (Ir), silver (Ag), aluminum (Al), titanium (Ti), tantalum (Ta), tungsten (W), silicon (Si), copper (Cu), nickel (Ni), cobalt (Co), or molybdenum (Mo), or an alloy thereof, but are not limited thereto.
[0045] Referring to FIGS. 1, FIGS. 3a, FIGS. 3b, and FIGS. 3c, the first signal lines (130) can be selectively recessed so that the level of the upper surface of the first signal lines (130) is lower than the level of the upper surface of the first insulation patterns (123). As a result, the sidewalls of the first insulation patterns (123) can be exposed on both sides of each first signal line (130). The recessing can be performed using an anisotropic dry etching method.
[0046] Referring to FIGS. 1, FIGS. 4a, FIGS. 4b, and FIGS. 4c, first insulating spacers (125) can be formed on the sidewalls of first insulating patterns (123) exposed on both sides of each recessed first signal line (130). Specifically, after forming a first spacer layer on the recessed first signal lines (130) and the first insulating patterns (123), the first insulating spacers (125) can be formed by anisotropic dry etching of the first spacer layer. The first spacer layer and the first insulating spacers (125) formed therefrom may be a silicon oxide film, a silicon nitride film, or a silicon oxynitride film, but are not limited thereto. In one example, the first spacer layer and the first insulating spacers (125) formed therefrom may be a silicon nitride film.
[0047] Referring to FIGS. 1, FIGS. 5a, FIGS. 5b, and FIGS. 5c, first signal lines (130), first insulating patterns (123), and a first interlayer insulating film (140) covering the first insulating spacers (125) can be formed on a substrate on which first insulating spacers (125) are formed. The first interlayer insulating film (140) is an insulating film having an etching selectivity ratio with respect to the first insulating patterns (123) and the first insulating spacers (125), and may be a silicon oxide film, a silicon nitride film, or a silicon oxynitride film. In one example, when the first insulating patterns (123) and the first insulating spacers (125) are silicon nitride films, the first interlayer insulating film (140) may be a silicon oxide film.
[0048] Referring to FIG. 1, FIG. 6a, FIG. 6b, and FIG. 6c, a plurality of second insulation patterns (143) extending in the X-axis direction can be formed on the first interlayer insulating film (140) and positioned between adjacent second signal lines (150) and a plurality of mutually parallel second signal lines (150) that intersect with the first signal lines (130). Specifically, the second insulation patterns (143) and the second signal lines (150) can be alternately arranged in the Y-axis direction. Furthermore, the second insulation patterns (143) can be arranged on both sides of a single second signal line (150) extending in one direction. The upper surface of the second signal lines (150) and the upper surface of the second insulation patterns (143) can have the same level.
[0049] In one example, a second insulating layer is formed on a first interlayer insulating film (140), and then patterned to form second insulating patterns (143) extending in the X-axis direction. A second conductive layer is formed on top of the second insulating patterns, and the formed second conductive layer is polished until the surface of the second insulating patterns (143) is exposed to form second signal lines (150) located between adjacent second insulating patterns (143). In another example, a second conductive layer is formed on a first interlayer insulating film (140), and then patterned to form second signal lines (150) extending in the X-axis direction. A second insulating layer is formed on top of the second insulating layer, and the formed second insulating layer is polished until the surface of the second signal lines (150) is exposed to form second insulating patterns (143) located between adjacent second signal lines (150). Here, polishing can be chemical mechanical polishing (CMP).
[0050] The second insulating layer and the second insulating patterns (143) formed therefrom may be a silicon oxide film, a silicon nitride film, or a silicon oxynitride film, but are not limited thereto. In one example, the second insulating layer and the second insulating patterns (143) may be a silicon nitride film.
[0051] The second conductive layer and the second signal lines (150) formed therefrom may include a conductive metal such as platinum (Pt), ruthenium (Ru), iridium (Ir), silver (Ag), aluminum (Al), titanium (Ti), tantalum (Ta), tungsten (W), silicon (Si), copper (Cu), nickel (Ni), cobalt (Co), or molybdenum (Mo), or an alloy thereof, but are not limited thereto.
[0052] Referring to FIG. 1, FIG. 7a, FIG. 7b, and FIG. 7c, the second signal lines (150) can be selectively recessed so that the level of the upper surface of the second signal lines (150) is lower than the level of the upper surface of the second insulation patterns (143). As a result, the sidewalls of the second insulation patterns (143) can be exposed on both sides of each second signal line (150). The recessing can be performed using an anisotropic dry etching method.
[0053] Referring to FIGS. 1, FIGS. 8a, FIGS. 8b, and FIGS. 8c, second insulating spacers (145) can be formed on the sidewalls of second insulating patterns (143) exposed on both sides of each second signal line (150). Specifically, after forming a second spacer layer on the recessed second signal lines (150) and the second insulating patterns (143), the second insulating spacers (145) can be formed by anisotropic dry etching of the second spacer layer. The second spacer layer and the second insulating spacers (145) formed therefrom may be a silicon oxide film, a silicon nitride film, or a silicon oxynitride film, but are not limited thereto. In one example, the second spacer layer and the second insulating spacers (145) formed therefrom may be a silicon nitride film.
[0054] Referring to FIGS. 1, FIGS. 9a, FIGS. 9b, and FIGS. 9c, second signal lines (150), second insulating patterns (143), and a second interlayer insulating film (160) covering the second insulating spacers (145) can be formed on a substrate on which second insulating spacers (145) are formed. The second interlayer insulating film (160) is an insulating film having an etching selectivity ratio with respect to the second insulating patterns (143) and the second insulating spacers (145), and may be a silicon oxide film, a silicon nitride film, or a silicon oxynitride film. In one example, when the second insulating patterns (143) and the second insulating spacers (145) are silicon nitride films, the second interlayer insulating film (160) may be a silicon oxide film.
[0055] Referring to FIG. 1, FIG. 10a, FIG. 10b, and FIG. 10c, a photoresist pattern (not shown) having holes on each of the intersection regions where a plurality of first signal lines (130) extending in the Y-axis direction and a plurality of second signal lines (150) extending in the X-axis direction intersect is formed on a second interlayer insulating film (160), and the second interlayer insulating film (160), the second signal lines (150), and the first interlayer insulating film (140) are etched in sequence using the photoresist pattern as a mask to form openings (H) on the bottom in which the first signal lines (130) are each exposed.
[0056] As previously described, the second interlayer insulating film (160) is an insulating film having an etching selectivity ratio with respect to the second insulating spacers (145), so that when the second interlayer insulating film (160) is etched, the second insulating spacers (145) may remain without being etched. The remaining second insulating spacers (145) may act as an etching mask during the process of etching the second signal lines (150) located below them. Additionally, as previously described, the first interlayer insulating film (140) is an insulating film having an etching selectivity ratio with respect to the first insulating spacers (125), so that when the first interlayer insulating film (140) is etched, the first insulating spacers (125) may remain without being etched. Accordingly, a first signal line (130) may be exposed within the bottom of each opening (H), a pair of first insulating spacers (125) may remain within the side walls on both sides in the X-axis direction, and a pair of second insulating spacers (145) may remain within the side walls on both sides in the Y-axis direction. Additionally, the first insulating spacers (125), the first interlayer insulating film (140), the second signal lines (150), and the second interlayer insulating film (160) may be exposed sequentially from bottom to top within the side walls on both sides in the X-axis direction of the opening (H), and the first interlayer insulating film (140), the second signal lines (150), the second insulating spacers (145), and the second interlayer insulating film (160) may be exposed sequentially from bottom to top within the side walls on both sides in the Y-axis direction of the opening (H).
[0057] In this way, each opening (H) may be formed to have a width (Hw1) smaller than the width (130w) of the first signal line (130) by means of first insulating spacers (125) near the first signal line (130), and may also be formed to have a width (Hw2) smaller than the width (150w) of the second signal line (150) by means of second insulating spacers (145) near the second signal line (150). Accordingly, by means of the first insulating spacers (125) and second insulating spacers (145) remaining within each opening (H), the opening (H) may be self-aligned with the first signal line (130) and the second signal line (150). As a result, the alignment margin when forming the opening (H) may be improved. To elaborate, when forming the opening (H), the maximum allowable alignment error value can be increased without affecting the device performance.
[0058]
[0059] FIG. 11 is a layout diagram showing a vertical channel transistor as an example of a semiconductor device including the aperture shown in FIG. 1. FIG. 12a is a perspective view of the vertical channel thin-film transistor shown in FIG. 11, showing the process after forming the aperture shown in FIG. 11a. FIG. 12b is a cross-sectional view taken along the cutting line II′ of FIG. 11 and FIG. 12a, and FIG. 12c is a cross-sectional view taken along the cutting line II-II′ of FIG. 11 and FIG. 12a.
[0060] Referring to FIG. 11, FIG. 12a, FIG. 12b, and FIG. 12c, a gate insulating film (170) can be formed to cover the side wall of the opening (H). At this time, a portion of the first signal line (130) that is not covered by the gate insulating film (170) may be exposed within the bottom of the opening (H).
[0061] Specifically, to this end, a gate insulating film (170) can be conformally formed to overlap the bottom surface and the side surface within the opening (H). The gate insulating film (170) may be a silicon oxide film, a silicon nitride film, or a silicon oxynitride film, or may include a high dielectric constant film such as aluminum oxide (e.g., Al2O3), hafnium oxide (e.g., HfO2), lanthanum oxide (e.g., La2O3), or zirconium oxide (e.g., ZrO2), or may include a combination of two or more of the aforementioned materials. However, it is not limited thereto. The gate insulating film (170) may be formed using an atomic layer deposition (ALD) method, but is not limited thereto.
[0062] A gate insulating film (170) can be patterned to form a contact hole (170a) that exposes a first signal line (130) while being surrounded by the gate insulating film (170) within the bottom surface of the opening (H). In one example, such a contact hole (170a) can be formed by conformally forming a sacrificial film (not shown) that overlaps with the bottom surface and side wall within the opening (H) where the gate insulating film (170) is formed, then anisotropically etching the sacrificial film to form a sacrificial pattern (not shown) that is located only on the side wall of the opening (H) and exposes the gate insulating film (170) above the first signal line (130), and then etching the gate insulating film (170) using this sacrificial pattern as a mask. The above sacrificial layer is a layer having an etching selectivity ratio with respect to the gate insulating layer (170), and as an example, it may be an amorphous carbon layer (ACL), but is not limited thereto. Afterwards, the sacrificial pattern located on the side wall within the opening (H) can be removed to expose the gate insulating layer (170) below it.
[0063] A channel layer can be formed and patterned on the exposed gate insulating film (170). The patterned channel layer (180) may be connected to a first signal line (130) located within the bottom surface of the opening (H) and may overlap with a second signal line (150) located within the side wall of the opening (H). Meanwhile, the patterned channel layer (180) may be extended onto a second interlayer insulating film (160) adjacent to the opening (H) but may be confined and arranged within a unit cell region (UC). In one example, the patterned channel layer (180) may be aligned with the area where the second signal line (150) and the first signal line (130) overlap when viewed from above, and may have an area substantially equal to or slightly larger than the area where the second signal line (150) and the first signal line (130) overlap.
[0064] The channel layer (180) may be an n-type or p-type polysilicon layer or an oxide semiconductor layer. The oxide semiconductor layer may be an In-Ga oxide semiconductor layer, an In-Zn oxide semiconductor layer, or an In-Ga-Zn oxide semiconductor layer, but is not limited thereto. The channel layer (180) may be formed using an atomic layer deposition (ALD) method, but is not limited thereto.
[0065] An internal insulating film (175) may be formed on the channel layer (180) such that it can fill the opening (H) formed by the gate insulating film (170) and the channel layer (180). The internal insulating film (175) may be referred to as a gap-fill dielectric and, as an example, may be a silicon oxide film. Subsequently, the internal insulating film (175) may be polished using chemical mechanical polishing (CMP) until the channel layer (180) is exposed. As a result, the internal insulating film (175) and the channel layer (180) may have upper surfaces at substantially the same level.
[0066] After forming a third conductive layer connected thereto on the channel layer (180), the electrode pattern (190) can be formed by patterning it. The electrode pattern (190) may include a conductive metal such as platinum (Pt), ruthenium (Ru), iridium (Ir), silver (Ag), aluminum (Al), titanium (Ti), tantalum (Ta), tungsten (W), silicon (Si), copper (Cu), nickel (Ni), cobalt (Co), or molybdenum (Mo), or an alloy thereof, but is not limited thereto.
[0067] The first signal lines (130) may be bit lines, the second signal lines (150) may be word lines, and the electrode pattern (190) may be a source / drain electrode. In a vertical channel transistor in a unit cell (UC) region, the first signal line (130) may be a first source / drain electrode, the second signal line (150) may be a gate electrode, and the electrode pattern (190) may be a second source / drain electrode.
[0068]
[0069] FIG. 13 is a layout diagram showing a vertical channel transistor, which is another example of a semiconductor device including the aperture shown in FIG. 1. FIG. 14a is a perspective view of the vertical channel transistor shown in FIG. 13, showing the process after forming the aperture shown in FIG. 11a. FIG. 14b is a cross-sectional view taken along the cutting line II′ of FIG. 13 and FIG. 14a, and FIG. 14c is a cross-sectional view taken along the cutting line II-II′ of FIG. 13 and FIG. 14a.
[0070] Referring to FIG. 13, FIG. 14a, FIG. 14b, and FIG. 14c, a channel layer (180) covering the bottom surface and side of the opening (H) can be conformally formed. The channel layer (180) can be connected to a first signal line (130) exposed within the bottom surface of the opening (H), and can also be connected to a second signal line (150) exposed within the side wall of the opening (H).
[0071] The channel layer (180) may be an n-type or p-type polysilicon layer or an oxide semiconductor layer. The oxide semiconductor layer may be an In-Ga oxide semiconductor layer, an In-Zn oxide semiconductor layer, or an In-Ga-Zn oxide semiconductor layer, but is not limited thereto. The channel layer (180) may be formed using an atomic layer deposition (ALD) method, but is not limited thereto.
[0072] A gate insulating film (170) can be conformally formed on the channel layer (180) overlapping the bottom surface and side surface within the opening (H). The gate insulating film (170) may be a silicon oxide film, a silicon nitride film, or a silicon oxynitride film, or may include a high dielectric constant film such as aluminum oxide (e.g., Al2O3), hafnium oxide (e.g., HfO2), lanthanum oxide (e.g., La2O3), or zirconium oxide (e.g., ZrO2), or may include a combination of two or more of the aforementioned materials. However, it is not limited thereto. The gate insulating film (170) may be formed using an atomic layer deposition (ALD) method, but is not limited thereto.
[0073] An electrode pattern (200) can be formed by patterning a third conductive layer formed on the gate insulating film (170). The electrode pattern (200) can be formed to fill the opening (H) formed by the channel layer (180) and the gate insulating film (170). The electrode pattern (200) may include a conductive metal such as platinum (Pt), ruthenium (Ru), iridium (Ir), silver (Ag), aluminum (Al), titanium (Ti), tantalum (Ta), tungsten (W), silicon (Si), copper (Cu), nickel (Ni), cobalt (Co), or molybdenum (Mo), or an alloy thereof. These materials are exemplary and the present invention is not limited thereto. For example, the electrode pattern (200) may include a conductive nitride of the aforementioned metals (e.g., TiN, MoN, etc.), a conductive oxynitride (e.g., TiON, etc.), or a combination thereof (e.g., TiSiN, TiAlON, etc.). Alternatively, the electrode pattern (200) may include polysilicon that is over-doped with impurities.
[0074] When forming the electrode pattern (200), the gate insulating film (170) and the channel layer (180) located below the electrode pattern (200) may also be patterned on the second interlayer insulating film (160).
[0075] Meanwhile, the electrode pattern (200) may be extended onto the second interlayer insulating film (160) adjacent to the opening (H) and may be confined to a unit cell area (UC). In one example, the electrode pattern (200) may be aligned with the area where the second signal line (150) and the first signal line (130) overlap when viewed from above, and may have an area substantially equal to or slightly larger than the area where the second signal line (150) and the first signal line (130) overlap.
[0076] In a vertical channel transistor in a unit cell (UC) region, the first signal line (130) may be a first source / drain electrode, the second signal line (150) may be a second source / drain electrode, and the electrode pattern (200) may be a gate electrode.
[0077]
[0078] FIG. 15 is a layout diagram showing another example of a semiconductor device including the opening shown in FIG. 1. FIG. 16a is a cross-sectional view taken along the cutting line II′ of FIG. 15, and FIG. 16b is a cross-sectional view taken along the cutting line II-II′ of FIG. 15.
[0079] In this embodiment, unlike as illustrated in FIG. 1, only one first signal line (130) is formed instead of multiple mutually parallel first signal lines (130), and only one first signal line (150) is formed instead of multiple mutually parallel second signal lines (150).
[0080] Referring to FIGS. 15, 16a, and 16b, an electrode pattern (210) can be formed that is connected to a first signal line (130) exposed within the bottom surface of the opening (H) and also connected to a second signal line (150) exposed within the side wall of the opening (H). The electrode pattern (210) may comprise a conductive metal such as platinum (Pt), ruthenium (Ru), iridium (Ir), silver (Ag), aluminum (Al), titanium (Ti), tantalum (Ta), tungsten (W), silicon (Si), copper (Cu), nickel (Ni), cobalt (Co), or molybdenum (Mo), or an alloy thereof. These materials are exemplary and the invention is not limited thereto.
[0081] The electrode pattern (210) may be a via electrode connecting the first signal line (130) and the second signal line (150).
[0082]
[0083] Although the present invention has been described in detail with reference to preferred embodiments, the present invention is not limited to the above embodiments, and various modifications and changes are possible by those skilled in the art within the technical spirit and scope of the present invention.
Claims
1. A step of forming a first signal line extending in a first direction on a substrate and first insulation patterns disposed on both sides thereof, wherein the upper surface of the first signal line is lower than the upper surface of the first insulation patterns so that the sidewalls of the first insulation patterns are exposed on both sides of the first signal line; A step of forming first insulating spacers on the sidewalls of the first insulating patterns exposed on both sides of the first signal line; A step of forming the first signal line, the first insulation patterns, and a first interlayer insulating film covering the first insulation spacers on a substrate on which the first insulation spacers are formed; A step of forming a second signal line extending in a second direction intersecting the first signal line and second insulation patterns disposed on both sides thereof on the first interlayer insulating film, wherein the upper surface of the second signal line is lower than the upper surface of the second insulation patterns so that the sidewalls of the second insulation patterns are exposed on both sides of the second signal line; A step of forming second insulating spacers on the sidewalls of the second insulating patterns exposed on both sides of the second signal line; A step of forming the second signal line, the second insulation patterns, and a second interlayer insulating film covering the second insulation spacers on a substrate on which the second insulation spacers are formed; A method for manufacturing a semiconductor device comprising the step of forming an opening within the second interlayer insulating film that penetrates an area where the second signal line intersects the first signal line and exposes the first signal line within the bottom.
2. In Claim 1, The step of forming the first signal line and the first insulation patterns disposed on both sides thereof is, A method for manufacturing a semiconductor device comprising the step of forming the first signal line and the first insulation patterns such that the upper surface of the first signal line and the upper surface of the first insulation patterns have the same level, and then recessing the first signal line.
3. In Claim 1, The step of forming the second signal line and the second insulation patterns disposed on both sides thereof is, A method for manufacturing a semiconductor device comprising the step of forming the second signal line and the second insulation patterns such that the upper surface of the second signal line and the upper surface of the second insulation patterns have the same level, and then recessing the second signal line.
4. In Claim 1, The first insulation patterns, the first insulation spacers, the second insulation patterns, and the second insulation spacers are silicon nitride films, and A method for manufacturing a semiconductor device in which the first interlayer insulating film and the second interlayer insulating film are silicon oxide films.
5. In Claim 1, The above opening is formed by forming a photoresist pattern having a hole on the upper portion of the area where the second signal line intersects the first signal line on the second interlayer insulating film, and etching the second interlayer insulating film, the second signal line, and the first interlayer insulating film in sequence using the photoresist pattern as a mask. When etching the second interlayer insulating film, the second insulating spacers are not etched, and the second insulating spacers act as an etching mask during the process of etching the second signal line located below them. A method for manufacturing a semiconductor device in which the first insulating spacers are not etched when the first interlayer insulating film is etched.
6. In Claim 5, The first insulating spacers, the first interlayer insulating film, the second signal lines, and the second interlayer insulating film are exposed sequentially from bottom to top within the side walls of the second direction of the opening, and A method for manufacturing a semiconductor device in which the first interlayer insulating film, the second signal lines, the second insulating spacers, and the second interlayer insulating film are exposed sequentially from bottom to top within the side walls of the first direction of the opening.
7. In Claim 1, The method further includes the step of forming a gate insulating film covering the side wall of the opening, wherein a portion of a first signal line not covered by the gate insulating film is exposed within the bottom of the opening. A step of forming a channel layer on a first signal line exposed within the bottom of the opening and on the gate insulating film; and The method further includes the step of forming an electrode pattern connected to the channel layer, and The first signal line above is a first source / drain electrode, and The above second signal line is a gate electrode, and A method for manufacturing a semiconductor device in which the above electrode pattern is a second source / drain electrode.
8. In Claim 1, A step of forming a channel layer covering the bottom and side walls of the above-mentioned opening; A step of forming a gate insulating film on the above channel layer; and The method further includes the step of forming an electrode pattern on the gate insulating film, and The first signal line above is a first source / drain electrode, and The above second signal line is a second source / drain electrode, and A method for manufacturing a semiconductor device in which the above electrode pattern is a gate electrode.
9. In Claim 1, The method further includes the step of forming an electrode pattern covering the bottom and side walls of the opening, and A method for manufacturing a semiconductor device in which the above electrode pattern is a via electrode.
10. A first signal line extending in a first direction on a substrate and first insulation patterns disposed on both sides thereof, wherein the upper surface of the first signal line is lower than the upper surface of the first insulation patterns so that the sidewalls of the first insulation patterns are exposed on both sides of the first signal line, and First insulating spacers respectively disposed on the sidewalls of the first insulating patterns exposed on both sides of the first signal line; A first interlayer insulating film covering the first signal line, the first insulating patterns, and the first insulating spacers; A second signal line extending in a second direction intersecting the first signal line on the first interlayer insulating film and second insulating patterns disposed on both sides thereof, wherein the upper surface of the second signal line is lower than the upper surface of the second insulating patterns so that the sidewalls of the second insulating patterns are exposed on both sides of the second signal line, and Second insulating spacers respectively disposed on the sidewalls of the second insulating patterns exposed on both sides of the second signal line; A second interlayer insulating film covering the second signal line, the second insulating patterns, and the second insulating spacers; and A semiconductor device comprising an opening that penetrates an area where the second signal line intersects the first signal line within the second interlayer insulating film and exposes the first signal line within the bottom.
11. In Claim 10, The first insulation patterns, the first insulation spacers, the second insulation patterns, and the second insulation spacers are silicon nitride films, and A semiconductor device in which the first interlayer insulating film and the second interlayer insulating film are silicon oxide films.
12. In Claim 10, The first insulating spacers, the first interlayer insulating film, the second signal lines, and the second interlayer insulating film are exposed sequentially from bottom to top within the side walls of the second direction of the opening, and A semiconductor device in which the first interlayer insulating film, the second signal lines, the second insulating spacers, and the second interlayer insulating film are exposed sequentially from bottom to top within the side walls of the first direction of the opening.
13. In Claim 10, A gate insulating film covering the side wall of the opening, wherein a portion of a first signal line not covered by the gate insulating film is exposed within the bottom of the opening, and A first signal line exposed within the bottom of the opening and a channel layer disposed on the gate insulating film; and It further includes an electrode pattern connected to the above channel layer, and The first signal line above is a first source / drain electrode, and The above second signal line is a gate electrode, and The above electrode pattern is a semiconductor device that is a second source / drain electrode.
14. In Claim 10, A channel layer covering the bottom and side walls of the above-mentioned opening; A gate insulating film disposed on the above channel layer; and It further includes an electrode pattern disposed on the gate insulating film, and The first signal line above is a first source / drain electrode, and The above second signal line is a second source / drain electrode, and The above electrode pattern is a semiconductor device that is a gate electrode.
15. In Claim 10, It further includes an electrode pattern covering the bottom and side walls of the above-mentioned opening, and The above electrode pattern is a semiconductor device that is a via electrode.