Cyclic deposition of silicon nitride based dielectric films

Abstract

A method for depositing silicon nitride (SiN) films within high aspect ratio (HAR) features with a reduced number of deposition cycles is provided. The method includes depositing three layers, for example, a silicon seed / silicon nitride / a silicon cap. The silicon seed and cap layers demonstrate improved bottom deposition performance with minimum sidewall and top deposition relative to silicon nitride. The silicon seed layer fills a portion of the HAR feature thus reducing the number of silicon nitride cycles needed to fill the HAR feature to targeted levels. The silicon cap layer protects the deposited silicon nitride during subsequent etching processes, which are performed to remove silicon nitride material formed on sidewalls and top surface of the feature.

Description

CYCLIC DEPOSITION OF SILICON NITRIDE BASED DIELECTRIC FILMSTECHNICAL FIELD

[0001] The present disclosure generally relates to the fabrication of microelectronic devices, and more specifically, related to gap fill deposition during the fabrication of microelectronic devices and microelectronic devices fabricated using gap fill deposition.BACKGROUND

[0002] Semiconductor device geometries have dramatically decreased in size since their introduction several decades ago. Modern semiconductor fabrication equipment routinely produce devices with feature sizes of 10 nm and sub-10 nm, and new equipment is being developed and implemented to make devices with even smaller geometries. The decreasing feature sizes result in structural features on the device having decreased spatial dimensions. The widths of gaps and trenches on the device narrow to a point where the aspect ratio of gap depth to its width becomes high enough to make it challenging to fill the gap with dielectric material. As a result, the deposition of dielectric material is prone to clog at the top before the gap is completely filled, producing a void or seam in the middle of the gap.

[0003] Therefore, there is a need for an improved method of gap fill deposition.SUMMARY

[0004] The present disclosure generally provides methods of gap fill deposition.

[0005] In one or more implementations, a method of forming a semiconductor device is provided. The method includes forming an amorphous silicon seed layer on a surface of a substrate through a first process cycle, including depositing a first amorphous silicon layer on the surface of the substrate and exposing the substrate to a hydrogen plasma treatment. The method further includes forming a silicon nitride layer on the amorphous silicon seed layer through a second process cycle including forming a secondamorphous silicon layer on the amorphous silicon seed layer, exposing the substrate to the hydrogen plasma treatment, and exposing the second amorphous silicon layer to a nitrogen plasma to form the silicon nitride layer.

[0006] Implementations may include one or more of the following. The method further includes forming an amorphous silicon capping layer on the silicon nitride layer through a third process cycle including forming a third amorphous silicon layer on the silicon nitride layer and exposing the substrate to the hydrogen plasma treatment. Depositing the first amorphous silicon layer includes exposing the surface of the substrate to a silane-containing precursor in the presence of a plasma at a first pressure. The hydrogen plasma treatment includes treating the substrate with a capacitively coupled plasma at a second pressure that is greater than the first pressure. The method is performed in a processing chamber without breaking vacuum. The substrate has a plurality of alternating semiconductor layers and at least one feature. The at least one feature includes a bottom surface and at least one sidewall, the at least one sidewall is defined by the plurality of alternating semiconductor layers. The first amorphous silicon layer is deposited on the bottom surface of the feature and the at least one sidewall of the at least one feature. The plurality of alternating semiconductor layers includes alternating layers of silicon (Si) and silicon germanium (SiGe). The amorphous silicon seed layer has a thickness that is greater than a thickness of the amorphous silicon capping layer.

[0007] In one or more implementations, a method of forming a semiconductor device is provided. The method includes depositing an amorphous silicon seed layer on a bottom surface of a feature, wherein the feature has at least one sidewall defined by a plurality of alternating semiconductor layers and a portion of the feature extends into a substrate, the bottom surface of the feature defined by the substrate, and the amorphous silicon seed layer fills the portion of the feature that extends into the substrate, depositing a silicon nitride layer on the amorphous silicon seed layer and the at least one sidewall, depositing a silicon capping layer on the silicon nitride layer formed on the amorphous silicon seed layer, and removing the silicon nitride layer formed on the at least one sidewall, wherein the silicon nitride layerformed on the at least one sidewall is removed at a faster rate than the silicon capping layer.

[0008] Implementations may include one or more of the following. Depositing the amorphous silicon seed layer includes depositing a first amorphous silicon layer on the bottom surface of the feature and exposing the substrate to a hydrogen plasma treatment. Depositing the silicon nitride layer on the amorphous silicon seed layer includes forming a second amorphous silicon layer on the amorphous silicon seed layer, exposing the substrate to the hydrogen plasma treatment, and exposing the second amorphous silicon layer to a nitrogen plasma to form the silicon nitride layer. Depositing the silicon capping layer on the silicon nitride layer, includes forming a third amorphous silicon layer on the silicon nitride layer and exposing the substrate to the hydrogen plasma treatment. Depositing the first amorphous silicon layer includes exposing the bottom surface of the feature to a silane-containing precursor in the presence of a plasma at a first pressure. The hydrogen plasma treatment includes treating the substrate with a capacitively coupled plasma at a second pressure that is greater than the first pressure.

[0009] In one or more implementations, a non-transitory computer readable medium including instructions, that, when executed by a controller of a processing chamber, causes the processing chamber to perform a plurality of operations is provided. The operation include depositing an amorphous silicon seed layer on a bottom surface of a feature, wherein the feature has at least one sidewall defined by a plurality of alternating semiconductor layers and a portion of the feature extends into a substrate, the bottom surface of the feature defined by the substrate, and the amorphous silicon seed layer fills the portion of the feature that extends into the substrate, depositing a silicon nitride layer on the amorphous silicon seed layer and the at least one sidewall, and depositing a silicon capping layer on the silicon nitride layer formed on the amorphous silicon seed layer.

[0010] Implementations may include one or more of the following. The plurality of operations further includes removing the silicon nitride layer formed on the at least one sidewall, wherein the silicon nitride layer formed on the atleast one sidewall is removed at a faster rate than the silicon capping layer. Depositing the amorphous silicon seed layer includes depositing a first amorphous silicon layer on the bottom surface of the feature and exposing the substrate to a hydrogen plasma treatment. Depositing the silicon nitride layer on the amorphous silicon seed layer includes forming a second amorphous silicon layer on the amorphous silicon seed layer, exposing the substrate to the hydrogen plasma treatment, and exposing the second amorphous silicon layer to a nitrogen plasma to form the silicon nitride layer. Depositing the silicon capping layer on the silicon nitride layer, includes forming a third amorphous silicon layer on the silicon nitride layer and exposing the substrate to the hydrogen plasma treatment. Depositing the first amorphous silicon layer includes exposing the surface of the substrate to a silane-containing precursor in the presence of a plasma at a first pressure and the hydrogen plasma treatment includes treating the substrate with a capacitively coupled plasma at a second pressure that is greater than the first pressure.

[0011] In another aspect, a non-transitory computer readable medium has stored thereon instructions, which, when executed by a processor, causes the process to perform operations of the above apparatus and / or method.BRIEF DESCRIPTION OF THE DRAWINGS

[0012] So that the manner in which the above-recited features of the present disclosure can be understood in detail, a more particular description of the aspects, briefly summarized above, may be had by reference to implementations, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only typical implementations of this disclosure and are therefore not to be considered limiting of its scope, for the disclosure may admit to other equally effective implementations.

[0013] FIG. 1 is a flowchart showing a method of gap fill deposition, in accordance with one or more implementations of the present disclosure.

[0014] FIGS. 2A-2E illustrate schematic views of various stages of forming a semiconductor device structure, in accordance with one or more implementations of the present disclosure.

[0015] FIG. 3 is a schematic view of a cluster tool, in accordance with one or more implementations of the present disclosure.

[0016] FIG. 4A is a schematic view of a processing chamber, in accordance with one or more implementations of the present disclosure.

[0017] FIG. 4B is a schematic bottom view of a shower head, in accordance with one or more implementations of the present disclosure.

[0018] FIG. 5 is a schematic view of a plasma chamber, in accordance with one or more implementations of the present disclosure.

[0019] To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements and features of one implementation may be beneficially incorporated in other implementations without further recitation.DETAILED DESCRIPTION

[0020] The present disclosure generally relates to the fabrication of microelectronic devices, and more specifically, related to gap fill deposition during the fabrication of microelectronic devices and microelectronic devices fabricated using gap fill deposition.

[0021] Parasitic sub-fin capacitance and leakage is a chronic issue of GAA transistors and FinFETs, degrading the performance of the device. To suppress the leakage and the capacitance, an isolation is needed to block the current path. In microelectronics device fabrication there is a need to fill narrow trenches / openings having high aspect ratios (HAR) greater than 10:1 having no voiding. As aspect ratios increase, the number of deposition cycles for forming a dielectric material increases, which adversely impact the number of defects in the dielectric material and overall production throughput. In addition, someGAA structures have pre-recessed silicon germanium (“SiGe”) areas, which cause shadowing effects when dielectric material is deposited on sidewalls of the HAR feature forming voids or seams at the corner of the pre-recessed SiGe area.

[0022] Implementations of the present disclosure provide methods of depositing silicon nitride (SiN) films within HAR features with a reduced number of deposition cycles. The reduced number of deposition cycles leads to a reduced number of defects in the deposited dielectric material while also improving overall throughput. In one or more implementations, the method includes depositing three layers, for example, a silicon seed / silicon nitride / a silicon cap. The silicon seed and cap layers demonstrate improved bottom deposition performance with minimum sidewall and top deposition relative to silicon nitride. The silicon seed layer fills a portion of the HAR feature thus reducing the number of silicon nitride cycles needed to fill the HAR feature to targeted levels. The silicon cap layer protects the deposited silicon nitride during subsequent etching processes, which are performed to remove silicon nitride material formed on sidewalls and top surface of the feature. Thus, throughput can be improved, corner fill can be improved, defects can be reduced, and the SiN film deposited at the bottom of the feature can be protected during subsequent etching processes.

[0023] FIG. 1 is a flow diagram depicting a method 100 of gap fill deposition for forming a semiconductor device structure, in accordance with one or more implementations of the present disclosure. FIGS. 2A-2E illustrate views of various stages of forming a semiconductor device structure, in accordance with one or more implementations described herein. Although FIGS. 2A-2E are described in relation to the method 100, the structures disclosed in FIGS. 2A-2E are not limited to the method 100 but instead may stand alone as structures that are independent of the method 100. Similarly, although the method 100 is described in relation to FIGS. 2A-2E, the method 100 is not limited to the structures disclosed in FIGS. 2A-2E but instead may stand alone independent of the structures disclosed in FIGS. 2A-2E. It should be understood that FIGS.2A-2E illustrate only partial schematic views of the semiconductor devicestructure 200, and the semiconductor device structure 200 may contain any number of transistor sections and additional materials having aspects as illustrated in the figures. It should also be noted that although the method 100 illustrated in FIG. 1 is described sequentially, other process sequences that include one or more operations that have been omitted and / or added, and / or has been rearranged in another desirable order, fall within the scope of the implementations of the disclosure provided herein.

[0024] At operation 110, a semiconductor device structure is received. The semiconductor device structure may be the semiconductor device structure 200 as shown in FIG. 2A. The semiconductor device structure 200 may be positioned on a substrate support of a plasma processing system, for example, the substrate support 430 of the processing chamber 400 or the substrate support 530 of the plasma chamber 500. The semiconductor device structure 200 may be or include the substrate 428 or the substrate 528. The semiconductor device structure 200 may be or be part of a multi-gate device with three-dimensional architecture, such as fin based semiconductor devices or FINFETs and gate-all around (GAA) transistor devices.

[0025] Referring to FIG. 2A, the semiconductor device structure 200 includes a first semiconductor region 202 and a second semiconductor region 204 formed on a substrate 206. The first semiconductor region 202 and the second semiconductor region 204 are separated by a feature, such as a trench 208, which exposes the substrate 206. A portion 211 of the trench 208 extends into the substrate 206.

[0026] As shown in FIG. 2A, the first semiconductor region 202 and the second semiconductor region 204 each include a plurality of alternating semiconductor layers 209. The plurality of alternating semiconductor layers 209 include first semiconductor layers 210 and second semiconductor layers 212 that are alternately and repeatedly stacked on the substrate 206. Although the example shown in FIG. 2A shows three pair, each pair including the first semiconductor layer 210 and the second semiconductor layer 212, the number of pairs may be varied based on different process needs with or without the first semiconductor layers 210 and the second semiconductor layers 212 beingneeded. The first semiconductor layers 210 are formed of a first material having etch selectivity to a second material of which the second semiconductor layers 212 are formed, for example, an etch rate of the first material is higher than an etch rate of the second material. The etch selectivity, a ratio of the etch rate of the first material to the etch rate of the second material, is between about 10:1 to 200:1. Example combinations of the first material and the second material include silicon germanium (SiGe) / silicon (Si), silicon germanium (SiGe) / germanium (Ge), and germanium tin (GeSn) / silicon (Si). The first semiconductor layers 210 may be selectively etched to form indentations or recesses 218 at an end of the first semiconductor layers 210 facing the trench 208, in each of which a spacer (not shown) may be formed. The spacers may be formed of dielectric material, such as silicon nitride (Si₃N₄), silicon oxynitride (SiON), or silicon oxycarbide (SiOCN). In one or more implementations, which can be combined with other implementations, the first semiconductor layers 210 are or include SiGe and the second semiconductor layers 212 are or include silicon, for example, crystalline silicon. The second semiconductor layers 212 may serve as channels having a width of between several nanometers and several tens of nanometers.

[0027] The first semiconductor layers 210 and the second semiconductor layers 212 may be formed using any suitable deposition technique, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD), and the trench 208 is formed by a patterning technique, such as lithography followed by an etch or ashing process. The first semiconductor layers 210 and the second semiconductor layers 212 may each have thickness of between about 1 nm and about 15 nm, for example, about 10 nm. The selective etching of the first semiconductor layers 210 may be performed by any appropriate etch process, such as a dry plasma etch process.

[0028] The semiconductor device structure 200 further includes a dummy gate layer (also referred to as a “dielectric layer”) 216 formed over at least a portion of each of the first semiconductor region 202 and the second semiconductor region 204. The dummy gate layer 216 may be formed of a dielectric material, such as silicon dioxide (SiO₂). The dummy gate layer 216includes a top surface 216t, which defines a top surface of the semiconductor device structure 200.

[0029] The substrate 206 has a frontside 206f (also referred to as a front surface) and a backside 206b opposite the frontside 206f. The substrate 206 may be a material such as crystalline silicon (e.g., Si< 100> or Si< 111 >), silicon oxide, strained silicon, silicon germanium, germanium, doped or undoped polysilicon, doped or undoped silicon wafers and patterned or non-patterned wafers silicon on insulator (SOI), carbon doped silicon oxides, silicon nitride, doped silicon, germanium, gallium arsenide, glass, or sapphire. The substrate 206 may have various dimensions, such as 200 mm, 300 mm, 450 mm, or other diameter, as well as, being a rectangular or square panel. Unless otherwise noted, examples described are conducted on substrates with a 200 mm diameter, a 300 mm diameter, or a 450 mm diameter substrate. In one or more implementations, which can be combined with other implementations, the substrate 206 is or includes crystalline silicon.

[0030] The trench 208 is defined by a pair of opposing sidewalls 208s and a bottom surface 208b. The sidewalls 208s may be defined by the dummy gate layer 216 and the alternating pairs of the first semiconductor layer 210 and the second semiconductor layer 212. The bottom surface 208b of the trench is defined by the substrate 206. The portion 211 of the trench 208 extends from the frontside 206f of the substrate 206 toward the backside 206b of the substrate 206. The trench 208 may be a high aspect ratio (HAR) feature. The trench 208 extends from the top surface 216t of the dummy gate layer to the bottom surface 208b defined by the substrate 206. The trench 208 has a first depth “D1” from the top surface 216t of the dummy gate layer 216 to the bottom surface 208b and a width “W1” between the sidewalls 208s. In some implementations, the depth D1 is in a range of 2 nm to 200 nm, 3 nm to 200 nm, 5 nm to 100 nm, 2 nm to 100 nm, or 50 nm to 100 nm. In some implementations, the width W1 is in a range of 10 nm to 100 nm, 10 nm to 20 nm, 10 nm to 50 nm, or 50 nm to 100 nm. In some implementations, the feature 322 has an aspect ratio (D / W) in a range of 1 to 20, 1 to 10, 5 to 20, 10 to 20, or 15 to 20.

[0031] At operation 120, an amorphous silicon (a-Si) seed layer 220 is formed as shown in FIG. 2B. Forming the a-Si seed layer includes a cyclic process of depositing an amorphous silicon layer at operation 122 followed by a hydrogen plasma treatment process at operation 124. The cyclic process of operation 122 and operation 124 may be repeated until the a-Si seed layer 220 achieves a targeted thickness. Referring to FIG. 2B, the a-Si seed layer 220 is formed on the bottom surface 208b of the trench 208 and fills the portion 211 of the trench 208 that extends into the substrate 206. A top surface of the a-Si seed layer 220 may be coplanar with or substantially coplanar with the frontside 206f of the substrate 206.

[0032] At operation 122, the a-Si seed layer 220 or a portion of the a-Si seed layer 220 is formed. The a-Si seed layer 220 may be formed by a flowable chemical vapor deposition (FCVD) process or a plasma-enhanced chemical vapor deposition (PECVD) process. In one or more implementations, the plasma deposition process of operation 122 includes exposing the semiconductor device structure 200 to a silicon-containing precursor gas and optionally an inert gas or diluent gas. The silicon-containing precursor gas can be or include a silane-containing precursor gas. Examples of suitable silicon precursors include silanes such as silane (SiH₄) and higher-order silanes with the empirical formula SiaH(2a+2)wherein a = 2, 3, 4, 5, 6,..., such as disilane (Si₂H₆), trisilane (Si₃H₈), tetrasilane (Si₄H₁₀), isotetrasilane (Si₄H₁₀), neopentasilane (Si₅H₁₂), hexasilane (Si₆H₁₄), as well as others. Other examples of suitable silanes include cyclic silanes such as cyclopentasilane (Si₅H₁₀), cyclohexasilane (Si₆H₁₂), as well as others. Other suitable silicon precursors include halogenated silanes. For example, halogenated silanes include silicon tetrafluoride (SiF4), silicon tetrachloride (SiCl₄), dichlorosilane (SiH₂Cl₂), hexachlorodisilane (Si₂Cl₆) and the like. In one or more particular implementations the silicon-containing precursor gas is silane.

[0033] In one or more implementations, the plasma deposition process of operation 122 includes exposing the semiconductor device structure 200 to a reactive gas or a reactant gas. The reactive gas can include a mixture of one or more species. In one or more implementations, the reactive gas includesone or more of argon (Ar), oxygen (02), hydrogen (H2), nitrogen (N2), hydrogen / nitrogen (H2 / N2), and ammonia (NH3). In one or more particular implementations, the reactive gas is or includes hydrogen.

[0034] The plasma gas can be or include any suitable gas that can be ignited to form a plasma and / or can act as a carrier or diluent for the precursor. In one or more implementations, the plasma gas includes one or more of hydrogen (H2), ammonia (NH3), oxygen (O2), and nitrous oxide (N2O), and the plasma gas may be used as a plasma treatment to activate one or more of the precursors.

[0035] In one or more implementations, a high plasma density dissociates the reactant gases, for example, argon (Ar), oxygen (O2), hydrogen (H2), nitrogen (N2), hydrogen / nitrogen (H2 / N2), and ammonia (NH3)) to generate radicals, which then react with other precursors downstream in the chamber to result in deposition of the a-Si seed layer on the bottom surface 208b of the trench 208.

[0036] In one or more implementations, the deposition gas mixture further includes an inert gas or dilution gas. Suitable dilution gases include helium (He), argon (Ar), hydrogen (H2), nitrogen (N2), ammonia (NH3), or combinations thereof, among others. The addition of H2 and / or NH3 may be used to control the hydrogen ratio (e.g., silicon to hydrogen ratio) of the deposited amorphous silicon layer.

[0037] In one or more implementations, the plasma is generated remotely by a remote plasma source (RPS) and delivered to the processing region of the processing chamber. In one or more other implementations, the plasma is generated in the processing region of the processing chamber.

[0038] In one or more implementations, the deposition process of operation 122 is carried out in a process region a first pressure. The first pressure can be in a range from about 0.1 mTorr to about 10 Torr, or in a range from about 0.1 Torr to about 5.0 Torr, or in a range from about 0.1 Torr to about 2 Torr, or in a range from about 0.5 Torr to about 1 Torr.

[0039] The plasma (e.g., capacitive-coupled plasma) may be formed from either top and bottom electrodes or side electrodes. The electrodes may be formed from a single powered electrode, dual powered electrodes, or more electrodes with multiple frequencies such as, but not limited to, 350 KHz, 2 MHz, 13.56 MHz, 27 MHz, 40 MHz, 60 MHz, and 100 MHz, being used alternatively or simultaneously with any or all of the reactant gases listed herein to deposit a thin film of amorphous silicon. In some implementations, the plasma is a capacitively coupled plasma (CCP). In some implementations, the plasma is an inductively coupled plasma (ICP). In some implementations, the plasma is a microwave plasma. In one or more implementations, the plasma is formed at a frequency of 27 MHz.

[0040] The RF source can have a power of about 40 watts (W) to about 60 W, e.g., about 40 W to about 45 W, about 45 W to about 50 W, about 50 W to about 55 W, or about 55 W to about 60 W, when operating at a very high frequency of about 20 MHz to about 30 MHz, e.g., about 20 MHz to about 22 MHz, about 22 MHz to about 24 MHz, about 24 MHz to about 26 MHz, about 26 MHz to about 28 MHz, or about 28 MHz to about 30 MHz during the plasma treatment. In an implementation, the plasma may have a power of about 60 W when operating at a frequency of about 27 MHz.

[0041] In one or more implementations, the plasma is an inductively coupled plasma (ICP) or a conductively coupled plasma (CCP). Any suitable power can be used depending on, for example, the reactants, or the other process conditions. In some implementations, the plasma is generated with a plasma power in the range of about 10 W to about 10 kW.

[0042] In one or more implementations, the a-Si seed layer 220 can be formed at any suitable temperature. In some implementations, the a-Si seed layer 220 is formed at a temperature in a range from about -10 °C to about 600 °C, or in a range from about 350 °C to about 500 °C.

[0043] At operation 124, the semiconductor device structure 200 is exposed to a plasma treatment process. The plasma treatment process selectively removes amorphous silicon formed on the top surface 216t and the sidewalls208s without damaging the a-Si seed layer 220. The plasma treatment process can be an inductively coupled plasma (ICP) process or a capacitively coupled plasma (CCP) process. The plasma can be formed ex-situ in a remote plasma source (RPS). The plasma can be a direct plasma formed in-situ, for example, generated within a processing region. In one or more implementations, which can be combined with other implementations, the plasma treatment process includes exposing the semiconductor device structure 200 to a plasma formed from a process gas including a hydrogen-containing gas. The process gas may further include an inert gas, for example, argon (Ar), helium (He), krypton (Kr), or a combination thereof. The inert gas helps stabilize the plasma. In one or more implementations, which can be combined with other implementations, the plasma treatment process includes exposing the trench 208 to a plasma formed form a process gas including one or more of hydrogen and argon.

[0044] In one or more implementations, the plasma treatment process of operation 124 is carried out in the process region a second pressure. The second pressure of operation 124 can be greater than the first pressure of operation 122. The second pressure can be in a range from about 1 Torr to about 10 Torr, or in a range from about 1 Torr to about 5.0 Torr, or in a range from about 2 Torr to about 3 Torr.

[0045] Operation 122 and operation 124 may be repeated for a number of cycles until the a-Si seed layer 220 achieves a targeted thickness. In one or more implementations, the number of cycles is in a range from 4 cycles to 20 cycles, or in a range from 5 cycles to 15 cycles, or in a range from 10 cycles to 15 cycles. The a-Si seed layer 220 may have any suitable thickness. In one or more implementations, the a-Si seed layer 220 has a thickness sufficient to fill the portion 211 fills the portion 211 of the trench 208 that extends into the substrate 206 while remaining coplanar with or substantially coplanar with the frontside 206f of the substrate 206. In one or more implementations, the a-Si seed layer 220 has a first thickness in a range from about 4 nanometers to about 20 nanometers, or in a range from about 5 nanometers to about 15 nanometers, or in a range from about 10 nanometers to about 15 nanometers.

[0046] At operation 130, a silicon nitride layer 230 is formed as shown in FIG. 2C. Forming the silicon nitride layer 230 includes a cyclic process of depositing an amorphous silicon layer at operation 132, performing a hydrogen plasma treatment at operation 134, and exposing the amorphous silicon layer to a nitrogen plasma at operation 136. The cyclic process of operation 132, operation 134, and operation 136 may be repeated until the silicon nitride layer 230 achieves a targeted thickness. Referring to FIG. 2C, the silicon nitride layer 230 may be formed on or over the a-Si seed layer 220 within the trench 208. During formation of the silicon nitride layer 230 at operation 130, a silicon nitride layer 232 may also be deposited on the top surface 216t, along the sidewalls 208s, and within the recesses 218. The silicon nitride layer 232 will be removed or partially removed during the etching process of operation 150.

[0047] At operation 132, an amorphous silicon layer is formed on or over the a-Si seed layer 220. The amorphous silicon layer may be formed using the same or a similar process to the amorphous silicon layer formed at operation 122.

[0048] At operation 134, the a-Si layer is exposed to a hydrogen plasma treatment process. The hydrogen plasma treatment process of operation 132 may be performed using the same or a similar process to the plasma treatment process of operation 122.

[0049] At operation 136, the a-Si layer is exposed to a nitrogen plasma to nitridate to the amorphous silicon layer forming the silicon nitride layer 230. At operation 136, one or more radicals (also referred to as reactive gas) in the substrate processing region react with the amorphous silicon layer to form a silicon nitride layer. The radicals may be generated by a plasma generated in a remote plasma source (RPS) outside the processing chamber. The radicals may be flowed into a substrate processing region of the processing chamber along with a carrier gas (e.g., Ar, He). The plasma can be generated by the dissociation of a processing precursor gas including molecular oxygen (O2), ozone (O3), molecular hydrogen (H2), a nitrogen-hydrogen compound (e.g., NH3, N2H4), a nitrogen-oxygen compound (e.g., NO, NO2, N2O), a hydrogenoxygen compound (e.g., H2O, H2O2), a nitrogen-hydrogen-oxygen compound(e.g., NH4OH), a carbon-oxygen compound (e.g., CO, CO2), a fluorine-containing compound (e.g., NF3), or a combination thereof. In the plasma, 0*, H*, F*, and / or N*-containing radicals may be activated, such as O*, H*, F*, N*, NH3*, N2H4*, NH2*, NH*, N*O*, C3H6*, C2H2*, or a combination thereof.

[0050] In some implementations, the radicals activated in the RPS are flowed into the processing chamber (referred to as “radical flux”) at a flow rate between about 1 seem and about 10000 seem. The composition of the formed silicon nitride can be adjusted by changing the composition of the reactive gas in the radical flux. To form a nitrogen-containing film, such as SiON, SiCON, and SiN films, the reactive gas may be, for example, ammonia (NH3), hydrogen (H2), hydrazine (N2H4), nitrogen dioxide (NO2), or nitrogen (N2). Without being bound by theory, when the reactive gas in the substrate processing region reacts with the delivered dielectric precursor, Si— H and N-H bonds (weaker bonds) are partially broken and replaced by Si— N, Si-NH, and / or Si-NH2 bonds (stronger bonds) to form a SiN-dielectric film.

[0051] In one or more implementations, the nitridation process of operation 136 is carried out in a process region a third pressure. The third pressure of operation 136 can be greater than the second pressure of operation 134. The third pressure can be in a range from about 1 Torr to about 10 Torr, or in a range from about 3 Torr to about 10 Torr, or in a range from about 5 Torr to about 8 Torr.

[0052] During the nitridation process of operation 136 the RF source has a power that is greater than the power used during operation 132 and operation 134. During operation 136, the RF source can have a power in a range from about 10 W to about 10 kW. During operation 136, the RF source can have a power in a range from about 100 watts (W) to about 1500 W, or in a range from about 500 W to about 1500 W, or in a range from about 800 W to about 1200 W, or in a range from about 1000 W to about 1200 W, when operating at a very high frequency of about 20 MHz to about 30 MHz, e.g., about 20 MHz to about 22 MHz, about 22 MHz to about 24 MHz, about 24 MHz to about 26 MHz, about 26 MHz to about 28 MHz, or about 28 MHz to about 30 MHz during the plasmatreatment. In an implementation, the plasma may have a power of about 1000 W when operating at a frequency of about 27 MHz.

[0053] In one or more implementations, the silicon nitride layer 230 can be formed at any suitable temperature. In some implementations, the silicon nitride layer 230 is formed at a temperature in a range from about -10 °C to about 600 °C, or in a range from about 350 °C to about 500 °C.

[0054] Operation 132, operation 134, and operation 136 may be repeated for a number of cycles to until the silicon nitride layer 230 achieves a targeted thickness. In one or more implementations, the number of cycles is in a range from 4 cycles to 20 cycles, or in a range from 5 cycles to 15 cycles, or in a range from 8 cycles to 10 cycles. The silicon nitride layer 230 may have any suitable thickness. In one or more implementations, the silicon nitride layer 230 has a thickness in a range from about 4 nanometers to about 20 nanometers, or in a range from about 5 nanometers to about 15 nanometers, or in a range from about 8 nanometers to about 10 nanometers.

[0055] Optionally, at operation 140 an amorphous silicon (a-Si) capping layer 240 is formed. Forming the silicon capping layer includes a cyclic process of depositing an amorphous silicon layer at operation 142 followed by a hydrogen plasma treatment process at operation 144. The cyclic process of operation 142 and operation 144 may be repeated until the a-Si capping layer 240 achieves a targeted thickness. Referring to FIG. 2D, the a-Si capping layer 240 on or over the silicon nitride layer 230 within the trench 208. The a-Si capping layer 240 protects the silicon nitride layer 230 from damage during subsequent processing. For example, if the semiconductor device structure 200 is exposed to an etching process to remove the silicon nitride layer 232 formed on the top surface 216t, along the sidewalls 208s, and along the recesses 218, the a-Si capping layer 240 is removed at a slower rate than the silicon nitride layer 232 and thus protects the silicon nitride layer 230 from being damaged by the etchant.

[0056] At operation 142, an amorphous silicon layer is formed on or over the silicon nitride layer 230. The amorphous silicon layer may be formed using thesame or a similar process to the amorphous silicon layer formed at operation 122.

[0057] At operation 144, the a-Si layer is exposed to a hydrogen plasma treatment process. The hydrogen plasma treatment process of operation 142 may be performed using the same or a similar process to the hydrogen plasma treatment process of operation 122.

[0058] Operation 142 and operation 144 may be repeated for a number of cycles until the a-Si capping layer 240 achieves a targeted thickness. In one or more implementations, the number of cycles is in a range from 1 cycle to 10 cycles, or in a range from 2 cycles to 5 cycles, or in a range from 3 cycles to 5 cycles. The a-Si capping layer 240 may have any suitable thickness. In one or more implementations, a-Si capping layer 240 has a thickness sufficient to protect the underlying silicon nitride layer 230 while the silicon nitride layer 232 is removed from the semiconductor device structure 200 during operation 150. In one or more implementations, the a-Si capping layer 240 has a third thickness in a range from about 1 nanometer to about 10 nanometers, or in a range from about 2 nanometers to about 5 nanometers, or in a range from about 3 nanometers to about 5 nanometers.

[0059] Operations 110, 120, 130, and 140 of the method 100 can be performed without breaking vacuum. In one or more implementations, operations 110, 120, 130, and 140 are performed in the same processing chamber, for example, the processing chamber 400 or the plasma chamber 500. In one or more implementations, operations 110, 120, 130, and 140 are performed on the same cluster tool, for example, the cluster tool system 301.

[0060] Optionally, at operation 150 the semiconductor device structure 200 is exposed to an etching process. Referring to FIG. 2E, the silicon nitride layer 232 will be removed or partially removed during the etching process of operation 150. During operation 150 the a-Si capping layer 240 is also removed or partially removed. Any suitable etching process may be used. The etching process can be a wet etch or dry etch process. In one or more implementations, the etching process includes exposing the semiconductor device structure 200is exposed to hot phosphoric acid to remove the silicon nitride layer 232. In one example, the hot phosphoric acid etch is performed using phosphoric acid (85%), 160 °C. The etchant used during operation 150 may be selected so that the silicon nitride layer 232 is removed at a removal rate that is greater than the removal rate of the a-Si capping layer 240.

[0061] Implementations of the deposition systems and techniques may be incorporated into larger fabrication systems for producing integrated circuit chips. FIG. 3 shows one such cluster tool system 301 that includes processing chambers 308a-f, according to one implementation. In FIG. 3, a pair of front opening unified pods (FOUPs) 302 supply substrates, for example, 300 mm diameter wafers, which are received by robotic arms 304 and placed into a low-pressure holding area 306. A second robotic arm 310 may be used to transport the substrate between the low-pressure holding area 306 and the processing chambers 308a-f.

[0062] The cluster tool system 301 further includes a system controller 380 for controlling processes performed by the cluster tool system 301 and the processing chambers 308a-f. The system controller 380 can be any type of controller used in an industrial setting, such as a programmable logic controller (PLC). The system controller 380 includes a processor 382, a memory 384, and input / output (I / O) circuits 386. The system controller 380 can further include one or more of the following components (not shown), such as one or more power supplies, clocks, communication components (e.g., network interface card), and user interfaces typically found in controllers for semiconductor equipment.

[0063] The memory 384 can include non-transitory memory. The non-transitory memory can be used to store the computer readable instructions, programs and settings described below. The memory 384 can include one or more readily available types of memory, such as read only memory (ROM) (e.g., electrically erasable programmable read-only memory (EEPROM), flash memory, floppy disk, hard disk, or random-access memory (RAM) (e.g., nonvolatile random-access memory (NVRAM).

[0064] The processor 382 is coupled to the memory. The processor 382 is configured by the computer readable instructions or programs stored in the memory 384 that when executed by the processor 382 perform a plurality of operations, for example, the plurality of operations of the method 100 described in reference to FIG. 1. During execution of these instructions or programs, the system controller 380 can communicate to I / O devices through the I / O circuits 386. For example, during execution of these programs and communication through the I / O circuits 386, the system controller 380 can control outputs. The memory 384 can further include various operational settings used to control the processing chambers 308a-f. For example, the settings can include temperature and pressure settings as well as settings to control gas delivery from the gas sources described herein.

[0065] FIG. 4A is a schematic view of a processing chamber 400 having a chamber body 402 and lid assembly 404, according to one implementation. The processing chamber 400 may be used to perform the method 100. The processing chamber 400 may be one or more of the processing chambers 308a-f in the cluster tool system 301. The lid assembly 404 generally includes a remote plasma source (RPS) 406, a lid 408, and a dual channel showerhead (DCSH) 410. The RPS 406 may process a processing precursor gas provided from a processing precursor gas source 412. The plasma formed in the RPS 406 may be then delivered through a gas inlet assembly 414 and baffle 416, which are coupled to the lid 408, and into a chamber plasma region 418. A carrier gas, for example, may be delivered into the chamber plasma region 418. The lid 408 (that is a conductive top portion) and the dual channel showerhead (DCSH) 410 are disposed with an insulating ring 420 in between, which allows an AC potential to be applied to the lid 408 relative to the DCSH 410.

[0066] The DCSH 410 is disposed between the chamber plasma region 418 and a substrate processing region 424 and allows radicals activated in the plasma present within the chamber plasma region 418 to pass through a plurality of through-holes 426 into the substrate processing region 424. The flow of the radicals (radical flux) is indicated by the solid arrows “A” in FIG. 4A. A substrate 428 is disposed on a substrate support 430 disposed within thesubstrate processing region 424. The DCSH 410 also has one or more hollow volumes 432 which can be filled with a dielectric precursor provided from a precursor source 434. The dielectric precursor passes from the one or more hollow volumes 432 through small holes 436 and into the substrate processing region 424, bypassing the chamber plasma region 418. The flow of the dielectric precursor is indicated by the dotted arrows in FIG. 4A. An exhaust ring 438 is used to uniformly evacuate the substrate processing region 424 by use of an exhaust pump 440. The DCSH 410 may be thicker than the length of the smallest diameter of the through-holes 426. The length of the smallest diameter of the through-holes 426 may be restricted by forming larger diameter portions of through-holes 426 partially through the DCSH 410, to maintain a flow of radical flux from the chamber plasma region 418 into the substrate processing region 424. In some implementations, the length of the smallest diameter of the through-holes 426 may be the same order of magnitude as the smallest diameter of the through-holes 426 or less.

[0067] In some implementations, a pair of processing chambers, for example, the processing chambers 308c-d in FIG. 3 (referred to as a twin chamber) may be used to deposit a dielectric precursor on the substrate. Each of the processing chambers for example, the processing chambers 308c-d can have a cross-sectional structure of the processing chamber 400 depicted in FIG. 4A. The flow rates per channel of the DCSH described above correspond to flow rates into each of the processing chambers, for example, the processing chambers 308c-d, via the corresponding DCSH 410.

[0068] FIG. 4B is a schematic bottom view of the DCSH 410 according to one implementation. The DCSH 410 may deliver via through-holes 426 the radical flux and the carrier gas present within the chamber plasma region 418.

[0069] In some implementations, the number of through-holes 426 may be about 60 holes to about 2000 holes. Through-holes 426 may have round shapes or a variety of shapes. In some implementations, the smallest diameter of through-holes 426 may be about 0.5 mm to about 20 mm, such as about 1 mm to about 6 mm. The cross-sectional shape of through-holes 426 may be made conical, cylindrical or a combination of the two shapes. In someimplementations, a number of small holes 436 may be used to introduce a dielectric precursor into the substrate processing region 424 and may be about 100 holes to about 5000 holes or about 500 holes to about 2000 holes. The diameter of the small holes 436 may be about 0.1 mm to about 2 mm.

[0070] FIG.5 is a schematic view of a plasma chamber 500 having a chamber body 502 and lid assembly 504, according to one implementation. The plasma chamber 500 may be used to perform the method 100. The plasma chamber 500 may be one or more of the processing chambers 308a-f in the cluster tool system 301. The lid assembly 504 includes a gas delivery assembly 506 and a lid 508. The lid 508 has an opening 510 to allow entrance of one or more processing precursor gases. The gas delivery assembly 506 is disposed over the lid 508 through the opening 510. The gas delivery assembly 506 may be connected to a gas source 512 through a gas inlet 514 to supply one or more processing precursor gases into a substrate processing region 524. A substrate 528 is disposed on a substrate support 530 disposed within the substrate processing region 524 and coupled to a bias power source (not shown). The one or more processing precursor gases may exit the substrate processing region 524 by use of an exhaust ring 538 and an exhaust pump 540.

[0071] In the lid assembly 504, inner coils 542, middle coils 544, and outer coils 546 are disposed over the lid 508. The inner coils 542 and the outer coils 546 are coupled to an RF power source 548 through a matching circuit 550. Power applied to the outer coils 546 from the RF power source 548 is inductively coupled through the lid 508 to generate plasma from the processing precursor gases provided from the gas source 512 within the substrate processing region 524. The RF power source 548 can provide current at different frequencies to control the plasma density ( / .e., number of ions per cc) in the plasma and thus the density of ion flux (ions / cm2-sec). The bias power source controls a voltage between the substrate 528 and the plasma and thus controls the energy and directionality of the ions. Thus, both ion flux and ion energy can be independently controlled. A heater assembly 552 may be disposed over the lid 508. The heater assembly 552 may be secured to the lid 508 by clamping members 554, 556.

[0072] The previously described implementations of the present disclosure have many advantages. However, the present disclosure does not necessitate that all the advantageous features and all the advantages need to be incorporated into every implementation of the present disclosure.

[0073] In the Summary and in the Detailed Description, and the Claims, and in the accompanying drawings, reference is made to particular features (including method operations) of the present disclosure. It is to be understood that the disclosure in this specification includes all possible combinations of such particular features. For example, where a particular feature is disclosed in the context of a particular aspect, implementation, embodiment, or example of the present disclosure, or a particular claim, that feature can also be used, to the extent possible in combination with and / or in the context of other particular aspects and implementations of the present disclosure, and in the present disclosure generally.

[0074] Embodiments and all of the functional operations described in this specification can be implemented in digital electronic circuitry, or in computer software, firmware, or hardware, including the structural means disclosed in this specification and structural equivalents thereof, or in combinations of them. Embodiments described herein can be implemented as one or more non-transitory computer program products, i.e., one or more computer programs tangibly embodied in a machine readable storage device, for execution by, or to control the operation of, data processing apparatus, e.g., a programmable processor, a computer, or multiple processors or computers.

[0075] The processes and logic flows described in this specification can be performed by one or more programmable processors executing one or more computer programs to perform functions by operating on input data and generating output. The processes and logic flows can also be performed by, and apparatus can also be implemented as, special purpose logic circuitry, e.g., an FPGA (field programmable gate array) or an ASIC (application specific integrated circuit).

[0076] The term “data processing apparatus” encompasses all apparatus, devices, and machines for processing data, including by way of example a programmable processor, a computer, or multiple processors or computers. The apparatus can include, in addition to hardware, code that creates an execution environment for the computer program in question, e.g., code that constitutes processor firmware, a protocol stack, a database management system, an operating system, or a combination of one or more of them. Processors suitable for the execution of a computer program include, by way of example, both general and special purpose microprocessors, and any one or more processors of any kind of digital computer.

[0077] Computer readable media suitable for storing computer program instructions and data include all forms of nonvolatile memory, media and memory devices, including by way of example semiconductor memory devices, e.g., EPROM, EEPROM, and flash memory devices; magnetic disks, e.g., internal hard disks or removable disks; magneto optical disks; and CD ROM and DVD-ROM disks. The processor and the memory can be supplemented by, or incorporated in, special purpose logic circuitry.

[0078] The term “comprises” and grammatical equivalents thereof are used herein to mean that other components, ingredients, operations, etc. are optionally present. For example, an article “comprising” (or “which comprises”) components A, B, and C can consist of (i.e., contain only) components A, B, and C, or can contain not only components A, B, and C but also one or more other components. In addition, whenever a composition, an element or a group of elements is preceded with the transitional phrase “comprising” or grammatical equivalents thereof, it is understood that it is contemplated that the same composition or group of elements may be preceded with transitional phrases “consisting essentially of,” “consisting of,” “selected from the group of consisting of,” or “is” preceding the recitation of the composition, element, or elements and vice versa.

[0079] Where reference is made herein to a method comprising two or more defined operations, the defined operations can be carried out in any order or simultaneously (except where the context excludes that possibility), and themethod can include one or more other operations which are carried out before any of the defined operations, between two of the defined operations, or after all of the defined operations (except where the context excludes that possibility).

[0080] When introducing elements of the present disclosure or exemplary aspects or embodiment(s) thereof, the articles “a,” “an,” “the” and “said” are intended to mean that there are one or more of the elements.

[0081] The terms “comprising,” “including” and “having” are intended to be inclusive and mean that there may be additional elements other than the listed elements.

[0082] While the foregoing is directed to embodiments of the present disclosure, other and further embodiments of the disclosure may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.

Claims

Claims:

1. A method of forming a semiconductor device, comprising:forming an amorphous silicon seed layer on a surface of a substrate through a first process cycle, comprising:depositing a first amorphous silicon layer on the surface of the substrate; andexposing the substrate to a hydrogen plasma treatment; and forming a silicon nitride layer on the amorphous silicon seed layer through a second process cycle comprising:forming a second amorphous silicon layer on the amorphous silicon seed layer;exposing the substrate to the hydrogen plasma treatment; and exposing the second amorphous silicon layer to a nitrogen plasma to form the silicon nitride layer.

2. The method of claim 1, further comprising:forming an amorphous silicon capping layer on the silicon nitride layer through a third process cycle comprising:forming a third amorphous silicon layer on the silicon nitride layer; andexposing the substrate to the hydrogen plasma treatment.

3. The method of claim 1, wherein depositing the first amorphous silicon layer comprises exposing the surface of the substrate to a silane-containing precursor in the presence of a plasma at a first pressure.

4. The method of claim 3, wherein the hydrogen plasma treatment comprises treating the substrate with a capacitively coupled plasma at a second pressure that is greater than the first pressure.

5. The method of claim 1, wherein the method is performed in a processing chamber without breaking vacuum.

6. The method of claim 1, wherein the substrate has a plurality of alternating semiconductor layers and at least one feature.

7. The method of claim 6, wherein the at least one feature comprises a bottom surface and at least one sidewall, the at least one sidewall is defined by the plurality of alternating semiconductor layers.

8. The method of claim 7, wherein the first amorphous silicon layer is deposited on the bottom surface of the feature and the at least one sidewall of the at least one feature.

9. The method of claim 7, wherein the plurality of alternating semiconductor layers comprise alternating layers of silicon (Si) and silicon germanium (SiGe).

10. The method of claim 2, wherein the amorphous silicon seed layer has a thickness that is greater than a thickness of the amorphous silicon capping layer.

11. A method of forming a semiconductor device, comprising:depositing an amorphous silicon seed layer on a bottom surface of a feature, wherein the feature has at least one sidewall defined by a plurality of alternating semiconductor layers and a portion of the feature extends into a substrate, the bottom surface of the feature defined by the substrate, and the amorphous silicon seed layer fills the portion of the feature that extends into the substrate;depositing a silicon nitride layer on the amorphous silicon seed layer and the at least one sidewall;depositing a silicon capping layer on the silicon nitride layer formed on the amorphous silicon seed layer; andremoving the silicon nitride layer formed on the at least one sidewall, wherein the silicon nitride layer formed on the at least one sidewall is removed at a faster rate than the silicon capping layer.

12. The method of claim 11, wherein depositing the amorphous silicon seed layer, comprises:depositing a first amorphous silicon layer on the bottom surface of the feature; andexposing the substrate to a hydrogen plasma treatment.

13. The method of claim 12, wherein depositing the silicon nitride layer on the amorphous silicon seed layer, comprises:forming a second amorphous silicon layer on the amorphous silicon seed layer;exposing the substrate to the hydrogen plasma treatment; and exposing the second amorphous silicon layer to a nitrogen plasma to form the silicon nitride layer.

14. The method of claim 13, wherein depositing the silicon capping layer on the silicon nitride layer, comprises:forming a third amorphous silicon layer on the silicon nitride layer; and exposing the substrate to the hydrogen plasma treatment.

15. The method of claim 12, wherein depositing the first amorphous silicon layer comprises exposing the bottom surface of the feature to a silane-containing precursor in the presence of a plasma at a first pressure.

16. The method of claim 15, wherein the hydrogen plasma treatment comprises treating the substrate with a capacitively coupled plasma at a second pressure that is greater than the first pressure.

17. A non-transitory computer readable medium including instructions, that, when executed by a controller of a processing chamber, causes the processing chamber to perform a plurality of operations, comprising:depositing an amorphous silicon seed layer on a bottom surface of a feature, wherein the feature has at least one sidewall defined by a plurality of alternating semiconductor layers and a portion of the feature extends into a substrate, the bottom surface of the feature defined by the substrate, and theamorphous silicon seed layer fills the portion of the feature that extends into the substrate;depositing a silicon nitride layer on the amorphous silicon seed layer and the at least one sidewall; anddepositing a silicon capping layer on the silicon nitride layer formed on the amorphous silicon seed layer.

18. The non-transitory computer readable medium of claim 17, wherein the plurality of operations further comprise:removing the silicon nitride layer formed on the at least one sidewall, wherein the silicon nitride layer formed on the at least one sidewall is removed at a faster rate than the silicon capping layer.

19. The non-transitory computer readable medium of claim 17, wherein: depositing the amorphous silicon seed layer, comprises:depositing a first amorphous silicon layer on the bottom surface of the feature; andexposing the substrate to a hydrogen plasma treatment; depositing the silicon nitride layer on the amorphous silicon seed layer, comprises:forming a second amorphous silicon layer on the amorphous silicon seed layer;exposing the substrate to the hydrogen plasma treatment; and exposing the second amorphous silicon layer to a nitrogen plasma to form the silicon nitride layer; anddepositing the silicon capping layer on the silicon nitride layer, comprises:forming a third amorphous silicon layer on the silicon nitride layer; andexposing the substrate to the hydrogen plasma treatment.

20. The non-transitory computer readable medium of claim 19, wherein depositing the first amorphous silicon layer comprises exposing the surface of the substrate to a silane-containing precursor in the presence of a plasma at afirst pressure and the hydrogen plasma treatment comprises treating the substrate with a capacitively coupled plasma at a second pressure that is greater than the first pressure.

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