One-step packaged multi-mode CMOS BIO-analyzer for point-of-care

Abstract

A point-of-care microfluidics device includes a substrate having a cavity holding an integrated circuit, the integrated circuit having one or more sensing circuits, a source of wireless power that is one of either integrated with the integrated circuit or electrically connected to the integrated circuit residing on the substrate, a layer residing on the substrate, the layer that includes one or more inlets, and one or more microfluidic structures positioned to direct fluids received through the one or more inlets to the sensing circuits on the integrated circuit, a memory to store results generated from the sensing circuits, and a wireless communication circuit to perform at least one of transmitting the results to an external reader when interrogated, receiving programming from the external reader, and supplying a clock signal.

Description

Patent Application U Cal No. BK-2025-042-2-PCT MN No. 407869-0220 ONE-STEP PACKAGED MULTI-MODE CMOS BIO-ANALYZERFOR POINT-OF-CARETECHNICAL FIELD

[0001] This disclosure relates to complementary metal-oxide semiconductor (CMOS) based bio-analyzers, more particularly to millimeter-sized CMOS integrated circuits with microfluidics at a point-of-care.BACKGROUND

[0002] Point-of-Care (POC) diagnostics enable real-time medical testing at or near the patient’s location, in contrast to current practices, where samples are collected at clinics or hospitals and shipped to centralized laboratories for processing and analysis. As a result, POC tests can significantly reduce turnaround time, allowing healthcare professionals to make faster clinical decisions, and enable more personalized medicine. When deployed for at-home use, it can further enable longitudinal tracking of biomarker levels for early onset disease detection. An example includes frequently monitoring troponin levels to treat myocardial infarction at an earlier stage.

[0003] Paper-based lateral flow assays (LFAs) are the most prevalent POC test platform, with widespread commercial use in SARS-CoV-2 rapid antigen tests as well as fertility and pregnancy tests for detecting progesterone and human chorionic gonadotropin (HCG) levels. LFAs transport liquid samples along a test strip via capillary action, enabling target analytes to interact with immobilized capture antibodies and produce a visible color change through bead-based labeling. LFAs are ideal for POC use due to their fast assay time (~15 minutes), ease of use, low cost, and instrument-free operation. However, the simplicity of LFAs also presents limitations. The results are typically qualitative (positive / negative) or, at best, semi-quantitative with a specialized reader. Device reproducibility can be affected by the sample’s interaction with the glass fiber and nitrocellulose matrix as well as manufacturing variations. These constraints limit the broader application of LFAs in disease diagnostics where high sensitivity and low limits of detection (LoD) are critical.

[0004] On the other end of the spectrum are the benchtop analyzers used in centralized laboratories. These instruments are designed for automated sample processing using robotics,enabling the parallel analysis of multiple samples simultaneously. Examples include the Beckman Coulter UniCel Dxi® 800 for high-throughput immunoassays, the Roche LightCycler® 480 for qualitative polymerase chain reaction (qPCR) targeting DNA / RNA analysis, and the Agilent Ultivo® liquid chromatography / mass spectrometer (LC / MS), among others.

[0005] Between LFAs and benchtop analyzers are systems that use portable readers paired with disposable microfluidic cartridges or test strips featuring screen-printed electrodes. One example is the Abbott i-Stat Alinity®, which provides laboratory-grade accuracy and supports direct detection in whole blood samples without the need for sample preprocessing. These microfluidic cartridges typically store preloaded reagents that mix with the sample and include arrays of functionalized electrodes coated with specific immunosensors. Despite their performance, such systems are currently adopted primarily for bedside testing in hospitals. They have not yet achieved widespread distribution like LFAs, mainly due to the requirement for a dedicated reader and the relatively high cost of the cartridges. Table 1 provides a summary comparison of the different technologies.Table 1: Comparison of Different Point-of-Care molecular diagnostics technology

[0006] Integrating millimeter-sized CMOS (complementary metal oxide semiconductor) integrated circuits with microfluidics presents a promising solution. From a platform perspective, this approach can be viewed as either miniaturizing the sensing electronics and embedding CMOS within LFAs to enable precise quantification or downsizing portable readers like the i-Stat and integrating them directly into microfluidic cartridges. Sensitivity can be enhanced by placing the front-end circuits in close proximity to the biosensors, ideally directly above the CMOS circuits. Furthermore, the tailored design and optimizedperformance of CMOS ASICs enable multiplexed detection by accommodating specific sensing mechanisms and signal transduction. Recent examples include protein sensing, specific DNA / RNA detection for infectious diseases, and on-chip cell differentiation and sorting.

[0007] Nevertheless, system-level packaging complexity remains a significant challenge. Most lab-based demonstrations still rely on syringe pumps and external tubing for fluid delivery, making it difficult to integrate more sophisticated microfluidic functions into a fully miniaturized and self-contained system.BRIEF DESCRIPTION OF THE DRAWINGS

[0008] FIGs. 1 A-1B show an embodiment of a packaging flow for a microfluidic device and an embodiment of an integrated CMOS / microfluidics device.

[0009] FIG. 2 shows an embodiment of a one-step CMOS / microfluidic device assembly process.

[0010] FIGs. 3A-3C show an embodiment of a method operating a vacuum-driven microfluidic device.

[0011] FIG. 4 shows an embodiment of a hybrid microfluidic device.

[0012] FIG. 5 shows an embodiment of a method of operating a vacuum-driven device employing antibodies.

[0013] FIGs. 6A-6B show a system block diagram of an embodiment of a CMOS / microfluidic device and an operational timing diagram.

[0014] FIG. 7 shows an embodiment of a downlink demodulation circuit.

[0015] FIGs. 8A-8B show an embodiment of an HFSS simulation setup and an ESD circuit schematic.

[0016] FIG. 9 shows an embodiment of a low dropout regulator.

[0017] FIGs. 10A-10C show schematics of an electrochemical sensing front end, an analog front-end multiplier, and an equivalent impedance model of a three-electrode system.

[0018] FIGs. 11 A-l IB show equivalent circuit models of a resistive transimpedance amplifier (R-TIA) and a capacitive transimpedance amplifier (C-TIA).

[0019] FIGs. 12A-13C show an embodiment of a signal folding front end and its output signal and behavior and a time-domain waveform.

[0020] FIG. 13 shows an embodiment of a low-leakage switch.

[0021] FIGs 14A-14C show a schematic of a temperature sensor and a pH sensor, and crosssections of embodiments of sensing membranes.

[0022] FIGs. 15A-15B show an image of an embodiment of a CMOS chip, and an inner seal ring gap for metal routing.

[0023] FIG. 16 shows a schematic of an embodiment of a reader device.

[0024] FIGs. 17A-17D show an embodiment of wireless operation of a microfluidic device through four operation modes.

[0025] FIGs. 18A-18C show a design and images of an embodiment of a microfluidic device.

[0026] FIG. 19 shows a graph of the relationship between the sampled readouts and the target concentration follows a power law with an added offset.DETAILED DESCRIPTION OF THE EMBODIMENTS

[0027] The embodiments here present a fully integrated multi-mode POC device that requires single-step assembly and operates autonomously. Drawing inspiration from RFID technology and implantable systems, the embodiments employ inductively-coupled wireless powering and communication functionality into a CMOS bio-analyzer. The wireless source of power may be integrated into the integrated circuit or electrically connected to the integrated circuit. By making the chip fully wireless, it can be easily integrated into a substrate carrier. Sample delivery occurs via automated fluidic transport using a vacuum-driven flow, eliminating the need for pumps or manual operation. The chip integrates electrochemical, pH, and temperature sensors, providing a versatile platform for immunosensing applications.

[0028] Flowing fluids directly on top of a raw die with electrical connections presents significant challenges in device assembly, particularly due to the substantial size mismatch between the millimeter-sized CMOS chip and the centimeter-scale microfluidic device.Integrating CMOS and microfluidics while preventing fluidic leakage and maintaining a scalable, high-throughput assembly process is critical. Ideally, embedding CMOS chipsshould also be compatible with mainstream microfluidics manufacturing methods with minimal modifications.

[0029] Various packaging techniques have been developed. Here, the embodiments present an assembly flow. As illustrated in FIG. 1 A, in one embodiment of a package 10 the CMOS die 14 is first embedded in a printed circuit board (PCB) 12 using biocompatible epoxy 16 to create a level surface. Afterward, the CMOS pads are wirebonded to the PCB, and the wirebonds such as 18 are encapsulated with the same epoxy. Once complete, a PDMS microfluidic layer, which may be fabricated using a 50-pm thick SU-8 mold or 3D printing, can then be mechanically sealed or glued onto the PCB. FIG. IB shows the assembled device. However, the throughput is limited by the epoxy curing time (~24 hours at 25°C).Furthermore, the bonding wires reduces the available space for fluidic routing. Alternative approaches have been explored to address these limitations. One method replaces wirebonds with litho-graphically patterned thin metal traces across the chip-substrate interface while another approach uses liquid metal for electrical connections. These examples demonstrate that the need for electrical connections creates a primary bottleneck in CMOS / microfluidic integration.

[0030] The embodiments here present a solution that eliminates electrical connections by equipping CMOS dies with wireless capabilities. Motivated by the single-chip RFID technology, an inductive-coupling approach is chosen due to the ease of integrating coils on-chip. FIG. 2 illustrates the processing flow 20. The flow utilizes elastic and porous materials, such as polydimethylsiloxane (PDMS) as the substrate 22, into which the CMOS die 14 is press-fitted into a cavity 24 of matching dimensions, formed by molding onto a dummy CMOS chip. The microfluidics layer 28, which may also be fabricated through PDMS molding, are then plasma-bonded to the substrate, and the device assembly is complete in one step. During the readout, the microfluidics device will be placed on a reader such that the CMOS chip with a receiving coil is aligned to a PCB transmitting coil with a larger size. The coil-to-coil distance is governed by the microfluidics substrate and can be well-defined to within 1 ~ 2 mm. The embodiments use a thin coverslip 30, such as a glass slide of ~6 mil, to serve as the carrier to minimize electromagnetic attenuation. While PDMS is used in the illustration, the proposed concept is compatible with other microfluidic materials, such as 3D-printed resins or thermoplastic polymers like poly(methyl methacrylate)(PMMA).

[0031] Fluid delivery without external pumps is a critical requirement in POC devices. This has been achieved through capillary action in LFAs, active electro-osmotic, and many others. The device of the embodiments utilizes vacuum-driven flow but may also use capillary action. This method works by first evacuating air from a porous material (e.g., PDMS) using a vacuum. Upon subsequent exposure to atmospheric pressure, a negative pressure gradient is established as air slowly diffuses back into the porous matrix, thereby drawing liquid into the microfluidic channels, provided that the outlet is sealed as shown in FIG. 3 A. The blood enters the inlet 32 and through sedimentation in a first reservoir 34 plasma is extracted and flows through the channel 36 to the reservoir 38.

[0032] In one implementation of the final product, this vacuum is pre-established by sealing the device in a vacuum-sealed pouch 40 shown in FIG. 3C. During operation, the user tears open the pouch 40 and adds a drop of sample at inlet 42 shown in FIG. 3C, upon which the fluid flow automatically begins. A delay of a few minutes between opening the pouch and applying the sample is acceptable, since air diffuses slowly into PDMS. The addition of the reagent can be controlled by covering the reagent inlet 44, such as with a piece of tape 46. The microfluidic device can be designed with multiple inlets for sequential loading of samples and reagents. Some embodiments with multiple inlets may employ a hybrid microfluidic design that uses both porous and non-porous materials. For example, the main microfluidic body can be constructed from a non-porous material, while only the outlet region is packed with a piece of vacuumed PDMS slab.

[0033] FIG. 4 shows an embodiment of a microfluidic device design. The substrate 50 may comprise a non-porous material and has the microfluidic structures. A layer 52 of adhesive such as an epoxy is deposited, which may be laser cut. This forms the base device 56. The sample inlet 58 and the reagent inlet 60 are in the non-porous section of the substrate 56. The microfluidic device is designed to interface with various types of biofluids, including whole blood. It is crucial to filter out blood cells as it minimizes their interference with the readout sensor and other biofouling effects. Currently, blood cells are removed through centrifugation, which requires benchtop equipment. To integrate cell filtration directly into the microfluidic device, the embodiments incorporate a deep well, or trench filter, 64 near the sample inlet that allows heavier cells to sediment using gravity. The downstream fluidic channel 62 can be designed at a reduced height to physically constrain cells from entering. A porous PDMS or other material slab 54 resides only in the outlet area, which is also the region in which sensing is accomplished by the CMOS integrated circuit 66. The outletportion also contains the reservoir 68 to which the blood or other biological fluid flows past the sensing area.

[0034] The embodiments of the POC device employs antibody-based immunosensors based on enzyme-linked immunosorbent assay. There, two antibodies forming a sandwich with the target molecule to improve both the limit-of-detection (LOD) and specificity. Conventional ELISA requires multiple steps, including reagent additions, washing, and long incubation times. In contrast, the SimpleStep ELISA protocol from Abeam can be adopted to reduce assay times. Briefly, enzyme-conjugated detection antibodies are mixed with the sample of interest (e.g., plasma). After a wash step, the reaction substrate is added. This substrate is catalyzed by the enzyme, leading to a measurable color change. A common enzyme-substrate pair is horseradish peroxidase (HRP) and 3,3',5,5,5-tetramethylbenzidine (TMB).

[0035] There are multiple ways to adapt these well-based ELISA protocols into the CMOS / microfluidic device. The first approach is to directly load the reacted TMB substrate solution into the device, where it can be readout through electrochemical sensing. In the embodiments discussed here, the readout comprises current but other types of readouts including but not limited to charge, impedance, optical, magnetic based, etc. The measured redox current is proportional to the amount of unreacted TMB. Therefore, the readout is inversely proportional to the amount of HRP and, consequently, to the target concentration. In other words, a higher target concentration will result in a lower current readout. The second approach immobilizes the captured antibodies onto electrodes patterned on top of the CMOS chip. As the duplex formed by the target molecule and the detection antibody flows by, a sandwich complex is formed on chip, while unbound detection antibodies are washed into the waste reservoir. After approximately 15 minutes of incubation, the TMB substrate is added, and the CMOS chip measures the redox current to quantify the number of enzymes. Here, the wash-step is replaced by inserting an air bubble between the sample and the substrate fluids, creating an insulating barrier that separates unbound detection antibodies from the substrate. The workflow is summarized in FIG. 5.

[0036] In the embodiment of FIG. 5, the blood being tested in mixed with a detection antibody and HRP, or other material that acts as half of the enzyme-substrate pair, at 70. At 72, this sample mixture is added to the first inlet. The tape is then removed to allow air to flow into the second inlet at 74. The second half of the enzyme-substrate pair is then added to the second inlet at 76 and the device is prepared for readout from the sensing area by the IC.FIG. 5 shows an exploded view of the resulting immunocomplex. The demonstration employed the first approach for simplicity. The platform is designed to be generalizable and can be tailored for different types of biosensors, including but not limited to antibody -based immunosensors, DNA-based aptamers, and CRISPR-based biosensors, among many others Multiplexed readout of a panel of biomarkers can be achieved by functionalizing the electrodes with different immunosensors.

[0037] In addition to offering quantitative rather than qualitative results, the proposed CMOS / microfluidic platform is expected to provide an economic advantage by achieving a cost comparable to existing LFAs when mass produced at the wafer level using a mature technology node, such as the 180-nm CMOS mentioned above. The microfluidic materials and fabrication processes, such as injection molding, have been well-established over the past two decades, enabling high-throughput manufacturing. Furthermore, the embodiments have significantly simplified CMOS / microfluidic integration by embedding wireless capability, which further reduces the packaging costs. The dominant cost contributor will likely be the biosensing reagents and associated processing, estimated at a few dollars per device.However, since the reagent requirements are comparable to those in other bioassays, the overall cost can remain low, driven by the inexpensive CMOS die and the proposed packaging scheme. It is important to note that the cost of the reader cannot be ignored. As detailed below, a custom-built reader was developed to interface with the wireless CMOS chip, primarily due to the use of a non-standard carrier frequency and communication protocol. This reader is provided as an example to demonstrate how the POC device works. However, this limitation can be addressed in future designs by developing CMOS chips that directly interface with commercial smartphones. Such an approach would eliminate the need for a dedicated reader, thereby further reducing cost and improving portability.

[0038] The discussion now turns to a discussion of aspects of the electronics part of the POC device. FIG. 6A shows an embodiment of a system block diagram 80 and FIG. 6B shows an operational timing diagram. FIG. 7 shows an embodiment of a downlink (DL) demodulation circuitry.

[0039] In the examples here, the chip is inductively powered at 700 MHz through an on-chip, or receive, coil 82 measuring 1.5 mm x 1.5 mm in conjunction with an off-chip, or transmit, coil 84. The coil size is primarily determined by the area needed to accommodate all the integrated circuits at its center. The power management 86 begins with a two-stage cross-coupled rectifier that generates a supply voltage (Vrect) exceeding 2 V, which in turn powers a 1.25-V bandgap reference (BGR) and three separate 1.8-V low-dropout regulators (LDOs). These LDOs supply power to the FSM controllers and digital peripherals, the analog sensing circuits, and the on-chip memory. A 200-pF MIMcap stabilizes Vrect. Due to its small capacitance, the system must be operated with continuous wireless powering. One should note that the current wireless power involves the two coils, but any form or wireless power may be used such as acoustic powering, light powering, etc., including those currently in development. The wireless aspect allows for the POC device to be self-contained and not involve processes like wire bonding, as mentioned above.

[0040] Upon initialization, the chip undergoes a power-on-reset (POR), after which the digital LDO is enabled. A 16-bit chip ID is then generated using the intrinsic random variation of 6T-SRAM cells and transmitted via the data uplink (UL) in the digital control subsystem 88 for registration. The UL is driven by an on-chip 1.8-MHz relaxation oscillator and remains active for 1 msec. After this initial transmission, the system enters initialization mode.

[0041] The chip operates in four functional modes, cycled by 400-ns end-of-power (EOP) pulses. These modes are: (1) initialization, (2) data downlink (DL), (3) sensing, and (4) data uplink (UL). In downlink (DL) mode, the FSM enables the analog and memory LDOs and begins demodulating the incoming data. The demodulated bits are serialized into a 128-bit serial-in parallel-out (SIPO) shift register, shown in FIG. 7. A bit error checker compares the first eight bits to those hard-coded on-chip. The FSM proceeds to the next phase only if both the DL bit count and error checker validate the received DL data. The DL mode employs pulse width modulation-amplitude shift keying (PWM-ASK) where data is encoded based on the pulsewidth (PW). In this scheme, Vrect is first modulated with a triangular waveform by adjusting the carrier power at different durations. An asynchronous hysteresis comparator compares Vrect with its own moving average to generate digital pulses of different pulse width. These pulse-widths control the integration time of a current source onto a capacitor. A pulsewidth ratio of 3 : 1 (at a unit of 1 psec) between bit one and zero offers a reliable demodulation.

[0042] The multi-sensor readout 90 lies at the core of the system, in this embodiment involving three sensors measuring redox current, pH, and temperature, with only one sensor activated during each sensing cycle. The electrochemical sensor supports bothchronoamperometry (CA) and square-wave voltammetry (SWV), with the latter requiring high timing precision. To meet this requirement, the on-chip relaxation oscillator is bypassed during sensing; instead, a 2.5-MHz external clock (CLKDL) in the digital control 88 is provided via the downlink path. This clock is selected based on the sampling rate of the 10-bit SAR ADC and is recovered through a separate demodulation circuit. Data acquisition begins once the external clock is detected. The digitized sensor output data are stored in a 1 KB on-chip memory. Once the memory 92 is full, the FSM transitions the system to initialization mode, awaiting the next end-of-power (EOP) pulse to enter the uplink (UL) mode. The operation can also be interrupted from the reader by stopping delivering CLKDL. The pH sensor is implemented with ion-sensitive field-effect transistor (ISFET) and a BJT (bipolar junction transistor) is used as the temperature sensor. The UL employs Miller-encoded load-shift keying (LSK) and operates at up to 0.9 Mbps. The reader detects the UL data by monitoring the amount of reflected power. A preamble is included to facilitate pattern synchronization. After all stored data are transmitted, one complete operation cycle is concluded. If the system remains powered, it can re-enter sensing mode directly via the EOP signal, bypassing the need for reconfiguration through the downlink (DL) phase. FIG. 6B shows the timing diagram of the signals.

[0043] FIG. 8A illustrates on embodiment of the on-chip coil 84 geometry. While there are no strict constraints on the coil size, a millimeter-scale dimension (1.5 mm x 1.5 mm) is chosen to minimize silicon area while accommodating all necessary circuit components. The operating frequency (700 MHz) is selected to maximize power transfer efficiency (PTE) when interfacing with a single-turn, 5.4-mm diameter PCB coil with a 10-mil side copper trace, targeting a delivered power of approximately 5 mW. The size of PCB chip coil 84 is chosen for easier alignment. A powering distance of ~1 mm is assumed and is controlled precisely by the thickness of the microfluidic chip-hosting substrate. Since the microfluidic channels 94 run directly on top of the CMOS chip, fluid-induced loading and associated degradation are considered.

[0044] FIG. 8B shows an embodiment of the ESD diode chain 96, rectifier, and diode clamp 100. The results of the HFSS (high-frequency structure simulator) are as follows. The Q factor of the chip coil was compared under three loading conditions: (1) in air, (2) immersed completely by 0.9%-saline (c = 1.45 S / m), and (3) loaded with a saline-filled microfluidic channel having a cross-sectional area of 500 pm x 500 pm. The results show that the Q factor is reduced by nearly half when the entire coil is loaded with saline, from 9.7 to 5.2, butdecreases by only 13.4% under partial fluidic loading. This degradation is primarily because the dominating dielectric loss is from the fringing electric fields between the coil windings, and microfluidics only induce partial loading. The coupling factor (k) is 0.063 per simulation and a maximum available gain (Gmax) of -5.2 dB is achieved using a two-port transformer model resonating at 700 MHz. This corresponds to a theoretical PTE of 30%. The simulated Q of the PCB coil is approximately -100 and remains largely unaffected by fluidic loading. To avoid eddy currents degrading the coupling factor, the power distribution network was laid out using dense power grids in the top two metal layers while avoiding large metal planes. The circuits, which are implemented mostly with fully differential architecture, are also shielded by these power grids to minimize electromagnetic interference (EMI) from the powering carrier. Considering -50% efficiency from the rectifier 98 and the -1.5 dB matching circuit losses, the total efficiency is around 10%. Note that the powering frequency does not fall within the ISM band in this prototype work, and adaptation to the 915-MHz band would be required for future practical use. The elevation of the frequency indeed comes with the cost of a reduced PTE from 10% to 5% per an analysis, yet the drop can be compensated by either increasing the RF power from an external reader or reducing the powering distance by employing a thinner microfluidics substrate, with an ultimate limit set by the silicon die thickness. From the HFSS simulations, the total PTE ranges from 12.3 -4.6% when the powering distance is increased from 0.5 to 2 mm.

[0045] To prevent the 2.5-MHz Vrect ripples created from the downlink clock signal from impacting the sensor performance due to the low LDO power supply rejection (PSRR) at the MHz ranges, the embodiments introduce an additional feedforward RC filter path in the design to synthesize a notch filter. FIG. 9 shows a schematic of an embodiment of an LDO. The RC low-pass filter (Rnand Cn) 102 is added in the current mirror comprised of transistors M2, M3, and M4, of the source follower in between the error amplifier and the pass transistor M5. A notch in PSRR is formed by its low-pass filtering response and the high-pass filtering effect induced by the 4-pF Miller compensation capacitor (Cm). To compensate for process and layout-induced mismatches, the filter Cn capacitor is made programmable (2-4 pF). The notch frequency is inversely proportional to the square-root of Cn, and can be adjustable by -0.9 MHz centered around 2.5 MHz. The Miller compensation capacitor Cm also ensures the LDO stability. Simulation results show a phase margin (PM) of 74° and 50° under nominal and minimal load currents of 1.5 mA and 30 pA, respectively. The LDO consumes aquiescent current of 4 pA. The LDO achieves 40 dB and > 25 dB PSRR at near-DC and at the 2.5-MHz band, respectively.

[0046] FIG. 10A shows the complete sensor chain, with a primary focus on electrochemical sensing of immunosensor responses. FIGs. 10B-C, 11A-B, 12A-C, 13, 14A-C, and 15 show more detailed implementations of the various aspects of the system. The electrochemical cell consists of working (WE), reference (RE), and counter (CE) electrodes. Redox reactions are activated by sweeping the potential between the WE and RE. A potentiostat, implemented using a rail-to-rail amplifier Al consuming a total of 150 pA, locks the fluidic bias sensed at the RE to a desired potential through CE voltage adjustment. This configuration compensates for voltage drops caused by the ionic resistance between the RE and WE and enables higher voltage precision. The VWE is set by the common-mode feedback of the front-end transimpedance amplifier TIA 104, shown in FIG. 10B, and is tunable from 0.8 ~ 1.0V. The electrochemical cell potential (VWE-- VRE) can thus span from -0.9 V to +0.9V. The voltages are set using two on-chip voltage DACs at 11 -bit and 4-bit resolutions. The former is built from R-2R architecture.

[0047] The system also incorporates temperature and pH sensors 108 to compensate for environmental variations that affect electrochemical readouts through changing mass transport, electron transfer kinetics, antibody-antigen binding affinity, and the activity of enzymes. The correction can be implemented through a look-up table that maps changes in signal sensitivity and offsets across different pH and temperature conditions, based on measurements performed in advance.

[0048] The embodiments employ a fully differential transimpedance amplifier (TIA) topology as the current readout front-end for its superior common-mode and power-supply rejection when compared to the single-ended counterpart that are commonly used in the prior works. Here, the two inputs of the TIA are connected to two separate working electrodes (WEI and WE2), where biosensors are immobilized. Both WEs will be functionalized but with different capturing antibodies and therefore only one responds to the target molecule and the other serves as a reference. Another benefit of a differential TIA is the rejection of the common-mode noise originating from the POT and the upstream circuits. The extent of noise cancellation depends on the impedance matching between the two WEs with respect to RE, ZWEI and ZWE2, shown in FIG. 10C, which originates from the formation of electrical double layer at the electrode / electrolyte interface and the ionic resistance. Utilizing electricalimpedance spectroscopy (EIS) across 1 Hz - 1 MHz, it was found that the impedance mismatch can be controlled to within 5% if the electrode areas are well matched. This allows for the cancellation of more than 90% of the potentiostat’s output noise voltage. This could also translate to power savings in the potentiostat. Otherwise, every circuit in the signal chain will need to consume equal amounts of power so that the noise is evenly distributed.

[0049] One embodiment implements the TIA using a capacitive feedback topology shown in 1 IB. Unlike resistive feedback, shown in FIG. 11 A, the capacitive-feedback TIA (C-TIA) integrates the redox current over time and outputs a voltage corresponding to the accumulated charge. This approach can significantly amplify the signal magnitude, offering improvements in the sensitivity. While the operation is identical to standard chronoamperometry (CA) protocols, the C-TIA readout reflects the integrated charge, so the mode is referred to as chronocoulometry (CC). CC has been used in electrochemistry to study charge transport phenomena and is typically performed via software post-processing of the measured CA currents. In contrast, the embodiments integrate the CC function directly into the electronics front-end to gain signal-to-noise ratio (SNR) boost.

[0050] FIGs. 11 A-l IB shows the equivalent circuit models of the two TIAs for noise analysis. A single-ended version is adopted for simplicity. Note that the specific measurements here are for ease of understanding, and other implementations may have different measurements. From previously measured electrochemical impedance spectroscopy (EIS) responses from passivated gold electrodes between 1 Hz to 1 MHz, the solution resistance (Rsoi) was identified to be approximately IkQ, the double-layer capacitance (CDL) was ~5nF for a 250 pm-diameter circular electrode, and the charge transfer resistance varied depending on the redox species concentration, typically on the order of 20 MQ. At the upper bound of the integrated noise bandwidth (-100 Hz), the impedance of the double-layer capacitor (-318 k ) dominates, the interface can be further simplified as a single capacitor CDL. Noise from POT was assumed to be negligible, and thus the inputs to the double-layer capacitance (CDL) are terminated to a ground. Both the signal level and the voltage noise were derived at the outputs of the two TIAs. This approach differs slightly from conventional sensor chain design, where noise is typically referred to the input of the readout.

[0051] First, derive the voltage noise at the output of both TIAs. Assuming the transconductance amplifiers (OTAs) have sufficiently high gain, the noise power spectral density (PSD) at the TIA outputs can be approximated as:>where

[0052] Here, represents the current noise from the feedback resistor RF, andVV,OTA^ denotes the input-referred voltage noise of the OTA. In the R-TIA, the low-frequency noise is primarily dominated by the thermal noise of RF , but it exhibits noise peaking at higher frequencies due to the pole formed by RF and CDL. In contrast, the OT”s noise contribution in C-TIA is significantly amplified by the inverse of the feedback factor p. From the experiments, the CDL can exceed 5 nF for a passivated electrode. Thus, the amplification factor can be greater than 300, even with a relatively large integration capacitor (CINT) of 16 pF. Assuming RF of 1 M and an OTA input-referred voltage noise of 4 nV / Hz, the output noise voltage is approximately 128 nV / Hz for the R-TIA and 1.254 pV / ^Hz for the C-TIA, illustrating a -10 / difference between the two architectures.

[0053] One should also consider the signal levels at both TIA outputs and find the corresponding signal -to-noise ratio (SNR, expressed in a unit of V / V) at a given bandwidth (fnw):

[0054] Here, the OTA noise in the R-TIA was ignored for simplicity. In addition, both types of readouts are generally designed to be noise-limited with a bandwidth of larger than 10 kHz. For example, the bandwidth of R-TIA is set by l / (27t+RF+CF) and equals to 10 kHz with RF = 1 MQ and CF = 16 pF, and the unity-gain bandwidth (fu) of the C-TIA is gm / (27t+CINT+P), which equates to 127 kHz with a gm of 4 mS and CINT = 16 pF. Thus, a low-pass filter succeeding the TIAs is included to perform the necessary noise filtering to achieve a low bandwidth (-100 Hz). As such, the fBW in both eq. (4) and eq. (5) are identical. Assuming CDL » CINT, the ratio between two SNRs can be expressed as SNRC-TIA_ TINT■ [J TINT(6) SNRR_TIA CINT■ RF■ n CDL- RF- nwhere n represents the ratio between OTA and RF noise:

[0055] Results from (6) indicate that there is a minimum integration window (TINT) required for the C-TIA to achieve improved SNR. This is related to the time constant formed by the double-layer capacitance (CDL) and the feedback resistance (RF), which equals 5 msec based on the parameters described above. Since CDL is determined by the electrode area and the surface chemistry, the key parameters for improving SNR are reducing the OTA noise or increasing the integration time. Critically, the value of CINT has comparatively less impact, and therefore, CINT can be maximized for handling a larger input current while being constrained only by the available on-chip area. The design of the embodiments takes advantage of the inherently slow kinetics of immunosensors by extending the integration time Tint beyond a second and enhance the SNR by up to three orders of magnitude compared to the R-TIA. This extended integration time is also the key differentiator of the approach of the embodiments compared to the earlier works in discrete-time TIAs having a short integration time and at kHz sampling rates. Note also that the higher output noise in C-TIA relaxes the designs in the following stage for potential power saving. The C-TIA indeed requires a reset switch, and its sampling noise, which equates to ^2kT / CiNT, can be mitigated using correlated double sampling (CDS). Here, k is the Boltzmann constant, and T is the operatingtemperature.

[0056] The OTA is implemented using a current-reuse topology that employs both PMOS and NMOS input pairs to enhance transconductance efficiency, along with cascode stages for improved gain, shown in FIG. 10C. Each branch consumes 200 pA of current. A commonmode feedback (CMFB) circuit is included, where source followers buffer the OTA outputs, and the feedback loop regulates 1 / 5 of the total tail current. Accounting for both the current source and sink, the available output swing is limited to 0.6 Vpp single-endedly.

[0057] To extend the dynamic range, a signal-folding circuit is incorporated, as shown in FIG. 12A. This circuit automatically resets the integration capacitor with a short pulse whenever the C-TIA output exceeds a predefined threshold (VTH = 1.35 V), as detected by a continuous-time comparator shown in the timing diagram of FIG. 12B. The number of resets (Nrst) is counted, and the total accumulated charge is determined by:where Vswing is predefined at 0.45 V. The degree of dynamic range extension is dictated by two factors: the integrator gain-bandwidth product and the reset time. Assuming the integrator requires a minimum of 5 nsec for both the integration and reset, the equivalent time-average I max can be found by:and / max is -720 pA, shown in FIG. 12C. However, to ensure complete discharging in design, the reset-triggering signal was retimed by a 100 kHz clock and a 10-psec reset pulse was generated. Consequently, the maximum current is constrained by TRST and drops to 720 nA. Nevertheless, benchtop tests using a commercial potentiostat indicated that > 100 nA is sufficient in the intended applications. Another critical benefit of having an extended dynamic range is to accommodate the offset currents induced by the “electrochemical leakage currents” at the two working electrodes. Details are discussed below.

[0058] Following the TIA is a switched-capacitor variable-gain amplifier (VGA) with tunable gain (0-40 dB) and bandwidth (100 Hz to 10 kHz). The embodiments employ a 10-bit fully differential synchronous SAR ADC, 110 in FIG. 10 A, for digitization.

[0059] Careful attention must be given to the design of switches in the C-TIA to minimize the switch current leakage, particularly in the proposed chronocoulometry (CC) mode, where an integration window on the order of a second is used. The leakage stems from non-zero potential differences across PN junctions and along the device channel in a MOS transistor. To suppress leakage, one may adopt the body-driven low-leakage switch techniques such as 112 in FIG. 10A. FIG. 13 shows an embodiment of an implemented switch design. PMOS devices are used to avoid the need for a deep N-well, which is required for an NMOS switch. The body and drain of transistor Mi are actively driven by the unity-gain buffer to be identical with that from the source when the switch is off. The buffer amplifier A3 uses a PMOS-input folded cascode topology. Simulation results show an input leakage current of approximately 0.18 fA with the switch sizing (W7L = 8 pm / 0.18 pm) under fast-fast comer at 100 °C. Considering 3o offset (8.4 mV) of the unity gain buffer, the worst-case input leakage becomes 16.6 fA. Note that leakage currents can also inject shot noise (i„ / Af = 2ql), where q is the unit charge and I is the amount of leakage current, which equates to 2.3 fArms when integrated over 100 Hz. By having two reset switches in the fully-differential C-TIA, the shot noise increases to ~5 fArms and is negligible.

[0060] Another source of noise is those generated by the amplifier A3 during the integration while the switches are in their off states. In this phase, noise from the unity-gain buffer A3 may couple into the integrator through the off-state impedance of transistor Mi shown in FIG. 13. While accurately modeling the off-state impedance of a MOSFET is challenging, the simulations indicate that it can exceed 200 GQ under the typical corner. Given that buffer A3 exhibits a simulated output noise of ~55 Vrms, the resulting input-referred noise contribution is estimated to be < 1 fArms, which is over two orders of magnitude smaller than that of the main C-TIA input noise. In general, PMOS devices in the off-state can exhibit resistances > 1 GQ, as demonstrated in prior studies using PMOS transistors as pseudo-resistors for high-impedance biasing. In the design, the drain and body potentials were further controlled to increase the off-resistance, and a worst-case resistance of 10 GQ was estimated. Under this condition, the noise contributed from A3 remains ~10 fArms.

[0061] The temperature and pH sensors 108 are shown in FIG. 10A. Temperature sensors are implemented using bipolar junction transistors (BJTs) biased with a constant current source, producing a base-emitter threshold voltage (VBE) that decreases with reference, the differential voltage is amplified and digitized, shown in FIG. 14A.

[0062] An embodiment of a pH sensor is implemented using the ion-sensitive field-effect transistor (ISFET), where an ion-sensitive, such as a dielectric, membrane is coated over the gate of a transistor, shown in FIG. 14A. In one embodiment, the ISFETs are extended gate ISFETs (EG-ISFETs). The measured voltage change follows that from the Nernst equation and is approximately 59mV per pH change. A reference electrode (RE) and reference electrode FET (REFET) provides the gate bias through a capacitive divider formed by the oxide and the gate capacitance. Changes in the surface potential will modulate the gate voltage of the FET, which can be read out by configuring the FET as a source follower. FIG.14A shows the schematic of an embodiment. This embodiment adopts a differential architecture using two identical transistors with different sensing membranes to cancel common-mode noise and drift.

[0063] The sensors may employ one of two types of sensing membranes including (1) a naturally formed AI2O3 layer 113 that is about 4 ~ 5 nm thick, shown in FIG. 14B and (2) a deposited SiCE layer 114 using low-temperature (350 °C) plasma-enhanced chemical vapor deposition (PECVD), shown in FIG. 14C, with thicknesses tunable between 10-20 nm. The former is expected to provide better sensitivity, albeit at the cost of long-term electrode integrity and sensing stability.

[0064] The proposed wireless bio-analyzer is implemented in TSMC 180-nm CMOS technology. FIG. 15 shows an image of an embodiment of the chip 116. One embodiment of the chip measures 2 mm x 3.25 mm and the core system resides inside the 1.5 mm x 1.5 mm coil on the left. The design includes wired connections to bonding pads for testing, and all pads are grouped on the right side of the chip. The chip can be diced along a central diesawing lane, resulting in a pad-less chip with a smaller footprint. Both the left and right sections of the chip are enclosed by seal rings. To accommodate signal routing and, more importantly, to avoid degradation in inductive power transfer efficiency, a 100 pm gap 118 is introduced in each of the seal rings, shown in FIG. 15B. The entire chip is surrounded by another continuous outer seal ring to improve yield during wafer-level die-sawing. The embodiments employed laser cutting to selectively break the continuity of this outer seal ring and observed ~2x difference in the measured power transfer efficiency.

[0065] In an embodiment, the CMOS chip was post-processed by coating the aluminum pads with gold (Au) electrodes using an electroless nickel immersion gold (ENIG) process.Although ENIG is widely used in printed circuit board (PCB) fabrication, additional surface treatment is required to facilitate electroless nickel deposition onto non-catalytic aluminumsurfaces. The process is briefly described. First, the naturally formed aluminum oxide (AI2O3) layer on the pads is removed using nitric acid. The chips are immersed in a zincate solution (composed of zinc oxide and sodium hydroxide) for 20 seconds at room temperature, which partially displaces the aluminum with a thin zinc layer that serves as the catalytic base for the nickel (Ni). This step is conducted twice to form a more uniform zinc coating. Next, electroless nickel deposition is carried out via autocatalytic reduction of nickel ions. This process is performed in a water bath at 80 °C for 20 minutes. After rinsing, electroless gold deposition is performed at 80 °C for 6 minutes. Approximately 1 pm of aluminum was displaced by zinc, with final nickel and gold layer thicknesses of 2.5 pm and 200 nm, respectively. All chemicals were supplied by ChuangZhi Technology, Taiwan.

[0066] During the ENIG process, the ISFET sensing pads, which have an identical structure as the regular aluminum pads, are protected by passivation layers to prevent them from reacting with ions in the ENIG plating solutions. These passivation layers are only removed after the ENIG process is complete. The coating materials used include PECVD-deposited SiO? and manually applied Crystalbond 509. The SiCh can be removed with selective etching using reactive ion etching (RIE) while Crystalbond 509 dissolves in acetone.

[0067] In studies, the ENIG-coated electrodes exhibited reliable performance over the course of a few hours in the lab experiments with biofluids at a well-controlled pH centered around 7.2. No visible corrosion or significant degradation in electrode integrity is observed. That said, the possibility of nickel underneath the gold being exposed to the biofluids at the electrode edges, particularly if gold coverage is incomplete, could lead to localized reactions. This issue can be mitigated through passivation techniques, such as applying an additional oxide, nitride, or inert photoresist layer (e.g., SU-8), to encapsulate the electrode perimeter while leaving the central sensing region exposed.

[0068] As mentioned above, a custom modularly-implemented reader was designed to evaluate the wireless CMOS chip. FIG. 16 illustrates an embodiment of the reader schematic. The reader 120 includes a signal generator 122, a passive mixer 124, a waveform generator 126, a power amplifier 128, a directional coupler 130, a matching circuit 132, and a singleturn PCB coil 134. The specific examples of the components used are merely for ease of understanding and no limitation to these particular components is required. This path formulates the signals required for wireless powering and data / clock DL. The PCB coil is series-resonant with a SMD capacitor at 700 MHz, and an L-match circuit is used for impedance matching to 50Q. The S11 of the matching circuit was measured when the coil isloaded with the CMOS IC. For the UL, the directional coupler captures reflected power induced by the on-chip load-shift keying (LSK) modulation. The coupled signal is routed to a power detector 136, followed by a baseband amplifier 138. The output was sampled by an oscilloscope 140 and demodulated offline.

[0069] FIGs. 17A-17D show an embodiment of wireless operation through the four modes mentioned above. During initialization shown in FIG. 17 A, Vrect ramps up rapidly to approximately 3 V, then stabilizes at 2.5 V once the relaxation oscillator is enabled. Near the end of the 1-msec on-time, the chip transmits its ID number back to the reader for checking and registration. After an end-of-power (EOP) pulse, the chip enters the downlink (DL) mode. Pulse-width modulated amplitude shift keying (PWM-ASK) perturbs Vrect to activate the DL demodulation circuits. A correct demodulated pattern is shown in the inset of FIG. 17B. Thanks to the supply rejection of the low-dropout regulator (LDO), the digital VDD remains regulated at 1.8 V despite significant Vrect fluctuations. The error checker outputs a high if no error is detected when comparing the received data against the 16-bit fixed pattern hardwired into the chip. The reader asserts another EOP signal to switch the chip into sensing mode and supplies a precise 2.5-MHz off-chip clock via ASK modulation, shown in FIG. 17C. The ADC (analog-to-digital converter) digitizes the sensor signals, stores the data in on-chip memory, and subsequently transmits it to the reader through load-shift keying (LSK) once in uplink (UL) mode shown in FIG. 17D. After data transfer is complete, the chip enters the idle mode, awaiting the next EOP signal, which will place it back into DL mode for further configuration. The nominal Vrect required for stable operation is 2.5 V. With a peak current consumption of 2 mA, occurring during amperometric sensor operation, the system consumes an average power of 5 mW. The measured power supply rejection ratio (PSRR) of the LDO was obtained by superimposing a 10-mV sinewave onto Vrect. The measurements span from 1 kHz to 10 MHz. The PSRR is approximately -40 dB at low frequencies, showing a deviation of around lOdB compared to simulation. This discrepancy is recognized as a measurement limitation, since higher rejection levels result in signal amplitudes approaching the noise floor, making accurate measurement difficult. A peak was observed near 1 MHz, with a notch at approximately 2.5 MHz. By adjusting the capacitance of the low-pass filter, the notch frequency can be tuned to 2.5 MHz, achieving a maximum rejection of -38 dB. The measured results closely match simulation predictions.

[0070] The input-referred power spectral density (PSD) of the amperometry circuit was measured. The measurement setup includes two 5-nF SMD capacitors to model the electrodedouble-layer capacitance, characterized via electrical impedance spectroscopy (EIS) using a potentiostat (PalmSens4). With a 100-Hz low-pass filter, the measured input-referred noise current is 0.24 pArms. Next, the dynamic range of the front-end was characterized. Without the signal folding circuitry, the maximum measurable current is 960 pA using a 10-msec integration window. With signal folding enabled, the measurable range extends to 661 nA, resulting in an extended dynamic range of 128.8 dB. These results are consistent with simulations and are primarily limited by the 10-psec reset time, as discussed previously. Some embodiments may use inverters to generate sub-0.5-ns reset pulses, potentially extending the dynamic range beyond 150 dB.

[0071] The performance of other sensor circuits is summarized. The VGA has a tunable bandwidth from 100 Hz to 12 kHz. The 10-bit SAR ADC demonstrates measured DNL and INL of 0.74 / -0.98 LSB and 0.77 / -0.82 LSB, respectively, with a worst-case SNDR and SFDR of 58.0 dB and 68.3 dB. The R-2R DAC exhibits measured DNL and INL of-0.65 / +0.60 LSB and -2.27 / + 1.48 LSB, respectively. The combined output noise from the DAC and potentiostat is 9.5 pVrms at a 100-Hz bandwidth.

[0072] The temperature sensor exhibits a measured error of -1.24 ~ +1.46 °C when characterized from 0 ~ 50 °C in an oven. Wireless temperature readout is demonstrated by mounting a resistive heater (implemented using an SMD resistor) on the backside of the PCB that hosts the chip. A type J thermocouple connected to an NI USB-TC01 temperature sensor is placed near the chip for calibration. The measurement results show a linear correlation with R2= 0.97. The observed measurement error is primarily attributed to the open-air test environment, where air convection introduces temperature fluctuations.

[0073] Wireless pH measurements were also performed using standard pH solutions (Hanna Instruments) and compared the pH sensitivity of a naturally formed aluminum oxide (AI2O3) membrane with that of a 20-nm chemical vapor deposited (CVD) SiCh dielectric membrane. The AI2O3 membrane exhibited higher sensitivity due to its thinner and more reactive structure; however, its response varied between acidic and basic conditions. This variation is attributed to the higher reactivity of AI2O3 with hydroxide ions (OH ) compared to protons (H+) at room temperature, as well as the deprotonation of surface hydroxyl groups in basic environments. Measured sensitivities were 91.7 mV / pH from pH 4 to 6 and 172 mV / pH from pH 6 to 9. The pH sensor with the SiO2 membrane exhibits excellent stability with minimal drift when measured in a pH 7 buffer over the course of one hour. The measured pH noise was 0.064 pHrms, calculated by dividing the output RMS voltage noise by the sensor'ssensitivity (55 mV / pH). The AhOs-based pH sensor demonstrates good stability over a 5 ~ 10 minute period and achieved a comparable noise level of 0.07 pHrms due to a simultaneous increase in both output noise and sensitivity. The results of longer-term stability are not yet available and will be carried out in the future. Though the measurement drift remains small (< 3 mV) within the first three hours of intermittent measurements, AI2O3 membranes are known to degrade in acidic and basic environments and are therefore not suitable for longterm use. This limitation is less critical in the embodiments, as the developed device is intended for single-use applications. pH sensing is performed immediately upon sample contact with the electrode and typically completes within 15 minutes. Furthermore, the pH of the target biofluids is expected to remain within the physiological range of 6.8 to 7.4.

[0074] FIG. 18A illustrates an embodiment of the design and the photo of the microfluidics. The base structure is fabricated from thermoplastic material. Unlike prior designs using PDMS, the use of thermoplastics enables scalability through high-throughput manufacturing techniques such as injection molding. The base includes open fluidic channels, meaning without a top enclosure, which are sealed using a 3M Scotch double-sided adhesive film. The design features two inlets 144 and 146 for sample and reagent delivery, while outlet 148 is positioned above a waste reservoir 150.

[0075] Vacuum-driven flow is achieved by sealing the outlet with a piece of degassed PDMS. The duration of vacuum-driven flow is determined by the volume of the PDMS and requires careful optimization. With a PDMS volume of 2.5 cm x 2.5 cm x 0.5 cm, experiments show that the vacuum can be sustained for up to 20 ~ 25 minutes, which is sufficient for most user cases. Such a PDMS size also fits into the final device having a size close to a 3” x 1” glass slide, which is chosen to ensure the device can be held easily by hand. The PDMS is degassed under -1.0 atm pressure for 2 hours. After mounting the PDMS, the entire assembly is placed into a polymer vacuum pouch and sealed using a precision vacuum sealer. Slightly different from the earlier discussion, the new device does not require the user to tear open the vacuum pouch. Instead, the pouch can be punctured at the two inlets 144 and 146 using a single-pin or dual-pin needle for sample and / or reagent loading. A demonstration figure is shown in FIG. 18B. As shown in FIG. 18C, fluid flow begins upon loading, and the two fluids streams converge at a Y-junction 152 and reaches the sensing zone 154 where the CMOS readout IC 148 is located shown in FIG. 18B.

[0076] A standard enzyme-linked immunosorbent assay (ELISA, Invitrogen, KHA0031) was used to demonstrate the platform. The target of interest is C-reactive protein (CRP), a keyacute-phase inflammatory biomarker that plays a critical role in disease diagnosis, particularly in bacterial infections such as sepsis and pneumonia, where CRP levels can exceed 100 pg / mL. CRP molecules are captured with a sandwich format, where capture antibodies and HRP-conjugated detection antibodies bind to the target, forming an immunocomplex shown in the exploded view of FIG. 5. HRP can catalyze the oxidation of TMB (3,3',5,5'-tetramethylbenzidine), a chromogenic substrate of HRP. Upon the addition of TMB, the released electrons can be electrochemically measured by CC. In this demonstration, instead of immobilizing the capture antibodies directly on the CMOS electrodes, the procedure was simplified by transferring the post-reaction solution to the CMOS / microfluidic platform for indirect detection using unfunctionalized gold electrodes.

[0077] The goal was to quantify the remaining active TMB molecules after their reaction with HRP, thereby indirectly inferring the CRP concentration. A higher CRP level leads to more HRP being captured on the well surface, consuming more TMB, and thus resulting in fewer free-floating active TMB molecules in the solution. This yields a lower redox current during chronoamperometric measurements. Conversely, a lower CRP level results in less HRP and more unreacted TMB in the medium, leading to a higher redox current. It is important to note that this workflow is intended for wireless platform demonstration and does not reflect the final implementation for practical use.

[0078] The experimental workflow follows the kit instructions and are briefly summarized as follows. First, CRP samples were prepared at seven concentrations (18.75 to 1200 pg / mL) by diluting the lyophilized Hu CRP standards from the kit. A volume of 100 pL from each dilution was added to seven wells pre-functionalized with capture antibodies, and an additional well containing only buffer served as a control. The samples were incubated for 2 hours at 37°C. After washing, 100 pL of biotin-conjugated detection antibodies was added to each well and incubated for 1 hour at room temperature. Subsequently, 100 pL of streptavidin-HRP solution was added and incubated for another 30 minutes. Finally, 100 pL of TMB chromogen was added to each well, initiating a colorimetric reaction that turned the solution blue. The reacted solutions were transferred into eight 200-pL PCR tubes for electrochemical measurement. CC was performed using the CMOS / microfluidics platform and benchmarked against Palmsens 4. The WE were biased at -0.1 V relative to the RE. Measurements were conducted in descending TMB concentration order. Between each measurement, the electrodes are fully washed with a buffer solution to remove any remaining samples. Higher CRP concentrations resulted in lower voltage responses, indicating lowerredox currents due to greater TMB consumption. The waveforms were sampled at t = 0.7 seconds to construct the binding curve. The relationship between the sampled readouts and the target concentration follows a power law with an added offset. To benchmark the performance, readouts were compared with the CA measurements obtained with the PalmSens 4, shown in FIG. 19. The two datasets exhibited a linear relationship with a slope of 5.409 V / pA (FIG. 23(d)). The linear nature of the curve validates the accuracy of results from the wireless chip while the slope being greater than unity indicates an improved sensitivity over those measured by PalmSens 4. All measurements were conducted in triplicate, using three different electrodes, and the measured standard deviation was 1.34 pg / mL.

[0079] Variations and modifications are of course possible. The above discussion addressed the benefits of employing a differential front-end to reject noise originating from the potentiostat (POT). The degree of noise rejection strongly depends on the impedance matching between the two working electrodes. To quantify this, electrochemical impedance spectroscopy (EIS) measurements were performed on eight microfabricated gold electrodes with identical areas using a PalmSens 4. In the results, across 1 Hz to 1 MHz, the total coefficient of variation (CV) of the impedance magnitude was less than 3%, suggesting that the expected mismatch in double-layer capacitance (CDL) between area-matched electrodes can achieve approximately 30 dB of common-mode rejection. Here, the CV is a measure of relative variability and calculated as the standard deviation divided by the averaged impedance at each frequency point.

[0080] Assuming a noise level of ~1 pVrms injected from the potentiostat through the reference and counter electrodes, and a CDL of ~5 nF (equivalent to ~318 kQ at 100 Hz — the upper bound of the noise bandwidth), the resulting input-referred current noise caused by the 3% CDL mismatch is estimated to be ~94 fArms, which is less than the measured C-TIA input-referred noise of 240 fArms.

[0081] Note that the chemical noise presented at the two WEs is uncorrelated. The source of the chemical noise includes random ion fluctuations and shot noise associated with electron transfer processes. The former is strongly influenced by the quality of the passivated electrode surface and is typically characterized through empirical measurements. The latter, shot noise, is given by 2qlredox, where Iredox is the redox current.

[0082] As an example, with Iredox = 2 nA and a 100 Hz bandwidth, the resulting shot noise is approximately 0.25 pArms, which is comparable to the input-referred noise of the front-endelectronics (0.24 pArms). When chemical noise is also considered, the total noise observed during electrochemical sensing is typically higher than that seen in pure electronics characterization.

[0083] At the electrode-electrolyte interface, a potential difference exists across the interfacial region due to ion accumulation. This is primarily caused by positively charged metal ions dissolving into the medium, leaving behind electrons in the electrode.Additionally, the immobilization of charged molecules on the electrode surface can further influence this interfacial potential. This creates an electrode “offset” voltage, which is commonly observed in electrodes used in the biopotential measurements such as ECG, EEG, and neural recoding. A similar electrode voltage exists in the electrochemical cells, and the actual electrode potential is further impacted by the molecules immobilized on the electrode as the ion distributions at the electrode-electrolyte interface will be perturbed. The integrity of the molecular passivation is y formed pinholes or defects in the passivation layer are quite common.

[0084] On the other hand, the impact of electrode offset voltages in electrochemical sensors differs from that in biopotential amplifiers. In electrochemical sensing, where redox currents are measured, the effect of electrode offset voltages induced by WEI and WE2 are less critical. This is primarily because the front-end employs a low input-impedance current readout, unlike biopotential systems that typically utilize high-impedance voltage sensing. In electrochemical cells, the main effect of electrode offset voltages is to shift the voltage drop across the Debye layer slightly from the biases provided by the electronics, thereby altering the overpotential that drives redox reactions. This shift can potentially influence the measured redox current. However, this issue can be readily mitigated by adjusting the reference electrode (RE) voltage through an on-chip DAC (digital-to-analog converter). This compensation strategy is also utilized in cyclic voltammetry (CV) and square-wave voltammetry (SWV), where the potential difference between the working and reference electrodes is swept to identify oxidation and reduction current peaks. In other words, while electrode offset voltages may shift the observed oxidation / reduction potentials horizontally in CV or SWV measurements, their impact on redox current amplitudes is minimal. On the other hand, in both the chronoamperometry (CA) and chronocoulometry (CC), the electrode biases remain constant during current measurements and are more sensitive to the electrode voltages. Thus, a CV scan prior to CA / CC modes is included to calibrate the potential drifts induced by the electrode offsets.

[0085] The medium typically contains various ions and molecules that can also participate in charge transfer, especially if the electrode surface is not properly passivated. Randomly formed pinholes or defects in the passivation layer can allow unintended redox species or ions to directly interact with the electrode surface, resulting in undesired current flows. These are referred to as “electrochemical leakage currents” to separate them from the leakage currents induced by the electronics (such as those arising from the switches). These electrochemical leakage currents can vary from electrode to electrode, and are area sensitive, leading to different baseline offset currents that are integrated by the front-end integrator circuit. Additionally, it was found experimentally that the physical separation between the working electrode (WE) and the reference electrode (RE) can further alter these leakages. If the WE-to-RE distance varies among electrodes in a differential readout configuration, it can lead to additional current mismatch and unwanted signal integration. The experiments identified this variation in WE-RE distance and passivation quality as one of the major contributors to inter-electrode variability. The issue can be mitigated by implementing on-chip lithographically patterned electrodes with well-matched geometries and spacing.

[0086] The offset current (ios) induced by mismatches in electrochemical leakage currents between the two electrodes (ios = iwEi— iwE2) must either fall within the dynamic range of the front-end circuits, and is one of the key motivations for employing the signal-folding technique, or be compensated using on-chip configurable and bidirectional current DACs at the two inputs of the C-TIA, which are not implemented in this work. In contrast, the common-mode components of the electrochemical leakage currents are less critical, as they can be absorbed by the common-mode feedback circuitry of the C-TIA, which offers a compensation range of ±40 pA.

[0087] In a standard ELISA experiment, the antigen-antibody binding and subsequent enzymatic reaction typically follows power-law kinetics. The reaction is monitored via changes in optical density (OD) at a specific wavelength. Since the reaction solution begins as transparent with zero CRP concentration, the resulting OD increases proportionally with the amount of enzymatic reaction product. Therefore, the OD-concentration relationship can generally be described as a power law, which appears linear in the log-log domain:OD = X [C]kL (10)log(OD') = fc2X log([C]) + / q, (H)where [C] represents the CRP concentration, and ki and ki are fitted constants.

[0088] However, in the electrochemical measurement, there is a DC value in the readout, even in the absence of CRP. This DC value is mainly due to baseline electrochemical reactions. Assuming that the readout is proportional to the change in accumulated charge (Q), the charge-concentration relationship can be expressed as follows:Q = k x [C]fc3, (12)On the other hand, the output voltage from the integrator can be modeled as:where Voffset is the initial biasing voltage, CINT is the integration capacitor, and X)is the system time constant.

[0089] The signal (y) is sampled at a fixed sampling time (t=0.7 sec), therefore:

[0090] For simplification, one can assume T is independent of concentration, and the eq. (14) can be simplified to:y = Pi x [c + p3, (15) where pi, p2, and ps are fitted parameters of the developed model.

[0091] This expression models the integrator output as a power law with offset in the linear domain. The presence of ps distorts the response in the log-log domain, therefore it is essential to be included. By fitting the data using this model, the fitting accuracy improved significantly, achieving R2= 0.9905, compared to R2= 0.8285 using a simple power law fit (or linear fit in the log-log domain).

[0092] This derivation explains the deviation between the electrochemical measurements and the optical readout from the ELISA kits.

[0093] An embodiment of an assembly flow for CMOS / microfluidic devices may use mass production using industrial manufacturing equipment in a cleanroom environment. First, the CMOS dies with patterned electrodes, and the microfluidic substrates are cleaned with solvents and then sterilized via autoclaving at high temperature. Next, the die is placed into a cavity machined into the microfluidic substrate using robotic assembly tools. The two components are then laminated to complete the microfluidic integration. Third, capture antibodies are introduced into the microfluidic channel, where they immobilize onto the electrode surfaces. This incubation is carried out at room temperature or 2-8 °C for a few hours or overnight, depending on the surface chemistry. For example, thiol-based chemistry can be employed to orient antibodies on gold surfaces. Afterward, unbound reagents are washed away, followed by electrode passivation to prevent non-specific binding. In the next step, the device is vacuum-dried to remove residual moisture and prevent antibody denaturation during long-term storage. The degassed PDMS slab for vacuum-driven flow is then attached, and the whole device is immediately sealed under vacuum in moisture-barrier foil pouches with desiccant. The device can be stored at room temperature or in standard home refrigerators to extend shelflife prior to use. When ready for use, the user can open the pouch or use a needle to break the vacuum and apply the sample to the inlets.

[0094] The device shelflife will be governed by how well the vacuum can be retained after prolonged storage and the activity loss from the immunosensors. Regarding the vacuum-actuated microfluidics design, testing shows that the cartridges stored for two months under the same vacuum-sealed conditions exhibited no observable degradation in flow performance while it demonstrated that PDMS cartridges stored in vacuum-sealed pouches retained full flow functionality after three years. Their findings indicate that the limiting factor for shelflife is antibody stability rather than the vacuum itself. For immunosensors, most commercial antibody assays can tolerate storage at room temperature for up to one week without significant loss of activity. However, their shelflife can be extended to as long as one year if stored at 4 °C. In contrast, lateral flow assays (LFAs) typically achieve a shelflife of over six months at room temperature. It is anticipated that the final production-level devices will achieve similar stability as LFAs. This can be accomplished through vacuum-drying to remove residual moisture, followed by sealing the device in a foil pouch with a desiccant. In more demanding scenarios, lyophilization (freeze-drying) could be considered for further stability enhancement; however, its impact on antibody structure and function requires additional investigation.

[0095] The embodiments present a CMOS bio-analyzer system-on-chip with wireless powering and data communication. By employing near-field inductive coupling through an on-chip coil, electrical connections are eliminated, significantly simplifying the assembly of the millimeter-sized CMOS die with microfluidics into a single-step process. The system uses vacuum-driven flow to automate sample transport and delivery and integrates an electrochemical sensing front-end to read out signals from immunosensors.

[0096] All features disclosed in the specification, including the claims, abstract, and drawings, and all the steps in any method or process disclosed, may be combined in any combination, except combinations where at least some of such features and / or steps are mutually exclusive. Each feature disclosed in the specification, including the claims, abstract, and drawings, can be replaced by alternative features serving the same, equivalent, or similar purpose, unless expressly stated otherwise.

[0097] Additionally, this written description makes reference to particular features. It is to be understood that the disclosure in this specification includes all possible combinations of those particular features. For example, where a particular feature is disclosed in the context of a particular aspect, that feature can also be used, to the extent possible, in the context of other aspects.

[0098] Also, when reference is made in this application to a method having two or more defined steps or operations, the defined steps or operations can be carried out in any order or simultaneously, unless the context excludes those possibilities.

[0099] Although specific aspects of this disclosure have been illustrated and described for purposes of illustration, it will be understood that various modifications may be made without departing from the spirit and scope of the invention. Accordingly, the invention should not be limited except as by the appended claims.

Claims

IN THE CLAIMS:

1. A point-of-care microfluidics device, comprising:a substrate having a cavity holding an integrated circuit, the integrated circuit having one or more sensing circuits to generate results;a source of wireless power that is one of either integrated with the integrated circuit or electrically connected to the integrated circuit residing on the substrate;a layer residing on the substrate, the layer comprising:one or more inlets; andone or more microfluidic structures positioned to direct fluids received through the one or more inlets to the sensing circuits on the integrated circuit;a memory to store the results generated from the one or more sensing circuits; and a wireless communication circuit to perform at least one of transmitting the results to an external reader when interrogated, receiving programming from the external reader, and supplying a clock signal.2 The device as claimed in claim 1, further comprising a slide underneath the substrate, and a bond between the slide and the substrate.

3. The device as claimed in claim 1, wherein the source of wireless power comprises a chip coil electrically coupled to a transmit coil.

4. The device as claimed in claim 1, wherein the one or more inlets comprise at least one of a sample inlet.

5. The device as claimed in claim 1, wherein the one or more microfluidic structures comprise at least one of channels, cell filtration, mixing channels, and reservoirs.

6. The device as claimed in claim 1, wherein the one or more microfluidic structures comprise automated fluidic transports.

7. The device as claimed in claim 6, wherein the automated fluidic transports are automated by one of vacuum pull or capillary forces.

8. The device as claimed in claim 1, wherein at least one of the sensing circuits comprises a biosensor to measure biomarkers.

9. The device as claimed in claim 8, wherein the biosensor comprises a pseudodifferential capacitive transimpedance amplifier (C-TIA).

10. The device as claimed in claim 9, wherein the C-TIA includes one or more integration capacitors and a signal folding circuit electrically connected to at least one integrationcapacitor, the signal folding circuit configured to reset the at least one integration capacitor when an output of the at least one integration capacitor exceeds a pre-defined threshold.

11. The device as claimed in claim 1, wherein at least one of the sensing circuits comprises one or more of a pH sensor, and a biosensor.

12. The device as claimed in claim 11, wherein the pH sensor comprises differential extended-gate ion-sensitive field effect transistors (EG-ISFET) and at least one of the EG-ISFETs includes a sensing membrane.

13. The device as claimed in claim 12, wherein the sensing membrane comprises a dielectric membrane.

14. The device as claimed in claim 1, wherein at least one of the sensing circuits comprises a temperature sensor.

15. The device as claimed in claim 14, wherein the temperature sensor comprises a bipolar junction transistor and is configured to monitor a base-emitter threshold voltage of the bipolar junction transistor with respect to a bandgap reference as an indicator of temperature.

16. The device as claimed in claim 1, further comprising a multiplexer connected to the one or more sensing circuits.

17. The device as claimed in claim 1, further comprising at least one of a variable-gain amplifier and a filter electrically connected to the one or more sensing circuits.

18. The device as claimed in claim 17, further comprising an analog-to-digital converter electrically connected to an output of the at least one of the variable-gain amplifier and the filter to digitize the output producing a digitized output, and to store the digitized output in the memory.

19. The device as claimed in claim 1, further comprising at least one of a chip ID checker and an error checker.

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