Determining wafer bow characteristics

Abstract

Techniques for characterizing wafer bow are provided. In some embodiments, a method for determining wafer bow characteristics may involve projecting, using a projection device disposed in or on a portion of a semiconductor fabrication chamber, one or more fringe pattern images onto a surface of a wafer. The method may further involve capturing, using one or more camera devices, images representative of reflections of the one or more fringe pattern images from the surface of the wafer. The method may further involve generating an unwrapped phase map based on the captured images. The method may further involve generating a three-dimensional reconstruction of a surface of the wafer based on the unwrapped phase map using phase-measuring deflectometry.

Description

Attorney Docket No. LAM1P054WO-10182-1WODETERMINING WAFER BOW CHARACTERISTICSINCORPORATION BY REFERENCE

[0000] A PCT Request Form is filed concurrently with this specification as part of the present application. Each application that the present application claims benefit of or priority to as identified in the concurrently filed PCT Request Form is incorporated by reference herein in their entireties and for all purposes.BACKGROUND

[0001] During fabrication of a wafer or substrate, the wafer may bow, or warp. This may cause downstream problems. For example, it may be difficult to clamp a wafer to a chuck or pedestal when the wafer is bowed, which may cause improper device formation. Additionally, wafer bow may cause the wafer to break or otherwise be unstable. It may be difficult to determine whether a wafer is bowed, the degree to which a wafer is bowed, and / or regions of the wafer that are bowed, which may make it difficult or even impossible to mitigate wafer bow.

[0002] The background description provided herein is for the purposes of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.SUMMARY

[0003] Disclosed herein are techniques for determining wafer bow characteristics.

[0004] In some embodiments, a method for determining wafer bow characteristics may involve projecting, using a projection device disposed in or on a portion of a semiconductor fabrication chamber, one or more fringe pattern images onto a surface of a wafer. The method may involve capturing, using one or more camera devices, images representative of reflections of the one or more fringe pattern images from the surface of the wafer. The method may involve generating an unwrapped phase map based on the captured images. The method may involve generating a three-dimensional reconstruction of a surface of the wafer based on the unwrapped phase map using phase-measuring deflectometry.

[0005] In some examples, the method may further involve determining wafer bow characteristics based on the three-dimensional reconstruction. In some examples, the method may further involve determining one or more backside deposition parameters to correct wafer bow indicated by the wafer bow characteristics. In some examples, the method may further involveAttorney Docket No. LAM1P054WO-10182-1WO determining film stress metrics based on the wafer bow characteristics. In some examples, the method may further involve determining in-plane displacements for silicon overlay error correction of lithographic masks.

[0006] In some examples, the three-dimensional reconstruction is generated in situ under hot wafer bow conditions.

[0007] In some examples, the three-dimensional reconstruction is generated during a time period when the wafer is being moved on end effectors.

[0008] In some embodiments, a method for determining wafer bow characteristics using deflectometry may involve generating and projecting one or more fringe patterns on a wafer. The method may involve capturing resulting image(s) using one or more cameras. The method may involve generating an unwrapped phase map based on the images captured using the one or more cameras. The method may involve estimating slopes in the x and y directions for surface points of the wafer based on the unwrapped phase map. The method may involve generating a three-dimensional reconstruction of a surface of the wafer based on the estimated slopes. The method may involve determining wafer bow characteristics associated with the wafer based on the three-dimensional surface reconstruction.

[0009] In some examples, the wafer bow characteristics are determined on a cold wafer.

[0010] In some examples, the wafer bow characteristics are determined on a heated wafer. In some examples, wafer bow characteristics are determined for the heated wafer in situ as the wafer undergoes processing. In some examples, the method further involves determining parameters to clamp the heated wafer based on the determined wafer bow characteristics. In some examples, clamping the wafer comprises vacuum clamping, and wherein the parameters comprise a differential pressure to be applied to clamp the wafer that is determined based on the wafer bow characteristics. In some examples, clamping the wafer comprises electrostatic clamping, and wherein the parameters comprise an electrostatic force to be applied that is determined based on the wafer bow characteristics. In some examples, the one or more fringe patterns projected on the wafer comprise a single fringe pattern projected on the heated wafer. In some examples, generating the unwrapped phase map comprises providing the resulting image(s) to a trained machine learning model configured to generate, as output, the unwrapped phase map.

[0011] In some examples, generating the unwrapped phase map comprises performing temporal unwrapping using images associated with multiple fringe patterns projected on the wafer, the multiple fringe patterns having multiple phase shifts and fringe frequencies.Attorney Docket No. LAM1P054WO-10182-1WO

[0012] In some examples, the one or more fringe patterns projected on the wafer comprise a plurality of fringe frequencies and a plurality of phase shifts for each fringe frequency. In some examples, the method further involves performing system calibration to determine calibration parameters for: the one or more cameras used to capture the resulting image(s); a camera to wafer calibration: and a camera to projector calibration for the projector used to project the one or more fringe patterns. In some examples, the calibration parameters comprise: a focal length for each of the one or more cameras, a center of the camera sensor image plane for each of the one or more cameras, and / or lens distortion parameters for each of the one or more cameras. In some examples, the one or more cameras comprise two cameras, and wherein performing the system calibration comprises determining calibration parameters to calibrate the two cameras to each other.

[0013] In some examples, a slope-height ambiguity is resolved by one of: capturing the resulting images using two cameras at the same time; utilizing two projection devices to project the one or more fringe patterns, wherein the two projection devices are shifted by a known amount with respect to one another; determining distance to the wafer surface using a distance sensor; or utilizing multiple projection device to project the one or more fringe patterns and utilizing two cameras to capture the resulting images.

[0014] In some examples, estimating the slopes in the x and y directions comprises estimating normal vectors for a set of surface points on the surface of the wafer.

[0015] In some examples, determining the wafer bow characteristics comprises determining wafer bow magnitude and direction for a set of points corresponding to the surface of the wafer.

[0016] In some embodiments, a system for determining wafer bow characteristics may comprise: a projection device disposed in or on a portion of a semiconductor fabrication chamber, wherein the projection device is configured to project one or more fringe pattern images onto a surface of a wafer; a first camera disposed in or on a portion of the semiconductor fabrication chamber; a second camera disposed in or on a portion of the semiconductor fabrication chamber, wherein the first camera and the second camera are configured to capture images of reflections of the projected one or more fringe pattern images from the surface of the wafer; and one or more processors. The one or more processors may be configured to: generate an unwrapped phase map based on the captured images; and generate a three-dimensional reconstruction of a surface of the wafer based on the unwrapped phase map using phasemeasuring deflectometry.

[0017] In some examples, the portion of the semiconductor fabrication chamber comprises a portion of a front end module, and wherein the three-dimensional reconstruction of the surfaceAttorney Docket No. LAM1P054WO-10182-1WO of the wafer is generated when the wafer is transferred from a front opening unified pod (FOUP) to a load lock or from the load lock to the FOUP.

[0018] In some examples, the projection device is disposed in a first viewport of a process station of the semiconductor fabrication chamber, and wherein the first camera is disposed in a second viewport of the process station. In some examples, the second camera is disposed in a third viewport of the process station. In some examples, the first camera and the second camera have different viewing angles, and wherein the one or more processors are further configured to stitch together images captured by the first camera and the second camera.

[0019] In some embodiments, a system for determining wafer bow characteristics may comprise a metrology tool associated with a semiconductor fabrication apparatus comprising. The metrology tool may comprise: a projection device, wherein the projection device is configured to project one or more fringe pattern images onto a surface of a wafer; a first camera and a second camera, wherein the first camera and the second camera are configured to capture images of reflections of the projected one or more fringe pattern images from the surface of the wafer, wherein the metrology tool is configured to receive the wafer from the semiconductor fabrication apparatus; and one or more processors. The one or more processors may be configured to: generate an unwrapped phase map based on the captured images; and generate a three-dimensional reconstruction of a surface of the wafer based on the unwrapped phase map using phase-measuring deflectometry.BRIEF DESCRIPTION OF THE DRAWINGS

[0020] FIGS. 1A and IB illustrate diagrams representing a bowed wafer in accordance with some embodiments.

[0021] FIG. 2A is a diagram of an example system for characterizing wafer bow using deflectometry in accordance with some embodiments.

[0022] FIG. 2B is a diagram illustrating principles of deflectometry in accordance with some embodiments.

[0023] FIG. 3 is a flowchart of a process for determining wafer bow characteristics in accordance with some embodiments.

[0024] FIG. 4A and 4B are flowcharts of example processes for determining unwrapped phase maps in accordance with some embodiments.

[0025] FIG. 5 is a flowchart of an example process for estimating slopes for a set of surface points of a wafer in accordance with some embodiments.Attorney Docket No. LAM1P054WO-10182-1WO

[0026] FIG. 6 is a diagram that illustrates techniques for resolving points on a wafer surface in accordance with some embodiments.

[0027] FIG. 7 depicts graphs representing wafer bow characteristics for an example wafer in accordance with some embodiments.

[0028] FIGS. 8A, 8B, 9, and 10 depict examples of apparatuses that each include a system for characterizing wafer bow in accordance with some embodiments.

[0029] FIG. 11 presents an example computer system that may be employed to implement certain embodiments described herein.DETAILED DESCRIPTION

[0030] In the following description, numerous specific details are set forth to provide a thorough understanding of the presented embodiments. The disclosed embodiments may be practiced without some or all of these specific details. In other instances, well-known process operations have not been described in detail to not unnecessarily obscure the disclosed embodiments. While the disclosed embodiments will be described in conjunction with the specific embodiments, it will be understood that it is not intended to limit the disclosed embodiments.

[0031] During fabrication of a wafer or substrate, the wafer may bow, or warp. This may cause downstream problems. For example, it may be difficult to clamp a wafer to a chuck or pedestal when the wafer is bowed, which may cause improper device formation. Additionally, wafer bow may cause the wafer to break or otherwise be unstable. It may be difficult to determine whether a wafer is bowed, the degree to which a wafer is bowed, and / or regions of the wafer that are bowed, which may make it difficult or even impossible to mitigate wafer bow.

[0032] FIGS. 1 A and IB depict examples of wafer bow in accordance with some embodiments. FIG. 1 A is a two-dimensional diagram of an instance of wafer bow. As illustrated in FIG. 1 A, bowed wafer 104, compared to a flat wafer 102, has a curved surface. Wafer bow may be characterized in magnitude by determining a distance or a height of a point of the wafer relative to where the surface of the wafer would be if the wafer were perfectly flat. In some instances, bow magnitude may be determined with respect to a center point of the wafer (e.g., a height of bow at the center point of the wafer). Wafer bow may additionally or alternatively be characterized in shape. For example, characterization of wafer bow may involve determining whether the wafer bow is concave or complex, and where the direction of wafer bow changes over the surface of the wafer. For example, in some cases, a wafer may be bowed in a convex manner in one region and in a concave manner in another region.Attorney Docket No. LAM1P054WO-10182-1WO

[0033] FIG. IB illustrates a three-dimensional depiction of a bowed wafer. Note that, as illustrated in FIG. IB, in some cases, the wafer may be bowed with different magnitude and / or direction in different regions of the wafer. It should be noted that a bowed wafer may have a convex bow, a concave bow, and / or a complex bow (e.g., that includes multiple bowed regions having different bow shapes and / or magnitudes). For example, in some cases, a bowed wafer may have a saddle-shaped bow.

[0034] As described above, wafer bow may occur as a material is deposited, which may cause the wafer to warp. Processing stations and fabrication apparatuses, when performing a process on a wafer, may clamp the wafer undergoing processing to a surface, such as a pedestal or chuck. Clamping a bowed wafer may cause numerous problems. For example, non-uniform bow may cause backside leakage. As another example, the wafer may break due to instabilities over time, e.g., if the bowed wafer is clamped with inappropriate force. As yet another example, devices and / or spacing on wafer may be inaccurate. For example, wafer bow may have downstream effects of causing inaccuracies in patterning masks and subsequent processing steps, which may cause overlay errors and inaccurate spacing and placement of devices on the wafer. Accordingly, it is important to understand the magnitude and characteristics of wafer bow both on a cold wafer (before the wafer undergoes subsequent processing steps) and / or on the heated wafer in situ. Wafer bow characteristics may then be used to control clamping of the wafer as it undergoes processing. By utilizing the appropriate clamping characteristics, the bowed wafer may be securely clamped without inducing breakage and / or inaccuracies in fabricated devices.

[0035] Conventional techniques generally utilize a stylus such as a scanning laser stylus or a spring-loaded stylus that scans a line of the wafer to measure wafer bow. Based on reflections along the line, wafer bow along the line may be determined. However, conventional techniques do not allow for wafer bow to be characterized across the entire surface of the wafer. For example, because wafer bow may be different at, e.g., wafer edges relative to the center and / or in one region relative to another, conventional techniques are not able to fully and accurately characterize wafer bow. Moreover, conventional techniques can only characterize wafer bow on a cold wafer. Because wafer bow changes as a wafer is heated, and may change in unpredictable ways, accurate in situ characterization of wafer bow may allow for in situ control of clamping of the wafer, which may allow for improved device fabrication, less wafer breakage, and higher wafer yield.

[0036] Disclosed herein are techniques for utilizing deflectometry to characterize wafer bow.Attorney Docket No. LAM1P054WO-10182-1WO Deflectometry refers to computer vision algorithms and techniques that use the laws of reflection to characterize and / or re-construct a surface. In particular, if a surface under test, such as a wafer surface, is tilted by a given angle (e.g., due to wafer bow), the reflected ray will have an angle that is twice the surface tilt angle. Deflectometry techniques, as used herein, may utilize this law of reflection to characterize a wafer surface, and accordingly, characterize wafer bow. The techniques may be used on a cold wafer and / or in situ on a wafer as it undergoes processing and as the wafer heats and reaches a final heated temperature. Note that although the techniques described herein generally utilize deflectometry, in some embodiments, the techniques may be utilized with a phase measuring profilometry approach. Profilometry refers to techniques to reconstruct a surface (e.g., a wafer surface) using closed form solutions based on the intensity of a reflected light source. It should be noted that, deflectometry, as generally described herein, may be preferable for characterizing specular surfaces, such as a wafer surface.

[0037] FIG. 2A illustrates an example deflectometry system 200 in accordance with some embodiments. Deflectometry system 200 may be used to characterize the surface of a wafer 202. As illustrated, a computing device 204 may be used to control projection of a screen pattern by a monitor device 208. Computing device 204 may be a desktop computer, a laptop computer, a tablet computer, or the like. In some implementations, computing device 204 may be a projection system such as a projector (e.g., utilizing a laser, a broadband white light source, etc.), or any other type of projection system that is capable of imposing fringe patterns on a wafer surface either by reflection or direct projection on the wafer surface . Computing device 204 may be local to a semiconductor fabrication apparatus or may be remote. In instances in which computing device 204 is remote from monitor device 208, computing device 204 may communicate with monitor device 208 via a communication channel, such as a wireless communication channel.

[0038] The screen pattern that is projected onto the wafer surface is generally referred to herein as a fringe pattern. In general, a fringe pattern is a pattern that alternates light and dark bands in a two-dimensional sinusoidal light pattern. As illustrated, the screen pattern projected by monitor device 208 includes bands of high contrast which repeat at a given frequency, generally referred to herein as a “fringe frequency,” which refers to the number of fringe cycles. Note that although the bands in the screen pattern repeat horizontally, in some embodiments, the bands may repeat vertically. It should be noted that fringe frequency is based on the spatial resolution and is generally represented as a number of pixels a dark and bright band (e.g., one “cycle” of the fringe pattern) cover. The fringe frequency is specifiedAttorney Docket No. LAM1P054WO-10182-1WO for a given camera resolution, e.g., 20 pixels for a 2 megapixel camera, or may be expressed as a number of cycles for a fixed camera resolution.

[0039] Monitor device 208 is configured to project the screen pattern onto a surface of wafer 202. Monitor 208 may be a liquid crystal display (LCD) monitor or other similar monitor, and / or a projection source. Monitor device 208 may be communicatively coupled to computing device 204 via a wired or wireless communication coupling.

[0040] Camera 210 is configured to capture images, such as camera image 212, of a surface of wafer 202 as the screen pattern is projected on the surface of wafer 202. Note that although only one camera is illustrated in FIG. 2A, in some embodiments, two cameras may be utilized to form a stereoscopic image, as discussed below in more detail. As illustrated, camera image 212 includes distortions relative to the screen pattern that was projected. These distortions may be due to curvature of the surface of wafer 202 that cause changes in the reflection angle. Camera image 212, and in particular the distortions relative to the projected fringe pattern, may be analyzed to characterize the surface of wafer 202, as described below in connection with FIG. 3. The images captured by camera 210 may be considered images representative of reflections of the one or more fringe patterns from the surface of the wafer.

[0041] Deflectometry operates on the principle of reflection, which may be utilized to characterize the surface of a wafer. FIG. 2B illustrates the principle of reflection associated with deflectometry. As illustrated, an angle change of a of the wafer surface with respect to a flat surface causes a doubling in the reflected angle of 2a. As illustrated, a ray from the camera is reflected onto the surface of the wafer at a point having a tilt angle of a. Accordingly, the reflected ray has a reflection angle of 2a.

[0042] The reflection angles and associated phases may be utilized to characterize the slope of the wafer surface at a given point. By characterizing slopes at a set of surface points, a three- dimensional reconstruction of the wafer is generated, which allows for characterization of wafer bow across the surface of the wafer.

[0043] In some embodiments, phase measuring deflectometry (PMD) may be utilized to characterize wafer bow. One or more fringe patterns may be projected onto the surface of a wafer. In some embodiments, the one or more fringe patterns may include multiple fringe frequencies and multiple phase shifts for each frequency. Alternatively, in some embodiments, a single fringe frequency may be used (which is generally referred to herein as “single shot deflectometry”). The resulting reflected images, captured by one or more cameras, may beAttorney Docket No. LAM1P054WO-10182-1WO used to generate an unwrapped phase map of the reflected image. Based on the unwrapped phase map, slopes at different points on the surface of the wafer may be determined. Based on the slope estimates, a three-dimensional reconstruction of the wafer surface may be generated. For example, a three-dimensional point cloud representing the wafer surface may be constructed based on the slope estimates.

[0044] FIG. 3 is a flowchart of an example process 300 for characterizing wafer bow using deflectometry in accordance with some embodiments. Blocks of process 300 may be executed by one or more processors of one or more computing devices (e.g., computing device 204 shown in FIG. 2A). An example implementation of a computing device is shown in and described below in connection with FIG. 11. In some embodiments, blocks of process 300 may be executed in an order other than what is shown in FIG. 3. In some embodiments, two or more blocks of process 300 may be executed substantially in parallel. In some implementations, one or more blocks of process 300 may be omitted.

[0045] Process 300 may begin by generating and projecting one or more fringe patterns on a wafer and capturing the resulting image(s) using one or more cameras. In some embodiments, the one or more fringe patterns may include multiple fringe patterns having different frequencies and / or phase shifts. The fringes may be in the horizontal direction and / or the vertical direction. Generally the images are captured both in the horizontal and vertical directions with phases shifted in both horizontal and vertical directions. In some embodiments, multiple frequencies (e.g., three, five, ten, etc.) of fringe may be used. In some embodiments, each fringe frequency may be repeated with a phase shift. The fringe frequencies and the number of fringe frequencies used may be dependent on the resolution to be achieved. For example, higher accuracy may be achieved (e.g., higher spatial resolution) when using relatively higher fringe frequencies. In one example, three different frequencies may be used, with four phase shifts per frequency, in both the horizontal and vertical directions, for a total of 24 images. In another example, five fringe frequencies may be used, and each fringe frequency may be repeated for four phase shifts (e.g., with each shifted 90 degrees with respect to the previous fringe image in the set). The fringe frequencies may be in a range from, e.g., 6 to 200. In general, in some embodiments, the one or more fringe patterns may comprise a plurality of fringe frequencies and a plurality of phase shifts for each fringe frequency. Alternatively, in an instance in which single shot deflectometry is performed, a single fringe frequency may be used. In instances in which a single fringe frequency is used, the fringe frequency may be relatively high, e.g., greater than about 200.Attorney Docket No. LAM1P054WO-10182-1WO

[0046] The resulting images may be captured by one or more cameras, e.g., camera 210 as shown in and described above in connection with FIG. 2A. In some embodiments, two cameras may be used to provide stereoscopic imaging. Stereoscopic imaging may allow for disambiguation of points on the wafer surface, as described below in connection with FIG. 4A. The one or more cameras may have any suitable resolution, e.g., 1 Megapixel, 5 Megapixels, 10 Megapixels, 20 Megapixels, etc.

[0047] At 304, process 300 can generate an unwrapped phase map based on the images captured by the one or more cameras. An unwrapped phase map, as used herein, generally refers to a phase map in which the carrier phase components have been removed from a wrapped phase distribution. In some embodiments, the unwrapped phase distribution may be determined based on multiple images captured from multiple projected fringe patterns (e.g., using temporal or spatial unwrapping algorithms), as described below in connection with FIG. 4A. Alternatively, in some embodiments, the unwrapped phase distribution may be determined using machine learning using a single image, as described below in connection with FIG. 4B.

[0048] At 306, process 300 can estimate slopes in the x and y directions for the wafer based on the unwrapped phase map. In some embodiments, normal vectors may be estimated for a set of surface points, where the surface points may correspond to a set of points on the surface of the wafer. In some embodiments, the estimated slopes in the x and y directions may be determined for the set of surface points based on the estimated normal vectors, for example, based on a ratio of magnitude of normal vectors in the x and y directions for a given point. Example techniques for estimating the slopes in the x and y directions are shown in and described below in connection with FIG. 5.

[0049] Note that, in some embodiments, the system may be calibrated. Calibration may involve determining calibration parameters. The calibration parameters may be related to determining intrinsic camera parameters, calibrating two cameras with respect to one another, calibrating each camera with respect to the projector that projects the fringe pattem(s), and / or calibrating each camera with respect to the wafer. More detailed techniques for performing system calibration are described below in connection with block 504 of FIG. 5.

[0050] Additionally, it should be noted that the system shown in FIG. 2A may cause slope-height ambiguity, where there are multiple candidate points that may have a given slope, where only one of the candidate points are on the surface of the wafer. Slope-height ambiguity may be addressed in numerous ways. For example, in some implementations, as described above, two cameras may be used to obtain a stereoscopic camera image, and the stereoscopic cameraAttorney Docket No. LAM1P054WO-10182-1WO image may be used to disambiguate points in order to locate a point that is on the wafer surface. In other implementations, a single camera may be used with two projector screens (e.g., translated in position with respect to one another), or a distance sensor may be used to select a point that is on the wafer surface. In some embodiments, multiple cameras and multiple projectors may be used.

[0051] At 308, process 300 can generate a three-dimensional surface reconstruction based on the estimated slopes. For example, in some implementations, the three-dimensional surface reconstruction may include a three-dimensional point cloud that represents the surface of the wafer. In some implementations, the three-dimensional reconstruction of the surface of the wafer may involve iterative reconstruction. Using iterative reconstruction, not all surface points need be reconstructed. Rather, an effective interpolation of the wafer surface may be generated, which reduces computational complexity.

[0052] At 310, process 300 can determine wafer bow characteristics associated with the wafer based on the three-dimensional surface reconstruction. The wafer bow characteristics may include various points on the surface of the wafer, a magnitude and / or a direction of bow for the points. In some embodiments, the wafer bow characteristics may additionally or alternatively include a radius of curvature, one or more stress metrics, an in-plane displacement which may be used for lithography mask corrections (e.g., to resolve silicon overlay errors), and / or any other suitable bow dependent properties. In some embodiments, the wafer bow characteristics may be used to estimate film stresses

[0053] Note that the techniques shown in and described above in connection with process 300 may be performed on a cold wafer. Additionally or alternatively, the techniques to determine wafer bow characteristics may be perfonned on a wafer in situ as it is being heated and / or as the wafer is at a final heated temperature. As used herein, a heated wafer may have a temperature of above 50 degrees Celsius, above 100 degrees Celsius, above 200 degrees Celsius, above 300 degrees Celsius, above 400 degrees Celsius, or the like. In instances in which the wafer bow characteristics are performed in situ, the wafer bow characteristics may be used to perform in situ process control. For example, the wafer bow characteristics may be used to determine parameters associated with one or more backside deposition processes configured to counteract wafer bow. Backside deposition parameters may include a thickness of film to be deposited on the backside to counteract wafer bow, composition of film to be deposited, a number of cycles of a deposition process to be performed to deposit the backside film to counteract wafer bow, etc. As a more particular example, the backside depositionAttorney Docket No. LAM1P054WO-10182-1WO process parameters may be determined based on a magnitude and / or direction of bow, and / or may be determined based on bowing in particular regions of the wafer. As another example, the wafer bow characteristics may be used to modify clamping of the wafer to a chuck. As a more particular example, differential pressure parameters used to perform vacuum clamping may be determined and / or modified based on the wafer bow characteristics. As another more particular example, electrostatic force parameters used to perform electrostatic clamping may be determined and / or modified based on the wafer bow characteristics. As yet another example, wafer bow characteristics may be used to estimate in plane displacement for calculating silicon overlay errors. Note that the techniques described herein may be particularly useful for estimating bow of a heated wafer (e.g., in “hot bow” conditions), particularly because hot bow values may be different from cod wafer bow measurements.

[0054] As described above, in connection with block 304 of process 300 shown in and described above in connection with FIG. 3, an unwrapped phase map may be generated based on images captured by one or more cameras. In general, a “wrapped phase” refers to phase values that are constrained to a particular phase range (e.g., between -pi and pi, between -180 degrees and 180 degrees, etc.). An “unwrapped phase” refers to phase values that are unconstrained and therefore include an original phase of a signal. As used herein, an “unwrapped phase map” refers to matrix or other data structure that includes unwrapped phase values for pixels associated with the captured camera image(s). In instances in which multiple fringe patterns are projected onto the wafer surface (e.g., to determine cold wafer bow), phase unwrapping may be performed using temporal phase unwrapping. Techniques for performing phase unwrapping in which multiple fringe patterns are projected are shown in and described below in connection with FIG. 4A. In instances in which a single fringe pattern is projected (e.g., a relatively high frequency fringe pattern, and which is generally referred to herein as “single shot” deflectometry), phase unwrapping may be performed using a trained machine learning model, as shown in and described below in connection with FIG. 4B.

[0055] FIG. 4A is a flowchart of an example process 400 for determining unwrapped phase information from multiple camera images associated with multiple fringe patterns projected on a wafer surface. Blocks of process 400 may be executed by one or more processors of one or more computing devices (e.g., computing device 204 shown in FIG. 2 A). An example implementation of a computing device is shown in and described below in connection with FIG. 11. In some embodiments, blocks of process 400 may be executed in an order other than what is shown in FIG. 4A. In some embodiments, two or more blocks of process 400 may be executed substantially in parallel. In some implementations, one or more blocks of processAttorney Docket No. LAM1P054WO-10182-1WO400 may be omitted.

[0056] Process 400 can begin at 402 by obtaining a set of camera images corresponding to different fringe frequencies and different fringe phase shifts projected onto a wafer under test. For a given projected fringe pattern n, the distorted image due to the reflections on the surface of the wafer that is captured by the camera may be represented as 7,,. In general, / „ may be represented by:

[0057] In the equation given above, A(x,y) represents the average intensity due to pattern brightness, and B(x,y) represents the intensity modulation due to fringe pattern contrast and the reflectivity of the wafer surface. The index n represents the index of the phase shift of the projected fringe pattern, e.g., where n is 1, 2, 3, 4, etc. The wrapped phase is represented by (x, y). Because there are three unknowns (e.g., A, B, and ), at least three fringe patterns having different frequencies and phase shifts and three corresponding images I(x,y) may be obtained in order to solve for the three unknowns. Note that, in some implementations, more than three fringe patterns may be utilized in order to increase accuracy.

[0058] At 404, process 400 can determine a wrapped phase distribution from the set of camera images. Determination of the wrapped phase distribution may involve solving for <|>(x, y), e.g., to determine a wrapped phase value at each pixel (x, y). Note that solving for <|>(x, y) may involve using at least three camera images due to the three unknown variables. In some embodiments, the wrapped phase distribution may be determined by:

[0059] Note that, as shown in the equation given above, because the arctangent function has a range between -n to n, the wrapped phase distribution may also constrained to the range of -it to 71.

[0060] At 406, process 400 may determine an unwrapped phase map. For example, in some implementations, process 400 may remove carrier phase components from the wrapped phase distribution obtained at block 400. By determining the unwrapped phase map, the phase values may no longer be constrained, e.g., from -71 to JI.Attorney Docket No. LAM1P054WO-10182-1WO

[0061] In general, the unwrapped phase map may be represented as <D(x, y). The unwrapped phase map may be determined by: (x, y) = < >(%, y) + 2nk(x, y)

[0062] In the equation given above, note that 4>(x, y) represents the wrapped phase distribution. In the equation given above, k(x,y) represents a fringe order for the pixel (x, y). Various techniques may be used to determine the fringe order k(x,y) for each pixel. For example, in some embodiments, multi-frequency temporal phase unwrapping may be used. As a more particular example, in some implementations, an initial phase unwrapping may be performed using images associated with a lowest frequency fringe pattern projected on the wafer surface, which may provide initial phase unwrapping information that may be used to bootstrap phase unwrapping for subsequent, higher frequency fringe images.

[0063] The unwrapped phase map generated as a result of process 400 may then be used to, e.g., estimate slopes in the x and y directions for the wafer surface (e.g., as described above in connection with FIG. 3).

[0064] FIG. 4B is a flowchart of an example process 450 for determining unwrapped phase information from a single camera image associated with a single fringe pattern projected onto a wafer surface. Note that, in some implementations, a single fringe pattern projection and associated single camera image (generally referred to herein as “single shot deflectometry”) may be used to characterize wafer bow. Note that while single shot deflectometry is often described herein as particularly useful for characterizing wafer bow while the wafer is heating and / or has reached a final heated temperature (e.g., “hot bow” conditions), single shot deflectometry may be used to characterize cold wafer bow in order to substantially reduce processing time. This is generally referred to as determining or characterizing “hot wafer bow.” Blocks of process 450 may be executed by one or more processors of one or more computing devices (e.g., computing device 204 shown in FIG. 2A). An example implementation of a computing device is shown in and described below in connection with FIG. 11. In some embodiments, blocks of process 450 may be executed in an order other than what is shown in FIG. 4B. In some embodiments, two or more blocks of process 450 may be executed substantially in parallel. In some implementations, one or more blocks of process 450 may be omitted.

[0065] Process 450 can begin at 452 by obtaining a camera image corresponding to a fringe image projected onto a wafer under test. Note that the fringe image may be associated with aAttorney Docket No. LAM1P054WO-10182-1WO relatively high fringe frequency, e.g., with fringes at greater than about 200 cycles.

[0066] At 454, process 450 can provide the camera image as input to a trained machine learning model. Note that, in some embodiments, rather than providing the camera image itself, process 450 can perform Fourier-based phase unwrapping using the camera image, and may provide information associated with the Fourier transform to the machine learning model.

[0067] It should be understood that the machine learning model may have been trained using phase maps previously obtained for training purposes. For example, in some implementations, the phase maps may be associated with room temperature data, whereas process 450 may occur under heated conditions.

[0068] At 456, process 450 can obtain, an output, unwrapped phase information associated with the camera image from the trained machine learning model. In other words, the trained machine learning model may predict, as an output, the unwrapped phase information. Note that, when multiple camera images are used, as described above in connection with FIG. 4A, temporal unwrapping may be used to obtain the unwrapped phase information. However, when a single image is used, the trained machine learning model may be used to predict the unwrapped phase information.

[0069] In some implementations, a three-dimensional reconstruction of the surface of the wafer may be determined based at least in part on the unwrapped phase map (e.g., as generated using any of the techniques shown in and described above in connection with FIGS. 4A and / or 4B). For example, in some embodiments, the three-dimensional reconstruction may be generated by estimating slopes in the x and y directions for surface points of the wafer based on the unwrapped phase map. In some embodiments, slopes may be estimated based on a surface normal vector N. In some embodiments, reconstructed three-dimensional points of the wafer surface may be determined based on estimated slopes and / or estimated surface normal.

[0070] In some embodiments, three-dimensional surface reconstruction may be performed in an iterative manner. For example, in some implementations, a seed point may be used (which may be arbitrary selected), which resides on the surface of the wafer. An initial surface may be determined which may correspond to a plane at the height of the seed point. The surface may be reconstructed using slopes from the seed point, e.g., by integrating the surface using the estimated slopes from the seed point. This reconstructed surface may form the surface for a next iteration, during which slopes may be computed again. This iterative process may repeat until heights converge (e.g., a difference between two iterations is less than a predeterminedAttorney Docket No. LAM1P054WO-10182-1WO threshold).

[0071] FIG. 5 is a flowchart of an example process 500 for reconstructing a wafer surface in accordance with some embodiments. Blocks of process 500 may be executed by one or more processors of one or more computing devices (e.g., computing device 204 shown in FIG. 2A). An example implementation of a computing device is shown in and described below in connection with FIG. 11. In some embodiments, blocks of process 500 may be executed in an order other than what is shown in FIG. 5. In some embodiments, two or more blocks of process 500 may be executed substantially in parallel. In some implementations, one or more blocks of process 500 may be omitted.

[0072] At 501, process 500 can perform system calibration. System calibration may involve any combination of: intrinsic camera calibration (e.g., to determine internal parameters associated with the camera, which may allow three-dimensional points to be projected on a two- dimensional image plane, or vice versa), extrinsic camera calibration, stereo camera calibration (e.g., calibration of two cameras of the system with respect to each other), camera to wafer calibration (sometimes referred to as camera to surface under test (SUT) calibration), and / or camera to screen calibration (e.g., to calibrate each camera to a projection screen used to project fringe patterns onto the wafer surface). Note that system calibration may be performed before capturing any images in order to characterize the geometry (e.g., distances between the camera, screen, and wafer) prior to any three-dimensional reconstruction.

[0073] At 502, process 500 can obtain an unwrapped phase map for a wafer under test. In instances in which multiple fringe patterns of different frequencies / phases were projected on the wafer and a corresponding set of multiple images were obtained from a camera indicative of reflections of the fringe patterns, the unwrapped phase may be generated using temporal unwrapping, as described above in connection with FIG. 4A. Alternatively, in some embodiments, the unwrapped phase map may be determined using a trained machine learning model, e.g., as described above in connection with FIG. 4B.

[0074] In some implementations, determining intrinsic and / or extrinsic camera parameters may involve determining a focal length (generally represented herein as / ) of each camera, a center of the camera sensor plane, and / or camera lens distortion parameters. Camera lens distortion parameters may include distortion coefficients related to different types of distortion (e.g., barrel distortion, or the like).

[0075] In some implementations, performing stereo camera calibration may involve projectingAttorney Docket No. LAM1P054WO-10182-1WO a chessboard pattern of known dimensions onto a wafer surface. Multiple views of the chessboard pattern may be obtained from both cameras, e.g., at the same time, or simultaneously. Each individual camera may be separately calibrated. Then, stereo calibration may be performed with respect to the two cameras, e.g., to determine parameters representing rotational and / or translational matrices of one camera with respect to the other.

[0076] In some implementations, performing camera to wafer calibration may involve projecting a chessboard pattern onto the wafer surface. Camera calibration rotational and translational matrices may be determined based on the flat mirror. A printed chessboard pattern may then be placed on a flat wafer. The orientation and translation of the wafer may be determined using the printed chessboard pattern. Once the orientation and translation of the wafer is known, the normal vector from the wafer surface may be determined.

[0077] In some implementations, camera to screen calibration may be performed. For example, the distance from the camera to the wafer may be determined, and rotational and translational matrices associated with each camera to the projection screen may be determined based on the known distance.

[0078] At 506, process 500 estimate normal vectors for a set of surface points. The normal vector for a given point on the surface of the wafer may be presented as N, which may have components in the x, y, and z directions of Az, Ny, and Az, respectively. The normal vector N may generally be considered the difference between a reflected ray and an incident ray (e.g., an incident ray from a fringe pattern projected onto the wafer surface). For example, the normal for a given point on the surface may be represented by:

[0079] It should be understood that, in some implementations, process 500 may estimate normal vectors for multiple surface points. The normal vector may be determined by triangulation, e.g., to solve the slope-height ambiguity. For example, use of stereo cameras may be used for triangulation to determine the normal vectors.

[0080] At 508, process 500 can estimate slopes in the x and y directions for the set of surface points based on the estimated normal vectors. For example, the slope in the x direction for a given surface point having a normal vector A may be determined by:Attorney Docket No. LAM1P054WO-10182-1WONxSr = -Nz

[0081] The slope in the y direction for the given surface point may be determined by:Ny y Nz

[0082] In some implementations, a three-dimensional reconstruction of the wafer surface may be determined by determining a correct three-dimensional point on the wafer surface based on a comparison of surface normal associated with points projected to two cameras. The three- dimensional point may be one where two surface normal associated with each camera are substantially the same (e.g., that the angle between the two surface normal are less than a predetermined threshold).

[0083] FIG. 6 illustrates an example technique for determining a three-dimensional point on a wafer surface in accordance with some embodiments. As illustrated, a pixel p associated with the image captured by a first camera may be considered. A vector, represented as vl may be projected from the pixel p. Several points may lie along the vector vl, such as points P, Pl, and P2 as shown in FIG. 6. A correspondence between the camera point and the point on the screen may be determined using the unwrapped phase map. Triangulation may be performed between the screen, the first camera, and the assumed point (e.g., for each of P, Pl, and P2) on the wafer surface. The normal may be computed from the assumed point. The normal associated with the first camera is represented as nl in FIG. 6. Each point (e.g., each of P, Pl, and P2) may be projected to the second camera, and a similar triangulation and computation of the normal (represented as n2) may be performed. The point (e.g., of P, Pl, and P2) for which the normal associated with the first camera (nl) is substantially the same as the normal associated with the second camera (n2) is considered the point that lies on the surface of the wafer. For example, in FIG. 6, the point P is considered to be on the surface of the wafer because nl = n.2. In some embodiments, the point may be considered to be on the surface of the wafer if the angle between nl and n2 is less than a predetermined angle (e.g., less than 5 degrees, less than 1 degree, less than 0.5 degrees, less than 0.01 degrees, etc.).

[0084] In some embodiments, surface reconstruction may be iterative. When performing iterative reconstruction, an initial surface may be estimated. The initial surface may be estimated using normal vectors, as described above, and then the surface may be fully reconstructed based on the initial surface. The initial surface may be estimated based on a seedAttorney Docket No. LAM1P054WO-10182-1WO point that corresponds to a center of the wafer surface. The seed point may lie anywhere along a line joining a camera to the seed point, and the line may be estimated based on the camera calibration (e.g., described above in connection with block 501 of FIG. 5). Because the seed point may lie anywhere along the line, the distance of the seed point from the camera is unknown. The correct distance of the seed point may be determined based on the distance at which the normal vectors to two cameras match, e.g., as shown in and described above in connection with FIG. 6. In other words, the line may be searched to identify the point the correct distance from the camera as the one where the normal vectors match (i.e., the angle between two normal vectors is zero, or less than a predetermined angle, as described in connection with FIG. 6). Once the distance of the seed point has been computed, an initial plane may be constructed based on the seed point (e.g., a plane at the determined distance), which may be treated as the initial surface. The initial estimated surface may then be refined based on iterative reconstruction. The initial surface is assumed to be a flat plane. The slope at every pixel may be computed by triangulating between the camera, monitor, and the surface. Based on the computed slopes, the initially assumed flat surface will become curved to reflect the actual surface of the wafer (e.g., with a surface that is bowed according to the wafer bow). The iteration on the wafer surface may be repeated until the shape does not change by more than a threshold amount between two consecutive iterations.

[0085] In some embodiments, the reconstruction of the wafer surface may be represented as a three-dimensional point cloud. For example, the points in the point cloud may be those that are sampled on the wafer surface without characterizing every point on the wafer surface. In some embodiments, wafer bow characteristics may be determined based on the three- dimensional reconstruction. For example, the wafer bow characteristics may include a magnitude of wafer bow, a direction and / or magnitude of wafer bow at different locations on the surface of the wafer, a radius of curvature, stresses (e.g., film stress), in-plane displacements for lithography mask corrections (e.g., for silicon overlay error correction of lithographic masks), or the like.

[0086] FIG. 7 illustrates wafer bow characteristics determined using the techniques described herein in accordance with some embodiments. Three-dimensional graph 702 represents a three-dimensional reconstruction of the wafer surface. As illustrated, the height of the wafer surface is plotted for each location in the x and y directions. In aggregate, graph 702 illustrates the determined bow of the wafer.

[0087] Two-dimensional color plot 704 illustrates the data shown in three-dimensional graphAttorney Docket No. LAM1P054WO-10182-1WO 702 in a two-dimensional format. As illustrated, grayscale values represent height at different x and y pixel coordinate locations. Wafer bow is depicted as shown by the variation in color across the x and y directions.

[0088] Graph 706 depicts variation in wafer height or depth for a fixed x-coordinate position. Note that as the y-coordinate changes, the depth / height changes, illustrating wafer bow along a slice of graph 702. Similarly, graph 708 illustrates variation in wafer height or depth for a fixed y-coordinate position.

[0089] Wafer bow characteristics may be determined by analyzing any of graphs 702, e.g., to determine an average bow at a particular region of the wafer, a maximum bow, a direction of bow, etc.

[0090] The techniques described herein may be used to determine wafer bow characteristics of a cold wafer and / or of a wafer as it is heated within a process station or chamber or upon reaching a heated state or temperature. Accordingly, system components used to determine the wafer bow characteristics, such as one or more cameras and / or one or more projectors to project fringe patterns onto the wafer surface, may be disposed in or on components of a process station or process chamber in order to perform the phase-measuring deflectometry techniques described herein to determine wafer bow characteristics.

[0091] For example, in some embodiments, one or more cameras and / or one or more projection devices may be disposed in on a front end module. Accordingly, wafer bow may be measured when a wafer is transferred from a front opening unified pod (FOUP) to a load lock or vice versa within the front end module. In some embodiments, the front end module may include a projection device (e.g., an LCD monitor), or may project a static fringe image onto the wafer, and reflections may be captured by one or more cameras disposed in or on a portion of the front end module. It should be noted that, in some cases, rather than projecting a fringe pattern on the wafer surface, a reflection of holes of the showerhead may be captured, and the techniques described herein may be applied using the captured images of the reflection of showerhead holes. Accordingly, the techniques described herein may be performed without a projection device or monitor to project fringe patterns, and may utilize the intrinsic pattern of the showerhead holes as a pattern that may be leveraged to generate an unwrapped phase map.

[0092] As another example, one or more cameras and / or one or more projection devices may be part of an integrated metrology module, which may be disposed in a wafer handler or within the process station.Attorney Docket No. LAM1P054WO-10182-1WO

[0093] As yet another example, in some embodiments, a projection device may be disposed in or otherwise attached to a viewport of a process station. The projection device may accordingly at least partially project fringe patterns onto the wafer surface. One or more cameras may be disposed in one or more other viewports of the process station to capture reflections of the fringe patterns off the wafer surface. In one example, a projection device is disposed in a first viewport of a process station, and a camera is disposed in a second viewport of the process station. Note that, in some embodiments, multiple cameras may be used, where each camera captures images from a different angle. In one example, a projection device may be disposed in a first viewport of a process station, a first camera may be disposed in a second viewport, and a second camera may be disposed in a third viewport. The entire wafer surface may be recreated by stitching together the camera images from different angles.

[0094] As shown in and described above in connection with FIG. 2A, a computing device may control a projection device, and may receive the captured camera image(s). The computing device may be local to the process station. As described above, various computational techniques may be applied to the captured camera images, e.g., to determine an unwrapped phase map, determine points on the wafer surface, reconstruct the wafer surface, and / or characterize wafer bow based on the reconstructed surface. These techniques may be performed on a computing device that controls the projection device and / or receives the camera images from the one or more cameras. Alternatively, in some embodiments, a local computing device may transmit the camera images to a remote device (e.g., a server device) configured to perform various computational techniques to determine wafer bow characteristics.

[0095] FIGS. 8A, 8B, 9, and 10 illustrate example implementation of components for performing phase-measuring deflectometry in conjunction with a semiconductor process chamber or process station in accordance with some embodiments.

[0096] In some implementations, a system for performing phase-measuring deflectometry in conjunction with a semiconductor process chamber or process station may be a standalone tool. Such a standalone tool may receive a wafer, perform wafer bow characterization, and subsequently place the wafer back in a FOUP. Accordingly, such a system may function as a standalone metrology tool.

[0097] In some embodiments, a system for perfonning phase-measuring deflectometry may be implemented as part of an equipment front end module (EFEM). Wafer bow may be measured and / or characterized by obtaining measurements using an integrated metrology module (e.g., integrated within the EFEM). Additionally or alternatively, in some implementations,Attorney Docket No. LAM1P054WO-10182-1WO measurements may be made while the wafer is in transit (e.g., within a side station attached to the EFEM). For example, measurements may be made, and a three-dimensional reconstruction may be generated during a time period when the wafer is being moved on an end effector.

[0098] FIG. 8A shows an example implementation in which a display projector 802 and a camera system 804 are disposed within an EFEM 800. The wafer 810 may reside on and / or be supported by a mount 808 within the EFEM. Display projector 802 may be configured and / or controlled to project one or more fringe patterns on wafer 810 while in the EFEM, and camera system 804 may be configured and / or controlled to capture the reflected images.

[0099] In the example implementation shown in FIG. 8B, the phase-measuring deflectometry system is disposed in a side station 852 attached to EFEM 800. In particular, as illustrated in FIG. 8B, display projector 802 and camera system 804 are within side station 852. Mount 808 is configured to support wafer 810 within side station 852.

[0100] In some implementations, a system for phase-measuring deflectometry may be implemented within a vacuum transfer module (VTM). For example, wafer bow may be measured and / or characterized within the VTM as the wafer is moved. FIG. 9 illustrated an example in which wafer bow measurements may be made within a vacuum chamber 900. As illustrated, wafer 810 may reside on a robot arm 902 within the vacuum chamber 900. Display 802 may be configured to project one or more fringe patterns on the wafer through a transparent window 904 into vacuum chamber 900. Camera system 804 may be configured to capture the reflected images via transparent window 904.

[0101] As described above, in some embodiments, wafer bow may be characterized in situ, e.g., within a process station as a wafer is being heated and / or undergoing a fabrication process. Wafer bow measured while the wafer is in the process station may be considered a “hot bow” measurement. FIG. 10 illustrates an example implementation of a phase-measuring deflectometry system to measure wafer bow while a wafer is in a process station 1000 in accordance with some embodiments. As illustrated, wafer 810 may reside on a pedestal 1002 within process station 1000. Display 802 may be configured to project one or more fringe patterns on wafer 810 through a transparent window 1004. Camera system 804 may be configured to capture reflected images through transparent window 1004.

[0102] Note that a computing device to control a projection device and / or receive images from a camera system is not depicted in FIGS. 8A, 8B, 9, and 10 for simplicity. Such a computing device may be a local computing device (e.g., local to the fabrication chamber). In someAttorney Docket No. LAM1P054WO-10182-1WO embodiments, a local computing device may control the projection device and / or receive images from the camera system, and may transmit received images to a remote server device or cloud device for processing. Alternatively, in some embodiments, the local computing device may perform some or all of the processing to determine wafer bow.CONTEXT FOR DISCLOSED COMPUTATIONAL EMBODIMENTS

[0103] Systems including fabrication tools as described herein may include logic for determining wafer bow characteristics.

[0104] The analysis logic may be designed and implemented in any of various ways. For example, the logic can be implemented in hardware and / or software. Examples are presented in the controller section herein. Hardware-implemented control logic may be provided in any of a variety of forms, including hard coded logic in digital signal processors, applicationspecific integrated circuits, and other devices that have algorithms implemented as hardware. Analysis logic may also be implemented as software or firmware instructions configured to be executed on a general-purpose processor. System control software may be provided by “programming” in a computer readable programming language.

[0105] The computer program code for controlling processes in a process sequence can be written in any conventional computer readable programming language: for example, assembly language, C, C++, Pascal, Fortran, Python, or others. Compiled object code or script is executed by the processor to perform the tasks identified in the program. Also as indicated, the program code may be hard coded.

[0106] Integrated circuits used in logic may include chips in the form of firmware that store program instructions, digital signal processors (DSPs), chips defined as application specific integrated circuits (ASICs), and / or one or more microprocessors, or microcontrollers that execute program instructions (e.g., software). Program instructions may be instructions communicated in the form of various individual settings (or program files), defining operational parameters for carrying out a particular analysis or image analysis application.

[0107] Figure 11 is a block diagram of an example of the computing device 1100 suitable for use in implementing some embodiments of the present disclosure. For example, device 1100 may be suitable for implementing some or all functions for determining wafer bow characteristics, projecting fringe patterns, obtaining and / or analyzing captured reflection images, or the like.

[0108] Computing device 1100 may include a bus 1102 that directly or indirectly couples the following devices: memory 1104, one or more central processing units (CPUs) 1106, one orAttorney Docket No. LAM1P054WO-10182-1WO more graphics processing units (GPUs) 1108, a communication interface 1110, input / output (I / O) ports 1 112, input / output components 1114, a power supply 1116, and one or more presentation components 1118 (e.g., display(s)). In addition to CPU 1106 and GPU 1108, computing device 1100 may include additional logic devices that are not shown in Figure 11, such as but not limited to an image signal processor (ISP), a digital signal processor (DSP), an ASIC, an FPGA, or the like.

[0109] Although the various blocks of Figure 11 are shown as connected via the bus 1102 with lines, this is not intended to be limiting and is for clarity only. For example, in some embodiments, a presentation component 1118, such as a display device, may be considered an I / O component 1114 (e.g., if the display is a touch screen). As another example, CPUs 1106 and / or GPUs 1108 may include memory (e.g., the memory 1104 may be representative of a storage device in addition to the memory of the GPUs 1 108, the CPUs 1106, and / or other components). In other words, the computing device of Figure 11 is merely illustrative. Distinction is not made between such categories as “workstation,” “server,” “laptop,” “desktop,” “tablet,” “client device,” “mobile device,” “hand-held device,” “electronic control unit (ECU),” “virtual reality system,” and / or other device or system types, as all are contemplated within the scope of the computing device of Figure 11.

[0110] Bus 1102 may represent one or more busses, such as an address bus, a data bus, a control bus, or a combination thereof. The bus 1102 may include one or more bus types, such as an industry standard architecture (ISA) bus, an extended industry standard architecture (EISA) bus, a video electronics standards association (VESA) bus, a peripheral component interconnect (PCI) bus, a peripheral component interconnect express (PCIe) bus, and / or another type of bus.

[0111] Memory 1104 may include any of a variety of computer-readable media. The computer- readable media may be any available media that can be accessed by the computing device 1100. The computer-readable media may include both volatile and nonvolatile media, and removable and non-removable media. By way of example, and not limitation, the computer- readable media may comprise computer-storage media and / or communication media.

[0112] The computer-storage media may include both volatile and nonvolatile media and / or removable and non-removable media implemented in any method or technology for storage of information such as computer-readable instructions, data structures, program modules, and / or other data types. For example, memory 1104 may store computer-readable instructions (e.g., that represent a program(s) and / or a program element(s), such as an operating system. Computer-storage media may include, but is not limited to, RAM, ROM, EEPROM, flashAttorney Docket No. LAM1P054WO-10182-1WO memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can be accessed by computing device 1100. As used herein, computer storage media does not comprise signals per se.

[0113] The communication media may embody computer-readable instructions, data structures, program modules, and / or other data types in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media. The term “modulated data signal” may refer to a signal that has one or more of its characteristics set or changed in such a manner as to encode information in the signal. By way of example, and not limitation, the communication media may include wired media such as a wired network or direct-wired connection, and wireless media such as acoustic, RF, infrared and other wireless media. Combinations of any of the above should also be included within the scope of computer- readable media.

[0114] CPU(s) 1106 may be configured to execute the computer-readable instructions to control one or more components of the computing device 1100 to perform one or more of the methods and / or processes described herein. CPU(s) 1106 may each include one or more cores (e.g., one, two, four, eight, twenty-eight, seventy-two, etc.) that are capable of handling a multitude of software threads simultaneously. CPU(s) 1106 may include any type of processor and may include different types of processors depending on the type of computing device 1100 implemented (e.g., processors with fewer cores for mobile devices and processors with more cores for servers). For example, depending on the type of computing device 1100, the processor may be an ARM processor implemented using Reduced Instruction Set Computing (RISC) or an x86 processor implemented using Complex Instruction Set Computing (CISC). Computing device 1100 may include one or more CPUs 1106 in addition to one or more microprocessors or supplementary co-processors, such as math co-processors.

[0115] GPU(s) 1108 may be used by computing device 1100 to render graphics (e.g., 3D graphics). GPU(s) 1108 may include many (e.g., tens, hundreds, or thousands) of cores that are capable of handling many software threads simultaneously. GPU(s) 1108 may generate pixel data for output images in response to rendering commands (e.g., rendering commands from CPU(s) 1106 received via a host interface). GPU(s) 1108 may include graphics memory, such as display memory, for storing pixel data. The display memory may be included as part of memory 1104. GPU(s) 1108 may include two or more GPUs operating in parallel (e.g., via a link). When combined, each GPU 1108 can generate pixel data for different portions of anAttorney Docket No. LAM1P054WO-10182-1WO output image or for different output images (e.g., a first GPU for a first image and a second GPU for a second image). Each GPU can include its own memory or can share memory with other GPUs.

[0116] In examples where the computing device 1100 does not include the GPU(s) 1108, the CPU(s) 1106 may be used to render graphics.

[0117] Communication interface 1110 may include one or more receivers, transmitters, and / or transceivers that enable computing device 1100 to communicate with other computing devices via an electronic communication network, included wired and / or wireless communications. Communication interface 1110 may include components and functionality to enable communication over any of a number of different networks, such as wireless networks (e.g., Wi-Fi, Z-Wave, Bluetooth, Bluetooth LE, ZigBee, etc.), wired networks (e.g., communicating over Ethernet), low-power wide-area networks (e.g., LoRaWAN, SigFox, etc.), and / or the internet.

[0118] I / O ports 1112 may enable the computing device 1100 to be logically coupled to other devices including I / O components 11 14, presentation component(s) 1118, and / or other components, some of which may be built in to (e.g., integrated in) computing device 1100. Illustrative I / O components 1114 include a microphone, mouse, keyboard, joystick, track pad, satellite dish, scanner, printer, wireless device, etc. I / O components 1114 may provide a natural user interface (NUI) that processes air gestures, voice, or other physiological inputs generated by a user. In some instances, inputs may be transmitted to an appropriate network element for further processing. An NUI may implement any combination of speech recognition, stylus recognition, facial recognition, biometric recognition, gesture recognition both on screen and adjacent to the screen, air gestures, head and eye tracking, and touch recognition (as described in more detail below) associated with a display of computing device 1100. Computing device 1100 may be include depth cameras, such as stereoscopic camera systems, infrared camera systems, RGB camera systems, touchscreen technology, and combinations of these, for gesture detection and recognition. Additionally, computing device 1100 may include accelerometers or gyroscopes (e.g., as part of an inertia measurement unit (IMU)) that enable detection of motion. In some examples, the output of the accelerometers or gyroscopes may be used by computing device 1100 to render immersive augmented reality or virtual reality.

[0119] Power supply 1116 may include a hard-wired power supply, a battery power supply, or a combination thereof. Power supply 1116 may provide power to computing device 1100 to enable the components of computing device 1100 to operate.

[0120] Presentation component(s) 1118 may include a display (e.g., a monitor, a touch screen, aAttorney Docket No. LAM1P054WO-10182-1WO television screen, a heads-up-display (HUD), other display types, or a combination thereof), speakers, and / or other presentation components. Presentation component(s) 1118 may receive data from other components (e.g., GPU(s) 1108, CPU(s) 1106, etc.), and output the data (e.g., as an image, video, sound, etc.).

[0121] The disclosure may be described in the general context of computer code or machine- useable instructions, including computer-executable instructions such as program modules, being executed by a computer or other machine, such as a personal data assistant or other handheld device. Generally, program modules including routines, programs, objects, components, data structures, etc., refer to code that perform particular tasks or implement particular abstract data types. The disclosure may be practiced in a variety of system configurations, including hand-held devices, consumer electronics, general-purpose computers, more specialty computing devices, etc. The disclosure may also be practiced in distributed computing environments where tasks are performed by remote -processing devices that are linked through a communications network.Additional Considerations

[0122] As used in this specification and appended claims, the singular forms “a”, “an”, and “the” include plural referents unless the content and context dictates otherwise. For example, reference to “a cell” includes a combination of two or more such cells. Unless indicated otherwise, an “or” conjunction is used in its correct sense as a Boolean logical operator, encompassing both the selection of features in the alternative (A or B, where the selection of A is mutually exclusive from B) and the selection of features in conjunction (A or B, where both A and B are selected).

[0123] It is to be understood that the phrases “for each <item> of the one or more <items>,” “each <item> of the one or more <items>,” or the like, if used herein, are inclusive of both a single -item group and multiple-item groups, i.e., the phrase “for . . . each” is used in the sense that it is used in programming languages to refer to each item of whatever population of items is referenced. For example, if the population of items referenced is a single item, then “each” would refer to only that single item (despite the fact that dictionary definitions of “each” frequently define the term to refer to “every one of two or more things”) and would not imply that there must be at least two of those items. Similarly, the term “set” or “subset” should not be viewed, in itself, as necessarily encompassing a plurality of items — it will be understood that a set or a subset can encompass only one member or multiple members (unless the context indicates otherwise).

[0124] The use, if any, of ordinal indicators, e.g., (a), (b), (c) . . . or the like, in this disclosure andAttorney Docket No. LAM1P054WO-10182-1WO claims is to be understood as not conveying any particular order or sequence, except to the extent that such an order or sequence is explicitly indicated. For example, if there are three steps labeled (i), (ii), and (iii), it is to be understood that these steps may be performed in any order (or even concurrently, if not otherwise contraindicated) unless indicated otherwise. For example, if step (ii) involves the handling of an element that is created in step (i), then step (ii) may be viewed as happening at some point after step (i). Similarly, if step (i) involves the handling of an element that is created in step (ii), the reverse is to be understood. It is also to be understood that use of the ordinal indicator “first'’ herein, e.g., “a first item,” should not be read as suggesting, implicitly or inherently, that there is necessarily a “second” instance, e.g., “a second item.”

[0125] Various computational elements including processors, memory, instructions, routines, models, or other components may be described or claimed as “configured to” perform a task or tasks. In such contexts, the phrase “configured to” is used to connote structure by indicating that the component includes structure (e.g., stored instructions, circuitry, etc.) that performs the task or tasks during operation. As such, the unit / circuit / component can be said to be configured to perform the task even when the specified component is not necessarily currently operational (e.g., is not on).

[0126] The components used with the “configured to” language may refer to hardware — for example, circuits, memory storing program instructions executable to implement the operation, etc. Additionally, “configured to” can refer to generic structure (e.g., generic circuitry) that is manipulated by software and / or firmware (e.g., an FPGA or a general-purpose processor executing software) to operate in manner that is capable of performing the recited task(s). Additionally, “configured to” can refer to one or more memories or memory elements storing computer executable instructions for performing the recited task(s). Such memory elements may include memory on a computer chip having processing logic. In some contexts, “configured to” may also include adapting a manufacturing process (e.g., a semiconductor fabrication facility) to fabricate devices (e.g., integrated circuits) that are adapted to implement or perform one or more tasks.

[0127] Although the foregoing embodiments have been described in some detail for purposes of clarity of understanding, it will be apparent that certain changes and modifications may be practiced within the scope of the appended claims. It should be noted that there are many alternative ways of implementing the processes, systems, and apparatus of the present embodiments. Accordingly, the present embodiments are to be considered as illustrative and not restrictive, and the embodiments are not to be limited to the details given herein.

Claims

Attorney Docket No. LAM1P054WO-10182-1WOCLAIMSWhat is claimed is:

1. A method for determining wafer bow characteristics, the method comprising: projecting, using a projection device disposed in or on a portion of a semiconductor fabrication chamber, one or more fringe pattern images onto a surface of a wafer; capturing, using one or more camera devices, images representative of reflections of the one or more fringe pattern images from the surface of the wafer; generating an unwrapped phase map based on the captured images; and generating a three-dimensional reconstruction of a surface of the wafer based on the unwrapped phase map using phase-measuring deflectometry.

2. The method of claim 1, further comprising determining wafer bow characteristics based on the three-dimensional reconstruction.

3. The method of claim 2, further comprising determining one or more backside deposition parameters to correct wafer bow indicated by the wafer bow characteristics.

4. The method of claim 2, further comprising determining film stress metrics based on the wafer bow characteristics.

5. The method of claim 2, further comprising determining in-plane displacements for silicon overlay error correction of lithographic masks.

6. The method of claim 1, wherein the three-dimensional reconstruction is generated in situ under hot wafer bow conditions.

7. The method of claim 1, wherein the three-dimensional reconstruction is generated during a time period when the wafer is being moved on end effectors.

8. A method for determining wafer bow characteristics using deflectometry, the method comprising: generating and projecting one or more fringe patterns on a wafer; capturing resulting image(s) using one or more cameras; generating an unwrapped phase map based on the images captured using the oneAttorney Docket No. LAM1P054WO-10182-1WO or more cameras; estimating slopes in the x and y directions for surface points of the wafer based on the unwrapped phase map; generating a three-dimensional reconstruction of a surface of the wafer based on the estimated slopes; and determining wafer bow characteristics associated with the wafer based on the three-dimensional surface reconstruction.

9. The method of claim 8, wherein the wafer bow characteristics are determined on a cold wafer.

10. The method of claim 8, wherein the wafer bow characteristics are determined on a heated wafer.

11. The method of claim 10, wherein wafer bow characteristics are determined for the heated wafer in situ as the wafer undergoes processing.

12. The method of claim 11 , further comprising determining parameters to clamp the heated wafer based on the determined wafer bow characteristics.

13. The method of claim 12, wherein clamping the wafer comprises vacuum clamping, and wherein the parameters comprise a differential pressure to be applied to clamp the wafer that is determined based on the wafer bow characteristics.

14. The method of claim 12, wherein clamping the wafer comprises electrostatic clamping, and wherein the parameters comprise an electrostatic force to be applied that is determined based on the wafer bow characteristics.

15. The method of claim 10, wherein the one or more fringe patterns projected on the wafer comprise a single fringe pattern projected on the heated wafer.

16. The method of claim 15, wherein generating the unwrapped phase map comprises providing the resulting image(s) to a trained machine learning model configured to generate, as output, the unwrapped phase map.Attorney Docket No. LAM1P054WO-10182-1WO17. The method of claim 8, wherein generating the unwrapped phase map comprises performing temporal unwrapping using images associated with multiple fringe patterns projected on the wafer, the multiple fringe patterns having multiple phase shifts and fringe frequencies.

18. The method of claim 8, wherein the one or more fringe patterns projected on the wafer comprise a plurality of fringe frequencies and a plurality of phase shifts for each fringe frequency.

19. The method of claim 8, further comprising performing system calibration to determine calibration parameters for: the one or more cameras used to capture the resulting image(s); a camera to wafer calibration; and a camera to projector calibration for the projector used to project the one or more fringe patterns.

20. The method of claim 19, wherein the calibration parameters comprise: a focal length for each of the one or more cameras, a center of a camera sensor image plane for each of the one or more cameras, and / or lens distortion parameters for each of the one or more cameras.

21. The method of claim 19, wherein the one or more cameras comprise two cameras, and wherein performing the system calibration comprises determining calibration parameters to calibrate the two cameras to each other.

22. The method of claim 8, wherein a slope-height ambiguity is resolved by one of: capturing the resulting images using two cameras at the same time; utilizing two projection devices to project the one or more fringe patterns, wherein the two projection devices are shifted by a known amount with respect to one another; determining distance to the wafer surface using a distance sensor; or utilizing multiple projection device to project the one or more fringe patterns and utilizing two cameras to capture the resulting images.

23. The method of claim 8, wherein estimating the slopes in the x and y directions comprises estimating normal vectors for a set of surface points on the surface of the wafer.Attorney Docket No. LAM1P054WO-10182-1WO24. The method of claim 8, wherein determining the wafer bow characteristics comprises determining wafer bow magnitude and direction for a set of points corresponding to the surface of the wafer.

25. A system for determining wafer bow characteristics, the system comprising: a projection device disposed in or on a portion of a semiconductor fabrication chamber, wherein the projection device is configured to project one or more fringe pattern images onto a surface of a wafer; a first camera disposed in or on a portion of the semiconductor fabrication chamber; a second camera disposed in or on a portion of the semiconductor fabrication chamber, wherein the first camera and the second camera are configured to capture images of reflections of the projected one or more fringe pattern images from the surface of the wafer; and one or more processors configured to; generate an unwrapped phase map based on the captured images; and generate a three-dimensional reconstruction of a surface of the wafer based on the unwrapped phase map using phase-measuring deflectometry.

26. The system of claim 25, wherein the portion of the semiconductor fabrication chamber comprises a portion of a front end module, and wherein the three-dimensional reconstruction of the surface of the wafer is generated when the wafer is transferred from a front opening unified pod (FOUP) to a load lock or from the load lock to the FOUP.

27. The system of claim 25, wherein the projection device is disposed in a first viewport of a process station of the semiconductor fabrication chamber, and wherein the first camera is disposed in a second viewport of the process station.

28. The system of claim 27, wherein the second camera is disposed in a third viewport of the process station.

29. The system of claim 28, wherein the first camera and the second camera have different viewing angles, and wherein the one or more processors are further configured to stitch together images captured by the first camera and the second camera.Attorney Docket No. LAM1P054WO-10182-1WO30. A system for determining wafer bow characteristics, the system comprising: a metrology tool associated with a semiconductor fabrication apparatus comprising: a projection device, wherein the projection device is configured to project one or more fringe pattern images onto a surface of a wafer; a first camera and a second camera, wherein the first camera and the second camera are configured to capture images of reflections of the projected one or more fringe pattern images from the surface of the wafer, wherein the metrology tool is configured to receive the wafer from the semiconductor fabrication apparatus; and one or more processors configured to: generate an unwrapped phase map based on the captured images; and generate a three-dimensional reconstruction of a surface of the wafer based on the unwrapped phase map using phase-measuring deflectometry.

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