Trench gate semiconductor device and manufacturing method therefor

Abstract

The present disclosure provides a trench gate semiconductor device and a manufacturing method therefor. Compared with the related art in which a gate oxide layer is formed by oxidizing a first epitaxial layer, in the embodiments of the present disclosure, the gate oxide layer is formed by oxidizing a prefabricated epitaxial layer, so as to address the problem of high roughness of trench sidewalls caused by the etching process during the forming the trench by means of etching on the first epitaxial layer, thereby reducing the influence of surface roughness scattering of the trench on channel mobility. Further, a shielding layer is arranged between the gate oxide layer on the outer bottom wall of the trench and the first epitaxial layer, so as to reduce the peak electric field at the bottom corners of the trench, thereby improving the breakdown voltage.

Description

Trench gate semiconductor devices and their fabrication methods Technical Field

[0001] This invention relates to the field of semiconductor devices, and more particularly to a trench gate semiconductor device and its fabrication method. Background Technology

[0002] A trench MOSFET (or trench gate MOSFET) is a specially designed MOSFET (metal-oxide-semiconductor field-effect transistor).

[0003] Compared to planar MOSFETs, trench MOSFETs offer better channel utilization and eliminate the resistance inherent in JFET (Junction Field-Effect Transistor) regions. However, their deep trench etching technology presents significant process challenges. The morphology of the etched surface, including etching depth, etching vertical angle, roughness of the etching sidewalls and bottom, and trench bottom angle, all have a substantial impact on device performance. Technical solutions

[0004] The main technical problem addressed by this disclosure is how to improve the performance of trench gate semiconductor devices.

[0005] To solve the above-mentioned technical problems, the first technical solution adopted in this disclosure is: to provide a trench gate semiconductor device, wherein, it includes:

[0006] Substrate;

[0007] A first epitaxial layer is disposed on the surface of a substrate, and the substrate and the first epitaxial layer are of a first conductivity type; a plurality of cells and a trench located between two adjacent cells are disposed on the side of the first epitaxial layer away from the substrate.

[0008] The gate oxide layer includes a first gate oxide layer and a second gate oxide layer connected to each other, the first gate oxide layer being located on the outer wall of the trench and the second gate oxide layer being located on the outer bottom wall of the trench;

[0009] A shielding layer is located between the gate oxide layer and the first epitaxial layer on the outer bottom wall of the trench; the shielding layer is of the second conductivity type.

[0010] The gate oxide layer is obtained by oxidizing the surface of the pre-epitaxial layer, and the shielding layer is formed by the unoxidized portion of the pre-epitaxial layer; the pre-epitaxial layer is located at least on the outer surface of the trench, and the surface roughness of the pre-epitaxial layer is less than 0.2 nm.

[0011] The shielding layer comprises multiple semiconductor sublayers arranged sequentially along the direction from the substrate to the epitaxial layer, with the uniformity of each semiconductor sublayer being less than 6%.

[0012] In this process, the ion doping concentrations of adjacent semiconductor sublayers differ.

[0013] The trench gate semiconductor device further includes a second epitaxial layer; the second epitaxial layer is disposed on the surface of the cell away from the substrate and covers multiple cells;

[0014] The second epitaxial layer is formed from the unoxidized portion of the pre-fabricated epitaxial layer.

[0015] The trench gate semiconductor device further includes a first doped region located within the second epitaxial layer; the first doped region is a heavily doped region; and the first doped region is of a second conductivity type.

[0016] The shielding layer has a thickness of 100nm to 600nm and an ion doping concentration greater than 1E16cm-3; the gate oxide layer has a thickness of 5nm to 30nm.

[0017] The cell includes a source region. The trench gate semiconductor device also includes a gate electrode layer, an interlayer dielectric layer, and a source electrode layer. The gate electrode layer is disposed at least in the trench and is insulated from the first epitaxial layer through the gate oxide layer. The interlayer dielectric layer covers the gate electrode layer. The source electrode layer is disposed on the side of the interlayer dielectric layer away from the substrate and is insulated from the gate electrode layer through the interlayer dielectric layer.

[0018] in,

[0019] The source electrode layer achieves electrical connection with the source region through the surface of the source region away from the substrate;

[0020] And / or,

[0021] The source electrode layer is electrically connected to the source region through the side of the source region near the trench; the side portion of the source region is exposed in the trench to form an exposed surface, and part of the source electrode layer extends into the trench to form an extension, which is electrically connected to the exposed surface.

[0022] The cell also includes a second doped region; the second doped region is located between the source regions; the second doped region is of a second conductivity type.

[0023] And / or,

[0024] The trench gate semiconductor device also includes an ohmic contact layer, which is located at least between the source region and the source electrode layer. The ohmic contact layer is electrically connected to the source region and to the source electrode layer.

[0025] The corners within the trench are either rounded or right angles.

[0026] To solve the above-mentioned technical problems, the second technical solution adopted in this disclosure is: providing a method for fabricating a trench gate semiconductor device, comprising:

[0027] A first epitaxial layer is prepared on a substrate; the substrate and the first epitaxial layer are of a first conductivity type;

[0028] Doping and trenching are performed on the surface of the first epitaxial layer away from the substrate to form multiple cells and grooves between two adjacent cells;

[0029] A pre-fabricated epitaxial layer is grown in the groove; the surface roughness of the pre-fabricated epitaxial layer is less than 0.2 nm, and the pre-fabricated epitaxial layer is of the second conductivity type;

[0030] The surface of the pre-fabricated epitaxial layer is oxidized. A portion of the pre-fabricated epitaxial layer along the sidewall of the groove is oxidized to form a first gate oxide layer, and a portion along the bottom wall of the groove is oxidized to form a second gate oxide layer. A shielding layer is formed along the unoxidized portion of the bottom wall of the groove. The first gate oxide layer and the second gate oxide layer form a trench. The shielding layer is located on the bottom wall of the groove and between the gate oxide layer and the first epitaxial layer.

[0031] in,

[0032] The steps for growing a prefabricated epitaxial layer within a groove include:

[0033] A pre-fabricated epitaxial layer is grown in the groove, and the growth rate of the pre-fabricated epitaxial layer on the bottom wall of the groove is greater than the growth rate of the pre-fabricated epitaxial layer on the side wall of the groove.

[0034] The steps of oxidizing the surface of the pre-fabricated epitaxial layer, wherein a portion of the pre-fabricated epitaxial layer along the sidewall of the groove is oxidized to form a first gate oxide layer, and a portion along the bottom of the groove is oxidized to form a second gate oxide layer, include:

[0035] The surface of the pre-fabricated epitaxial layer is oxidized. The portion of the pre-fabricated epitaxial layer along the sidewall of the groove is oxidized to form a first gate oxide layer, and the portion along the bottom of the groove is oxidized to form a second gate oxide layer. The portion along the bottom wall of the groove that is not oxidized forms a shielding layer. The thickness of the shielding layer is 100nm~600nm, and the thickness of the gate oxide layer is 5nm~30nm.

[0036] in,

[0037] Growing a prefabricated epitaxial layer within the groove also includes:

[0038] Multiple pre-fabricated semiconductor sublayers are sequentially grown on the surface of the groove, with the uniformity of each pre-fabricated semiconductor sublayer being less than 6%.

[0039] The prefabricated epitaxial layer grown within the trench includes:

[0040] A pre-formed epitaxial layer is grown within the groove and on the surface of the cell away from the substrate, and the pre-formed epitaxial layer outside the groove is configured as a second epitaxial layer.

[0041] The process of growing a prefabricated epitaxial layer within the groove also includes:

[0042] The second epitaxial layer is etched away. Beneficial effects

[0043] Unlike existing technologies, this disclosure provides a trench gate semiconductor device and its fabrication method. The trench gate semiconductor device includes a substrate, a first epitaxial layer, a gate oxide layer, and a shielding layer. The first epitaxial layer is disposed on the surface of the substrate, and the substrate and the first epitaxial layer are of a first conductivity type. Multiple cells and trenches located between adjacent cells are disposed on the side of the first epitaxial layer away from the substrate. The gate oxide layer includes a first gate oxide layer and a second gate oxide layer connected to each other. The first gate oxide layer is located on the outer wall of the trench, and the second gate oxide layer is located on the outer bottom wall of the trench. The shielding layer is located between the gate oxide layer on the outer bottom wall of the trench and the first epitaxial layer. The shielding layer is of a second conductivity type. The gate oxide layer is obtained by oxidizing the surface of the pre-fabricated epitaxial layer, and the shielding layer is formed from the unoxidized portion of the pre-fabricated epitaxial layer. The pre-fabricated epitaxial layer is located at least on the outer surface of the trench, and the surface roughness of the pre-fabricated epitaxial layer is less than 0.2 nm. Compared to related technologies where the gate oxide layer is formed by oxidizing a first epitaxial layer, the gate oxide layer in this embodiment is formed by oxidizing a pre-fabricated epitaxial layer. This addresses the issue of high roughness on the trench sidewalls caused by the etching process during trench formation on the first epitaxial layer, thereby reducing the impact of trench surface roughness scattering on channel mobility. Furthermore, a shielding layer is provided between the gate oxide layer and the first epitaxial layer on the bottom wall of the trench, which reduces the peak electric field at the bottom corner of the trench, thereby improving the breakdown voltage. Attached Figure Description

[0044] Figure 1 is a schematic diagram of the structure of a first embodiment of the trench gate semiconductor device provided in this disclosure;

[0045] Figure 2 is a schematic diagram of the structure of a second embodiment of the trench gate semiconductor device provided in this disclosure.

[0046] Figure 3 is a schematic diagram of the structure of a third embodiment of the trench gate semiconductor device provided in this disclosure;

[0047] Figure 4 is a schematic diagram of the structure of a fourth embodiment of the trench gate semiconductor device provided in this disclosure.

[0048] Figure 5 is a schematic diagram of the structure of the fifth embodiment of the trench gate semiconductor device provided in this disclosure;

[0049] Figure 6 is a flowchart illustrating one embodiment of the trench gate semiconductor device provided in this disclosure;

[0050] Figure 7 is a structural schematic diagram corresponding to the implementation method of step S1 in Figure 6;

[0051] Figure 8 is a schematic diagram of the structure corresponding to one embodiment of the source region formation provided in this disclosure;

[0052] Figure 9 is a structural schematic diagram corresponding to the implementation method of step S2 in Figure 6;

[0053] Figure 10 is a structural schematic diagram corresponding to the first embodiment of step S3 in Figure 6;

[0054] Figure 11 is a structural schematic diagram corresponding to the second embodiment of step S3 in Figure 6;

[0055] Figure 12 is a structural schematic diagram corresponding to the third embodiment of step S3 in Figure 6;

[0056] Figure 13 is a structural schematic diagram corresponding to the first embodiment of step S4 in Figure 6;

[0057] Figure 14 is a structural schematic diagram corresponding to the second embodiment of step S4 in Figure 6;

[0058] Figure 15 is a structural schematic diagram corresponding to the third embodiment of step S4 in Figure 6;

[0059] Figure 16 is a structural schematic diagram corresponding to the fourth embodiment of step S4 in Figure 6;

[0060] Figure 17 is a structural schematic diagram corresponding to the fifth embodiment of step S4 in Figure 6;

[0061] Figure 18 is a schematic diagram of the structure corresponding to an embodiment of forming a gate electrode layer, an interlayer dielectric layer, an ohmic contact layer and a source electrode layer provided by this common embodiment.

[0062] Figure 19 is a schematic diagram of another embodiment of the formation of a gate electrode layer, an interlayer dielectric layer, an ohmic contact layer and a source electrode layer provided by this common embodiment.

[0063] Figure label:

[0064] 100. Trench gate semiconductor device; 10. Substrate; 20. First epitaxial layer; 21. First layer region; 22. Second layer region; 23. Cell; 231. Source region; 2311. Exposure surface; 232. Second doped region; 24. Trench; 241. Corner; 30. Gate oxide layer; 31. First gate oxide layer; 32. Second gate oxide layer; 40. Shielding layer; 41. Semiconductor sublayer; 50. Source electrode layer; 51. Extension; 60. Interlayer dielectric layer; 70. Ohmic contact layer; 80. Gate electrode layer; 90. Second epitaxial layer; 91. First doped region; 110. Pre-fabricated epitaxial layer; 120. Oxide layer; 130. Trench; 140. Insulating dielectric layer; 141. Window. Embodiments of the present invention

[0065] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the embodiments of this disclosure.

[0066] The terms "first," "second," and "third" in this disclosure are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first," "second," or "third" may explicitly or implicitly include at least one of that feature. In the description of this disclosure, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified. All directional indications (such as up, down, left, right, front, back, etc.) in this disclosure are only used to explain the relative positional relationships and movements between components in a specific orientation (as shown in the figures). If the specific orientation changes, the directional indication will change accordingly. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or devices.

[0067] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of the embodiments disclosed herein. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0068] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings and examples.

[0069] Please refer to Figures 1 to 5. Figure 1 is a structural schematic diagram of the first embodiment of the trench gate semiconductor device provided in this disclosure. Figure 2 is a structural schematic diagram of the second embodiment of the trench gate semiconductor device provided in this disclosure. Figure 3 is a structural schematic diagram of the third embodiment of the trench gate semiconductor device provided in this disclosure. Figure 4 is a structural schematic diagram of the fourth embodiment of the trench gate semiconductor device provided in this disclosure. Figure 5 is a structural schematic diagram of the fifth embodiment of the trench gate semiconductor device provided in this disclosure.

[0070] This disclosure provides a trench gate semiconductor device 100. The trench gate semiconductor device 100 includes a substrate 10, a first epitaxial layer 20, a gate oxide layer 30, and a shielding layer 40. The first epitaxial layer 20 is disposed on the surface of the substrate 10, and the substrate 10 and the first epitaxial layer 20 are of a first conductivity type. A plurality of cells 23 and trenches 24 located between adjacent cells 23 are disposed on the side of the first epitaxial layer 20 away from the surface of the substrate 10. The gate oxide layer 30 includes a first gate oxide layer 31 and a second gate oxide layer 32 connected to each other. The first gate oxide layer 31 is located on the outer wall of the trench 24, and the second gate oxide layer 32 is located on the outer bottom wall of the trench 24. The shielding layer 40 is located between the gate oxide layer 30 on the outer bottom wall of the trench 24 and the first epitaxial layer 20. The shielding layer 40 is of a second conductivity type. The gate oxide layer 30 is obtained by oxidizing the surface of a pre-fabricated epitaxial layer 110, and the shielding layer 40 is formed from the unoxidized portion of the pre-fabricated epitaxial layer 110. The pre-fabricated epitaxial layer 110 is located at least on the outer surface of the trench 24, and the surface roughness of the pre-fabricated epitaxial layer 110 is less than 0.2 nm.

[0071] Compared to related technologies where the gate oxide layer 30 is formed by oxidizing the first epitaxial layer 20, the gate oxide layer 30 in this embodiment is formed by oxidizing a pre-fabricated epitaxial layer 110. This addresses the issue of high roughness on the sidewalls of the trench 24 caused by the etching process during the etching of the groove 130 (see Figure 9) on the first epitaxial layer 20, thereby reducing the impact of surface roughness scattering on the channel mobility. Furthermore, a shielding layer 40 is provided between the gate oxide layer 30 and the first epitaxial layer 20 on the outer bottom wall of the trench 24. This reduces the peak electric field at the bottom corner 241 of the trench 24, thereby improving the breakdown voltage.

[0072] In some embodiments, the substrate 10 may be silicon carbide. The first conductivity type is N-type, and the second conductivity type is P-type.

[0073] In some embodiments, the first epitaxial layer 20 includes a first layer region 21 and a second layer region 22 sequentially stacked, wherein the first layer region 21 is located between the second layer region 22 and the substrate 10, serving as a drift region. Ion implantation is performed on the second layer region 22 to form a well region. The well region is of a second conductivity type.

[0074] For example, the first epitaxial layer 20 may be silicon carbide.

[0075] Ion implantation is performed on the surface of the first epitaxial layer 20 away from the substrate 10 to form a plurality of cells 23 on the surface of the first epitaxial layer 20 away from the substrate 10. Trench 24 extends from the surface of the first epitaxial layer 20 away from the substrate 10 toward the first layer region 21 and enters the interior of the first layer region 21. In a direction parallel to the substrate 10, the trench 24 is located between two adjacent cells 23.

[0076] In some embodiments, the sidewalls and bottom walls of the groove 24 can be arranged vertically or inclined, and the angle between the sidewalls and bottom walls of the groove 24 is adjustable.

[0077] For example, the sidewalls of the groove 24 are perpendicular to the bottom wall of the groove 24.

[0078] In some embodiments, cell 23 includes source region 231. The trench gate semiconductor device 100 further includes a gate electrode layer 80, an interlayer dielectric layer 60, and a source electrode layer 50. The gate electrode layer 80 is disposed at least within the trench 24 and is insulated from the first epitaxial layer 20 by the gate oxide layer 30. The interlayer dielectric layer 60 covers the gate electrode layer 80. The source electrode layer 50 is electrically connected to the source region 231 through the upper surface of the source region 231 and / or the side surface of the source region 231 near the trench 24.

[0079] In some embodiments, as shown in FIG1, the source electrode layer 50 is electrically connected to the source region 231 through the side surface of the source region 231 away from the substrate 10.

[0080] Exemplarily, the gate oxide layer 30 covers the side of the source region 231 near the trench 24. The gate oxide layer 30 surrounds and forms the trench 24. The upper surface of the gate electrode layer 80 is higher than the lower surface of the source region 231. The gate electrode layer 80 is at least partially disposed within the trench 24. The interlayer dielectric layer 60 is partially located within the trench 24, or the interlayer dielectric layer 60 is completely located outside the trench 24.

[0081] Specifically, the gate electrode layer 80 may be entirely located within the trench 24; or, a portion of the gate electrode layer 80 may be located outside the trench 24, with the portion outside the trench 24 embedded in the source electrode layer 50.

[0082] In other embodiments, the source electrode layer 50 is electrically connected to the source region 231 near the side of the trench 24 (see FIG3). A portion of the side of the source region 231 is exposed within the trench 24 to form an exposure surface 2311, and a portion of the source electrode layer 50 extends into the trench 24 to form an extension 51, which is electrically connected to the exposure surface 2311. The first epitaxial layer 20 and the gate oxide layer 30 together enclose and form the trench 24.

[0083] For example, an interlayer dielectric layer 60 is disposed within the trench 24. The upper surface of the interlayer dielectric layer 60 is lower than the upper surface of the first epitaxial layer 20, and the upper surface of the gate electrode layer 80 is higher than the lower surface of the source region 231. The gate oxide layer 30 only covers the portion of the source region 231 near the trench 24. The portion of the surface of the source region 231 near the trench 24 that is not covered by the gate oxide layer 30 is the exposed surface 2311. Specifically, the upper surface of the first epitaxial layer 20 is at least 0.1 micrometers higher than the upper surface of the interlayer dielectric layer 90 to ensure good electrical connection between the source electrode layer 50 and the side of the source region 231 near the trench 24.

[0084] In some embodiments, as shown in FIG2, the source electrode layer 50 is electrically connected to the source region 231 via the side of the source region 231 near the trench 24, and also via the side surface of the source region 231 away from the substrate 10. This design increases the electrical connection area between the source electrode layer 50 and the source region 231, and can reduce the width of the source region 231 without affecting the good electrical connection between the source electrode layer 50 and the source region 231. Referring to the above description, it will not be repeated here.

[0085] The source electrode layer 50 includes, but is not limited to, various elemental metals and their alloys.

[0086] Source region 231 is used to provide charge carriers (such as electrons or holes).

[0087] For example, the source region 231 is located within the second layer region 22 and is spaced apart from the first layer region 21.

[0088] In some embodiments, a pre-fabricated epitaxial layer 110 is disposed on the outer surface of the trench 24. The oxidized pre-fabricated epitaxial layer 110 is partially oxidized to obtain a gate oxide layer 30 and a shielding layer 40 (see Figures 1, 2 and 5).

[0089] In other embodiments, as shown in Figures 3 and 4, a pre-fabricated epitaxial layer 110 is disposed on the outer surface of the trench 24 and also on the side surface of the first epitaxial layer 20 away from the substrate 10. The trench gate semiconductor device 100 further includes a second epitaxial layer 90. The second epitaxial layer 90 is disposed on the surface of the cell 23 away from the substrate 10 and covers a plurality of cells 23. The second epitaxial layer 90 is formed from the unoxidized portion of the pre-fabricated epitaxial layer 110. That is, the second epitaxial layer 90 is formed from the unoxidized portion of the pre-fabricated epitaxial layer 110 disposed on the side surface of the first epitaxial layer 20 away from the substrate 10. The pre-fabricated epitaxial layer 110 is partially oxidized to obtain the gate oxide layer 30, the shielding layer 40, and the second epitaxial layer 90.

[0090] In some embodiments, as shown in FIG4, the trench gate semiconductor device 100 further includes a first doped region 91, which is located within the second epitaxial layer 90. The first doped region 91 is a heavily doped region. The first doped region 91 is a second conductivity type.

[0091] The first doped region 91 is provided to reduce the ohmic contact resistivity between the second epitaxial layer 90 and the source electrode layer 50.

[0092] The shielding layer 40 is equipotentially connected to the source region 231.

[0093] In some embodiments, the thickness of the shielding layer 40 is 100 nm to 600 nm, and the ion doping concentration of the shielding layer 40 is greater than 1E16 cm⁻³. The thickness of the gate oxide layer 30 is 5 nm to 30 nm.

[0094] In some embodiments, as shown in FIG5, the shielding layer 40 includes: a multilayer semiconductor sublayer 41, wherein the multilayer semiconductor sublayer 41 is sequentially disposed along the direction from the substrate 10 to the epitaxial layer, and the uniformity of each semiconductor sublayer 41 is less than 6%.

[0095] For example, the pre-fabricated epitaxial layer 110 has a multilayer structure. Specifically, the shielding layer 40 includes three semiconductor sublayers 41.

[0096] There is no restriction on the number of semiconductor sublayers 41 here; the number can be selected according to actual needs.

[0097] The adjacent semiconductor sublayers 41 have different ion doping concentrations. The different ion doping concentration gradient distributions can match the different doped regions in the second layer region 22 and the CEL (current spread layer) design, achieving the electric field shielding effect at the bottom of the trench 24 while ensuring low resistance for forward conduction.

[0098] For example, the pre-fabricated epitaxial layer 110 may be silicon carbide (SIC), and the crystal form of silicon carbide may include 4H-SIC, 3C-SIC or 6H-SiC.

[0099] The shielding layer 40 in the embodiments of this disclosure may include multiple semiconductor sublayers 41.

[0100] Compared to the design in related technologies that uses ion implantation to form an implantation region at the bottom of the trench 24, the present invention uses a secondary epitaxial method to form a shielding layer 40 at the bottom of the trench 24. The shielding layer 40 has fewer ion defects and a better PN junction morphology, avoiding the accumulation of electric field lines at the bottom corner of the trench 24, thereby reducing the peak electric field at the bottom corner and improving the breakdown voltage.

[0101] In some embodiments, cell 23 further includes a second doped region 232 located between source regions 231. The second doped region 232 is of a second conductivity type.

[0102] For example, the second doped region 232 extends from the side surface of the first epitaxial layer 20 away from the substrate 10 toward the first layer region 21 and enters the interior of the first layer region 21.

[0103] In some embodiments, the trench gate semiconductor device 100 further includes an ohmic contact layer 70, which is located at least between the source region 231 and the source electrode layer 50. The ohmic contact layer 70 is electrically connected to the source region 231 and to the source electrode layer 50.

[0104] For example, when the gate oxide layer 30 covers the side of the source region 231 near the trench 24, the ohmic contact layer 70 is located between the upper surface of the first epitaxial layer 20 and the source electrode layer 50, and the source electrode layer 50 is electrically connected to the source region 231 only through the upper surface of the source region 231. When the side portion of the source region 231 is exposed in the trench 24 to form an exposure surface 2311, the ohmic contact layer 70 is located between the upper surface of the first epitaxial layer 20 and the source electrode layer 50, and is also located between the exposure surface 2311 and the source electrode layer 50, and the source electrode layer 50 is electrically connected to the source region 231 through the upper surface of the source region 231 and the exposure surface 2311.

[0105] The ohmic contact layer 70 can be formed by high-temperature nickel tempering, high-temperature titanium tempering, or an alloy of the two tempering.

[0106] In some embodiments, cell 23 further includes a second doped region 232, and trench gate semiconductor device 100 further includes an ohmic contact layer 70.

[0107] In some embodiments, the corners 241 within the groove 24 are rounded or right angles.

[0108] The corner 241 within the trench 24 includes a top corner and a bottom corner. The top corner is located at the opening of the trench 24 and is the corner 241 formed by the sidewall of the trench 24 and the adjacent surface of the first epitaxial layer 20 away from the substrate 10. The bottom corner is the corner 241 formed by the sidewall of the trench 24 and the bottom wall of the trench 24. The top corner is a rounded corner or a right angle, and / or, the bottom corner is a rounded corner or a right angle.

[0109] For example, the top corner and the bottom corner are different; the bottom corner is rounded, while the top corner is a right angle. Designing the bottom corner as a rounded corner can distribute the electric field more evenly, reduce the concentration of the electric field at the bottom corner, and thus improve the breakdown voltage of the device.

[0110] Please refer to Figures 1 to 6. Figure 6 is a flowchart illustrating one embodiment of the trench gate semiconductor device provided in this disclosure.

[0111] This disclosure provides a method for fabricating a trench gate semiconductor device, used to fabricate the trench gate semiconductor device 100 described above. The specific steps of the method for fabricating the trench gate semiconductor device are as follows:

[0112] Please refer to Figures 1 to 7. Figure 7 is a schematic diagram of the structure corresponding to the implementation method of step S1 in Figure 6.

[0113] S1: A first epitaxial layer is prepared on a substrate; the substrate and the first epitaxial layer are of a first conductivity type.

[0114] Specifically, a first epitaxial layer 20 is epitaxially grown on the substrate 10. The substrate 10 and the first epitaxial layer 20 are of a first conductivity type.

[0115] In some embodiments, the substrate 10 may be silicon carbide. The first epitaxial layer 20 may be silicon carbide. The first conductivity type is N-type.

[0116] In some embodiments, the first epitaxial layer 20 includes a first layer region 21 and a second layer region 22 stacked sequentially, the first layer region 21 being located between the second layer region 22 and the substrate 10, serving as a drift region. Ion implantation is performed on the second layer region 22 to form a well region. The well region is of a second conductivity type.

[0117] Please refer to Figures 1 to 9. Figure 8 is a structural schematic diagram corresponding to one embodiment of the source region formation provided by this disclosure, and Figure 9 is a structural schematic diagram corresponding to one embodiment of step S2 in Figure 6.

[0118] S2: Doping and trenching are performed on the surface of the first epitaxial layer away from the substrate to form multiple cells and grooves located between two adjacent cells.

[0119] Specifically, the surface of the first epitaxial layer 20 away from the substrate 10 is doped and grooved to form a plurality of cells 23 and a groove 130 located between two adjacent cells 23.

[0120] In some embodiments, the sidewalls and bottom walls of the groove 130 can be arranged vertically or inclined, and the angle between the sidewalls and bottom walls of the groove 130 is adjustable.

[0121] For example, the sidewall of the groove 130 is perpendicular to the bottom wall of the groove 130.

[0122] Cell 23 is formed on the surface of the first epitaxial layer 20 away from the substrate 10 by ion implantation. Cell 23 includes source region 231.

[0123] For example, an insulating dielectric layer 140 is deposited on the surface of the first epitaxial layer 20 away from the substrate 10. The insulating dielectric layer 140 is exposed, developed, and etched to form a window 141 on the insulating dielectric layer 140. Ions are implanted through the window 141 to form a source region 231.

[0124] A groove 130 is formed by etching on the surface of the first epitaxial layer 20 away from the substrate 10.

[0125] In some embodiments, the depth of the groove 130 is greater than or equal to 1 micrometer. The width of the groove 130 is greater than 0.2 micrometers. The surface roughness of the groove 130 is greater than 1 nm.

[0126] There are no restrictions on the order of doping and grooving; the choice can be made based on actual needs.

[0127] In some embodiments, cell 23 further includes a second doped region 232, which is formed by ion implantation. The doping order of the second doped region 232 and the source region 231 is not limited here and can be selected according to actual needs.

[0128] In one specific embodiment, cell 23 further includes a second doped region 232, and a source region 231, a second doped region 232 and a groove 130 are sequentially formed on the surface of the first epitaxial layer 20 away from the substrate 10.

[0129] The structural descriptions of the source region 231, the second doped region 232, and the groove 130 are as described above and will not be repeated here.

[0130] Please refer to Figures 1 to 12. Figure 10 is a structural schematic diagram corresponding to the first embodiment of step S3 in Figure 6, Figure 11 is a structural schematic diagram corresponding to the second embodiment of step S3 in Figure 6, and Figure 12 is a structural schematic diagram corresponding to the third embodiment of step S3 in Figure 6.

[0131] S3: A pre-fabricated epitaxial layer is grown in the groove; the surface roughness of the pre-fabricated epitaxial layer is less than 0.2 nm, and the pre-fabricated epitaxial layer is of the second conductivity type.

[0132] In some embodiments, the specific steps of growing the prefabricated epitaxial layer in the groove in step S3 include: growing the prefabricated epitaxial layer in the trench, and making the growth rate of the prefabricated epitaxial layer on the bottom wall of the trench greater than the growth rate of the prefabricated epitaxial layer on the side wall of the trench.

[0133] The thickness of the prefabricated epitaxial layer 110 on the sidewall of the groove 130 is 5nm~30nm.

[0134] For example, the thickness of the prefabricated epitaxial layer 110 on the bottom wall of the groove 130 is 100nm~600nm.

[0135] By controlling the growth rate of the pre-fabricated epitaxial layer 110 on the bottom wall of the groove 130 to be greater than the growth rate of the pre-fabricated epitaxial layer 110 on the side wall of the groove 130, the thickness of the pre-fabricated epitaxial layer 110 on the bottom wall of the groove 130 is made greater than the thickness of the pre-fabricated epitaxial layer 110 on the side wall of the groove 130, and the thickness of the pre-fabricated epitaxial layer 110 on the side wall of the groove 130 is made to be 5nm~30nm. This facilitates the complete oxidation of the pre-fabricated epitaxial layer 110 on the side wall of the groove 130 in subsequent steps, avoiding the influence of the residual pre-fabricated epitaxial layer 110 on the side wall of the groove 130 on the control of the electric field in the finished device. Secondly, during the complete oxidation of the pre-fabricated epitaxial layer 110 on the side wall of the groove 130, the entire pre-fabricated epitaxial layer 110 is prevented from being oxidized.

[0136] In some embodiments, as shown in FIG10, the specific steps of growing a pre-epitaxial layer in the groove in step S3 include: growing a pre-epitaxial layer in the groove and on the surface of the cell away from the substrate, wherein the pre-epitaxial layer outside the groove is configured as a second epitaxial layer.

[0137] For example, a pre-formed epitaxial layer 110 is grown within the groove 130 and on the surface of the first epitaxial layer 20 away from the substrate 10. The growth rate of the pre-formed epitaxial layer 110 on the bottom wall of the groove 130 is greater than the growth rate of the pre-formed epitaxial layer 110 on the side wall of the groove 130, and the growth rate of the pre-formed epitaxial layer 110 on the surface of the first epitaxial layer 20 away from the substrate 10 is greater than the growth rate of the pre-formed epitaxial layer 110 on the side wall of the groove 130, such that when the pre-formed epitaxial layer 110 on the side wall of the groove 130 is completely oxidized, the unoxidized portion of the pre-formed epitaxial layer 110 on the bottom wall of the groove 130 forms a shielding layer 40, and the unoxidized portion of the pre-formed epitaxial layer 110 on the surface of the first epitaxial layer 20 away from the substrate 10 forms a second epitaxial layer 90.

[0138] The thickness of the second epitaxial layer 90 is not limited here and can be selected according to actual needs. The thickness of the second epitaxial layer 90 and the shielding layer 40 can be the same or different.

[0139] In some embodiments, as shown in FIG11, step S3 further includes: performing ion implantation on the second epitaxial layer to form a first doped region.

[0140] For example, the first doped region 91 is located within the second epitaxial layer 90 to reduce the ohmic contact rate between the first epitaxial layer 20 and the source electrode layer 50.

[0141] In some embodiments, as shown in FIG12, the specific steps of growing a pre-epitaxial layer in the groove in step S3 include: growing a pre-epitaxial layer in the groove and on the surface of the cell away from the substrate, and etching away the pre-epitaxial layer grown on the surface of the cell away from the substrate.

[0142] Specifically, the pre-fabricated epitaxial layer 110 is etched to remove the pre-fabricated epitaxial layer 110 located on the upper surface of the first epitaxial layer 20, while retaining the pre-fabricated epitaxial layer 110 located in the groove 130.

[0143] For example, a hard mask is prepared on the groove 130 and the upper surface of the first epitaxial layer 20, the hard mask on the upper surface of the first epitaxial layer 20 and the prefabricated epitaxial layer 110 on the upper surface of the first epitaxial layer 20 are removed, and then the hard mask in the groove 130 is removed, while the prefabricated epitaxial layer 110 in the groove 130 is retained.

[0144] The methods for removing the pre-fabricated epitaxial layer 110 located on the upper surface of the first epitaxial layer 20 include, but are not limited to, at least one of grinding, CMP (Chemical Mechanical Polishing), and Etch Back.

[0145] Before secondary epitaxy is performed on the sidewalls of the groove 130, i.e., before the pre-epitaxial layer 110 is grown, the roughness of the sidewalls of the groove 130 is greater than 1 nm. After secondary epitaxy is performed on the sidewalls of the groove 130, i.e., the pre-epitaxial layer 110 is grown on the sidewalls of the groove 130, the pre-epitaxial layer 110 is the secondary epitaxy layer, and the surface roughness of the pre-epitaxial layer 110 is less than 0.2 nm.

[0146] In some embodiments, step S4, which involves growing a pre-epitaxial layer on the surface of the groove, further includes growing multiple pre-epitaxial sub-layers sequentially on the surface of the groove, wherein the uniformity of each pre-epitaxial sub-layer is less than 6%.

[0147] For example, the pre-fabricated epitaxial layer 110 is obtained through multiple growths, and the ion doping concentrations of two adjacent pre-fabricated semiconductor sub-layers (not shown) are different.

[0148] In some embodiments, the prefabricated epitaxial layer 110 may be grown only within the groove 130.

[0149] Please refer to Figures 1 to 15. Figure 13 is a structural schematic diagram corresponding to the first embodiment of step S4 in Figure 6. Figure 14 is a structural schematic diagram corresponding to the second embodiment of step S4 in Figure 6. Figure 15 is a structural schematic diagram corresponding to the third embodiment of step S4 in Figure 6.

[0150] S4: The surface of the pre-fabricated epitaxial layer is oxidized, and a portion of the pre-fabricated epitaxial layer along the sidewall of the groove is oxidized to form a first gate oxide layer, and a portion along the bottom wall of the groove is oxidized to form a second gate oxide layer; and a shielding layer is formed along the unoxidized portion of the bottom wall of the groove; the first gate oxide layer and the second gate oxide layer form a trench, and the shielding layer is located on the bottom wall of the groove and between the gate oxide layer and the first epitaxial layer.

[0151] In some embodiments, as shown in FIG14, the oxide layer 120 located on the upper surface of the first epitaxial layer 20 is removed, and the oxide layer 120 located on the sidewall of the groove 130 is partially removed to expose a portion of the side surface of the source region 231 near the groove 130, thereby forming the gate oxide layer 30. The side surface of the source region 231 is partially exposed within the groove 130 to form an exposure surface 2311. The gate oxide layer 30 and the first epitaxial layer 20 together form a trench 24. Specifically, the surface of the gate oxide layer 30 and the exposure surface 2311 together form the trench 24.

[0152] In some embodiments, the pre-fabricated epitaxial layer 110 is located within the groove 130. Step S4, which involves oxidizing the surface of the pre-fabricated epitaxial layer, wherein a portion of the pre-fabricated epitaxial layer along the sidewall of the groove is oxidized to form a first gate oxide layer, and a portion along the bottom wall of the groove is oxidized to form a second gate oxide layer, includes: oxidizing the surface of the pre-fabricated epitaxial layer; oxidizing the entire portion of the pre-fabricated epitaxial layer along the sidewall of the groove to form a first gate oxide layer; oxidizing the portion along the bottom wall of the groove to form a second gate oxide layer; and forming a shielding layer along the unoxidized portion of the bottom wall of the groove; the thickness of the shielding layer is 100 nm to 600 nm, and the thickness of the gate oxide layer is 5 nm to 30 nm.

[0153] In one specific embodiment, as shown in FIG13, only the surface of the pre-fabricated epitaxial layer 110 is oxidized to form the gate oxide layer 30 and the shielding layer 40.

[0154] In another specific embodiment, as shown in FIG14, the surface of the pre-fabricated epitaxial layer 110 and the surface of the first epitaxial layer 20 are oxidized to form an oxide layer 120. The oxide layer 120 located on the upper surface of the first epitaxial layer 20 is removed, and the oxide layer 120 located in the groove 130 is retained to form the gate oxide layer 30 and the shielding layer 40.

[0155] For example, the gate oxide layer 30 covers the side of the source region 231 near the recess 130, and the gate oxide layer 30 surrounds and forms a trench 24 (see Figures 13 and 14). Alternatively, the side portion of the source region 231 is exposed within the recess 130 to form an exposed surface 2311, and the gate oxide layer 30 and the first epitaxial layer 20 together surround and form the trench 24. Specifically, the surface of the gate oxide layer 30 and the exposed surface 2311 together surround and form the trench 24 (see Figure 15).

[0156] Please refer to Figures 1 to 17. Figure 16 is a structural schematic diagram corresponding to the fourth embodiment of step S4 in Figure 6, and Figure 17 is a structural schematic diagram corresponding to the fifth embodiment of step S4 in Figure 6.

[0157] In some embodiments, as shown in FIG16, the pre-fabricated epitaxial layer 110 is located within the groove 130 and is also located on the side surface of the first epitaxial layer 20 away from the substrate 10. The step of oxidizing the surface of the pre-fabricated epitaxial layer in step S4, wherein a portion of the pre-fabricated epitaxial layer along the sidewall of the groove is oxidized to form a first gate oxide layer and a portion along the bottom wall of the groove is oxidized to form a second gate oxide layer, includes: oxidizing the surface of the pre-fabricated epitaxial layer, wherein the entire portion of the pre-fabricated epitaxial layer along the sidewall of the groove is oxidized to form a first gate oxide layer, a portion along the bottom wall of the groove is oxidized to form a second gate oxide layer, a shielding layer is formed along the unoxidized portion of the bottom wall of the groove, and a second epitaxial layer is formed along the unoxidized portion of the surface of the first epitaxial layer away from the substrate.

[0158] For example, the surface of the pre-fabricated epitaxial layer 110 is oxidized to form an oxide layer 120, the oxide layer 120 located on the upper surface of the first epitaxial layer 20 is removed, and the oxide layer 120 located in the groove 130 is retained to form a gate oxide layer 30, a shielding layer 40 and a second epitaxial layer 90.

[0159] In some embodiments, as shown in FIG17, the pre-fabricated epitaxial layer 110 is located within the trench 24 and is also located on the surface of the first epitaxial layer 20 away from the substrate 10. Step S4 further includes etching away the second epitaxial layer.

[0160] For example, the surface of the pre-fabricated epitaxial layer 110 is oxidized to form an oxide layer 120. The oxide layer 120 is located within the trench 24 and also on the side of the first epitaxial layer 20 away from the substrate 10. The second epitaxial layer 90 is located between the first epitaxial layer 20 and the oxide layer 120. The oxide layer 120 and the second epitaxial layer 90 located on the side of the first epitaxial layer 20 away from the substrate 10 are sequentially etched using a hard mask to form the gate oxide layer 30 and the shielding layer 40.

[0161] In related technologies, the gate oxide layer 30 formed by oxidation is directly formed by thermal oxidation of the sidewalls of the groove 130. The gate oxide layer 30 surrounds and forms the trench 24. That is, the large roughness of the sidewalls of the groove 130 caused by the etching process leads to a large roughness of the sidewalls of the trench 24. However, in this embodiment, the gate oxide layer 30 formed by oxidation is formed by thermal oxidation of the pre-fabricated epitaxial layer 110. It can be understood that performing a secondary epitaxial treatment on the sidewalls of the groove 130 can repair the problem of large roughness of the sidewalls of the groove 130 caused by the etching process. The gate oxide layer 30 is formed by oxidation of the pre-fabricated epitaxial layer 110 and surrounds and forms the trench 24 to reduce the surface roughness of the trench 24, thereby reducing the impact of surface roughness scattering of the trench 24 on the channel mobility.

[0162] Please refer to Figures 1 to 19. Figure 18 is a schematic diagram of the structure corresponding to one embodiment of forming a gate electrode layer, an interlayer dielectric layer, an ohmic contact layer and a source electrode layer provided by this common embodiment. Figure 19 is a schematic diagram of the structure corresponding to another embodiment of forming a gate electrode layer, an interlayer dielectric layer, an ohmic contact layer and a source electrode layer provided by this common embodiment.

[0163] In some embodiments, after step S4, the method further includes: sequentially forming a gate electrode layer, an interlayer dielectric layer, an ohmic contact layer, and a source electrode layer.

[0164] In one exemplary embodiment, as shown in FIG18, the gate oxide layer 30 covers the side of the source region 231 near the trench 24, and the source electrode layer 50 is electrically connected to the source region 231 only through the upper surface of the source region 231. After the gate oxide layer 30 is formed, the gate electrode layer 80, the interlayer dielectric layer 60, the ohmic contact layer 70, and the source electrode layer 50 are formed sequentially.

[0165] In another specific embodiment, as shown in FIG19, the gate oxide layer 30 covers a portion of the source region 231 near the side of the trench 24, and the side portion of the source region 231 is exposed in the trench 24 to form an exposure surface 2311. After the gate oxide layer 30 is formed, the gate electrode layer 80, the interlayer dielectric layer 60, the ohmic contact layer 70, and the source electrode layer 50 are formed sequentially.

[0166] The structural descriptions of the gate electrode layer 80, the interlayer dielectric layer 90, and the gate oxide layer 30 are as described above and will not be repeated here.

[0167] In other embodiments, after step S4, the method further includes: sequentially forming a gate electrode layer, an interlayer dielectric layer, and a source electrode layer. Alternatively, after step S4, the method further includes: sequentially forming a gate electrode layer, an ohmic contact layer, an interlayer dielectric layer, and a source electrode layer.

[0168] For example, the ohmic contact layer 70 may be formed by high-temperature nickel tempering, high-temperature titanium tempering, or an alloy of both tempering.

[0169] This disclosure provides a method for fabricating a trench gate semiconductor device. The method includes: fabricating a first epitaxial layer 20 on a substrate 10; the substrate 10 and the first epitaxial layer 20 having a first conductivity type; doping and trenching on the surface of the first epitaxial layer 20 away from the substrate 10 to form a plurality of cells 23 and a groove 130 located between two adjacent cells 23; growing a pre-fabricated epitaxial layer 110 within the groove 130; the surface roughness of the pre-fabricated epitaxial layer 110 being less than 0.2 nm, and the pre-fabricated epitaxial layer 110 having a second conductivity type. The process involves oxidizing the surface of the pre-fabricated epitaxial layer 110. A portion of the pre-fabricated epitaxial layer 110 along the sidewall of the groove 130 is oxidized to form a first gate oxide layer 31, and a portion along the bottom wall of the groove 130 is oxidized to form a second gate oxide layer 32. A shielding layer 40 is formed along the unoxidized portion of the bottom wall of the groove 130. The first gate oxide layer 31 and the second gate oxide layer 32 form a trench 24. The shielding layer 40 is located on the bottom wall of the groove 130 and between the gate oxide layer 30 and the first epitaxial layer 20. This secondary epitaxial treatment of the sidewall of the groove 130 repairs the problem of high roughness on the sidewall of the groove 130 caused by the etching process, thereby reducing the impact of surface roughness scattering of the trench 24 on the channel mobility. Furthermore, the pre-fabricated epitaxial layer 110 on the sidewall of the groove 130 is completely oxidized during the formation of the gate oxide layer 30 to ensure good electric field control. Secondly, the shielding layer 40 is disposed at the bottom of the trench 24, which can reduce the peak electric field at the bottom corner 241 of the trench 24, thereby improving the breakdown voltage.

[0170] In the above embodiments and implementations, the descriptions of each embodiment and implementation have different focuses. For parts not described in detail in a certain embodiment or implementation, please refer to the relevant descriptions of other embodiments or implementations.

[0171] The above description is merely an implementation method of the present disclosure and does not limit the patent scope of the present disclosure. Any equivalent structural or procedural transformations made based on the description and drawings of the present disclosure, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of the present disclosure.

Claims

1. A trench gate semiconductor device, characterized by, The trench gate semiconductor device comprises a substrate, a first epitaxial layer arranged on a surface of the substrate, the substrate and the first epitaxial layer being of a first conductivity type, a plurality of cells and a plurality of trenches arranged between adjacent two of the cells on a side of the first epitaxial layer away from the surface of the substrate, a gate oxide layer comprising a first gate oxide layer arranged on an outer sidewall of the trench and a second gate oxide layer arranged on an outer bottom wall of the trench, and a shielding layer arranged between the gate oxide layer on the outer bottom wall of the trench and the first epitaxial layer, the shielding layer being of a second conductivity type. The trench gate semiconductor device further comprises a second epitaxial layer arranged on a side of the cell away from the surface of the substrate and covering the plurality of cells, the second epitaxial layer being formed from the unoxidized part of the pre-prepared epitaxial layer. The trench gate semiconductor device further comprises a first doped region in the second epitaxial layer, the first doped region being a heavily doped region and being of the second conductivity type. The trench gate semiconductor device further comprises an ohmic contact layer arranged between the source region and the source electrode layer, the ohmic contact layer being electrically connected to the source region and the source electrode layer. The trench gate semiconductor device further comprises a source region in the cell, and a gate electrode layer, an interlayer dielectric layer and a source electrode layer, the gate electrode layer being arranged in the trench and being insulated from the first epitaxial layer by the gate oxide layer, the interlayer dielectric layer covering the gate electrode layer, and the source electrode layer being arranged on a side of the interlayer dielectric layer away from the substrate and being insulated from the gate electrode layer by the interlayer dielectric layer. The source electrode layer is electrically connected to the source region through a side surface of the source region away from the substrate. The source electrode layer is electrically connected to the source region through a side surface of the source region close to the trench, a part of the side surface of the source region being exposed in the trench to form an exposed surface, and the source electrode layer partially extends into the trench to form an extension part, the extension part being electrically connected to the exposed surface.

2. The trench gate semiconductor device according to claim 1, wherein The cell further comprises a second doped region between the source regions, the second doped region being of the second conductivity type.

3. The trench gate semiconductor device according to claim 2, wherein The trench gate semiconductor device further comprises an ohmic contact layer arranged between the source region and the source electrode layer, the ohmic contact layer being electrically connected to the source region and the source electrode layer.

4. The trench gate semiconductor device according to claim 1, wherein The corner in the trench is a rounded corner or a right angle. The trench gate semiconductor device comprises a substrate, a first epitaxial layer arranged on a surface 5. The trench gate semiconductor device according to claim 4, wherein ​ 6. The trench gate semiconductor device according to claim 1, wherein ​ 7. The trench gate semiconductor device according to Claim 1, wherein ​ ​ ​ ​ ​ 8. The trench gate semiconductor device according to Claim 7, wherein ​ ​ ​ 9. The trench gate semiconductor device according to Claim 1, wherein ​ 10. A method of manufacturing a trench gate semiconductor device, characterized by, ​ forming a first epitaxial layer on a substrate; the substrate and the first epitaxial layer are of a first conductivity type; doping and trenching a surface of the first epitaxial layer away from the substrate to form a plurality of cells and a groove between two adjacent cells; growing a pre-epitaxial layer in the groove; a surface of the pre-epitaxial layer has a roughness less than 0.2 nm, and the pre-epitaxial layer is of a second conductivity type; performing an oxidation treatment on the surface of the pre-epitaxial layer, a portion of the pre-epitaxial layer along a sidewall of the groove is oxidized to form a first gate oxide layer, a portion of the pre-epitaxial layer along a bottom wall of the groove is oxidized to form a second gate oxide layer, and a portion of the pre-epitaxial layer along the bottom wall of the groove is not oxidized to form a shielding layer; the first gate oxide layer and the second gate oxide layer form a trench, the shielding layer is on the bottom wall of the groove, and is between the gate oxide layer and the first epitaxial layer.

11. The method of claim 10, wherein: the step of growing the pre-epitaxial layer in the groove comprises: growing the pre-epitaxial layer in the groove, and causing a growth rate of the pre-epitaxial layer on the bottom wall of the groove to be greater than a growth rate of the pre-epitaxial layer on the sidewall of the groove; the step of performing the oxidation treatment on the surface of the pre-epitaxial layer, a portion of the pre-epitaxial layer along the sidewall of the groove is oxidized to form the first gate oxide layer, and a portion of the pre-epitaxial layer along the bottom of the groove is oxidized to form the second gate oxide layer, comprises: performing the oxidation treatment on the surface of the pre-epitaxial layer, a portion of the pre-epitaxial layer along the sidewall of the groove is entirely oxidized to form the first gate oxide layer, a portion of the pre-epitaxial layer along the bottom of the groove is oxidized to form the second gate, and a portion of the pre-epitaxial layer along the bottom wall of the trench is not oxidized to form the shielding layer; the shielding layer has a thickness of 100 nm to 600 nm, and the gate oxide layer has a thickness of 5 nm to 30 nm.

12. The method of claim 10, wherein: the step of growing the pre-epitaxy layer in the groove further comprises: growing a plurality of pre-epitaxy semiconductor sub-layers in the groove in sequence, each of the pre-epitaxy semiconductor sub-layers has a uniformity less than 6%.

13. The method of producing a trench-gate semiconductor device according to claim 10, wherein the step of growing the pre-epitaxy layer in the trench comprises: growing the pre-epitaxy layer in the trench and on the surface of the cell away from the substrate, and the pre-epitaxy layer outside the trench is configured as a second epitaxial layer.

14. The method of producing a trench gate semiconductor device according to Claim 13, wherein the step of growing the pre-epitaxy layer in the trench further comprises: etching away the second epitaxial layer.

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