Shift register, gate driving circuit, display panel, and display apparatus

Abstract

The present disclosure provides a shift register, a gate driving circuit, a display panel, and a display apparatus. The shift register comprises: a first node, a first node control circuit, and a first output circuit. The first node control circuit is separately coupled to a start signal input end, a first second level signal input end, and the first node, and is used for controlling, under the control of a start signal inputted at the start signal input end, an electrical connection between the first second level signal input end and the first node to be connected or disconnected. The first output circuit is separately coupled to the first node, a second second level signal input end, and a gate driving signal output end of the shift register, and is used for controlling, under the control of the potential of the first node, an electrical connection between the second second level signal input end and the gate driving signal output end to be connected or disconnected.

Description

Shift register, gate drive circuit, display panel and display device Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a shift register, a gate driving circuit, a display panel, and a display device. Background Technology

[0002] With the continuous development of display technology, the application fields of display products are becoming increasingly widespread. In order to better achieve narrow bezels in display products, related technologies integrate the gate driving circuit onto the display panel. This gate driving circuit scans the multiple rows of sub-pixels included in the display panel line by line, thereby realizing the display function of the display panel. Summary of the Invention

[0003] The purpose of this disclosure is to provide a shift register, a gate drive circuit, a display panel, and a display device.

[0004] To achieve the above objectives, this disclosure provides the following technical solution:

[0005] A first aspect of this disclosure provides a shift register, including: a first node, a first node control circuit, and a first output circuit;

[0006] The first node control circuit is coupled to the start signal input terminal, the first second level signal input terminal and the first node respectively, and is used to control the electrical connection between the first second level signal input terminal and the first node to be turned on or off under the control of the start signal input at the start signal input terminal;

[0007] The first output circuit is coupled to the first node, the second second-level signal input terminal, and the gate drive signal output terminal of the shift register, respectively, and is used to control the electrical connection between the second second-level signal input terminal and the gate drive signal output terminal to be turned on or off under the control of the potential of the first node.

[0008] Optionally, the voltage value of the second-level signal input at the first second-level signal input terminal is greater than the voltage value of the second-level signal input at the second second-level signal input terminal.

[0009] Optionally, the shift register further includes a second node, an input circuit, and a second output circuit;

[0010] The input circuit is coupled to the start signal input terminal and the second node respectively, and is used to control the electrical connection between the start signal input terminal and the second node to be turned on or off under the control of the start signal input at the start signal input terminal;

[0011] The second output circuit is coupled to the second node, the first clock signal input terminal and the gate drive signal output terminal respectively, and is used to control the electrical connection between the first clock signal input terminal and the gate drive signal output terminal to be turned on or off under the control of the potential of the second node.

[0012] Optionally, the first node control circuit includes a first transistor, the gate of the first transistor being coupled to the start signal input terminal, the first electrode of the first transistor being coupled to a first second level signal input terminal, and the second electrode of the first transistor being coupled to the first node.

[0013] The first output circuit includes a seventh transistor and a first capacitor. The gate of the seventh transistor is coupled to the first node, the first electrode of the seventh transistor is coupled to the second second-level signal input terminal, and the second electrode of the seventh transistor is coupled to the gate drive signal output terminal. The first plate of the first capacitor is coupled to the first node, and the second plate of the first capacitor is coupled to the second second-level signal input terminal.

[0014] The input circuit includes a second transistor, the gate of which is coupled to the start signal input terminal, the first terminal of which is coupled to the start signal input terminal, and the second terminal of which is coupled to the second node;

[0015] The second output circuit includes a sixth transistor and a second capacitor. The gate of the sixth transistor is coupled to the second node, the first terminal of the sixth transistor is coupled to the first clock signal input terminal, and the second terminal of the sixth transistor is coupled to the gate drive signal output terminal. The first plate of the second capacitor is coupled to the gate of the sixth transistor, and the second plate of the second capacitor is coupled to the gate drive signal output terminal.

[0016] Optionally, the first node control circuit is also coupled to the first level signal input terminal and the second clock signal input terminal respectively, and is used to control the electrical connection between the first level signal input terminal and the first node to be turned on or off under the control of the second clock signal input at the second clock signal input terminal;

[0017] The shift register further includes: a coupling circuit, a second node control circuit, a third node, and a third node control circuit;

[0018] The coupling circuit is coupled to the second node and the third node respectively, and is used to control the potential of the other of the second node and the third node according to the potential of one of the second node and the third node;

[0019] The second node control circuit is coupled to the second clock signal input terminal, the second node and the third node respectively, and is used to control the electrical connection between the second node and the third node to be turned on or off under the control of the second clock signal input to the second clock signal input terminal;

[0020] The third node control circuit is coupled to the first node, the first second-level signal input terminal and the third node respectively, and is used to control the electrical connection between the first second-level signal input terminal and the third node to be turned on or off according to the potential of the first node.

[0021] Optionally, the first node control circuit further includes a fourth transistor, the gate of which is coupled to the second clock signal input terminal, the first terminal of which is coupled to the first level signal input terminal, and the second terminal of which is coupled to the first node.

[0022] The coupling circuit includes a third capacitor, the first plate of which is coupled to the third node, and the second plate of which is coupled to the second node.

[0023] The second node control circuit includes a fifth transistor, the gate of which is coupled to the second clock signal input terminal, the first terminal of which is coupled to the third node, and the second terminal of which is coupled to the second node;

[0024] The third node control circuit includes a third transistor, the gate of which is coupled to the first node, the first terminal of which is coupled to the first second-level signal input terminal, and the second terminal of which is coupled to the third node.

[0025] Optionally, the first node control circuit is also coupled to a first first level signal input terminal and a second clock signal input terminal, respectively, for controlling the conduction or disconnection of the electrical connection between the first first level signal input terminal and the first node under the control of the second clock signal input terminal.

[0026] The shift register further includes: a coupling circuit, a second node control circuit, a third node, and a third node control circuit;

[0027] The coupling circuit is respectively coupled to the second first-level signal input terminal and the third node, and is used to control the potential of the other of the first first-level signal input terminal and the third node according to the potential of one of the first first-level signal input terminal and the third node;

[0028] The second node control circuit is coupled to the second clock signal input terminal, the second node and the third node respectively, and is used to control the electrical connection between the second node and the third node to be turned on or off under the control of the second clock signal input to the second clock signal input terminal;

[0029] The third node control circuit is coupled to the first node, the second second-level signal input terminal and the third node respectively, and is used to control the electrical connection between the second second-level signal input terminal and the third node to be turned on or off according to the potential of the first node.

[0030] Optionally, the voltage value of the first level signal input to the second first level signal input terminal is less than the voltage value of the first level signal input to the first first level signal input terminal.

[0031] Optionally, the first node control circuit further includes a fourth transistor, the gate of which is coupled to the second clock signal input terminal, the first terminal of which is coupled to the first first level signal input terminal, and the second terminal of which is coupled to the first node.

[0032] The coupling circuit includes a third capacitor, the first plate of which is coupled to the third node, and the second plate of which is coupled to the second first level signal input terminal.

[0033] The second node control circuit includes a fifth transistor, the gate of which is coupled to the second clock signal input terminal, the first terminal of which is coupled to the third node, and the second terminal of which is coupled to the second node;

[0034] The third node control circuit includes a third transistor, the gate of which is coupled to the first node, the first terminal of which is coupled to the second second-level signal input terminal, and the second terminal of which is coupled to the third node.

[0035] Optionally, the first node control circuit is also coupled to the first level signal input terminal and the second clock signal input terminal respectively, and is used to control the electrical connection between the first level signal input terminal and the first node to be turned on or off under the control of the second clock signal input at the second clock signal input terminal;

[0036] The shift register further includes: a transmission circuit, a third node, and a third node control circuit;

[0037] The transmission circuit is coupled to the first level signal input terminal, the second node and the third node respectively, and is used to control the conduction or disconnection of the electrical connection between the second node and the third node under the control of the first level signal input terminal.

[0038] The third node control circuit is coupled to the first node, the first second-level signal input terminal and the third node respectively, and is used to control the electrical connection between the first second-level signal input terminal and the third node to be turned on or off according to the potential of the first node;

[0039] The input circuit is coupled to the third node, and is coupled to the second node through the third node and the transmission circuit.

[0040] Optionally, the first node control circuit further includes a fourth transistor, the gate of which is coupled to the second clock signal input terminal, the first terminal of which is coupled to the first level signal input terminal, and the second terminal of which is coupled to the first node.

[0041] The transmission circuit includes a fifth transistor, the gate of which is coupled to the first level signal input terminal, the first terminal of which is coupled to the third node, and the second terminal of which is coupled to the second node;

[0042] The third node control circuit includes a third transistor, the gate of which is coupled to the first node, the first terminal of which is coupled to the first second-level signal input terminal, and the second terminal of which is coupled to the third node.

[0043] Optionally, the shift register further includes:

[0044] The third output circuit is coupled to the first node, the second second-level signal input terminal and the bias signal output terminal of the shift register respectively, and is used to control the electrical connection between the second second-level signal input terminal and the bias signal output terminal under the control of the potential of the first node.

[0045] The fourth output circuit is coupled to the second node, the bias clock signal input terminal and the bias signal output terminal respectively, and is used to control the electrical connection between the bias clock signal input terminal and the bias signal output terminal to be turned on or off under the control of the potential of the second node.

[0046] Optionally, the third output circuit includes a ninth transistor, the gate of which is coupled to the first node, the first terminal of which is coupled to the second second-level signal input terminal, and the second terminal of which is coupled to the bias signal output terminal.

[0047] The fourth output circuit includes an eighth transistor, the gate of which is coupled to the second node, the first terminal of which is coupled to the bias clock signal input terminal, and the second terminal of which is coupled to the bias signal output terminal.

[0048] Based on the above-described shift register technical solution, a second aspect of this disclosure provides a gate driving circuit, including multiple cascaded shift registers; the gate driving circuit further includes m1 ordinary clock signal lines, where m1 ≥ 3; the m1 ordinary clock signal lines provide effective voltage signals in a time-division multiplexing manner;

[0049] The first clock signal input terminal of the m1*n1+x1th shift register is coupled to the x1th ordinary clock signal line, 1≤x1≤m1, n1≥0;

[0050] When x1 < m1, the second clock signal input terminal of the m1*n1+x1th shift register is coupled to the x1+1th ordinary clock signal line;

[0051] When x1 = m1, the second clock signal input terminal of the m1*n1+x1th shift register is coupled to the first ordinary clock signal line.

[0052] Optionally, if the shift register includes a third output circuit and a fourth output circuit, the gate drive circuit further includes m2 bias clock signal lines, where m2 ≥ 3; the m2 bias clock signal lines provide effective voltage signals in a time-division multiplexing manner.

[0053] The bias clock signal input terminal of the m2*n2+x2th shift register is coupled to the x2th bias clock signal line, 1≤x2≤m2, n2≥0.

[0054] Based on the above-described gate driving circuit technical solution, a third aspect of this disclosure provides a display panel including the above-described gate driving circuit. The display panel further includes a plurality of sub-pixels, each sub-pixel including a sub-pixel driving circuit and a light-emitting element coupled together.

[0055] The gate drive signal output terminal of the shift register in the gate drive circuit is coupled to the gate of the target transistor in the corresponding sub-pixel drive circuit.

[0056] Optionally, the sub-pixel driving circuit includes a driving transistor, a compensation transistor, a fifth capacitor, and a sixth capacitor;

[0057] The first plate of the fifth capacitor is coupled to the gate of the driving transistor, the second plate of the fifth capacitor is coupled to the second terminal of the compensation transistor, and the first terminal of the compensation transistor is coupled to the second terminal of the driving transistor; the first plate of the sixth capacitor is coupled to the second plate of the fifth capacitor.

[0058] The bias signal output terminal of the shift register in the gate driving circuit is coupled to the second plate of the sixth capacitor in the corresponding sub-pixel driving circuit.

[0059] Optionally, the sub-pixel driving circuit further includes: a power control transistor, a light-emitting control transistor, a data writing transistor, a first reset transistor, a second reset transistor, a third reset transistor, a fourth reset transistor, and a fourth capacitor;

[0060] The gate of the power control transistor is coupled to the light emission control signal input terminal, the first terminal of the power control transistor is coupled to the power signal input terminal, and the second terminal of the power control transistor is coupled to the first terminal of the driving transistor.

[0061] The gate of the light-emitting control transistor is coupled to the light-emitting control signal input terminal, the first terminal of the light-emitting control transistor is coupled to the second terminal of the driving transistor, and the second terminal of the light-emitting control transistor is coupled to the anode of the light-emitting element.

[0062] The gate of the data writing transistor is coupled to the second scan signal input terminal, the first terminal of the data writing transistor is coupled to the data signal input terminal, and the second terminal of the data writing transistor is coupled to the second terminal of the driving transistor.

[0063] The gate of the first reset transistor is coupled to the first scan signal input terminal, the first terminal of the first reset transistor is coupled to the third initialization signal input terminal, and the second terminal of the first reset transistor is coupled to the second terminal of the driving transistor.

[0064] The gate of the second reset transistor is coupled to the fifth scan signal input terminal, the first terminal of the second reset transistor is coupled to the first initialization signal input terminal, and the second terminal of the second reset transistor is coupled to the first terminal of the driving transistor.

[0065] The gate of the third reset transistor is coupled to the third scan signal input terminal, the first terminal of the third reset transistor is coupled to the first initialization signal input terminal, and the second terminal of the third reset transistor is coupled to the gate of the driving transistor.

[0066] The gate of the fourth reset transistor is coupled to the fifth scan signal input terminal, the first terminal of the fourth reset transistor is coupled to the second initialization signal input terminal, and the second terminal of the fourth reset transistor is coupled to the anode of the light-emitting element.

[0067] The first plate of the fourth capacitor is coupled to the gate of the driving transistor, and the second plate of the fourth capacitor is coupled to the power signal input terminal.

[0068] Optionally, the ordinary clock signal line in the gate driving circuit extends along a first direction; the first transistor and the second transistor included in the shift register in the gate driving circuit are arranged along the first direction.

[0069] Optionally, the first transistor and / or the second transistor adopt a dual-gate transistor structure, wherein the channel portions of the first transistor and the channel portions of the second transistor are arranged sequentially along the first direction.

[0070] Optionally, the first transistor and the third transistor in the shift register are arranged along a second direction, which intersects with the first direction; the third transistor adopts a single-gate structure or a double-gate structure.

[0071] Optionally, the orthographic projection of the gate of the third transistor on the substrate of the display panel and the orthographic projection of the first plate of the third capacitor in the shift register on the substrate are aligned along a first direction.

[0072] Optionally, the fourth and fifth transistors in the shift register are both located on the side of the display panel closest to the third transistor.

[0073] Optionally, the third transistor and the fifth transistor in the shift register are arranged along a first direction, with the fifth transistor located on the side of the third transistor closer to the next-stage shift register.

[0074] Optionally, the fourth transistor in the shift register is located on the side of the display area of ​​the display panel closer to the third transistor.

[0075] Optionally, the seventh transistor and the sixth transistor in the shift register are arranged along a first direction;

[0076] The first capacitor in the shift register is located on the side of the seventh transistor closer to the display area of ​​the display panel;

[0077] The second capacitor in the shift register is located on the side of the sixth transistor closer to the display area.

[0078] Optionally, the channel width-to-length ratio of the sixth transistor is greater than that of the seventh transistor.

[0079] Based on the above-described display panel technical solution, the fourth aspect of this disclosure provides a display device including the above-described display panel. Attached Figure Description

[0080] The accompanying drawings, which are included to provide a further understanding of this disclosure and form part of this disclosure, illustrate exemplary embodiments of the present disclosure and are used to explain the disclosure, but do not constitute an undue limitation of the disclosure. In the drawings:

[0081] Figure 1 is a schematic diagram of a circuit structure of a shift register provided in an embodiment of this disclosure;

[0082] Figure 2 is the first driving timing diagram corresponding to the shift register structure in Figure 1;

[0083] Figure 3 is the second driving timing diagram corresponding to the shift register structure in Figure 1;

[0084] Figure 4 is a schematic diagram of the cascaded shift registers of the structure in Figure 1;

[0085] Figure 5 is a schematic diagram of a shift register module provided in an embodiment of this disclosure;

[0086] Figure 6 is a schematic diagram of the circuit structure corresponding to Figure 5;

[0087] Figure 7 shows a driving timing diagram corresponding to the shift register structure in Figure 6;

[0088] Figure 8 is a schematic diagram of a cascaded shift register provided in an embodiment of this disclosure;

[0089] Figure 9 shows a driving timing diagram corresponding to the shift register structure in Figure 6;

[0090] Figure 10 is a schematic diagram of a cascaded shift register provided in an embodiment of this disclosure;

[0091] Figure 11 shows a driving timing diagram for the shift register structure in Figure 6.

[0092] Figure 12 shows a driving timing diagram corresponding to the shift register structure in Figure 6;

[0093] Figure 13 is a schematic diagram of the output timing of the cascaded shift register provided in an embodiment of this disclosure;

[0094] Figure 14 is a schematic diagram of a shift register module provided in an embodiment of this disclosure;

[0095] Figure 15 is a schematic diagram of the circuit structure corresponding to Figure 14;

[0096] Figure 16 shows a driving timing diagram corresponding to the shift register structure in Figure 6;

[0097] Figure 17 is a schematic diagram of a shift register module provided in an embodiment of this disclosure;

[0098] Figure 18 is a schematic diagram of the circuit structure corresponding to Figure 17;

[0099] Figure 19 shows a driving timing diagram corresponding to the shift register structure in Figure 18;

[0100] Figure 20 is a schematic diagram of the circuit structure of the sub-pixel driving circuit provided in an embodiment of this disclosure;

[0101] Figure 21 is a driving timing diagram corresponding to the sub-pixel driving circuit of the structure in Figure 20;

[0102] Figure 22 is a driving timing diagram corresponding to the sub-pixel driving circuit of the structure in Figure 20;

[0103] Figures 23-29 are schematic diagrams of the layout of the shift register corresponding to the structure in Figure 18;

[0104] Figures 30-36 are schematic diagrams of the layout of the shift register corresponding to the structure in Figure 6;

[0105] Figure 37 is a schematic diagram of the layout of four cascaded shift registers provided in an embodiment of this disclosure;

[0106] Figure 38 is a schematic diagram of a shift register module provided in an embodiment of this disclosure;

[0107] Figure 39 is a schematic diagram of a shift register module provided in an embodiment of this disclosure;

[0108] Figure 40 is a schematic diagram of a shift register module provided in an embodiment of this disclosure;

[0109] Figure 41 is a schematic diagram of the circuit structure corresponding to Figure 40;

[0110] Figure 42 is a schematic diagram of a shift register module provided in an embodiment of this disclosure;

[0111] Figure 43 is a schematic diagram of the circuit structure corresponding to Figure 42. Detailed Implementation

[0112] To further illustrate the shift register, gate drive circuit, display panel, and display device provided in the embodiments of this disclosure, a detailed description is provided below with reference to the accompanying drawings.

[0113] When scanning sub-pixels, the shift register included in the gate drive circuit needs to control the conduction of the valid output transistors in the shift register to control the output of the scan signal at the gate drive signal output terminal. Simultaneously, it needs to control the cut-off of the invalid output transistors in the shift register to avoid affecting the signal output at the gate drive signal output terminal. However, in related technologies, the shift register suffers from insufficient cut-off of invalid output transistors during actual operation, which affects the signal output at the gate drive signal output terminal.

[0114] Please refer to Figures 5, 14, 17 and 38. This disclosure provides a shift register, including: a first node N1, a first node control circuit 10 and a first output circuit 11;

[0115] The first node control circuit 10 is coupled to the start signal input terminal GSTV, the first second level signal input terminal VGH1 and the first node N1 respectively, and is used to control the electrical connection between the first second level signal input terminal VGH1 and the first node N1 to be turned on or off under the control of the start signal input at the start signal input terminal GSTV.

[0116] The first output circuit 11 is coupled to the first node N1, the second second level signal input terminal VGH2 and the gate drive signal output terminal Gout of the shift register, respectively, and is used to control the conduction or disconnection of the electrical connection between the second second level signal input terminal VGH2 and the gate drive signal output terminal Gout under the control of the potential of the first node N1.

[0117] For example, the first node control circuit 10 includes a first transistor T1, the gate of the first transistor T1 is coupled to the start signal input terminal GSTV, the first terminal of the first transistor T1 is coupled to the first second level signal input terminal VGH1, and the second terminal of the first transistor T1 is coupled to the first node N1.

[0118] For example, the first output circuit 11 includes a seventh transistor T7 and a first capacitor C1. The gate of the seventh transistor T7 is coupled to the first node N1, the first terminal of the seventh transistor T7 is coupled to the second second-level signal input terminal VGH2, and the second terminal of the seventh transistor T7 is coupled to the gate drive signal output terminal Gout. The first plate of the first capacitor C1 is coupled to the first node N1, and the second plate of the first capacitor C1 is coupled to the second second-level signal input terminal VGH2.

[0119] For example, the start signal input terminal GSTV is used to input a start signal. When the shift register is applied to the gate drive circuit, the gate drive circuit includes multiple cascaded shift registers. The start signal input terminal GSTV of the first stage or several stages of the multiple shift registers can be coupled to the corresponding start signal line. The start signal input terminal GSTV of other shift registers can be coupled to the gate drive signal output terminal Gout of the adjacent previous stage or several stages of the shift register.

[0120] For example, both the second-level signal input at the first second-level signal input terminal VGH1 and the second-level signal input at the second second-level signal input terminal VGH2 are high-level signals. The voltage value of the second-level signal input at the first second-level signal input terminal VGH1 is greater than the voltage value of the second-level signal input at the second second-level signal input terminal VGH2.

[0121] According to the specific structure of the shift register described above, in the shift register provided in this embodiment, the first node control circuit 10 can control the potential of the first node N1 to be the same as the potential of the second level signal input at the first second level signal input terminal VGH1 by connecting the electrical connection between the first second level signal input terminal VGH1 and the first node N1; the first output circuit 11 can disconnect the electrical connection between the second second level signal input terminal VGH2 and the gate drive signal output terminal Gout under the potential control of the first node N1, so that the potential output by the gate drive signal output terminal Gout is not affected by the first output circuit 11.

[0122] Because the first second-level signal input terminal VGH1 and the second second-level signal input terminal VGH2 are set to be independent of each other, the second-level signals input to the first second-level signal input terminal VGH1 and the second second-level signal input terminal VGH2 can be controlled independently. In this way, by setting the second-level signal input to the first second-level signal input terminal VGH1 to have a larger voltage value, the potential of the first node N1 can be made to have a larger voltage value, thereby better controlling the transistors included in the first output circuit 11 to be fully turned off, and completely disconnecting the electrical connection between the second second-level signal input terminal VGH2 and the gate drive signal output terminal Gout.

[0123] Therefore, in the shift register provided in this embodiment, when the transistor included in the first output circuit 11 is used as an invalid output transistor, it can ensure that the invalid output transistor is fully turned off, thereby avoiding any impact on the signal output by the gate drive signal output terminal Gout.

[0124] More specifically, by setting the voltage value of the second-level signal input at the first second-level signal input terminal VGH1 to be greater than the voltage value of the second-level signal input at the second second-level signal input terminal VGH2, it can be ensured that the gate-source voltage Vgs of the seventh transistor T7 is greater than 0, so that the seventh transistor T7 can be fully turned off, ensuring that the output integrity of the effective output transistor (such as the sixth transistor T6) is not affected.

[0125] Please refer to Figures 5, 14 and 17. In some embodiments, the shift register further includes a second node N2, an input circuit 12 and a second output circuit 13.

[0126] The input circuit 12 is coupled to the start signal input terminal GSTV and the second node N2 respectively, and is used to control the electrical connection between the start signal input terminal GSTV and the second node N2 to be turned on or off under the control of the start signal input at the start signal input terminal GSTV.

[0127] The second output circuit 13 is coupled to the second node N2, the first clock signal input terminal CK1 and the gate drive signal output terminal Gout respectively, and is used to control the electrical connection between the first clock signal input terminal CK1 and the gate drive signal output terminal Gout under the control of the potential of the second node N2.

[0128] For example, the input circuit 12 includes a second transistor T2, the gate of the second transistor T2 is coupled to the start signal input terminal GSTV, the first terminal of the second transistor T2 is coupled to the start signal input terminal GSTV, and the second terminal of the second transistor T2 is coupled to the second node N2.

[0129] The second output circuit 13 includes a sixth transistor T6 and a second capacitor C2. The gate of the sixth transistor T6 is coupled to the second node N2, the first terminal of the sixth transistor T6 is coupled to the first clock signal input terminal CK1, and the second terminal of the sixth transistor T6 is coupled to the gate drive signal output terminal Gout. The first plate of the second capacitor C2 is coupled to the gate of the sixth transistor T6, and the second plate of the second capacitor C2 is coupled to the gate drive signal output terminal Gout.

[0130] More specifically, the input circuit 12, under the control of the start signal input at the start signal input terminal GSTV, controls whether to write the start signal to the second node N2, thereby controlling the potential of the second node N2. The potential of the second node N2 can control the operating state of the second output circuit 13. When the second output circuit 13 controls the electrical connection between the first clock signal input terminal CK1 and the gate drive signal output terminal Gout, the first clock signal input at the first clock signal input terminal CK1 is transmitted to the gate drive signal output terminal Gout, and the gate drive signal output terminal Gout is controlled to output the first clock signal.

[0131] For example, the gate and first terminal of the second transistor T2 are both coupled to the start signal input terminal GSTV, and the second terminal of the second transistor T2 is coupled to the second node N2, so that the second transistor T2 is formed as a diode structure. This diode structure can not only ensure that the start signal is transmitted to the second node N2 to control the potential of the second node N2, but also help the potential stability of the second node N2 and avoid adverse effects on the potential of the second node N2 when the start signal is at an invalid level (i.e. when the second transistor T2 is turned off).

[0132] In the shift register provided in the above embodiments, by setting the input circuit 12, the second output circuit 13, the first output circuit 11 and the first node control circuit 10, not only is the normal output function of the shift register realized, but also the first node N1 and the second node N2 have good potential stability at different time periods, which greatly improves the working performance of the shift register.

[0133] As shown in Figures 5 and 6, in some embodiments, the first node control circuit 10 is also coupled to the first level signal input terminal VGL and the second clock signal input terminal CK2, respectively, and is used to control the conduction or disconnection of the electrical connection between the first level signal input terminal VGL and the first node N1 under the control of the second clock signal input to the second clock signal input terminal CK2.

[0134] The shift register further includes: a coupling circuit 14, a second node control circuit 15, a third node N3, and a third node control circuit 16;

[0135] The coupling circuit 14 is coupled to the second node N2 and the third node N3 respectively, and is used to control the potential of the other of the second node N2 and the third node N3 according to the potential of one of the second node N2 and the third node N3;

[0136] The second node control circuit 15 is coupled to the second clock signal input terminal CK2, the second node N2 and the third node N3 respectively, and is used to control the conduction or disconnection of the electrical connection between the second node N2 and the third node N3 under the control of the second clock signal input to the second clock signal input terminal CK2.

[0137] The third node control circuit 16 is coupled to the first node N1, the first second-level signal input terminal VGH1 and the third node N3 respectively, and is used to control the electrical connection between the first second-level signal input terminal VGH1 and the third node N3 to be turned on or off according to the potential of the first node N1.

[0138] For example, the first node control circuit 10 further includes a fourth transistor T4, the gate of which is coupled to the second clock signal input terminal CK2, the first terminal of which is coupled to the first level signal input terminal VGL, and the second terminal of which is coupled to the first node N1.

[0139] The coupling circuit 14 includes a third capacitor C3, the first plate of the third capacitor C3 is coupled to the third node N3, and the second plate of the third capacitor C3 is coupled to the second node N2.

[0140] The second node control circuit 15 includes a fifth transistor T5, the gate of which is coupled to the second clock signal input terminal CK2, the first terminal of which is coupled to the third node N3, and the second terminal of which is coupled to the second node N2.

[0141] The third node control circuit 16 includes a third transistor T3, the gate of which is coupled to the first node N1, the first terminal of which is coupled to the first second level signal input terminal VGH1, and the second terminal of which is coupled to the third node N3.

[0142] With the shift register configured as described above, in stages t1 and t2, the third node N3 is potential-coupled to the second node N2 through the third capacitor C3, avoiding leakage caused by insufficient shutdown of the fifth transistor T5, avoiding affecting the potential stability of the second node N2, thereby avoiding affecting the output effect of the sixth transistor T6, and increasing the threshold voltage offset margin of the fifth transistor T5.

[0143] As shown in Figures 11 and 12, when the shift register adopts the above structure, its operation process is as follows:

[0144] In stage t1: The start signal input at the start signal input terminal GSTV is at a low level, controlling the first transistor T1 and the second transistor T2 to turn on. The second level signal input at the first second level signal input terminal VGH1 charges the first node N1 to a high potential through the first transistor T1, pulling the potential of the first node N1 high. At the same time, the second transistor T2 turns on. The low potential start signal input at the start signal input terminal GSTV charges the second node N2 to a low potential, lowering the potential of the second node N2. At this time, the second clock signal input at the second clock signal input terminal CK2 controls the fourth transistor T4 and the fifth transistor T5 to turn off. The high potential of the first node N1 controls the third transistor T3 and the seventh transistor T7 to turn off. The low potential charged into the second node N2 controls the sixth transistor T6 to turn on.

[0145] In stage t2: The start signal input at the start signal input terminal GSTV is at a high level, controlling the first transistor T1 and the second transistor T2 to turn off. The second clock signal is at a high level, controlling the third transistor T3, the fourth transistor T4, and the fifth transistor T5 to turn off. The first node N1 maintains a high potential of 1H. The second node N2 controls the sixth transistor T6 to turn on. The first clock signal input at the first clock signal input terminal CK1 is at a low potential, completing the low-potential bootstrapping of the second node N2 through the second capacitor C2, ensuring that the sixth transistor T6 is fully turned on. The first clock signal input at the first clock signal input terminal CK1 completes the low-potential scan output. During this process, the potential change of the second node N2 affects the third node N3 through the coupling of the third capacitor C3. It should be noted that 1H is the scan time of one line of sub-pixels.

[0146] In phase t3: The start signal input at the start signal input terminal GSTV remains high, and the first transistor T1 and the second transistor T2 remain off. At this time, the second clock signal controls the fourth transistor T4 and the fifth transistor T5 to turn on. The first level signal input at the first level signal input terminal VGL charges the first node N1 to a low potential through the fourth transistor T4. The first node N1 controls the seventh transistor T7 to turn on, and the gate drive signal output terminal Gout outputs the second level signal input at the second second level signal input terminal VGH2. Simultaneously, the third transistor T3 and the fifth transistor T5 turn on, and the second level signal input at the first second level signal input terminal is written to the second node N2, making the second node N2 high potential and controlling the sixth transistor T6 to turn off. The gate drive signal output terminal Gout completes one scan output.

[0147] In stage t1, the second-level signal input at the first second-level signal input terminal VGH1 is written into the first node N1. In stage t2, the first node N1 maintains the potential of the second-level signal input at the first second-level signal input terminal VGH1. Setting the voltage value of the second-level signal input at the first second-level signal input terminal VGH1 to be greater than the voltage value of the second-level signal input at the second second-level signal input terminal VGH2 ensures that the gate-source voltage of the seventh transistor T7 is greater than 0, allowing the seventh transistor T7 to be fully turned off, thus ensuring the complete output of the sixth transistor T6 without being affected. Simultaneously, in stage t3, the second-level signal input at the first second-level signal input terminal VGH1 has a higher potential, ensuring that the sixth transistor T6 is fully turned off, avoiding abnormal turn-on output pulses of the sixth transistor T6 caused by threshold voltage bias. Therefore, the above configuration increases the threshold voltage margin of the shift register, effectively reducing power consumption.

[0148] When multiple shift registers are cascaded to form a gate driving circuit, the gate driving circuit includes m1 ordinary clock signal lines, where m1 ≥ 3; the m1 ordinary clock signal lines provide effective voltage signals in a time-division multiplexing manner; the first clock signal input terminal CK1 of the m1*n1+x1th shift register is coupled to the x1th ordinary clock signal line, where 1 ≤ x1 ≤ m1, and n1 ≥ 0; when x1 < m1, the second clock signal input terminal CK2 of the m1*n1+x1th shift register is coupled to the x1+1th ordinary clock signal line; when x1 = m1, the second clock signal input terminal CK2 of the m1*n1+x1th shift register is coupled to the first ordinary clock signal line.

[0149] Taking a gate drive circuit with three ordinary clock signal lines as an example, as shown in Figures 7 and 8, the first clock signal input terminal CK1 of the first shift register Gate GOA1 is coupled to the first ordinary clock signal line CK1', and the second clock signal input terminal CK2 of the first shift register Gate GOA1 is coupled to the second ordinary clock signal line CK2'; the first clock signal input terminal CK1 of the second shift register Gate GOA2 is coupled to the second ordinary clock signal line CK2', and the second clock signal input terminal CK2 of the second shift register Gate GOA2 is coupled to the third ordinary clock signal line CK3'; the first clock signal input terminal CK1 of the third shift register Gate GOA3 is coupled to the third ordinary clock signal line CK3', and the second clock signal input terminal CK2 of the third shift register Gate GOA3 is coupled to the first ordinary clock signal line CK1'; the first clock signal input terminal CK1 of the fourth shift register Gate GOA4 is coupled to the first ordinary clock signal line CK1', and the fourth shift register Gate GOA4 is coupled to the first ordinary clock signal line CK1'. The second clock signal input terminal CK2, coupled to GOA4, is coupled to the second ordinary clock signal line CK2'.

[0150] Figure 13 illustrates the gate drive signal output terminal GO of a multi-stage shift register. <1> GO <2> GO <3> GO <4> GO <5> A timing diagram of the corresponding output gate drive signal.

[0151] Taking a gate drive circuit with four ordinary clock signal lines as an example, as shown in Figures 9 and 10, the first clock signal input terminal CK1 of the first shift register Gate GOA1 is coupled to the first ordinary clock signal line CK1', and the second clock signal input terminal CK2 of the first shift register Gate GOA1 is coupled to the second ordinary clock signal line CK2'; the first clock signal input terminal CK1 of the second shift register Gate GOA2 is coupled to the second ordinary clock signal line CK2', and the second clock signal input terminal CK2 of the second shift register Gate GOA2 is coupled to the third ordinary clock signal line CK3'; the first clock signal input terminal CK1 of the third shift register Gate GOA3 is coupled to the third ordinary clock signal line CK3', and the second clock signal input terminal CK2 of the third shift register Gate GOA3 is coupled to the fourth ordinary clock signal line CK4'; the fourth shift register Gate GOA3... The first clock signal input terminal CK1 of GOA4 is coupled to the fourth ordinary clock signal line CK4', and the second clock signal input terminal CK2 of the fourth shift register Gate GOA4 is coupled to the first ordinary clock signal line CK1'.

[0152] As shown in Figures 14 to 16, in some embodiments, the first node control circuit 10 is also coupled to the first first level signal input terminal VGL1 and the second clock signal input terminal CK2, respectively, for controlling the conduction or disconnection of the electrical connection between the first first level signal input terminal VGL1 and the first node N1 under the control of the second clock signal input terminal CK2.

[0153] The shift register further includes: a coupling circuit 14, a second node control circuit 15, a third node N3, and a third node control circuit 16;

[0154] The coupling circuit 14 is coupled to the second first level signal input terminal VGL2 and the third node N3 respectively, and is used to control the potential of the other of the first first level signal input terminal VGL1 and the third node N3 according to the potential of one of the first first level signal input terminal VGL1 and the third node N3;

[0155] The second node control circuit 15 is coupled to the second clock signal input terminal CK2, the second node N2 and the third node N3 respectively, and is used to control the conduction or disconnection of the electrical connection between the second node N2 and the third node N3 under the control of the second clock signal input to the second clock signal input terminal CK2.

[0156] The third node control circuit 16 is coupled to the first node N1, the second second level signal input terminal VGH2 and the third node N3 respectively, and is used to control the electrical connection between the second second level signal input terminal VGH2 and the third node N3 to be turned on or off according to the potential of the first node N1.

[0157] For example, the voltage value of the first-level signal input at the second first-level signal input terminal VGL2 is less than the voltage value of the first-level signal input at the first first-level signal input terminal VGL1. Both the first-level signal input at the first first-level signal input terminal VGL1 and the first-level signal input at the second first-level signal input terminal VGL2 are low-level signals.

[0158] For example, the first node control circuit 10 further includes a fourth transistor T4, the gate of which is coupled to the second clock signal input terminal CK2, the first terminal of which is coupled to the first first level signal input terminal VGL1, and the second terminal of which is coupled to the first node N1.

[0159] The coupling circuit 14 includes a third capacitor C3, the first plate of the third capacitor C3 is coupled to the third node N3, and the second plate of the third capacitor C3 is coupled to the second first level signal input terminal VGL2.

[0160] The second node control circuit 15 includes a fifth transistor T5, the gate of which is coupled to the second clock signal input terminal CK2, the first terminal of which is coupled to the third node N3, and the second terminal of which is coupled to the second node N2.

[0161] The third node control circuit 16 includes a third transistor T3, the gate of which is coupled to the first node N1, the first terminal of which is coupled to the second second level signal input terminal VGH2, and the second terminal of which is coupled to the third node N3.

[0162] By configuring the shift register with the above structure, the first-level signal with a lower potential input to the second first-level signal input terminal VGL2 can better stabilize the plate potential of the third capacitor C3, which is beneficial to further reduce the power consumption of the shift register.

[0163] As shown in Figures 14 to 16, when the shift register adopts the above structure, its operation process is as follows:

[0164] In stage t1: The start signal input at the start signal input terminal GSTV is at a low level, controlling the first transistor T1 and the second transistor T2 to turn on. The second level signal input at the first second level signal input terminal VGH1 charges the first node N1 to a high potential through the first transistor T1, pulling the potential of the first node N1 high. At the same time, the second transistor T2 turns on. The low potential start signal input at the start signal input terminal GSTV charges the second node N2 to a low potential, lowering the potential of the second node N2. At this time, the second clock signal input at the second clock signal input terminal CK2 controls the fourth transistor T4 and the fifth transistor T5 to turn off. The high potential of the first node N1 controls the third transistor T3 and the seventh transistor T7 to turn off. The low potential charged into the second node N2 controls the sixth transistor T6 to turn on.

[0165] In stage t2: The start signal input at the start signal input terminal GSTV is at a high level, controlling the first transistor T1 and the second transistor T2 to turn off. The second clock signal is at a high level, controlling the third transistor T3, the fourth transistor T4 and the fifth transistor T5 to turn off. The first node N1 maintains a high potential of 1H. The second node N2 controls the sixth transistor T6 to turn on. The first clock signal input at the first clock signal input terminal CK1 is at a low potential, and the second node N2 completes the low potential bootstrapping through the second capacitor C2, ensuring that the sixth transistor T6 is fully turned on. The first clock signal input at the first clock signal input terminal CK1 completes the low potential scan output. During this process, the potential change of the second node N2 affects the third node N3 through the coupling of the third capacitor C3.

[0166] In phase t3: The start signal input at the start signal input terminal GSTV remains at a high potential, and the first transistor T1 and the second transistor T2 remain off. At this time, the second clock signal controls the fourth transistor T4 and the fifth transistor T5 to turn on. The first level signal input at the first level signal input terminal VGL1 charges the first node N1 to a low potential through the fourth transistor T4. The first node N1 controls the seventh transistor T7 to turn on, and the gate drive signal output terminal Gout outputs the second level signal input at the second level signal input terminal VGH2. Simultaneously, the third transistor T3 and the fifth transistor T5 turn on, and the second level signal input at the second level signal input terminal VGH2 is written to the second node N2, making the second node N2 high potential, controlling the sixth transistor T6 to turn off, and the gate drive signal output terminal Gout completes one scan output.

[0167] By configuring the shift register with the above structure, the third node N3 can always maintain a high potential, which better stabilizes the plate potential of the third capacitor C3 and helps to reduce the power consumption of the shift register.

[0168] When multiple shift registers are cascaded to form a gate driving circuit, the gate driving circuit includes m1 ordinary clock signal lines, where m1 ≥ 3; the m1 ordinary clock signal lines provide effective voltage signals in a time-division multiplexing manner; the first clock signal input terminal CK1 of the m1*n1+x1th shift register is coupled to the x1th ordinary clock signal line, where 1 ≤ x1 ≤ m1, and n1 ≥ 0; when x1 < m1, the second clock signal input terminal CK2 of the m1*n1+x1th shift register is coupled to the x1+1th ordinary clock signal line; when x1 = m1, the second clock signal input terminal CK2 of the m1*n1+x1th shift register is coupled to the first ordinary clock signal line.

[0169] As shown in Figures 17 to 19, in some embodiments, the first node control circuit 10 is also coupled to the first level signal input terminal VGL and the second clock signal input terminal CK2, respectively, and is used to control the conduction or disconnection of the electrical connection between the first level signal input terminal VGL and the first node N1 under the control of the second clock signal input to the second clock signal input terminal CK2.

[0170] The shift register also includes: a transmission circuit 17, a third node N3, and a third node control circuit 16;

[0171] The transmission circuit 17 is coupled to the first level signal input terminal VGL, the second node N2 and the third node N3 respectively, and is used to control the conduction or disconnection of the electrical connection between the second node N2 and the third node N3 under the control of the first level signal input terminal VGL.

[0172] The third node control circuit 16 is coupled to the first node N1, the first second level signal input terminal VGH1 and the third node N3 respectively, and is used to control the electrical connection between the first second level signal input terminal VGH1 and the third node N3 to be turned on or off according to the potential of the first node N1.

[0173] The input circuit 12 is coupled to the third node N3, and is coupled to the second node N2 through the third node N3 and the transmission circuit 17.

[0174] For example, the first node control circuit 10 further includes a fourth transistor T4, the gate of which is coupled to the second clock signal input terminal CK2, the first terminal of which is coupled to the first level signal input terminal VGL, and the second terminal of which is coupled to the first node N1.

[0175] The transmission circuit 17 includes a fifth transistor T5, the gate of which is coupled to the first level signal input terminal VGL, the first terminal of which is coupled to the third node N3, and the second terminal of which is coupled to the second node N2.

[0176] The third node control circuit 16 includes a third transistor T3, the gate of which is coupled to the first node N1, the first terminal of which is coupled to the first second level signal input terminal VGH1, and the second terminal of which is coupled to the third node N3.

[0177] For example, the input circuit 12 is coupled to the third node N3, and is coupled to the second node N2 through the third node N3 and the fifth transistor T5.

[0178] When multiple shift registers are cascaded to form a gate driving circuit, the gate driving circuit includes m1 ordinary clock signal lines, where m1 ≥ 3; the m1 ordinary clock signal lines provide effective voltage signals in a time-division multiplexing manner; the first clock signal input terminal CK1 of the m1*n1+x1th shift register is coupled to the x1th ordinary clock signal line, where 1 ≤ x1 ≤ m1, and n1 ≥ 0; when x1 < m1, the second clock signal input terminal CK2 of the m1*n1+x1th shift register is coupled to the x1+1th ordinary clock signal line; when x1 = m1, the second clock signal input terminal CK2 of the m1*n1+x1th shift register is coupled to the first ordinary clock signal line.

[0179] By adopting the above structure for the shift register, after the second node N2 bootstraps in stage t2, there is a smaller Vds cross-voltage (i.e., the source-drain cross-voltage of the fifth transistor T5) between the third node N3 and the second node N2. This allows the third node N3 to act as a buffered low potential, reducing leakage current to the second transistor T2 and the third transistor T3. In the above shift register, the first second-level signal input terminal VGH1 can be directly connected to the third node N3 through the third transistor T3. Since the period when the first node N1 is at a high level is 2H in width, it does not affect the charging of the third node N3 and the second node N2 to a low potential before bootstrap. It should be noted that functionally, the fifth transistor T5 can be removed, but the leakage current to the second transistor T2 and the third transistor T3 will increase.

[0180] As shown in Figures 1 to 4 and Figures 39 to 43, in some embodiments, the shift register further includes:

[0181] The third output circuit 18 is coupled to the first node N1, the second second level signal input terminal VGH2 and the bias signal output terminal COBS of the shift register, respectively, and is used to control the conduction or disconnection of the electrical connection between the second second level signal input terminal VGH2 and the bias signal output terminal COBS under the control of the potential of the first node N1.

[0182] The fourth output circuit 19 is coupled to the second node N2, the bias clock signal input terminal OBCK and the bias signal output terminal COBS respectively, and is used to control the electrical connection between the bias clock signal input terminal OBCK and the bias signal output terminal COBS under the control of the potential of the second node N2.

[0183] For example, the third output circuit 18 includes a ninth transistor T9, the gate of which is coupled to the first node N1, the first terminal of which is coupled to the second second level signal input terminal VGH2, and the second terminal of which is coupled to the bias signal output terminal COBS.

[0184] The fourth output circuit 19 includes an eighth transistor T8, the gate of which is coupled to the second node N2, the first terminal of which is coupled to the bias clock signal input terminal OBCK, and the second terminal of which is coupled to the bias signal output terminal COBS.

[0185] In stage t1: The start signal input at the start signal input terminal GSTV is at a low level, controlling the first transistor T1 and the second transistor T2 to turn on. The second level signal input at the first second level signal input terminal VGH1 charges the first node N1 to a high potential through the first transistor T1, pulling the potential of the first node N1 high. At the same time, the second transistor T2 turns on. The low potential start signal input at the start signal input terminal GSTV charges the second node N2 to a low potential, lowering the potential of the second node N2. At this time, the second clock signal input at the second clock signal input terminal CK2 controls the fourth transistor T4 and the fifth transistor T5 to turn off. The high potential of the first node N1 controls the third transistor T3, the seventh transistor T7 and the ninth transistor T9 to turn off, and the sixth transistor T6 and the eighth transistor T8 to turn on.

[0186] In stage t2: The start signal input at the start signal input terminal GSTV is at a high level, controlling the first transistor T1 and the second transistor T2 to turn off. The second clock signal is at a high level, controlling the fourth transistor T4 and the fifth transistor T5 to turn off. The first node N1 remains at a high potential. The second node N2 is at a low potential, controlling the sixth transistor T6 and the eighth transistor T8 to turn on. The first clock signal input at the first clock signal input terminal CK1 is at a low potential, and the second node N2 is bootstrapping through the second capacitor C2 to complete the low-potential bootstrapping of the second node N2. The bootstrapping turn-on potential of the second node N2 controls the eighth transistor T8 to turn on, and ensures that the sixth transistor T6 and the eighth transistor T8 are fully turned on. The gate drive signal output terminal Gout completes the low-potential scan output, and the bias signal output terminal COBS completes the bias signal output.

[0187] In phase t3: The start signal input at the start signal input terminal GSTV remains at a high potential, and the first transistor T1 and the second transistor T2 remain off. At this time, the second clock signal controls the fourth transistor T4 and the fifth transistor T5 to turn on. The first level signal input at the first level signal input terminal VGL charges the first node N1 to a low potential through the fourth transistor T4. The first node N1 controls the seventh transistor T7 and the ninth transistor T9 to turn on, and the gate drive signal output terminal Gout and the bias signal output terminal COBS output high-level signals. Simultaneously, the third transistor T3 and the fifth transistor T5 turn on, and the second level signal input at the first second level signal input terminal VGH1 is written to the second node N2. The second node N2 is at a high potential, controlling the sixth transistor T6 and the eighth transistor T8 to turn off. The gate drive signal output terminal Gout and the bias signal output terminal COBS complete one scan output.

[0188] When multiple shift registers are cascaded to form a gate driving circuit, the gate driving circuit includes m1 ordinary clock signal lines, where m1 ≥ 3; the m1 ordinary clock signal lines provide effective voltage signals in a time-division multiplexing manner; the first clock signal input terminal CK1 of the m1*n1+x1th shift register is coupled to the x1th ordinary clock signal line, where 1 ≤ x1 ≤ m1, and n1 ≥ 0; when x1 < m1, the second clock signal input terminal CK2 of the m1*n1+x1th shift register is coupled to the x1+1th ordinary clock signal line; when x1 = m1, the second clock signal input terminal CK2 of the m1*n1+x1th shift register is coupled to the first ordinary clock signal line.

[0189] When multiple shift registers are cascaded to form a gate drive circuit, the gate drive circuit further includes m2 bias clock signal lines, where m2 ≥ 3; the m2 bias clock signal lines provide effective voltage signals in a time-division multiplexing manner; the bias clock signal input terminal OBCK of the m2*n2+x2th shift register is coupled to the x2th bias clock signal line, where 1 ≤ x2 ≤ m2, and n2 ≥ 0.

[0190] When the above shift register is applied to the gate drive circuit, m1=3 and m2=3 can be set. The gate drive signal output terminal Gout of the current stage shift register can be coupled to the start signal input terminal GSTV of the next stage shift register, and can also be used as the scan drive signal of the sub-pixel. The bias signal output terminal COBS can be connected to the second plate of the sixth capacitor C6 in the corresponding sub-pixel to realize the capacitor bias function.

[0191] More specifically, taking a gate drive circuit comprising three ordinary clock signal lines as an example, as shown in Figure 4, the first shift register Gate GOA1 is coupled to the first clock signal input CK1, which is coupled to the first ordinary clock signal line CK1'; the second clock signal input CK2 of the first shift register Gate GOA1 is coupled to the second ordinary clock signal line CK2'; the second shift register Gate GOA2 is coupled to the first clock signal input CK1, which is coupled to the second ordinary clock signal line CK2'; the second clock signal input CK2 of the second shift register Gate GOA2 is coupled to the third ordinary clock signal line CK3'; the third shift register Gate GOA3 is coupled to the first clock signal input CK1, which is coupled to the third ordinary clock signal line CK3'; the second clock signal input CK2 of the third shift register Gate GOA3 is coupled to the first ordinary clock signal line CK1'; the fourth shift register Gate GOA3... The first clock signal input terminal CK1 of GOA4 is coupled to the first normal clock signal line CK1', and the second clock signal input terminal CK2 of the fourth shift register Gate GOA4 is coupled to the second normal clock signal line CK2'.

[0192] Taking a gate drive circuit with three bias clock signal lines as an example, as shown in Figure 4, the bias clock signal input terminal OBCK of the first shift register Gate GOA1 is coupled to the first bias clock signal line OBCK1'; the bias clock signal input terminal OBCK of the second shift register is coupled to the second bias clock signal line OBCK2'; the bias clock signal input terminal OBCK of the third shift register is coupled to the third bias clock signal line OBCK3'; and the bias clock signal input terminal OBCK of the fourth shift register is coupled to the first bias clock signal line OBCK1'.

[0193] The low-level bias signal output by COBS at the bias signal output terminal can be adjusted by adjusting the low potential of the effective voltage signal provided by the bias clock signal line. With the shift register configured as described above, in stages t1 and t2, the third node N3 is potential-coupled to the second node N2 through the third capacitor C3. This avoids leakage problems caused by insufficient shutdown of the fifth transistor T5, prevents impact on the potential stability of the second node N2, and thus avoids affecting the output performance of the sixth transistor T6, while increasing the threshold voltage offset margin of the fifth transistor T5.

[0194] The shift registers provided in the above embodiments may include P-type transistors, but are not limited to this.

[0195] This disclosure also provides a gate driving circuit, including multiple cascaded shift registers as described above; the gate driving circuit further includes m1 ordinary clock signal lines, where m1 ≥ 3; the m1 ordinary clock signal lines provide effective voltage signals in a time-division multiplexing manner;

[0196] The first clock signal input terminal CK1 of the m1*n1+x1th shift register is coupled to the x1th ordinary clock signal line, 1≤x1≤m1, n1≥0;

[0197] When x1 < m1, the second clock signal input terminal CK2 of the m1*n1+x1th shift register is coupled to the x1+1th ordinary clock signal line;

[0198] When x1 = m1, the second clock signal input terminal CK2 of the m1*n1+x1th shift register is coupled to the first ordinary clock signal line.

[0199] The shift register provided in the above embodiments can ensure that invalid output transistors are fully turned off, avoiding any impact on the signal output from the gate drive signal output terminal Gout. Therefore, the gate drive circuit provided in this disclosure, when including the above-mentioned shift register, also has the above-mentioned beneficial effects, which will not be elaborated further here.

[0200] The number of ordinary clock signal lines included in the gate drive circuit provided in this disclosure embodiment can be set according to actual needs, for example: setting m1=3, m1=4, m1=6, etc., but not limited to this.

[0201] In some embodiments, when the shift register includes a third output circuit 18 and a fourth output circuit 19, the gate drive circuit further includes m2 bias clock signal lines, where m2 ≥ 3; the m2 bias clock signal lines provide effective voltage signals in a time-division multiplexing manner.

[0202] The bias clock signal input terminal OBCK of the m2*n2+x2th shift register is coupled to the x2th bias clock signal line, 1≤x2≤m2, n2≥0.

[0203] The number of bias clock signal lines included in the gate drive circuit provided in this disclosure embodiment can be set according to actual needs, for example: setting m2=3, m2=4, m2=6, etc., but not limited to this.

[0204] This disclosure provides an embodiment in a gate driving circuit where the low potential of the effective voltage signal output from the bias clock signal line is adjustable. By adjusting the low potential of the effective voltage signal output from the bias clock signal line, the potential of the bias signal output from the COBS terminal can be adjusted. The effective voltage signal output from the bias clock signal line can meet the driving requirements of the sub-pixel driving circuit.

[0205] This disclosure also provides a display panel, including the gate driving circuit provided in the above embodiments. The display panel further includes a plurality of sub-pixels arranged in an array, and each sub-pixel includes a sub-pixel driving circuit and a light-emitting element coupled to each other.

[0206] The gate drive signal output terminal Gout of the shift register in the gate drive circuit is coupled to the gate of the target transistor in the corresponding sub-pixel drive circuit.

[0207] For example, the display panel includes a display area and a peripheral area surrounding the display area, the plurality of sub-pixels are located in the display area, and the gate driving circuit is located in the peripheral area, but is not limited thereto.

[0208] For example, the plurality of sub-pixels includes multiple rows of sub-pixels, and the gate drive signal output terminal Gout of the shift register is coupled to the gate of the target transistor in the sub-pixel drive circuit of each sub-pixel in the corresponding at least one row of sub-pixels.

[0209] The gate driving circuit provided in the above embodiments can ensure that invalid output transistors are fully turned off, avoiding any impact on the signal output from the gate driving signal output terminal Gout. Therefore, when the display panel provided in this disclosure includes the above-mentioned gate driving circuit, the sub-pixels in the display panel can be driven by a stable gate driving signal output from the shift register, thus improving the display effect of the display panel.

[0210] As shown in Figure 20, in some embodiments, the sub-pixel driving circuit includes a driving transistor T03, a compensation transistor T02, a fifth capacitor C5, and a sixth capacitor C6.

[0211] The first plate of the fifth capacitor C5 is coupled to the gate of the driving transistor T03, the second plate of the fifth capacitor C5 is coupled to the second terminal of the compensation transistor T02, and the first terminal of the compensation transistor T02 is coupled to the second terminal of the driving transistor T03; the first plate of the sixth capacitor C6 is coupled to the second plate of the fifth capacitor C5.

[0212] The bias signal output terminal COBS of the shift register in the gate driving circuit is coupled to the second plate of the sixth capacitor C6 in the corresponding sub-pixel driving circuit.

[0213] As shown in Figure 20, the second plate of the sixth capacitor C6 receives the bias signal output from the COBS output terminal of the shift register. The low level of the bias signal can be achieved by adjusting the low level of the bias clock signal received by the shift register. The biasing process is that the potential of the second plate of the sixth capacitor C6 is coupled to the potential of the second plate of the fifth capacitor C5, and the potential of the second plate of the fifth capacitor C5 is coupled to the potential of the gate of the driving transistor T03, thereby negatively biasing or positively biasing the gate potential of the driving transistor T03, thus achieving the function of resetting the characteristics of the driving transistor T03.

[0214] The gate drive signal output terminal Gout of the shift register can be coupled to the start signal input terminal GSTV of the next-stage shift register, and can also be used as the scan drive signal of the sub-pixel. The bias signal output terminal COBS can be connected to the second plate of the sixth capacitor C6 in the corresponding sub-pixel to achieve the function of capacitor bias.

[0215] For example, the sub-pixel driving circuit further includes: a power control transistor T05, a light emission control transistor T06, a data writing transistor T07, a first reset transistor T09, a second reset transistor T04, a third reset transistor T01, a fourth reset transistor T08, and a fourth capacitor C4.

[0216] The gate of the power control transistor T05 is coupled to the light emission control signal input terminal EM, the first terminal of the power control transistor T05 is coupled to the power signal input terminal VDD, and the second terminal of the power control transistor T05 is coupled to the first terminal of the driving transistor T03.

[0217] The gate of the light-emitting control transistor T06 is coupled to the light-emitting control signal input terminal EM, the first terminal of the light-emitting control transistor T06 is coupled to the second terminal of the driving transistor T03, and the second terminal of the light-emitting control transistor T06 is coupled to the anode of the light-emitting element.

[0218] The gate of the data writing transistor T07 is coupled to the second scan signal input terminal Gate7, the first terminal of the data writing transistor T07 is coupled to the data signal input terminal DA, and the second terminal of the data writing transistor T07 is coupled to the second terminal of the driving transistor T03.

[0219] The gate of the first reset transistor T09 is coupled to the first scan signal input terminal Gate1, the first terminal of the first reset transistor T09 is coupled to the third initialization signal input terminal Vinit3, and the second terminal of the first reset transistor T09 is coupled to the second terminal of the driving transistor T03.

[0220] The gate of the second reset transistor T04 is coupled to the fifth scan signal input terminal GP1, the first terminal of the second reset transistor T04 is coupled to the first initialization signal input terminal Vinit1, and the second terminal of the second reset transistor T04 is coupled to the first terminal (i.e., node N6) of the driving transistor T03.

[0221] The gate of the third reset transistor T01 is coupled to the third scan signal input terminal GateN1, the first terminal of the third reset transistor T01 is coupled to the first initialization signal input terminal Vinit1, and the second terminal of the third reset transistor T01 is coupled to the gate of the driving transistor T03.

[0222] The gate of the fourth reset transistor T08 is coupled to the fifth scan signal input terminal GP1, the first terminal of the fourth reset transistor T08 is coupled to the second initialization signal input terminal Vinit2, the second terminal of the fourth reset transistor T08 is coupled to the anode (i.e., node N8) of the light-emitting element, and the cathode of the light-emitting element is coupled to the negative power supply signal terminal VSS.

[0223] The first plate of the fourth capacitor C4 is coupled to the gate of the driving transistor T03, and the second plate of the fourth capacitor C4 is coupled to the power signal input terminal VDD.

[0224] It should be noted that the third reset transistor T01 and the compensation transistor T02 in Figure 20 are N-type oxide transistors, but are not limited to this.

[0225] As shown in Figures 21 and 22, the specific working process of the above-mentioned sub-pixel driving circuit is as follows:

[0226] During the reset phase P1: the third scan signal input terminal GateN1 controls the third reset transistor T01 to turn on, and controls the first initialization signal input terminal Vinit1 to reset the gate of the driving transistor T03. Then, the fourth scan signal input terminal GateN7 controls the compensation transistor T02 to turn on, the first scan signal input terminal Gate1 controls the first reset transistor T09 to turn on, and controls the third initialization signal input terminal Vinit3 to reset the second electrode of the driving transistor T03 and the second plate of the fifth capacitor C5.

[0227] During the compensation phase P2: the third scan signal input terminal GateN1 continues to control the third reset transistor T01 to conduct, and the fourth scan signal input terminal GateN7 continues to control the compensation transistor T02 to conduct. At this time, the fifth scan signal input terminal GP1 controls the second reset transistor T04 and the fourth reset transistor T08 to conduct. The second reset transistor T04 charges the second terminal (i.e., node N7) of the driving transistor T03. When the gate-source voltage Vgs of the driving transistor T03 is equal to Vth, the threshold voltage Vth compensation of the driving transistor T03 is completed. At this time, the potential V1 of the first terminal (i.e., node N7) of the compensation transistor T02 is equal to the potential V2 of the second terminal (i.e., node N5) of the compensation transistor T02, which is equal to the difference between the voltage value V3 of the first initialization signal and Vth, that is: V1 = V2 = V3 - Vth.

[0228] During the writing phase P3: the second scan signal input terminal Gate7 controls the data writing transistor T07 to turn on, and the data signal input terminal controls the data signal to be written to the first and second terminals of the compensation transistor T02. At this time, the voltage change of the second terminal of the compensation transistor T02 is ΔV = Vdata - (V3 - Vth), where Vdata is the voltage value of the data signal. The potential of the gate (i.e., node N4) of the driving transistor T03 is: V3 + ΔV(C5 / (C4 + C5)).

[0229] During the biasing phase P4: GateN7, the fourth scan signal input terminal, controls the compensation transistor T02 to turn off. The bias signal reduces the bias to a low potential through the sixth capacitor C6 on the second plate of the fifth capacitor C5 and the gate of the driving transistor T03. After the gate potential of the driving transistor T03 is pulled low, the bias signal is reset, and the gate potential of the driving transistor T03 is restored.

[0230] During the light-emitting stage, P5: the light-emitting control signal input terminal EM controls the power control transistor T05 and the light-emitting control transistor T06 to turn on, and the light-emitting element emits light for display.

[0231] It should be noted that the IDS shown in Figure 22 represents the pixel current.

[0232] The sub-pixel driving circuit provided in the above embodiments is compatible with both high-frequency (240Hz) and low-frequency (1Hz) driving requirements, enabling the writing of different grayscale data signals. The sub-pixel driving circuit provided in the above embodiments, combined with the shift register provided in the above embodiments, adds a capacitor bias function, achieving a stronger bias voltage with a wider adjustable voltage range, resulting in a more significant reset effect on the device characteristics. It is worth noting that the biasing stage can be performed before or after the writing and compensation stages, ensuring that the driving transistor T03 achieves a strong bias voltage with capacitive coupling, thus resetting the characteristics of the driving transistor T03.

[0233] The above embodiment provides a sub-pixel driving circuit including an IGZO pixel circuit. It can control the pulse width of the scanning signal and adjust the Vth compensation time as needed to meet the driving requirements of higher frequencies. At the same time, it adds a capacitor bias structure (i.e., the sixth capacitor C6) to meet the display requirements of low frequency 1HZ. The gate voltage of the driving transistor T03 is biased through capacitive coupling to achieve strong Vgs bias and realize the function of resetting the characteristics of the driving transistor T03.

[0234] As shown in Figures 23 to 36, in some embodiments, the ordinary clock signal line in the gate drive circuit extends along a first direction; the first transistor T1 and the second transistor T2 included in the shift register in the gate drive circuit are arranged along the first direction.

[0235] For example, the first transistor T1 and / or the second transistor T2 adopt a dual-gate transistor structure, and the channel portions of the first transistor T1 and the second transistor T2 are arranged sequentially along the first direction.

[0236] For example, the first transistor T1 and the third transistor T3 in the shift register are arranged along a second direction, which intersects with the first direction; the third transistor T3 adopts a single-gate structure or a double-gate structure.

[0237] The above-described configuration of the transistors using a dual-gate structure improves their performance. Conversely, using a single-gate structure reduces the layout space required by the shift register, lowering its placement complexity. This approach to shift register placement utilizes the limited space more effectively and reduces the overall layout difficulty.

[0238] As shown in Figures 23 to 36, in some embodiments, the orthographic projection of the gate of the third transistor T3 onto the substrate of the display panel and the orthographic projection of the first plate of the third capacitor C3 in the shift register onto the substrate are arranged along a first direction.

[0239] For example, in the case where the shift register also includes a third capacitor C3, the third transistor T3 adopts a dual-gate structure, but is not limited to this.

[0240] For example, the fourth transistor T4 and the fifth transistor T5 in the shift register are both located on the side of the third transistor T3 that is close to the display area of ​​the display panel.

[0241] As shown in Figures 23 to 36, in some embodiments, the third transistor T3 and the fifth transistor T5 in the shift register are arranged along a first direction, and the fifth transistor T5 is located on the side of the third transistor T3 closer to the next-stage shift register.

[0242] For example, in the case where the shift register does not include the third capacitor C3, the third transistor T3 adopts a dual-gate structure, but is not limited to this.

[0243] For example, the fourth transistor T4 in the shift register is located on the side of the third transistor T3 near the display area of ​​the display panel.

[0244] As shown in Figures 23 to 36, in some embodiments, the seventh transistor T7 and the sixth transistor T6 in the shift register are arranged along a first direction; the first capacitor C1 in the shift register is located on the side of the seventh transistor T7 near the display area of ​​the display panel; and the second capacitor C2 in the shift register is located on the side of the sixth transistor T6 near the display area.

[0245] By arranging the shift registers in the above manner, the limited layout space is planned more rationally, reducing the difficulty of shift register layout.

[0246] As shown in Figures 25 to 27, in some embodiments, the channel width-to-length ratio of the sixth transistor T6 is greater than that of the seventh transistor T7. This arrangement not only improves the output capability of the shift register, but also reduces the length of the sixth conductive connection portion 36 corresponding to the seventh transistor T7 along the second direction, thus saving layout space.

[0247] It is worth noting that Figures 23-29 are schematic diagrams of the layout corresponding to the shift register structure in Figure 18; Figures 30-36 are schematic diagrams of the layout corresponding to the shift register structure in Figure 6.

[0248] More specifically, as shown in Figures 23 and 30, the first transistor T1 includes a first active layer 21, the second transistor T2 includes a second active layer 22, the third transistor T3 includes a third active layer 23, the fourth transistor T4 includes a fourth active layer 24, the fifth transistor T5 includes a fifth active layer 25, the sixth transistor T6 includes a sixth active layer 26, and the seventh transistor T7 includes a seventh active layer 27.

[0249] Figures 24 and 31 also illustrate the first plate C11 of the first capacitor C1 and the first plate C21 of the second capacitor C2; Figure 31 also illustrates the second plate C32 of the third capacitor C3.

[0250] Figures 25 and 32 also illustrate the second plate C12 of the first capacitor C1 and the second plate C22 of the second capacitor C2; Figure 32 also illustrates the first plate C31 of the third capacitor C3. Figures 25 and 32 also illustrate the first conductive connection 31, one end of which is coupled to the fourth conductive connection 34, and the other end of which is coupled to the fifth conductive connection 35.

[0251] As shown in Figures 26 to 29, one end of the second conductive connection portion 32 is coupled to the gate of the first transistor T1 in the current stage, and the other end of the second conductive connection portion 32 is coupled to the second terminal of the sixth transistor T6 in the previous stage shift register.

[0252] One end of the third conductive connection 33 is coupled to the gate of the fourth transistor T4, and the other end of the third conductive connection 33 is coupled to the second ordinary clock signal line CK2'.

[0253] The fourth conductive connection portion 34 is coupled to the gate of the third transistor T3, and the fourth conductive connection portion 34 is also coupled to the second electrode of the first transistor T1.

[0254] The fifth conductive connection portion 35 is coupled to the gate of the seventh transistor T7, and the fifth conductive connection portion 35 is also coupled to the second electrode of the fourth transistor T4.

[0255] The sixth conductive connection portion 36 serves as the first electrode of the seventh transistor and is coupled to the second second-level signal line VGH2'. The sixth conductive connection portion 36 is also coupled to the second electrode plate C12 of the first capacitor C1.

[0256] One end of the seventh conductive connection 37 is coupled to the first initialization signal line Vinit1', and the other end of the seventh conductive connection 37 is coupled to the sixteenth conductive connection 46.

[0257] One end of the eighth conductive connection 38 is coupled to the second initialization signal line Vinit2', and the other end of the eighth conductive connection 38 is coupled to the seventeenth conductive connection 47.

[0258] One end of the ninth conductive connection portion 39 is coupled to the gate of the second transistor T2, and the other end of the ninth conductive connection portion 39 is coupled to the first electrode of the second transistor T2.

[0259] One end of the tenth conductive connection part 40 is coupled to the first second level signal line VGH1', and the other end of the tenth conductive connection part 40 is coupled to the first electrode of the third transistor T3.

[0260] The eleventh conductive connection part 41 is coupled to the second terminal of the second transistor T2, the eleventh conductive connection part 41 is also coupled to the first terminal of the fifth transistor T5, and the eleventh conductive connection part 41 is also coupled to the second terminal of the third transistor T3.

[0261] One end of the twelfth conductive connection portion 42 is coupled to the second electrode of the fifth transistor T5, and the other end of the twelfth conductive connection portion 42 is coupled to the gate of the sixth transistor T6.

[0262] One end of the thirteenth conductive connection 43 is coupled to the gate of the fifth transistor T5, and the other end of the thirteenth conductive connection 43 is coupled to the first level signal line VGL'.

[0263] One end of the fourteenth conductive connection 44 serves as the first electrode of the sixth transistor T6, and the other end of the fourteenth conductive connection 44 is coupled to the first ordinary clock signal line CK1'.

[0264] The fifteenth conductive connection portion 45 serves as the second electrode of the sixth transistor T6 and is coupled to the eighteenth conductive connection portion 48, serving as the gate drive signal output terminal of the shift register.

[0265] As shown in Figures 33 to 36, one end of the nineteenth conductive connection portion 49 is coupled to the second electrode of the second transistor T2, the other end of the nineteenth conductive connection portion 49 is coupled to the gate of the sixth transistor T6, and the other end of the nineteenth conductive connection portion 49 is also coupled to the second electrode of the fifth transistor T5.

[0266] One end of the twentieth conductive connection portion 50 is coupled to the first electrode C31 of the third capacitor C3, and the other end of the twentieth conductive connection portion 50 is coupled to the first electrode of the fifth transistor T5 and the second electrode of the third transistor T3. The second electrode C32 of the third capacitor C3 and the gate of the sixth transistor T6 are formed as an integral structure.

[0267] One end of the twenty-first conductive connection portion 51 is coupled to the first electrode of the fourth transistor T4, and the other end of the twenty-first conductive connection portion 51 is coupled to the first level signal line VGL'.

[0268] As shown in Figures 29 and 36, the figures also illustrate the start signal line GSTV', which is coupled to the start signal input terminal of the first-stage shift register. The figures also illustrate the third initialization signal line Vinit3', which is coupled to the third initialization signal input terminal. The second initialization signal line Vinit3' is coupled to the second initialization signal input terminal. The first initialization signal line Vinit3' is coupled to the first initialization signal input terminal.

[0269] Figure 37 illustrates four cascaded shift registers. The part enclosed in the dashed box in the figure is one shift register.

[0270] This disclosure also provides a display device, including the display panel provided in the above embodiments.

[0271] It should be noted that the display device can be any product or component with display function, such as a television, monitor, digital photo frame, mobile phone, or tablet computer. The display device also includes flexible circuit boards, printed circuit boards, and backplanes.

[0272] The sub-pixels in the display panel provided in the above embodiments can be driven by a stable gate drive signal output from the shift register, thereby improving the display effect of the display panel. The display device provided in the embodiments of this disclosure, when including the above-described display panel, also has the above-described beneficial effects, which will not be repeated here.

[0273] It should be noted that the signal line extending in a certain direction means that the signal line includes a main part and a secondary part connected to the main part. The main part is a line, line segment, or strip-shaped body. The main part extends in a certain direction, and the length of the main part extending in a certain direction is greater than the length of the secondary part extending in other directions.

[0274] It should be noted that, in the embodiments of this disclosure, "same layer" can refer to film layers located on the same structural layer. Alternatively, for example, film layers located on the same layer can be layer structures formed by using the same film deposition process to form a specific pattern, and then patterning the film layer using the same photomask through a single patterning process. Depending on the specific pattern, the single patterning process may include multiple exposure, development, or etching processes, and the specific pattern in the formed layer structure can be continuous or discontinuous. These specific patterns may also be at different heights or have different thicknesses.

[0275] In the various method embodiments of this disclosure, the sequence numbers of each step are not intended to limit the order of the steps. For those skilled in the art, any changes in the order of the steps are within the scope of protection of this disclosure without any creative effort.

[0276] It should be noted that the various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the method embodiments are basically similar to the product embodiments, so the description is relatively simple, and the relevant parts can be referred to the description of the product embodiments.

[0277] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connection,” “coupling,” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “above,” “below,” “left,” and “right” are used only to indicate relative positional relationships, which may change accordingly when the absolute position of the described object changes. It is understood that when an element such as a layer, film, region, or substrate is referred to as being “above” or “below” another element, the element may be located “directly” above or below the other element, or there may be intermediate elements present. In the description of the above embodiments, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples. The above descriptions are merely specific embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A shift register, comprising: First node, first node control circuit and first output circuit; The first node control circuit is coupled to the start signal input terminal, the first second level signal input terminal and the first node respectively, and is used to control the electrical connection between the first second level signal input terminal and the first node to be turned on or off under the control of the start signal input at the start signal input terminal; The first output circuit is coupled to the first node, the second second-level signal input terminal, and the gate drive signal output terminal of the shift register, respectively, and is used to control the electrical connection between the second second-level signal input terminal and the gate drive signal output terminal to be turned on or off under the control of the potential of the first node.

2. The shift register according to claim 1, wherein, The voltage value of the second-level signal input at the first second-level signal input terminal is greater than the voltage value of the second-level signal input at the second second-level signal input terminal.

3. The shift register according to claim 1, wherein, The shift register also includes a second node, an input circuit, and a second output circuit; The input circuit is coupled to the start signal input terminal and the second node respectively, and is used to control the electrical connection between the start signal input terminal and the second node to be turned on or off under the control of the start signal input at the start signal input terminal; The second output circuit is coupled to the second node, the first clock signal input terminal and the gate drive signal output terminal respectively, and is used to control the electrical connection between the first clock signal input terminal and the gate drive signal output terminal to be turned on or off under the control of the potential of the second node.

4. The shift register according to claim 3, wherein, The first node control circuit includes a first transistor, the gate of the first transistor is coupled to the start signal input terminal, the first electrode of the first transistor is coupled to a first second level signal input terminal, and the second electrode of the first transistor is coupled to the first node. The first output circuit includes a seventh transistor and a first capacitor. The gate of the seventh transistor is coupled to the first node, the first terminal of the seventh transistor is coupled to the second second-level signal input terminal, and the second terminal of the seventh transistor is coupled to the gate drive signal output terminal. The first plate of the first capacitor is coupled to the first node, and the second plate of the first capacitor is coupled to the second second level signal input terminal; The input circuit includes a second transistor, the gate of which is coupled to the start signal input terminal, the first terminal of which is coupled to the start signal input terminal, and the second terminal of which is coupled to the second node; The second output circuit includes a sixth transistor and a second capacitor. The gate of the sixth transistor is coupled to the second node, the first terminal of the sixth transistor is coupled to the first clock signal input terminal, and the second terminal of the sixth transistor is coupled to the gate drive signal output terminal. The first plate of the second capacitor is coupled to the gate of the sixth transistor, and the second plate of the second capacitor is coupled to the gate drive signal output terminal.

5. The shift register according to claim 3, wherein, The first node control circuit is also coupled to the first level signal input terminal and the second clock signal input terminal respectively, and is used to control the electrical connection between the first level signal input terminal and the first node to be turned on or off under the control of the second clock signal input at the second clock signal input terminal; The shift register further includes: a coupling circuit, a second node control circuit, a third node, and a third node control circuit; The coupling circuit is coupled to the second node and the third node respectively, and is used to control the potential of the other of the second node and the third node according to the potential of one of the second node and the third node; The second node control circuit is coupled to the second clock signal input terminal, the second node and the third node respectively, and is used to control the electrical connection between the second node and the third node to be turned on or off under the control of the second clock signal input to the second clock signal input terminal; The third node control circuit is coupled to the first node, the first second-level signal input terminal and the third node respectively, and is used to control the electrical connection between the first second-level signal input terminal and the third node to be turned on or off according to the potential of the first node.

6. The shift register according to claim 5, wherein, The first node control circuit further includes a fourth transistor, the gate of which is coupled to the second clock signal input terminal, the first terminal of which is coupled to the first level signal input terminal, and the second terminal of which is coupled to the first node. The coupling circuit includes a third capacitor, the first plate of which is coupled to the third node, and the second plate of which is coupled to the second node. The second node control circuit includes a fifth transistor, the gate of which is coupled to the second clock signal input terminal, the first terminal of which is coupled to the third node, and the second terminal of which is coupled to the second node; The third node control circuit includes a third transistor, the gate of which is coupled to the first node, the first terminal of which is coupled to the first second-level signal input terminal, and the second terminal of which is coupled to the third node.

7. The shift register according to claim 3, wherein, The first node control circuit is also coupled to a first first level signal input terminal and a second clock signal input terminal, respectively, and is used to control the conduction or disconnection of the electrical connection between the first first level signal input terminal and the first node under the control of the second clock signal input terminal. The shift register further includes: a coupling circuit, a second node control circuit, a third node, and a third node control circuit; The coupling circuit is respectively coupled to the second first-level signal input terminal and the third node, and is used to control the potential of the other of the first first-level signal input terminal and the third node according to the potential of one of the first first-level signal input terminal and the third node; The second node control circuit is coupled to the second clock signal input terminal, the second node and the third node respectively, and is used to control the electrical connection between the second node and the third node to be turned on or off under the control of the second clock signal input to the second clock signal input terminal; The third node control circuit is coupled to the first node, the second second-level signal input terminal and the third node respectively, and is used to control the electrical connection between the second second-level signal input terminal and the third node to be turned on or off according to the potential of the first node.

8. The shift register according to claim 7, wherein, The voltage value of the first level signal input to the second first level signal input terminal is less than the voltage value of the first level signal input to the first first level signal input terminal.

9. The shift register according to claim 7, wherein, The first node control circuit further includes a fourth transistor, the gate of which is coupled to the second clock signal input terminal, the first terminal of which is coupled to the first first level signal input terminal, and the second terminal of which is coupled to the first node; The coupling circuit includes a third capacitor, the first plate of which is coupled to the third node, and the second plate of which is coupled to the second first level signal input terminal. The second node control circuit includes a fifth transistor, the gate of which is coupled to the second clock signal input terminal, the first terminal of which is coupled to the third node, and the second terminal of which is coupled to the second node; The third node control circuit includes a third transistor, the gate of which is coupled to the first node, the first terminal of which is coupled to the second second-level signal input terminal, and the second terminal of which is coupled to the third node.

10. The shift register according to claim 3, wherein, The first node control circuit is also coupled to the first level signal input terminal and the second clock signal input terminal respectively, and is used to control the electrical connection between the first level signal input terminal and the first node to be turned on or off under the control of the second clock signal input at the second clock signal input terminal; The shift register further includes: a transmission circuit, a third node, and a third node control circuit; The transmission circuit is coupled to the first level signal input terminal, the second node and the third node respectively, and is used to control the conduction or disconnection of the electrical connection between the second node and the third node under the control of the first level signal input terminal. The third node control circuit is coupled to the first node, the first second-level signal input terminal and the third node respectively, and is used to control the electrical connection between the first second-level signal input terminal and the third node to be turned on or off according to the potential of the first node; The input circuit is coupled to the third node, and is coupled to the second node through the third node and the transmission circuit.

11. The shift register according to claim 10, wherein, The first node control circuit further includes a fourth transistor, the gate of which is coupled to the second clock signal input terminal, the first terminal of which is coupled to the first level signal input terminal, and the second terminal of which is coupled to the first node. The transmission circuit includes a fifth transistor, the gate of which is coupled to the first level signal input terminal, the first terminal of which is coupled to the third node, and the second terminal of which is coupled to the second node; The third node control circuit includes a third transistor, the gate of which is coupled to the first node, the first terminal of which is coupled to the first second-level signal input terminal, and the second terminal of which is coupled to the third node.

12. The shift register according to any one of claims 3 to 11, wherein, The shift register also includes: The third output circuit is coupled to the first node, the second second-level signal input terminal and the bias signal output terminal of the shift register respectively, and is used to control the electrical connection between the second second-level signal input terminal and the bias signal output terminal under the control of the potential of the first node. The fourth output circuit is coupled to the second node, the bias clock signal input terminal and the bias signal output terminal respectively, and is used to control the electrical connection between the bias clock signal input terminal and the bias signal output terminal to be turned on or off under the control of the potential of the second node.

13. The shift register according to claim 12, wherein, The third output circuit includes a ninth transistor, the gate of which is coupled to the first node, the first terminal of which is coupled to the second second-level signal input terminal, and the second terminal of which is coupled to the bias signal output terminal. The fourth output circuit includes an eighth transistor, the gate of which is coupled to the second node, the first terminal of which is coupled to the bias clock signal input terminal, and the second terminal of which is coupled to the bias signal output terminal.

14. A gate driving circuit, comprising a plurality of cascaded shift registers as described in any one of claims 1 to 13; the gate driving circuit further comprising m1 ordinary clock signal lines, m1 ≥ 3; the m1 ordinary clock signal lines providing effective voltage signals in a time-division multiplexing manner; The first clock signal input terminal of the m1*n1+x1th shift register is coupled to the x1th ordinary clock signal line, 1≤x1≤m1, n1≥0; When x1 < m1, the second clock signal input terminal of the m1*n1+x1th shift register is coupled to the x1+1th ordinary clock signal line; When x1 = m1, the second clock signal input terminal of the m1*n1+x1th shift register is coupled to the first ordinary clock signal line.

15. The gate drive circuit according to claim 14, wherein, In the case where the shift register includes a third output circuit and a fourth output circuit, the gate drive circuit further includes m2 bias clock signal lines, where m2 ≥ 3; the m2 bias clock signal lines provide effective voltage signals in a time-division manner. The bias clock signal input terminal of the m2*n2+x2th shift register is coupled to the x2th bias clock signal line, 1≤x2≤m2, n2≥0.

16. A display panel, comprising the gate driving circuit as described in claim 14 or 15, the display panel further comprising a plurality of sub-pixels, each sub-pixel comprising a sub-pixel driving circuit and a light-emitting element coupled together; The gate drive signal output terminal of the shift register in the gate drive circuit is coupled to the gate of the target transistor in the corresponding sub-pixel drive circuit.

17. The display panel according to claim 16, wherein, The sub-pixel driving circuit includes a driving transistor, a compensation transistor, a fifth capacitor, and a sixth capacitor; The first plate of the fifth capacitor is coupled to the gate of the driving transistor, the second plate of the fifth capacitor is coupled to the second terminal of the compensation transistor, and the first terminal of the compensation transistor is coupled to the second terminal of the driving transistor; the first plate of the sixth capacitor is coupled to the second plate of the fifth capacitor. The bias signal output terminal of the shift register in the gate driving circuit is coupled to the second plate of the sixth capacitor in the corresponding sub-pixel driving circuit.

18. The display panel according to claim 17, wherein, The sub-pixel driving circuit further includes: a power control transistor, a light-emitting control transistor, a data writing transistor, a first reset transistor, a second reset transistor, a third reset transistor, a fourth reset transistor, and a fourth capacitor; The gate of the power control transistor is coupled to the light emission control signal input terminal, the first terminal of the power control transistor is coupled to the power signal input terminal, and the second terminal of the power control transistor is coupled to the first terminal of the driving transistor. The gate of the light-emitting control transistor is coupled to the light-emitting control signal input terminal, the first terminal of the light-emitting control transistor is coupled to the second terminal of the driving transistor, and the second terminal of the light-emitting control transistor is coupled to the anode of the light-emitting element. The gate of the data writing transistor is coupled to the second scan signal input terminal, the first terminal of the data writing transistor is coupled to the data signal input terminal, and the second terminal of the data writing transistor is coupled to the second terminal of the driving transistor. The gate of the first reset transistor is coupled to the first scan signal input terminal, the first terminal of the first reset transistor is coupled to the third initialization signal input terminal, and the second terminal of the first reset transistor is coupled to the second terminal of the driving transistor. The gate of the second reset transistor is coupled to the fifth scan signal input terminal, the first terminal of the second reset transistor is coupled to the first initialization signal input terminal, and the second terminal of the second reset transistor is coupled to the first terminal of the driving transistor. The gate of the third reset transistor is coupled to the third scan signal input terminal, the first terminal of the third reset transistor is coupled to the first initialization signal input terminal, and the second terminal of the third reset transistor is coupled to the gate of the driving transistor. The gate of the fourth reset transistor is coupled to the fifth scan signal input terminal, the first terminal of the fourth reset transistor is coupled to the second initialization signal input terminal, and the second terminal of the fourth reset transistor is coupled to the anode of the light-emitting element. The first plate of the fourth capacitor is coupled to the gate of the driving transistor, and the second plate of the fourth capacitor is coupled to the power signal input terminal.

19. The display panel according to claim 16, wherein, The ordinary clock signal line in the gate driving circuit extends along a first direction; the first transistor and the second transistor in the shift register of the gate driving circuit are arranged along the first direction.

20. The display panel according to claim 19, wherein, The first transistor and / or the second transistor adopt a dual-gate transistor structure, and the channel portions of the first transistor and the second transistor are arranged sequentially along the first direction.

21. The display panel according to claim 20, wherein, The first transistor and the third transistor in the shift register are arranged along a second direction, which intersects with the first direction; the third transistor adopts a single-gate structure or a double-gate structure.

22. The display panel according to claim 21, wherein, The orthographic projection of the gate of the third transistor on the substrate of the display panel and the orthographic projection of the first plate of the third capacitor in the shift register on the substrate are aligned along a first direction.

23. The display panel according to claim 22, wherein, The fourth and fifth transistors in the shift register are both located on the side of the display panel closest to the third transistor.

24. The display panel according to claim 21, wherein, The third transistor and the fifth transistor in the shift register are arranged along a first direction, with the fifth transistor located on the side of the third transistor closer to the next-stage shift register.

25. The display panel according to claim 24, wherein, The fourth transistor in the shift register is located on the side of the display panel closer to the third transistor.

26. The display panel according to claim 23 or 25, wherein, The seventh and sixth transistors in the shift register are arranged along a first direction; The first capacitor in the shift register is located on the side of the seventh transistor closer to the display area of ​​the display panel; The second capacitor in the shift register is located on the side of the sixth transistor closer to the display area.

27. The display panel according to claim 26, wherein, The channel width-to-length ratio of the sixth transistor is greater than that of the seventh transistor.

28. A display device comprising a display panel as claimed in any one of claims 16 to 27.

Images