Semiconductor device and preparation method therefor
By employing a bit line structure composed of silicides and carbon dopants in DRAM devices, the problem of bit line degradation caused by high-temperature processing is solved, thereby improving the thermal stability and performance of the devices.
Patent Information
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- INST OF MICROELECTRONICS CHINESE ACAD OF SCI LTD
- Filing Date
- 2025-03-12
- Publication Date
- 2026-06-04
AI Technical Summary
In dynamic random access memory (DRAM), embedded bit lines are prone to degradation during high-temperature oxidation processes and capacitor annealing heat treatments, which affects device performance.
The bit line structure consists of a first part and a second part. The first part is composed of silicide and carbon dopant, and the second part is composed of silicon. The carbon dopant improves thermal stability and reduces the adverse effects of high-temperature processing on the bit line.
This improves the thermal stability of bit lines, reduces bit line degradation, and enhances the performance of DRAM devices.
Smart Images
Figure CN2025082177_04062026_PF_FP_ABST
Abstract
Description
Semiconductor devices and their fabrication methods Technical Field
[0001] This application belongs to the field of semiconductor technology, and in particular relates to a semiconductor device and its fabrication method. Background Technology
[0002] Dynamic Random Access Memory (DRAM) is a type of semiconductor memory. Some DRAM devices use vertical transistors. However, in this architecture, the buried bit lines are formed before the gate stacking and capacitor annealing. They must withstand the heat from the high-temperature oxidation process of the gate and the heat treatment of capacitor annealing, which can easily cause the bit lines to degrade and thus affect the performance of the DRAM device. Summary of the Invention
[0003] The purpose of this application is to at least solve the problem of poor performance in semiconductor devices. This purpose is achieved through the following technical solution:
[0004] The first aspect of this application discloses a semiconductor device comprising:
[0005] Substrate;
[0006] Bit line structures are formed on the substrate, the bit line structures include a first portion and a second portion, the second portion being located on the side of the first portion away from the substrate, the first portion including silicide and carbon dopant, and the second portion including silicon.
[0007] In the semiconductor device provided in this application, a bit line structure is formed on a substrate. The bit line structure includes a first part and a second part. The first part includes silicide and carbon dopant. The carbon dopant is located inside and / or on the surface of the first part. The carbon dopant makes the first part have high thermal stability, thereby reducing the adverse effects of high temperatures during the fabrication of subsequent films on the bit line structure and reducing the degradation of the bit line structure. The second part is made of silicon and does not include carbon dopant and silicide, which facilitates the subsequent epitaxial growth of subsequent films. The bit lines of this semiconductor device are less prone to degradation after heating, and the performance is significantly improved.
[0008] A second aspect of this application also provides a method for fabricating a semiconductor device, comprising:
[0009] Provide semiconductor substrates;
[0010] The semiconductor substrate is patterned to form a substrate and a bit line forming portion located on one side of the substrate, the bit line forming portion including a first forming portion and a second forming portion located on the side of the first forming portion away from the substrate;
[0011] A protective structure is formed on the surface of the second forming part away from the substrate of the semiconductor and on the side surface of the second forming part;
[0012] A carbon structure layer is formed, the carbon structure layer being in contact with at least the side surface of the first molding part, the carbon structure layer including a contact surface that contacts the first molding part;
[0013] A bit line metal layer is formed, wherein the bit line metal layer is in contact with at least one side of the contact surface away from the first forming part;
[0014] The bit line forming portion is heat-treated to make the first forming portion become the first part and the second forming portion become the second part. The first part includes silicide and carbon dopant, and the second part includes silicon. Attached Figure Description
[0015] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the scope of this application. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings:
[0016] Figure 1 is a schematic diagram of the structure of a semiconductor device provided in an embodiment of this application;
[0017] Figure 2 is a top view of a semiconductor device provided in an embodiment of this application;
[0018] Figure 3 is a schematic diagram of the structure of a semiconductor device provided in an embodiment of this application;
[0019] Figure 4 is a flowchart of a method for fabricating a semiconductor device according to an embodiment of this application;
[0020] Figures 5 to 9 are schematic diagrams illustrating the film layer changes during the fabrication process of a semiconductor device provided in the embodiments of this application.
[0021] The reference numerals in the attached figures are as follows: 1. Semiconductor device; 11. Substrate; 12. Bit line structure; 121. First part; 122. Second part; 13. Isolation layer; 14. Transistor; 141. Source region; 142. Drain region; 143. Channel region; 15. Barrier layer; 16. Semiconductor substrate; 17. Bit line forming part; 171. First forming part; 172. Second forming part; 173. Isolation forming part; 18. Protective structure; 19. Carbon structure layer; 20. Bit line metal layer; 21. Capacitor. Detailed Implementation
[0022] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
[0023] It should be understood that the terminology used herein is for the purpose of describing particular exemplary embodiments only and is not intended to be limiting. Unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “described” as used herein may also include the plural forms. The terms “comprising,” “including,” “containing,” and “having” are inclusive and therefore indicate the presence of the stated features, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, elements, components, and / or combinations thereof. The method steps, processes, and operations described herein are not construed as requiring them to be performed in a particular order described or illustrated unless the order of performance is explicitly indicated. It should also be understood that additional or alternative steps may be used.
[0024] Although terms such as first, second, third, etc., may be used in this document to describe multiple elements, components, regions, layers, and / or segments, these elements, components, regions, layers, and / or segments should not be limited by these terms. These terms may be used only to distinguish one element, component, region, layer, or segment from another. Unless the context clearly indicates otherwise, terms such as "first," "second," and other numerical terms used herein do not imply order or sequence. Therefore, the first element, component, region, layer, or segment discussed below may be referred to as the second element, component, region, layer, or segment without departing from the teachings of the exemplary embodiments.
[0025] For ease of description, spatial relative terms may be used in the text to describe the relationship of one element or feature relative to another element or feature, as shown in the figure. These relative terms include, for example, "inside," "outside," "middle," "outer," "below," "below," "above," "over," etc. Such spatial relative terms are intended to include different orientations of the device in use or operation, other than those depicted in the figure. For example, if the device in the figure is flipped, an element described as "below other elements or features" or "below other elements or features" would subsequently be oriented as "above other elements or features" or "above other elements or features." Therefore, the example term "below" can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or in other directions), and the spatial relative descriptors used in the text will be interpreted accordingly.
[0026] Research has shown that advancements in photolithography technology over the past few decades have been one of the main drivers of the aggressive miniaturization of Dynamic Random Access Memory (DRAM). However, due to the lack of photolithography tools that offer reasonable cost and high throughput, miniaturization has become increasingly difficult to sustain. To circumvent patterning issues and continue reducing chip size, a cell architecture using vertical transistors instead of traditional horizontal transistors has been proposed to further extend DRAM technology. However, in this architecture, the buried bit lines are formed before the deposited gate stack and capacitor annealing, inevitably subjecting them to the heat generated during the high-temperature gate oxidation process and capacitor annealing heat treatment, which can easily lead to bit line degradation and thus affect the performance of the DRAM device. Therefore, this application provides a semiconductor device and its fabrication method to improve the performance of the semiconductor device.
[0027] As shown in Figure 1, according to an embodiment of this application, a semiconductor device 1 is proposed, including a substrate 11 and a bit line structure 12. The bit line structure 12 is formed on the substrate 11. The bit line structure 12 includes a first portion 121 and a second portion 122. The second portion 122 is located on the side of the first portion 121 away from the substrate 11. The first portion 121 includes silicide and carbon dopant, and the second portion 122 includes silicide.
[0028] In the semiconductor device 1 provided in this application, a bit line structure 12 is formed on a substrate 11. The bit line structure 12 includes a first portion 121 and a second portion 122. The first portion 121 includes silicide and carbon dopant. The carbon dopant is located inside and / or on the surface of the first portion 121. The carbon dopant makes the first portion 121 have high thermal stability, thereby reducing the adverse effects of high temperatures during the fabrication of subsequent films on the bit line structure 12 and reducing the degradation of the bit line structure 12. The second portion 122 is made of silicon and does not include carbon dopant or silicide, thereby facilitating the subsequent epitaxial growth of subsequent films. The bit line structure 12 of this semiconductor device 1 is not easily degraded after heating, and its thermal stability is greatly improved, thereby significantly improving the performance of the semiconductor device 1.
[0029] Specifically, the substrate 11 may include silicon or silicon-germanium material doped with N-type ions.
[0030] Specifically, as shown in Figure 2, the bit line structure 12 can be a strip structure extending along the thickness direction of the substrate 11.
[0031] In one feasible implementation, as shown in FIG1, an isolation layer 13 is also included, which is located between the bit line structure 12 and the substrate 11.
[0032] In the above embodiments, by forming an isolation layer 13 between the bit line structure 12 and the substrate 11, the isolation between the bit line structure 12 and the substrate 11 can be achieved. The isolation layer 13 is used to protect the substrate 11 and prevent the bit line structure 12 from causing adverse effects on the substrate 11 during the fabrication process.
[0033] In one feasible implementation, as shown in FIG1, there are multiple bit line structures 12, which are spaced apart, and there are multiple isolation layers 13, which correspond one-to-one with the bit line structures 12.
[0034] In the above embodiments, the semiconductor device 1 may include a plurality of bit line structures 12, which are spaced apart on the substrate 11 to avoid mutual interference. There are a plurality of isolation layers 13, which may be made of the same material as the substrate 11, and the isolation layers 13, the substrate 11, and the bit line structures 12 may be an integral structure.
[0035] The isolation layer 13 corresponds one-to-one with the bit line structure 12. On the one hand, it realizes the isolation between each bit line structure 12 and the substrate 11, reducing the adverse effects of each bit line on the substrate 11 during the fabrication process. On the other hand, multiple isolation layers 13 are arranged at intervals to isolate adjacent isolation layers 13 and prevent the bit line structures 12 corresponding to adjacent isolation layers 13 from affecting each other.
[0036] In one feasible implementation, as shown in FIG3, the semiconductor device 1 further includes a transistor 14, the transistor 14 including a source region 141, a drain region 142 and a channel region 143, the source region 141 being integrally formed with the bit line structure 12, the channel region 143 being located on the side of the second portion 122 away from the substrate 11 and the channel region 143 being in contact with the second portion 122, and the drain region 142 being located on the side of the channel region 143 away from the substrate 11.
[0037] In the above embodiment, transistor 14 is a vertical transistor 14, including a source region 141, a channel region 143, and a drain region 142 formed on substrate 11. The source region 141 and bit line structure 12 can be integrally formed, that is, the bit line structure 12 and the source region 141 are reused. The channel region 143 is located on the side of bit line structure 12 away from substrate 11 and is in contact with the second portion 122 in bit line structure 12. Since the second portion 122 includes silicon, the channel region 143 and the drain region 142 can be epitaxially grown above the second portion 122.
[0038] Specifically, the semiconductor device 1 may be a storage semiconductor device 1, which may include a transistor 14 and a capacitor 21 connected to the transistor 14. The transistor 14 also includes a gate, which may be disposed around the channel region 143. The semiconductor device 1 also includes a word line, which is connected to the gate. The gate is fabricated using a high-temperature oxidation process. The first portion 121 of the bit line structure 12 includes silicide and carbon dopant. The carbon dopant makes the first portion 121 have high thermal stability, thereby reducing the adverse effects of the high temperature during the fabrication of the gate on the bit line structure 12.
[0039] In semiconductor device 1, capacitor 21 is formed on the side of drain region 142 away from substrate 11. Capacitor 21 is annealed. The first part 121 of bit line structure 12 includes silicide and carbon dopant. The carbon dopant makes the first part 121 have high thermal stability, thereby reducing the adverse effects of high temperature during gate fabrication on bit line structure 12.
[0040] In one feasible implementation, as shown in FIG3, the semiconductor device 1 further includes a barrier layer 15 located on the substrate 11. The barrier layer 15 is disposed adjacent to the isolation layer 13 and the barrier layer 15 is in contact with the sidewall of the isolation layer 13. The barrier layer 15 and the isolation layer 13 have the same thickness.
[0041] In the above embodiments, the semiconductor device 1 further includes a barrier layer 15, which is used to cover the area in the substrate 11 where the bit line structure 12 is not provided, so as to avoid the bit line structure 12 causing adverse effects on the area in the substrate 11 not covered by the bit line structure 12 during the fabrication process.
[0042] This application also provides a method for fabricating a semiconductor device 1, as shown in Figure 4, including:
[0043] S200, as shown in Figure 5, provides a semiconductor substrate 16.
[0044] Specifically, the semiconductor substrate 16 includes a base, which may include silicon, germanium, or a silicon-germanium alloy. The base is implanted with N-type impurities and activated to form the semiconductor substrate 16. N-type impurities can be implanted into the base using ion implantation or in-situ doping processes, wherein the ion implantation process includes, but is not limited to, advanced ion implantation processes such as cold implantation.
[0045] S400, as shown in FIG6, the semiconductor substrate 16 is patterned to form a substrate 11 and a bit line forming portion 17 located on one side of the substrate 11. The bit line forming portion 17 includes a first forming portion 171 and a second forming portion 172 located on the side of the first forming portion 171 away from the substrate 11.
[0046] Specifically, the semiconductor substrate 16 can be patterned using a photolithography process. The bit line forming portion 17 can be a strip-shaped structure extending along the thickness direction perpendicular to the substrate 11.
[0047] S600, as shown in FIG7, a protective structure 18 is formed on the surface of the second molding portion 172 away from the substrate 11 of the semiconductor and on the side surface of the second molding portion 172.
[0048] Specifically, the first molding part 171 is used to form the first portion 121 in the bit line structure 12, and the second molding part 172 is used to form the second portion 122 in the bit line structure 12. The protective structure 18 is used to protect the second molding part 172 to prevent subsequent manufacturing processes of the first molding part 171 from affecting it.
[0049] S800, as shown in FIG8, a carbon structure layer 19 is formed, the carbon structure layer 19 is in contact with at least the side of the first molding part 171, and the carbon structure layer 19 includes a contact surface that contacts the first molding part 171.
[0050] S1000, as shown in FIG9, a bit line metal layer 20 is formed, and the bit line metal layer 20 is in contact with at least one side of the contact surface away from the first forming part 171.
[0051] Specifically, the material of the bit line metal layer 20 includes cobalt, or the material of the bit line metal layer 20 includes cobalt and titanium.
[0052] S1200, the alignment line forming part 17 is heat-treated so that the first forming part 171 becomes the first part 121 and the second forming part 172 becomes the second part 122. The first part 121 includes silicide and carbon dopant, and the second part 122 includes silicon.
[0053] In the method for fabricating the semiconductor device 1 provided in this application, a carbon structure layer 19 and a bit line metal layer 20 are formed on the side of the second forming portion 172, and the bit line forming portion 17 is heat-treated to form silicide. The presence of the carbon structure layer 19 can isolate the second forming portion 172 and the bit line metal layer 20, thereby preventing the second forming portion 172 from directly contacting the bit line metal layer 20 and forming oxides. The provision of the carbon structure layer 19 can suppress the formation of oxides between the second forming portion 172 and the bit line metal layer 20, resulting in better thermal stability of the first portion 121 formed after the heat treatment of the second forming portion 172. During the annealing process, the material of the first forming portion 171 reacts with the bit line metal to form silicide, and the carbon structure layer 19 is located within or on the surface of the silicide, forming a carbon dopant. Meanwhile, the second forming part 172 is protected by the protective structure 18 to prevent the second forming part 172 from contacting the carbon structure layer 19 and the bit line metal layer 20, so as to prevent the silicon material of the second forming part 172 from changing after heat treatment and forming silicide, so as to facilitate the subsequent generation of subsequent film layers by epitaxial growth.
[0054] Specifically, heat treatment includes rapid thermal annealing, laser annealing, etc.
[0055] In one feasible implementation, a carbon structural layer 19 is formed by a deposition process.
[0056] Specifically, the thickness of the carbon structure layer 19 is H, where 1 nm ≤ H ≤ 2 nm.
[0057] Specifically, the thickness of the carbon structure layer 19 can be 1 nm, 1.1 nm, 1.2 nm, 1.5 nm, 1.8 nm, 1 nm, 1.9 nm, 2 nm, etc.
[0058] In the above embodiment, if the thickness of the carbon structure layer 19 is too thin, it cannot achieve a good effect of isolating the first molding part 171 from the bit line metal layer 20; if it is too thick, it will affect the formation of silicide. When the thickness of the carbon structure layer 19 is 1 nm to 2 nm, both the isolation effect of the first molding part 171 from the bit line metal layer 20 and the silicide formation effect can be achieved.
[0059] In one feasible implementation, the bit line metal layer 20 is formed by a chemical vapor deposition process.
[0060] Traditional physical vapor deposition (PVD) processes result in poor coverage of the step locations for the bit line metal layer 20, making it difficult to form uniform silicides subsequently. In the embodiments provided in this application, chemical vapor deposition (CVD) is used to form the bit line metal layer 20, which improves the uniformity of the bit line metal layer 20 and provides stronger coverage of the step locations.
[0061] In one feasible embodiment, as shown in Figures 7 to 9, the bit line forming portion 17 further includes an isolation forming portion 173 located between the first forming portion 171 and the substrate 11; the method for fabricating the semiconductor device 1 further includes:
[0062] A barrier layer 15 is formed on the substrate 11 between adjacent isolation molding portions 173, and the barrier layer 15 has the same thickness as the isolation molding portion 173.
[0063] The alignment line forming part 17 is heat-treated, and the isolation forming part 173 becomes the isolation layer 13.
[0064] In the above embodiment, the isolation molding portion 173 and the bit line molding portion 17 are formed simultaneously, thereby simplifying the manufacturing process. After heat treatment, the isolation molding portion 173 becomes the isolation layer 13. The isolation molding portion 173 is used to isolate the substrate 11 from the first molding portion 171, preventing the first molding portion 171 from adversely affecting the substrate 11 during heat treatment. Specifically, a carbon structure layer 19 is formed on the sidewall of the first molding portion 171, and a bit line metal layer 20 is formed on the side surface of the carbon structure layer 19 facing away from the first molding portion 171. During heat treatment, the bit line metal layer 20 reacts with the silicon material within the first molding portion 171 to form a silicide. The carbon structure layer 19 is located within or on the surface of the silicide, thus making the first molding portion 171 the first part 121. The isolation molding portion 173 can prevent the bit line metal layer 20 and other materials from penetrating downwards from the first molding portion 171 and reacting with the substrate 11, thereby protecting the substrate 11. In the above embodiment, a barrier layer 15 is formed between adjacent isolation molding portions 173. The barrier layer 15 is used to cover the portion of the substrate 11 not covered by the isolation molding portion 173 and to cover the sidewall of the isolation molding portion 173. This prevents the carbon structure layer 19 and / or the bit line metal layer 20 from contacting the substrate 11 and the isolation molding portion 173 during the formation of the carbon structure layer 19 and the bit line metal layer 20, thereby protecting the substrate 11 and the isolation molding portion 173. This also prevents the formation of silicides in the isolation molding portion 173 and the substrate 11 during the heat treatment process, i.e., prevents changes in the properties of the isolation molding portion 173 and the substrate 11.
[0065] In one feasible implementation, as shown in FIG8, the carbon structure layer 19 covers the side surface of the protective structure 18 opposite to the second molding portion 172 and the side surface of the barrier layer 15 opposite to the substrate 11.
[0066] In the above embodiment, because the barrier layer 15 is provided, the carbon structure layer 19 can be fabricated on its entire surface during the fabrication process. This allows the carbon structure layer 19 to partially cover the side surface of the protective structure 18 facing away from the second molding portion 172, partially cover the side surface of the barrier layer 15 facing away from the substrate 11, and most importantly, partially cover the side surface of the first molding portion 171. Fabricating the carbon structure layer 19 on its entire surface simplifies the fabrication process.
[0067] In one feasible implementation, as shown in FIG9, the bit line metal layer 20 covers the side surface of the carbon structure layer 19 facing away from the substrate 11 and the side surface of the carbon structure layer 19 facing away from the bit line forming portion 17.
[0068] In the above embodiment, because the barrier layer 15 is provided, the bit line metal layer 20 can be fabricated on its entire surface during fabrication. This allows the bit line metal layer 20 to partially cover the side surface of the carbon structure layer 19 facing away from the bit line forming portion 17, and partially cover the side surface of the carbon structure layer 19 facing away from the substrate 11. Most importantly, the portion of the bit line metal layer 20 covers the side surface of the carbon structure layer 19 facing away from the first forming portion 171. Fabricating the bit line metal layer 20 on its entire surface simplifies the fabrication process.
[0069] The above are merely preferred embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.
Claims
1. A semiconductor device, characterized in that, include: Substrate; Bit line structures are formed on the substrate, the bit line structures include a first portion and a second portion, the second portion being located on the side of the first portion away from the substrate, the first portion including silicide and carbon dopant, and the second portion including silicon.
2. The semiconductor device according to claim 1, characterized in that, It also includes an isolation layer located between the bit line structure and the substrate.
3. The semiconductor device according to claim 2, characterized in that, The number of bit line structures is multiple, and the multiple bit line structures are arranged at intervals. The number of isolation layers is multiple, and the isolation layers correspond one-to-one with the bit line structures.
4. The semiconductor device according to claim 3, characterized in that, It also includes a transistor, which includes a source region, a drain region, and a channel region. The source region is integrally formed with the bit line structure. The channel region is located on the side of the second portion away from the substrate and is in contact with the second portion. The drain region is located on the side of the channel region away from the substrate.
5. The semiconductor device according to claim 3, characterized in that, It also includes a barrier layer located on the substrate, the barrier layer being disposed adjacent to the isolation layer and in contact with the sidewall of the isolation layer, the barrier layer and the isolation layer having the same thickness.
6. A method for fabricating a semiconductor device, characterized in that, include: Provide semiconductor substrates; The semiconductor substrate is patterned to form a substrate and a bit line forming portion located on one side of the substrate, the bit line forming portion including a first forming portion and a second forming portion located on the side of the first forming portion away from the substrate; A protective structure is formed on the surface of the second forming part away from the substrate of the semiconductor and on the side surface of the second forming part; A carbon structure layer is formed, the carbon structure layer being in contact with at least the side surface of the first molding part, the carbon structure layer including a contact surface that contacts the first molding part; A bit line metal layer is formed, wherein the bit line metal layer is in contact with at least one side of the contact surface away from the first forming part; The bit line forming portion is heat-treated to make the first forming portion become the first part and the second forming portion become the second part. The first part includes silicide and carbon dopant, and the second part includes silicon.
7. The method for fabricating a semiconductor device according to claim 6, characterized in that, The thickness of the carbon structure layer is H, where 1 nm ≤ H ≤ 2 nm.
8. The method for fabricating a semiconductor device according to claim 6, characterized in that, The bit line metal layer is formed by chemical vapor deposition.
9. The method for fabricating a semiconductor device according to claim 6, characterized in that, The bit line forming section further includes an isolation forming section located between the first forming section and the substrate; The method for fabricating the semiconductor device further includes: A barrier layer is formed on the substrate between adjacent isolation molding portions, the barrier layer having the same thickness as the isolation molding portion; The bit line forming part is heat-treated, and the isolation forming part becomes an isolation layer.
10. The method for fabricating a semiconductor device according to claim 9, characterized in that, The carbon structure layer covers the side surface of the protective structure opposite to the second molding part and the side surface of the barrier layer opposite to the substrate.
11. The method for fabricating a semiconductor device according to claim 9, characterized in that, The bit line metal layer covers the side surface of the carbon structure layer opposite to the substrate and the side surface of the carbon structure layer opposite to the bit line forming portion.
12. The method for fabricating a semiconductor device according to claim 6, characterized in that, The material of the bit line metal layer includes cobalt, or the material of the bit line metal layer includes cobalt and titanium.