LDO circuit and method for mitigating output overshoot

Abstract

Disclosed in the present invention are an LDO circuit and method for mitigating output overshoot. The LDO circuit comprises a comparator. A first amplifier is connected to a low static power consumption circuit by means of a first NMOS transistor; a first voltage-dividing sampling resistor and a second voltage-dividing sampling resistor are connected to the low static power consumption circuit and generate a feedback voltage; the comparator is connected to the low static power consumption circuit by means of a fourth PMOS transistor, and compares a second reference voltage and a driving voltage that are generated inside a circuit, to control the turning-on and turning-off of a fourth PMOS transistor switch controller; on the basis of a first reference voltage and the feedback voltage, the first amplifier outputs a first voltage signal, and outputs the driving voltage by means of the first NMOS transistor and the low static power consumption circuit; on the basis of an external input voltage and the driving voltage, a second PMOS transistor generates and controls an output voltage; and the driving voltage is modulated by means of a comparator circuit to control a power transistor, so as to mitigate output voltage overshoot during slow start-up under no-load conditions and output voltage overshoot during no-load hot-swapping.

Description

An LDO circuit and method for improving output overcharge Technical Field

[0001] This invention relates to the field of power management chip technology, and in particular to an LDO circuit and method for improving output overcharging. Background Technology

[0002] Please refer to Figure 2, which shows a static power LDO circuit in the prior art. As shown in Figure 2, the circuit may include a circuit input terminal, a circuit output terminal and a ground terminal, a first amplifier, a second amplifier, a third amplifier, a PMOS transistor M3 and an output sampling module.

[0003] When the external input voltage is lower than the preset output voltage, the output voltage of the circuit will decrease as the input voltage decreases. At this time, the first sampling signal decreases, the gate voltage of M1 increases, and the gate voltage of M3 decreases, placing PMOS transistor M3 in the linear region. The third amplifier, based on the drain voltage of M2 and the output voltage, outputs the gate voltage of M4, ensuring that the source voltage of M4 changes with the output voltage and has the same value. At this time, PMOS transistor M2 is in the linear region, and the gate, drain, and source voltages of PMOS transistor M2 are equal to those of PMOS transistor M3. The current IM2 of PMOS transistor M2 and the current IM3 of PMOS transistor M3 are mirror images of each other.

[0004]

[0005] Wherein, the preset voltage at the output terminal is greater than or equal to the first reference signal, IM2 is the current of PMOS transistor M2, IM3 is the current of PMOS transistor M3, (W / L)M2 is the width-to-length ratio of PMOS transistor M2, and (W / L)M3 is the width-to-length ratio of PMOS transistor M3; so that when the input voltage is lower than the preset voltage at the output terminal, the current of PMOS transistor M2 is:

[0006]

[0007] This avoids increased static power consumption in the circuit due to current mirror mismatch.

[0008] Those skilled in the art will understand that the above has very high application value in the fields of low power consumption and lithium batteries, manifested in the following way: when VIN is low, M2 is limited by M4, preventing the increase in static power consumption caused by current mirror mismatch. Currently, to improve response data and load capacity, the second-stage amplifier of low-power LDOs on the market typically uses a P-tube current mirror to replicate the power transistor's current; however, the aforementioned prior art has the following drawbacks:

[0009] Under no-load conditions, when VIN is low, the overall current is small, meaning the op-amp's response speed is slow, which can lead to VOUT overcharging, including:

[0010] During a slow start-up of VIN, VOUT may become overcharged.

[0011] When VIN is hot-swapped with residual charge, VOUT may become overcharged. Summary of the Invention

[0012] In view of the above-mentioned shortcomings in the current power management chip technology field, the present invention provides an LDO circuit and method to improve output overcharging and prevent output voltage overcharging during no-load, slow start-up and hot-plugging with residual power.

[0013] To achieve the above objectives, the embodiments of the present invention adopt the following technical solutions:

[0014] An LDO circuit for improving output overcharge includes: a first amplifier, a first NMOS transistor, a second PMOS transistor, a low quiescent power circuit, a fourth PMOS transistor, a first voltage divider sampling resistor and a second voltage divider sampling resistor, and an external input voltage. First reference voltage and output voltage The first amplifier is connected to a low static power circuit via a first NMOS transistor. The first and second voltage-dividing sampling resistors are connected to the low static power circuit and generate a feedback voltage. The system is characterized by further including a comparator, wherein the comparator is connected to the low static power circuit via a fourth PMOS transistor and compares a second reference voltage generated internally with a drive voltage to control the switching on and off of the fourth PMOS transistor. The first amplifier outputs a first voltage signal based on the first reference voltage and the feedback voltage, and outputs a drive voltage through the first NMOS transistor and the low static power circuit. The second PMOS transistor generates and controls the output voltage based on the external input voltage and the drive voltage. The power transistor is controlled by modulating the drive voltage through the comparator circuit.

[0015] According to one aspect of the present invention, the first NMOS transistor is a common-source amplifier with its source grounded, its drain connected to the drain of the fourth PMOS transistor and the low static power circuit, and its gate connected to the output terminal of the first amplifier. Based on the first voltage signal and the bias current provided by the low static power, it outputs a gate drive voltage. The source of the second PMOS transistor is connected to an external input voltage, its gate is connected to the low static power circuit, and its drain is connected to a first voltage divider sampling resistor.

[0016] According to one aspect of the present invention, the low static power consumption circuit includes a first PMOS transistor, a third PMOS transistor, and a second amplifier. The source of the first PMOS transistor is connected to the source of the second PMOS transistor and is connected to an external input voltage. The gate of the first PMOS transistor is connected to the gate of the second PMOS transistor, and the drain of the third PMOS transistor is connected to the source of the third PMOS transistor. The source of the third PMOS transistor is connected to the drain of the first PMOS transistor and the input terminal of the second amplifier. The gate of the third PMOS transistor is connected to the output terminal of the second amplifier, and the drain of the fourth PMOS transistor and the drain of the first PMOS transistor are connected.

[0017] According to one aspect of the present invention, the second amplifier and the third PMOS transistor constitute a buffer, and the drain of the first PMOS transistor is controlled to follow the output voltage based on the output voltage, so as to avoid the increase of circuit static power consumption due to current mirror mismatch.

[0018] According to one aspect of the present invention, the source of the fourth PMOS transistor is connected to the source of the third PMOS transistor, the drain is connected to the driving voltage, and the gate is connected to the output terminal of the comparator. When the fourth PMOS transistor is turned on, it rapidly pulls up the driving voltage.

[0019] According to one aspect of the present invention, a negative feedback loop is formed by the first amplifier, the first NMOS transistor, the bias current provided by the low quiescent power circuit, the second PMOS transistor, the first sampling voltage divider resistor, and the second sampling voltage divider resistor. One end of the first voltage divider sampling resistor is connected to the drain of the low quiescent power circuit and the second PMOS transistor, and the other end of the first voltage divider sampling resistor is connected to one end of the second voltage divider sampling resistor and outputs a feedback voltage signal. The other end of the second voltage divider sampling resistor is grounded. The negative feedback loop makes the first reference voltage and the feedback voltage consistent, and then the output voltage is set through the first sampling voltage divider resistor and the second sampling voltage divider resistor. The output voltage is: .

[0020] A method for improving slow-start output overcharge under no-load conditions, the method comprising the following steps: a comparator is connected to a low quiescent power circuit via a fourth PMOS transistor and compares a second reference voltage and a drive voltage to control the switching on and off of the fourth PMOS transistor; a first amplifier outputs a first voltage signal based on a first reference voltage and a feedback voltage, and outputs a drive voltage through a first NMOS transistor and the low quiescent power circuit; a second PMOS transistor generates and controls the output voltage based on an external input voltage and a drive voltage.

[0021] According to one aspect of the present invention, during no-load slow start-up, when the external input voltage exceeds the minimum operating voltage, the negative feedback loop pulls the drive voltage down to the point where the power transistor is fully on. The drive voltage is then lower than the second reference voltage, and the comparator outputs a high level, while the fourth PMOS transistor is in the off state. When the external input voltage is about to exceed the output voltage set by the first and second sampling voltage divider resistors, the negative feedback loop begins to pull the drive voltage up. The comparator detects that the drive voltage is higher than the second reference voltage and outputs a low level, turning on the fourth PMOS transistor, thus rapidly adjusting the power transistor.

[0022] A method for improving hot-swappable output overcharge under no-load residual current includes the following steps: a comparator is connected to a low quiescent power circuit via a fourth PMOS transistor and compares a second reference voltage with a drive voltage to control the switching on and off of the fourth PMOS transistor; a first amplifier outputs a first voltage signal based on a first reference voltage and a feedback voltage, and outputs a drive voltage through a first NMOS transistor and the low quiescent power circuit; a second PMOS transistor generates and controls the output voltage based on an external input voltage and a drive voltage.

[0023] According to one aspect of the present invention, under the condition of hot-swapping and disconnection of the external input voltage, when the external input voltage is lower than the output voltage set by the first and second sampling voltage divider resistors, the negative feedback loop pulls the drive voltage down to the point where the power transistor is fully on. The drive voltage is then lower than the second reference voltage, and the comparator outputs a high level, while the fourth PMOS transistor is in the off state. When the external input voltage is hot-swapped and powered on, the feedback loop starts to pull the drive voltage up and makes it higher than the second reference voltage. Upon detection, the comparator outputs a low level and turns on the fourth PMOS transistor, allowing the power transistor to be quickly regulated and improving the output voltage overcharging.

[0024] Advantages of this invention: This invention connects a first amplifier to a low quiescent power circuit via a first NMOS transistor. A first voltage divider sampling resistor and a second voltage divider sampling resistor are connected to the low quiescent power circuit to generate a feedback voltage. A comparator is connected to the low quiescent power circuit via a fourth PMOS transistor and compares a second reference voltage generated internally with a drive voltage to control the switching on and off of the fourth PMOS transistor. The first amplifier outputs a first voltage signal based on the first reference voltage and the feedback voltage, and outputs a drive voltage through the first NMOS transistor and the low quiescent power circuit. The second PMOS transistor generates and controls the output voltage based on the external input voltage and the drive voltage. The comparator circuit modulates the drive voltage to control the power transistor, thereby improving output voltage overcharging during slow startup under no-load conditions and improving output voltage overcharging during hot-plugging under no-load conditions. Attached Figure Description

[0025] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0026] Figure 1 is a circuit structure diagram of an LDO circuit for improving output overcharge according to the present invention;

[0027] Figure 2 is a prior art circuit structure diagram of an LDO circuit for improving output overcharge according to the present invention;

[0028] Figure 3 shows the no-load hot-swap simulation effect of an LDO circuit for improving output overcharge according to the present invention.

[0029] Figure 4 shows the simulation effect of slow start-up of an LDO circuit with no-load external input voltage according to the present invention to improve output overcharge.

[0030] Figure 5 is a diagram showing the effect of the static current of an LDO circuit for improving output overcharge as described in this invention varies with the external input voltage.

[0031] Figure 6 shows the no-load hot-plug simulation effect of an LDO circuit for improving output overcharge described in this invention without a comparator circuit.

[0032] Figure 7 is a simulation diagram of the slow start-up effect of an LDO circuit for improving output overcharge without a comparator circuit under no-load external input voltage according to the present invention.

[0033] Figure 8 is a fourth embodiment of an LDO circuit for improving output overcharge according to the present invention;

[0034] Figure 9 is a fifth embodiment of an LDO circuit for improving output overcharge according to the present invention. Detailed Implementation

[0035] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0036] Example 1:

[0037] As shown in Figure 1, an LDO circuit for improving output overcharge includes: a first amplifier and a first NMOS transistor. Second PMOS transistor Low static power consumption circuit, fourth PMOS transistor switch First voltage divider sampling resistor Second voltage divider sampling resistor and comparator, and external input voltage Power supply, ground voltage GND, first reference voltage and output voltage The first amplifier is connected to a low quiescent power circuit via a first NMOS transistor. The first and second voltage-dividing sampling resistors are connected to the low quiescent power circuit and generate a feedback voltage. The first amplifier is based on a first reference voltage. and feedback voltage Output voltage control signal . This is a common-source amplifier, with the source grounded and the drain connected to ground. The drain and the low static power circuit, the gate is connected to the output of the first amplifier, and based on The bias current provided by low quiescent power consumption, and the output gate drive voltage . The gate is connected to the output of the comparator, and the drain is connected to... The drain is connected to the low static power circuit, and the source is connected to the low static power circuit. The source is connected to an external input voltage, the gate is connected to the low static power circuit, and the drain is connected to the... , Based on external input voltage and driving voltage Control output voltage Size. One end is connected to the low static power consumption circuit and The drain electrode, The other end connects One end is connected to a feedback voltage signal ; The other end is grounded. First amplifier, The bias current provided by the low static power circuit , and The resulting loop forms a negative feedback loop, which causes the reference voltage to... and feedback voltage Consistency, then approval and Set output voltage The output voltage is: The output voltage set by the voltage divider resistors is the preset output voltage. The comparator is based on a second reference voltage generated internally by a circuit. and driving voltage Compare and control the switch The circuitry includes the ability to turn the circuit on and off. The low static power consumption circuitry includes... , Second amplifier, Source access The source is connected to an external input voltage, and the gate is connected to... The gate and drain are connected , The source pole; Source access The drain of the second amplifier and the input terminal of the second amplifier are controlled. The gate is connected to the output terminal of the second amplifier, and the drain is connected to... Drain and The drain of the amplifier. The second amplifier and... Construct a buffer based on the output voltage and control Drain follows output voltage This avoids increased static power consumption in the circuit due to current mirror mismatch.

[0038] No load Slow startup in progress Slow ascent, when Once the minimum operating voltage is exceeded, the negative feedback loop will... Pull the power transistor low until it is fully on. At this point... Voltage lower than The comparator outputs a high level, and the switch... It is in a closed state. For low, Rise, and then follow Rise; when When the voltage is about to exceed the preset output voltage, the negative feedback loop begins to slowly increase. Voltage; when The voltage has increased, but not yet reached the level limiting the power transistor's regulation. During the process, the comparator detected Voltage higher than When the comparator outputs a low level, it will switch... Open, make Becoming a load with a gate-drain connection greatly enhances pipe pull-up The ability, that is, to quickly When the voltage is pulled up, the power transistor is rapidly regulated, then when Higher than the preset At that time, since the power transistor has been adjusted, then Overcharging issues have been greatly improved.

[0039] Under the condition of unloaded hot-swappable external input voltage removal, when the aforementioned Later, when Lower than preset Then, the negative feedback loop pulls down This causes the power transistor to be fully open, and makes follow Descending; at this time, Voltage lower than The comparator outputs a high level, and the switch... In a closed state; when When hot-swapping is performed and powered on, the negative feedback loop starts to go high. Voltage; when The voltage has increased, but not yet reached the level limiting the power transistor's regulation. During the process, the comparator detected Voltage higher than When the comparator outputs a low level, it will switch... Open, make Becoming a load with a gate-drain connection greatly enhances pipe pull-up The ability, that is, to quickly A voltage surge causes the power transistor to be rapidly regulated, mitigating output voltage overcharging. Therefore, when... Higher than the preset At that time, because the power transistor is adjusted, then The overcharging situation has been greatly improved. The no-load conditions include the case where no load is connected, and the case where the load is connected to the output voltage but the switch turns the load off.

[0040] As shown in Figure 3, Under the condition of inconsistent residual hot-plug speed, The change. When removed Then, it is powered by the input capacitor. Since the LDO has low and constant static power consumption under no-load conditions, The manifestation is a uniform power loss; the above-mentioned hot-swap overcharging, when When the residual voltage is higher than 3.24V, the negative feedback op-amp is still in normal regulation state, so Unchanged; when Below 3.24V, Followers began to appear The decrease; the above simulation results When powered on at a speed of 3µs, When it falls to the 2.99-3.24V range, Overcharging may occur, and The closer to the preset When the overcharge is greater, as shown in the figure above, Maximum overcharge: 3.4V (normal) At 4.3V, =3.25V).

[0041] As shown in Figure 4, The voltage increases from 0V to 4.3V at a rate of 10ms. Overcharge is minimal, with a maximum overcharge amplitude of 3.256V. The overcharge duration is approximately 27ms before returning to the preset value. .

[0042] As shown in Figure 5, the horizontal axis is... The vertical axis represents the quiescent current of the entire LDO circuit. At 3.25V, IQ is at its maximum, reaching 1.54uA (normal). At 4.3V, IQ = 748nA.

[0043] As shown in Figure 6, The residual current hot-plugging conditions are the same as in Figure 3, but due to the lack of a comparison circuit, the circuit response speed is slow. After overcharging, the power transistor remains off until... Falling to the preset Later, the power transistor is released only after the negative feedback, so in the simulation diagram, After overcharging, it will last for 3-4 seconds.

[0044] As shown in Figure 7, The voltage increases from 0V to 4.3V at a rate of 10ms. An overcharge occurred, with a maximum overcharge voltage of 3.33V. The overcharge lasted for approximately 421ms before returning to the preset voltage. .

[0045] By changing some of the structures in this embodiment, the new embodiment can achieve the same function and effect.

[0046] Advantages of this invention: This invention connects a first amplifier to a low quiescent power circuit via a first NMOS transistor. A first voltage divider sampling resistor and a second voltage divider sampling resistor are connected to the low quiescent power circuit to generate a feedback voltage. A comparator is connected to the low quiescent power circuit via a fourth PMOS transistor and compares a second reference voltage generated internally with a drive voltage to control the switching on and off of the fourth PMOS transistor. The first amplifier outputs a first voltage signal based on the first reference voltage and the feedback voltage, and outputs a drive voltage through the first NMOS transistor and the low quiescent power circuit. The second PMOS transistor generates and controls the output voltage based on the external input voltage and the drive voltage. The comparator circuit modulates the drive voltage to control the power transistor, thereby improving output voltage overcharging during slow startup under no-load conditions and improving output voltage overcharging during hot-plugging under no-load conditions.

[0047] Example 2:

[0048] As shown in Figure 1, a method for improving slow start-up output overcharge under no-load conditions is presented. This embodiment is based on the LDO circuit of Embodiment 1. The specific method steps of this embodiment are as follows:

[0049] S1: Under no-load conditions Slow startup in progress Slow ascent, when Once the minimum operating voltage is exceeded, the negative feedback loop will... Pull the power transistor low until it is fully on. At this point... Voltage lower than The comparator outputs a high level, and the switch... It is in a closed state. For low, Rise, and then follow rise.

[0050] S2: When The voltage is about to be higher than the preset value. When the voltage is high, the negative feedback loop begins to slowly increase. Voltage.

[0051] S3: When The voltage has increased, but not yet reached the level limiting the power transistor's regulation. During the process, the comparator detected Voltage higher than When the comparator outputs a low level, it will switch... Open, make Becoming a load with a gate-drain connection greatly enhances pipe pull-up The ability, that is, to quickly When the voltage is pulled up, the power transistor is rapidly regulated, then when Higher than the preset At that time, since the power transistor has been adjusted, then Overcharging issues have been greatly improved.

[0052] By replacing or modifying parts of the LDO circuit structure in this embodiment, new LDO circuit structures can be obtained, with the new embodiments having the same function and effect. For example, the comparator circuit was modified in Embodiment 4. The comparator circuit was modified in Embodiment 5.

[0053] As shown in Figure 3, Under the condition of inconsistent residual hot-plug speed, The change. When removed Then, it is powered by the input capacitor. Since the LDO has low and constant static power consumption under no-load conditions, The manifestation is a uniform power loss; the above-mentioned hot-swap overcharging, when When the residual voltage is higher than 3.24V, the negative feedback op-amp is still in normal regulation state, so Unchanged; when Below 3.24V, Followers began to appear The decrease; the above simulation results When powered on at a speed of 3µs, When it falls to the 2.99-3.24V range, Overcharging may occur, and The closer to the preset When the overcharge is greater, as shown in the figure above, Maximum overcharge: 3.4V (normal) At 4.3V, =3.25V).

[0054] As shown in Figure 4, The voltage increases from 0V to 4.3V at a rate of 10ms. Overcharge is minimal, with a maximum overcharge amplitude of 3.256V. The overcharge duration is approximately 27ms before returning to the preset value. .

[0055] As shown in Figure 6, The residual current hot-plugging conditions are the same as in Figure 3, but due to the lack of a comparison circuit, the circuit response speed is slow. After overcharging, the power transistor remains off until... Falling to the preset Later, the power transistor is released only after the negative feedback, so in the simulation diagram, After overcharging, it will last for 3-4 seconds.

[0056] As shown in Figure 7, The voltage increases from 0V to 4.3V at a rate of 10ms. An overcharge occurred, with a maximum overcharge voltage of 3.33V. The overcharge lasted for approximately 421ms before returning to the preset voltage. .

[0057] Advantages of this invention: This invention connects a first amplifier to a low quiescent power circuit via a first NMOS transistor. A first voltage divider sampling resistor and a second voltage divider sampling resistor are connected to the low quiescent power circuit to generate a feedback voltage. A comparator is connected to the low quiescent power circuit via a fourth PMOS transistor and compares a second reference voltage generated internally with a drive voltage to control the switching on and off of the fourth PMOS transistor. The first amplifier outputs a first voltage signal based on the first reference voltage and the feedback voltage, and outputs a drive voltage through the first NMOS transistor and the low quiescent power circuit. The second PMOS transistor generates and controls the output voltage based on the external input voltage and the drive voltage. The comparator circuit modulates the drive voltage to control the power transistor, thereby improving output voltage overcharging during slow startup under no-load conditions and improving output voltage overcharging during hot-plugging under no-load conditions.

[0058] Example 3:

[0059] As shown in Figure 1, a method for improving the overcharging of hot-swappable output with residual charge under no-load conditions is presented in this embodiment, which is based on the LDO circuit of Embodiment 1. The specific steps of this embodiment are as follows:

[0060] S1: Hot-plugging under no-load conditions Under the condition of being pulled out, Slow ascent, when When the minimum operating voltage is exceeded, the negative feedback op-amp will... Pull the power transistor low until it is fully on. At this point... Voltage lower than The comparator outputs a high level, and the switch... It is in a closed state. For low, Rise, and then follow rise.

[0061] S2: When The voltage is about to be higher than the preset value. When the voltage is high, the negative feedback loop begins to slowly increase. Voltage.

[0062] S3: When The voltage has increased, but not yet reached the level limiting the power transistor's regulation. During the process, the comparator detected Voltage higher than When the comparator outputs a low level, it will switch... Open, make Becoming a load with a gate-drain connection greatly enhances pipe pull-up The ability, that is, to quickly A voltage surge causes the power transistor to be rapidly regulated, mitigating output voltage overcharging. Therefore, when... Higher than the preset At that time, since the power transistor has been adjusted, then Overcharging issues have been greatly improved.

[0063] By replacing or modifying parts of the LDO circuit structure in this embodiment, new LDO circuit structures can be obtained, with the new embodiments having the same function and effect. For example, the comparator circuit was modified in embodiment 4. The comparator circuit was modified in embodiment 5.

[0064] As shown in Figure 3, Under the condition of inconsistent residual hot-plug speed, The change. When removed Then, it is powered by the input capacitor. Since the LDO has low and constant static power consumption under no-load conditions, The manifestation is a uniform power loss; the above-mentioned hot-swap overcharging, when When the residual voltage is higher than 3.24V, the negative feedback op-amp is still in normal regulation state, so Unchanged; when Below 3.24V, Followers began to appear The decrease; the above simulation results When powered on at a speed of 3µs, When it falls to the 2.99-3.24V range, Overcharging may occur, and The closer to the preset When the overcharge is greater, as shown in the figure above, Maximum overcharge: 3.4V (normal) At 4.3V, =3.25V).

[0065] As shown in Figure 4, The voltage increases from 0V to 4.3V at a rate of 10ms. Overcharge is minimal, with a maximum overcharge amplitude of 3.256V. The overcharge duration is approximately 27ms before returning to the preset value. .

[0066] As shown in Figure 6, The residual current hot-plugging conditions are the same as in Figure 3, but due to the lack of a comparison circuit, the circuit response speed is slow. After overcharging, the power transistor remains off until... Falling to the preset Later, the power transistor is released only after the negative feedback, so in the simulation diagram, After overcharging, it will last for 3-4 seconds.

[0067] As shown in Figure 7, The voltage increases from 0V to 4.3V at a rate of 10ms. An overcharge occurred, with a maximum overcharge voltage of 3.33V. The overcharge lasted for approximately 421ms before returning to the preset voltage. .

[0068] Advantages of this invention: This invention connects a first amplifier to a low quiescent power circuit via a first NMOS transistor. A first voltage divider sampling resistor and a second voltage divider sampling resistor are connected to the low quiescent power circuit to generate a feedback voltage. A comparator is connected to the low quiescent power circuit via a fourth PMOS transistor and compares a second reference voltage generated internally with a drive voltage to control the switching on and off of the fourth PMOS transistor. The first amplifier outputs a first voltage signal based on the first reference voltage and the feedback voltage, and outputs a drive voltage through the first NMOS transistor and the low quiescent power circuit. The second PMOS transistor generates and controls the output voltage based on the external input voltage and the drive voltage. The comparator circuit modulates the drive voltage to control the power transistor, thereby improving output voltage overcharging during slow startup under no-load conditions and improving output voltage overcharging during hot-plugging under no-load conditions.

[0069] Example 4:

[0070] As shown in Figure 8, an LDO circuit for improving output overcharge includes: a first amplifier, , Low static power consumption circuits, switches , , Comparator, and external power supply Power supply, ground voltage GND, reference voltage and external output voltage The first amplifier is connected to a low quiescent power circuit via a first NMOS transistor. The first and second voltage-dividing sampling resistors are connected to the low quiescent power circuit and generate a feedback voltage. The first amplifier is based on a first reference voltage. and feedback voltage Output voltage control signal . This is a common-source amplifier, with the source grounded and the drain connected to ground. The drain and the low static power circuit, the gate is connected to the output of the first amplifier, and based on The bias current provided by low quiescent power consumption, and the output gate drive voltage . The gate is connected to the output of the comparator, and the drain is connected to... The drain is connected to the low static power circuit, and the source is connected to the low static power circuit. The source is connected to an external input voltage, the gate is connected to the low static power circuit, and the drain is connected to the... , Based on external input voltage and driving voltage Control output voltage Size. One end is connected to the low static power consumption circuit and The drain electrode, The other end connects One end is connected to a feedback voltage signal ; The other end is grounded. First amplifier, The bias current provided by the low static power circuit , and The resulting loop forms a negative feedback loop, which causes the reference voltage to... and feedback voltage Consistency, then approval and Set output voltage The output voltage is: The comparator controls the switch. The circuitry includes the ability to turn the circuit on and off. The low static power consumption circuitry includes... , Second amplifier, Source access The source is connected to an external input voltage, and the gate is connected to... The gate and drain are connected , The source pole; Source access The drain of the second amplifier and the input terminal of the second amplifier are controlled. The gate is connected to the output terminal of the second amplifier, and the drain is connected to... Drain and The drain of the amplifier. The second amplifier and... Construct a buffer based on the output voltage and control Drain follows output voltage This avoids increased static power consumption in the circuit due to current mirror mismatch.

[0071] In this embodiment, the comparator includes: , , , Current source , and . The source is grounded, and the gate and drain are connected. The source pole; Gate and drain connections The gate; source terminal Drain connection The gate; The drain is connected and The gate is connected to the source. .in , Based on current source Generate reference voltage Used for making Gate voltage; Based on current source , and Voltage, generates drain voltage ; Generate output voltage , As The switch control signal. When Overcharging is imminent, and negative feedback is pulling up the charge. During the process, when Detected Voltage higher than back, Turn off, If the voltage is high, then End, thus The voltage goes low, the switch If enabled, It was short-circuited.

[0072] No load Slow startup in progress Slow ascent, when When the minimum operating voltage is exceeded, the negative feedback op-amp will... Pull the power transistor low until it is fully on. At this point... Voltage lower than The comparator outputs a high level, and the switch... It is in a closed state. For low, Rise, and then follow Rise; when The voltage is about to be higher than the preset value. When the voltage is high, the negative feedback loop begins to slowly increase. Voltage, the preset The output voltage is set by the voltage divider resistors; when The voltage has increased, but not yet reached the level limiting the power transistor's regulation. During the process, the comparator detected Voltage higher than When the comparator outputs a low level, it will switch... Open, make Becoming a load with a gate-drain connection greatly enhances pipe pull-up The ability, that is, to quickly When the voltage is pulled up, the power transistor is rapidly regulated, then when Higher than the preset At that time, because the power transistor is adjusted, then Overcharging issues have been greatly improved.

[0073] Under no-load hot-swap conditions, when the aforementioned Later, when Lower than preset Then, the negative feedback pulls down This causes the power transistor to be fully open, and follow Descending; at this time, Voltage lower than The comparator outputs a high level, and the switch... In a closed state; when When hot-swapping is performed and powered on, the negative feedback loop starts to go high. Voltage; when The voltage has increased, but not yet reached the level limiting the power transistor's regulation. During the process, the comparator detected Voltage higher than When the comparator outputs a low level, it will switch... Open, make Becoming a load with a gate-drain connection greatly enhances pipe pull-up The ability, that is, to quickly When the voltage is pulled up, the power transistor is rapidly regulated, then when Higher than the preset At that time, because the power transistor is adjusted, then Overcharging issues have been greatly mitigated. The no-load hot-swap conditions include both situations where no load is connected and situations where the load is connected to the output voltage but the switch turns the load off.

[0074] As shown in Figure 3, Under the condition of inconsistent residual hot-plug speed, The change. When removed Then, it is powered by the input capacitor. Since the LDO has low and constant static power consumption under no-load conditions, The manifestation is a uniform power loss; the above-mentioned hot-swap overcharging, when When the residual voltage is higher than 3.24V, the negative feedback op-amp is still in normal regulation state, so Unchanged; when Below 3.24V, Followers began to appear The decrease; the above simulation results When powered on at a speed of 3µs, When it falls to the 2.99-3.24V range, Overcharging may occur, and The closer to the preset When the overcharge is greater, as shown in the figure above, Maximum overcharge: 3.4V (normal) At 4.3V, =3.25V).

[0075] As shown in Figure 4, The voltage increases from 0V to 4.3V at a rate of 10ms. Overcharge is minimal, with a maximum overcharge amplitude of 3.256V. The overcharge duration is approximately 27ms before returning to the preset value. .

[0076] As shown in Figure 6, The residual current hot-plugging conditions are the same as in Figure 3, but due to the lack of a comparison circuit, the circuit response speed is slow. After overcharging, the power transistor remains off until... Falling to the preset Later, the power transistor is released only after the negative feedback, so in the simulation diagram, After overcharging, it will last for 3-4 seconds.

[0077] As shown in Figure 7, The voltage increases from 0V to 4.3V at a rate of 10ms. An overcharge occurred, with a maximum overcharge voltage of 3.33V. The overcharge lasted for approximately 421ms before returning to the preset voltage. .

[0078] By changing some of the structures in this embodiment, the new embodiment can achieve the same function and effect.

[0079] Advantages of this invention: This invention connects a first amplifier to a low quiescent power circuit via a first NMOS transistor. A first voltage divider sampling resistor and a second voltage divider sampling resistor are connected to the low quiescent power circuit to generate a feedback voltage. A comparator is connected to the low quiescent power circuit via a fourth PMOS transistor and compares a second reference voltage generated internally with a drive voltage to control the switching on and off of the fourth PMOS transistor. The first amplifier outputs a first voltage signal based on the first reference voltage and the feedback voltage, and outputs a drive voltage through the first NMOS transistor and the low quiescent power circuit. The second PMOS transistor generates and controls the output voltage based on the external input voltage and the drive voltage. The comparator circuit modulates the drive voltage to control the power transistor, thereby improving output voltage overcharging during slow startup under no-load conditions and improving output voltage overcharging during hot-plugging under no-load conditions.

[0080] Example 5:

[0081] As shown in Figure 9, an LDO circuit for improving output overcharge includes: a first amplifier, , Low static power consumption circuits, switches , , Comparator, and external power supply Power supply, ground voltage GND, reference voltage and external output voltage The first amplifier is based on a first reference voltage. and feedback voltage Output voltage control signal . This is a common-source amplifier, with the source grounded and the drain connected to ground. The drain and the low static power circuit, the gate is connected to the output of the first amplifier, and based on The bias current provided by low quiescent power consumption, and the output gate drive voltage . The gate is connected to the output of the comparator, and the drain is connected to... The drain is connected to the low static power circuit, and the source is connected to the low static power circuit. The source is connected to an external input voltage, the gate is connected to the low static power circuit, and the drain is connected to the... , Based on external input voltage and driving voltage Control output voltage Size. One end is connected to the low static power consumption circuit and The drain electrode, The other end connects One end is connected to a feedback voltage signal ; The other end is grounded. First amplifier, The bias current provided by the low static power circuit , and The resulting loop forms a negative feedback loop, which causes the reference voltage to... and feedback voltage Consistency, then approval and Set output voltage The output voltage is: The comparator controls the switch. The circuitry includes the ability to turn the circuit on and off. The low static power consumption circuitry includes... , Second amplifier, Source access The source is connected to an external input voltage, and the gate is connected to... The gate and drain are connected , The source pole; Source access The drain of the second amplifier and the input terminal of the second amplifier are controlled. The gate is connected to the output terminal of the second amplifier, and the drain is connected to... Drain and The drain of the amplifier. The second amplifier and... Construct a buffer based on the output voltage and control Drain follows output voltage This avoids increased static power consumption in the circuit due to current mirror mismatch.

[0082] In this embodiment, the comparator includes: , , , and current source The aforementioned The source is grounded, and the gate is connected to the ground. The gate and drain are connected The drain is connected to the gate, and the gate and drain are connected simultaneously. The source is grounded, and the drain is connected to the ground. The drain electrode; The gate is connected to a second reference voltage. The source is connected to the current source. ; Gate drive voltage The source is connected to the current source. Drain connection The drain of the current source is connected in parallel to output the first voltage signal; Connect external input voltage .in , , , and current source This constitutes a five-transistor amplifier, which is based on a second reference voltage. and driving voltage Comparison, output voltage .

[0083] No load Slow startup in progress Slow ascent, when When the minimum operating voltage is exceeded, the negative feedback op-amp will... Pull the power transistor low until it is fully on. At this point... Voltage lower than The comparator outputs a high level, and the switch... It is in a closed state. For low, Rise, and then follow Rise; when The voltage is about to be higher than the preset value. When the voltage is high, the negative feedback loop begins to slowly increase. Voltage, the preset The output voltage is set by the voltage divider resistors; when The voltage has increased, but not yet reached the level limiting the power transistor's regulation. During the process, the comparator detected Voltage higher than When the comparator outputs a low level, it will switch... Open, make Becoming a load with a gate-drain connection greatly enhances pipe pull-up The ability, that is, to quickly When the voltage is pulled up, the power transistor is rapidly regulated, then when Higher than the preset At that time, because the power transistor is adjusted, then Overcharging issues have been greatly improved.

[0084] Under no-load hot-swap conditions, when the aforementioned Later, when Lower than preset Then, the negative feedback pulls down This causes the power transistor to be fully open, and follow Descending; at this time, Voltage lower than The comparator outputs a high level, and the switch... In a closed state; when When hot-swapping is performed and powered on, the negative feedback loop starts to go high. Voltage; when The voltage has increased, but not yet reached the level limiting the power transistor's regulation. During the process, the comparator detected Voltage higher than When the comparator outputs a low level, it will switch... Open, make Becoming a load with a gate-drain connection greatly enhances pipe pull-up The ability, that is, to quickly A voltage surge causes the power transistor to be rapidly regulated, mitigating output voltage overcharging. Therefore, when... Higher than the preset At that time, since the power transistor has been adjusted, then Overcharging issues have been greatly mitigated. The no-load conditions include both situations where no load is connected and situations where the load is connected to the output voltage but the switch turns the load off.

[0085] As shown in Figure 3, Under the condition of inconsistent residual hot-plug speed, The change. When removed Then, it is powered by the input capacitor. Since the LDO has low and constant static power consumption under no-load conditions, The manifestation is a uniform power loss; the above-mentioned hot-swap overcharging, when When the residual voltage is higher than 3.24V, the negative feedback op-amp is still in normal regulation state, so Unchanged; when Below 3.24V, Followers began to appear The decrease; the above simulation results When powered on at a speed of 3µs, When it falls to the 2.99-3.24V range, Overcharging may occur, and The closer to the preset When the overcharge is greater, as shown in the figure above, Maximum overcharge: 3.4V (normal) At 4.3V, =3.25V).

[0086] As shown in Figure 4, The voltage increases from 0V to 4.3V at a rate of 10ms. Overcharge is minimal, with a maximum overcharge amplitude of 3.256V. The overcharge duration is approximately 27ms before returning to the preset value. .

[0087] As shown in Figure 6, The residual current hot-plugging conditions are the same as in Figure 3, but due to the lack of a comparison circuit, the circuit response speed is slow. After overcharging, the power transistor remains off until... Falling to the preset Later, the power transistor is released only after the negative feedback, so in the simulation diagram, After overcharging, it will last for 3-4 seconds.

[0088] As shown in Figure 7, The voltage increases from 0V to 4.3V at a rate of 10ms. An overcharge occurred, with a maximum overcharge voltage of 3.33V. The overcharge lasted for approximately 421ms before returning to the preset voltage. .

[0089] Advantages of this invention: This invention connects a first amplifier to a low quiescent power circuit via a first NMOS transistor. A first voltage divider sampling resistor and a second voltage divider sampling resistor are connected to the low quiescent power circuit to generate a feedback voltage. A comparator is connected to the low quiescent power circuit via a fourth PMOS transistor and compares a second reference voltage generated internally with a drive voltage to control the switching on and off of the fourth PMOS transistor. The first amplifier outputs a first voltage signal based on the first reference voltage and the feedback voltage, and outputs a drive voltage through the first NMOS transistor and the low quiescent power circuit. The second PMOS transistor generates and controls the output voltage based on the external input voltage and the drive voltage. The comparator circuit modulates the drive voltage to control the power transistor, thereby improving output voltage overcharging during slow startup under no-load conditions and improving output voltage overcharging during hot-plugging under no-load conditions.

[0090] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. An LDO circuit for improving output overcharge, comprising: First amplifier, first NMOS transistor, second PMOS transistor, low quiescent power circuit, fourth PMOS transistor, first voltage divider sampling resistor Second voltage divider sampling resistor and external input voltage First reference voltage and output voltage The first amplifier is connected to a low quiescent power circuit via a first NMOS transistor. The first and second voltage-dividing sampling resistors are connected to the low quiescent power circuit and the second PMOS transistor to generate a feedback voltage. The amplifier further includes a comparator, which is connected to the low quiescent power circuit via a fourth PMOS transistor and compares a second reference voltage and a drive voltage generated internally within the circuit to control the switching on and off of the fourth PMOS transistor. The first amplifier outputs a first voltage signal based on the first reference voltage and the feedback voltage, and outputs a drive voltage through the first NMOS transistor and the low quiescent power circuit. The second PMOS transistor generates and controls the output voltage based on the external input voltage and the drive voltage. The low quiescent power... The circuit includes a first PMOS transistor, a third PMOS transistor, and a second amplifier. The source of the first PMOS transistor is connected to the source of the second PMOS transistor and is connected to an external input voltage. The gate of the first PMOS transistor is connected to the gate of the second PMOS transistor, and the drain of the first PMOS transistor is connected to the source of the third PMOS transistor. The source of the third PMOS transistor is connected to the drain of the first PMOS transistor and the input terminal of the second amplifier. The gate of the third PMOS transistor is connected to the output terminal of the second amplifier, and the drain of the third PMOS transistor is connected to the drain of the fourth PMOS transistor and the drain of the first NMOS transistor. The source of the fourth PMOS transistor is connected to the source of the third PMOS transistor, the drain of the fourth PMOS transistor is connected to a driving voltage, and the gate of the fourth PMOS transistor is connected to the output terminal of the comparator. When the fourth PMOS transistor is turned on, it quickly pulls the driving voltage high.

2. The LDO circuit for improving output overcharge according to claim 1, characterized in that, The first NMOS transistor is a common-source amplifier with its source grounded, its drain connected to the drain of the fourth PMOS transistor and the low static power consumption circuit, and its gate connected to the output terminal of the first amplifier. Based on the first voltage signal and the bias current provided by the low static power consumption circuit, it outputs a gate drive voltage. The source of the second PMOS transistor is connected to an external input voltage, its gate is connected to the low static power consumption circuit, and its drain is connected to the first voltage divider sampling resistor.

3. The LDO circuit for improving output overcharge according to claim 1, characterized in that, The second amplifier and the third PMOS transistor form a buffer, and the drain of the first PMOS transistor is controlled to follow the output voltage based on the output voltage, so as to avoid the increase of static power consumption of the circuit due to current mirror mismatch.

4. The LDO circuit for improving output overcharge according to claim 1, characterized in that, The loop formed by the first amplifier, the first NMOS transistor, the low quiescent power circuit, the second PMOS transistor, the first sampling voltage divider resistor, and the second sampling voltage divider resistor constitutes a negative feedback loop. One end of the first voltage divider sampling resistor is connected to the drain of the low quiescent power circuit and the second PMOS transistor, and the other end of the first voltage divider sampling resistor is connected to one end of the second voltage divider sampling resistor and outputs a feedback voltage signal; the other end of the second voltage divider sampling resistor is grounded. The negative feedback loop makes the first reference voltage and the feedback voltage consistent, and then sets the output voltage through the first and second sampling voltage divider resistors. The output voltage is: 。 5. A method for improving slow start-up output overcharge under no-load conditions, implemented based on the LDO circuit described in any one of claims 1 to 4, characterized in that, The method includes the following steps: the comparator is connected to a low static power circuit through a fourth PMOS transistor, and compares the fourth PMOS transistor with a second reference voltage and a drive voltage to control the turning on and off of the fourth PMOS transistor; the first amplifier outputs a first voltage signal based on a first reference voltage and a feedback voltage, and outputs a drive voltage through a first NMOS transistor and a low static power circuit; the second PMOS transistor generates and controls the output voltage based on the external input voltage and the drive voltage.

6. The method for improving slow start-up overcharge under no-load conditions according to claim 5, characterized in that, During no-load slow start-up, when the external input voltage exceeds the minimum operating voltage, the drive voltage is pulled down to the second PMOS transistor being fully on. The drive voltage is then lower than the second reference voltage, and the comparator outputs a high level, while the fourth PMOS transistor is in the off state. When the external input voltage is about to exceed the output voltage set by the first and second sampling voltage divider resistors, the drive voltage is pulled up. After the comparator detects that the drive voltage is higher than the second reference voltage, it outputs a low level and turns on the fourth PMOS transistor, allowing the second PMOS transistor to be quickly regulated.

7. A method for improving overcharging of hot-swappable output with residual charge under no-load conditions, implemented based on the LDO circuit described in any one of claims 1 to 4, characterized in that, The method includes the following steps: the comparator is connected to a low static power circuit through a fourth PMOS transistor, and compares the fourth PMOS transistor with a second reference voltage and a drive voltage to control the turning on and off of the fourth PMOS transistor; the first amplifier outputs a first voltage signal based on a first reference voltage and a feedback voltage, and outputs a drive voltage through a first NMOS transistor and a low static power circuit; the second PMOS transistor generates and controls the output voltage based on the external input voltage and the drive voltage.

8. A method for improving overcharging of hot-swappable output with residual charge under no-load conditions according to claim 7, characterized in that, Under no-load hot-swappable external input voltage conditions, when the external input voltage is lower than the output voltage set by the first and second sampling voltage divider resistors, the drive voltage is pulled down to the second PMOS transistor being fully on. The drive voltage is then lower than the second reference voltage, and the comparator outputs a high level, while the fourth PMOS transistor is in the off state. When the external input voltage is hot-swapped and powered on, the drive voltage is pulled up to a level higher than the second reference voltage. Upon detection, the comparator outputs a low level and turns on the fourth PMOS transistor, allowing the second PMOS transistor to be quickly regulated, thus improving the output voltage overcharge.

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