METHOD FOR PRODUCING A POWER MODULE FOR WEAKENING A VOLTAGE SWING

Abstract

A power inverter can include multiple DC busbars. Each DC busbar has a terminal end and a chip mounting area. The power inverter can also include multiple circuit breaker chips. Each circuit breaker chip is attached to the chip mounting area at one of multiple chip locations. The specific chip location for each circuit breaker chip is selected to minimize drain-source voltage overshoot during switching.

Description

INTRODUCTION

[0001] The present disclosure relates to methods for manufacturing systems and devices for power conversion.

[0002] Power modules can be used to convert power in vehicle applications. Power modules are self-contained power electronic devices, typically containing semiconductor switches configured to be controllable for power conversion tasks such as direct current (DC) to alternating current (AC) conversion, AC to DC conversion, DC to DC conversion, and / or the like. In some examples, power modules are configured as a half-bridge with four semiconductor devices, enabling DC to AC conversion. Multiple power modules can be used in tandem to provide multiphase AC power to a load, such as a vehicle's traction motor.

[0003] While current methods for manufacturing power conversion devices fulfill their intended purpose, there is a need for a new and improved method for manufacturing power modules for power inverters in order to mitigate voltage overshoots. DESCRIPTION

[0004] A power inverter can incorporate multiple DC busbars, depending on several factors. Each DC busbar has a terminal end and a chip mounting area. The power inverter can also incorporate multiple circuit breaker chips. Each circuit breaker chip is attached to the chip mounting area at one of several chip locations. The specific chip location for each circuit breaker chip is selected to minimize drain-source voltage overshoot during switching.

[0005] In another aspect of the present disclosure, one of the plurality of chip locations for each of the plurality of power switch chips is selected at least partially based on a parasitic inductance of each of the plurality of chip locations. The parasitic inductance of each of the plurality of chip locations is a parasitic inductance between each of the plurality of chip locations and the terminal end of one of the plurality of DC busbars.

[0006] In another aspect of the present disclosure, the parasitic inductance of each of the plurality of chip locations varies directly with a busbar length between each of the plurality of chip locations and the terminal end.

[0007] In another aspect of the present disclosure, one of the plurality of chip locations for each of the plurality of power switch chips is selected at least partially based on a threshold voltage of each of the plurality of power switch chips.

[0008] In another aspect of the present disclosure, a first power switch chip of the plurality of power switch chips is attached to a first chip position of the plurality of chip positions. The first power switch chip has a first threshold voltage, and the first chip position has a first parasitic inductance. A second power switch chip of the plurality of power switch chips is attached to a second chip position of the plurality of chip positions. The second power switch chip has a second threshold voltage, and the second chip position has a second parasitic inductance. The second threshold voltage is greater than the first threshold voltage, and the second parasitic inductance is greater than the first parasitic inductance.

[0009] In another aspect of the present disclosure, the plurality of DC busbars includes a positive DC busbar. The positive DC busbar has a positive terminal and a positive chip mounting area. The plurality of DC busbars further includes a negative DC busbar. The negative DC busbar has a negative terminal and a negative chip mounting area. The plurality of power-switch chips includes a plurality of high-side power-switch chips. Each of the plurality of high-side power-switch chips is attached to the positive chip mounting area of ​​the positive DC busbar at one of a plurality of high-side chip locations. The plurality of power-switch chips further includes a plurality of low-side power-switch chips.Each of the numerous low-side power switch chips is attached to the negative chip mounting area of ​​the negative DC busbar at one of a number of low-side chip locations.

[0010] In another aspect of the present disclosure, the second chip location is one of the multitude of high-side chip locations.

[0011] In another aspect of the present disclosure, one of the plurality of chip locations for each of the plurality of power switch chips is selected at least partially based on a material type of each of the plurality of power switch chips.

[0012] In another aspect of the present disclosure, a third power switch chip of the plurality of power switch chips is attached to a first chip position of the plurality of chip positions. The third power switch chip has a first material type, and the first chip position has a first parasitic inductance. A fourth power switch chip of the plurality of power switch chips is attached to a second chip position of the plurality of chip positions. The fourth power switch chip has a second material type, and the second chip position has a second parasitic inductance. The second parasitic inductance is greater than the first parasitic inductance.

[0013] In another aspect of the present disclosure, the first material type is silicon carbide and the second material type is silicon.

[0014] A method for manufacturing a power inverter is provided, based on several aspects. The method may involve attaching a plurality of direct current (DC) busbars to a dielectric substrate. Each DC busbar has a terminal end and a chip mounting area. The method may further involve attaching a plurality of power switch chips to the DC busbars. Each power switch chip is attached to the chip mounting area at one of several chip locations. The specific chip location for each power switch chip is selected to minimize drain-source voltage overshoot during switching.

[0015] In another aspect of the present disclosure, the mounting of the plurality of power switch chips can further involve selecting one of the plurality of chip locations for each of the plurality of power switch chips, at least partially based on a parasitic inductance of each of the plurality of chip locations. The parasitic inductance of each of the plurality of chip locations is a parasitic inductance between each of the plurality of chip locations and the terminal end of one of the plurality of DC busbars.

[0016] In another aspect of the present disclosure, the selection of one of the plurality of chip locations for each of the plurality of power switch chips may further involve the selection of one of the plurality of chip locations for each of the plurality of power switch chips at least partially based on a threshold voltage of each of the plurality of power switch chips.

[0017] In another aspect of the present disclosure, attaching the plurality of power-switch chips can further include attaching a first power-switch chip of the plurality of power-switch chips to a first chip location of the plurality of chip locations. The first power-switch chip has a first threshold voltage, and the first chip location has a first parasitic inductance. Attaching the plurality of power-switch chips can further include attaching a second power-switch chip of the plurality of power-switch chips to a second chip location of the plurality of chip locations. The second power-switch chip has a second threshold voltage, and the second chip location has a second parasitic inductance. The second threshold voltage is greater than the first threshold voltage, and the second parasitic inductance is greater than the first parasitic inductance.

[0018] In another aspect of the present disclosure, mounting the plurality of DC busbars can further include mounting a positive DC busbar to the dielectric substrate. The positive DC busbar has a positive terminal and a positive chip mounting area. The positive terminal is electrically connected to a positive DC terminal. Mounting the plurality of DC busbars can further include mounting the plurality of power-switch chips and can also include mounting a plurality of high-side power-switch chips to the positive chip mounting area of ​​the positive DC busbar at one of a plurality of high-side chip locations. The second chip location is one of the plurality of high-side chip locations.

[0019] In another aspect of the present disclosure, the selection of one of the plurality of chip locations for each of the plurality of circuit breaker chips may further involve the selection of one of the plurality of chip locations for each of the plurality of circuit breaker chips at least partially based on a material type of each of the plurality of circuit breaker chips.

[0020] In another aspect of the present disclosure, attaching the plurality of power-switch chips can further include attaching a third power-switch chip to a first chip position within the plurality of chip positions. The third power-switch chip has a silicon carbide material type, and the first chip position has a first parasitic inductance. Attaching the plurality of power-switch chips can further include attaching a fourth power-switch chip to a second chip position within the plurality of chip positions. The fourth power-switch chip has a silicon material type, and the second chip position has a second parasitic inductance. The second parasitic inductance is greater than the first parasitic inductance.

[0021] A power inverter is provided for a vehicle according to several aspects. The power inverter can include multiple DC busbars. Each DC busbar has a terminal end and a chip mounting area. The power inverter can also include multiple power-switching chips. Each power-switching chip is attached to the chip mounting area at one of multiple chip locations. The specific chip location for each power-switching chip is selected to minimize drain-source voltage overshoot during switching. This selection is based, at least in part, on the parasitic inductance of each chip location.The parasitic inductance of each of the multitude of chip locations is a parasitic inductance between each of the multitude of chip locations and the terminal end of one of the multitude of DC busbars.

[0022] In another aspect of the present disclosure, a first power switch chip of the plurality of power switch chips is attached to a first chip position of the plurality of chip positions. The first power switch chip has a first threshold voltage, and the first chip position has a first parasitic inductance. A second power switch chip of the plurality of power switch chips is attached to a second chip position of the plurality of chip positions. The second power switch chip has a second threshold voltage, and the second chip position has a second parasitic inductance. The second threshold voltage is greater than the first threshold voltage, and the second parasitic inductance is greater than the first parasitic inductance.

[0023] In another aspect of the present disclosure, a third power switch chip of the plurality of power switch chips is attached to a first chip position of the plurality of chip positions. The third power switch chip has a first material type, and the first chip position has a first parasitic inductance. A fourth power switch chip of the plurality of power switch chips is attached to a second chip position of the plurality of chip positions. The fourth power switch chip has a second material type, and the second chip position has a second parasitic inductance. The second parasitic inductance is greater than the first parasitic inductance.

[0024] Further areas of application will become apparent from the description provided herein. It is understood that the description and specific examples serve only for illustrative purposes and are not intended to limit the scope of this disclosure. BRIEF DESCRIPTION OF THE FIGURES

[0025] The drawings described herein serve only for illustrative purposes and are not intended to limit the scope of the present disclosure in any way. Fig. Figure 1 is a schematic diagram of a power system for a vehicle according to an exemplary embodiment; Fig. Figure 2 is a schematic diagram of a power inverter of the power system according to an exemplary embodiment; Fig. Figure 3A is a schematic diagram of a first power module of the power inverter according to an exemplary embodiment; Fig. Figure 3B is a schematic diagram of a second power module of the power inverter according to an exemplary embodiment; and Fig. Figure 4 is a flowchart of a method for manufacturing the power inverter according to an exemplary embodiment. DETAILED DESCRIPTION

[0026] The following description is merely exemplary and is not intended to limit the present disclosure, application or uses.

[0027] In aspects of the present disclosure, it is advantageous in the manufacture of power electronic devices, such as power inverters for vehicles, to use components with known electrical properties within acceptable ranges. However, due to manufacturing variations, electrical properties can vary within component batches. The present disclosure provides a new and improved method for manufacturing power inverters for vehicles that enables the use of components with varying electrical properties to minimize voltage overshoot.

[0028] With reference to Fig. Figure 1 illustrates a power system for a vehicle and is generally designated by reference numeral 10. The system 10 is shown with an exemplary vehicle 12. Although a passenger car is illustrated, it is understood that the vehicle 12 can be any type of vehicle without derogating from the scope of this disclosure. The system 10 generally includes a controller 14, a rechargeable energy storage system (RESS) 16, a traction motor 18, and a power inverter 20.

[0029] The controller 14 is used to control the RESS 16, the traction motor 18, and the power inverter 20. The controller 14 includes at least one processor 22 and one or more non-volatile, computer-readable storage devices or media 24. The processor 22 can be a custom or commercially available processor, a central processing unit (CPU), a graphics processing unit (GPU), an auxiliary processor among several processors assigned to the controller 14, a microprocessor-based microprocessor (in the form of a microchip or chipset), a macroprocessor, a combination thereof, or, more generally, a device for executing instructions.

[0030] The one or more computer-readable storage devices or media 24 can include volatile and non-volatile storage, for example in read-only memory (ROM), random-access memory (RAM), and keep-alive memory (KAM). KAM is a persistent or non-volatile memory that can be used to store various operating variables while the processor 22 is turned off.The one or more computer-readable storage devices or media 24 can be implemented using a variety of storage devices, such as PROMs (programmable read-only memory), EPROMs (electrical PROMs), EEPROMs (electrically erasable PROMs), flash memory, or other electrical, magnetic, optical, or combination storage devices capable of storing data, some of which represent executable instructions used by the controller 14 to control various systems of the vehicle 12. The controller 14 can also consist of multiple controllers that are in electrical communication with each other.

[0031] The controller 14 communicates electrically with the RESS 16, the traction motor 18, and the power inverter 20. The controller 14 can also be connected to additional systems and / or controllers of the vehicle 12, allowing it to access data such as the vehicle 12's speed, acceleration, braking, and steering angle. In one exemplary embodiment, the electrical communication is established, for example, using a CAN network, a FLEXRAY network, a local area network (e.g., WiFi, Ethernet, and the like), a serial peripheral interface (SPI) network, or the like. It is understood that various additional wired and wireless techniques and communication protocols for communicating with the controller 14 are within the scope of this disclosure.It is further understood that, within the scope of the present disclosure, electrical communication also includes the transfer of power and / or energy between electrical devices (e.g., using conductive wires and / or wireless power transmission techniques).

[0032] The RESS 16 stores and provides electrical energy in the form of direct current (DC) energy to power the vehicle 12. In one exemplary embodiment, the RESS 16 includes a plurality of battery cells (e.g., lithium-ion battery cells) connected electrically in series and / or parallel to provide increased voltage and / or current carrying capacity. In a non-limiting example, the plurality of battery cells is housed in an enclosure configured to protect the plurality of battery cells from mechanical vibration, water ingress, and dust ingress. The enclosure is also configured to provide temperature control (e.g., using a liquid cooling system, a resistance heating system, and / or the like).

[0033] In one exemplary embodiment, the RESS 16 further includes a battery management system (BMS) in electrical communication with the controller 14, configured to monitor battery characteristics such as state of charge (SOC), state of health (SOH), temperature, and / or the like, and to transmit these characteristics to the controller 14. In a non-limiting example, the BMS includes a BMS controller in electrical communication with a plurality of BMS sensors arranged within the housing of the RESS 16. In another non-limiting example, the BMS further includes one or more electronic switches (e.g.,Relays, contactors, semiconductor-based switches, and / or the like, which can be operated to interrupt the current flow through the plurality of battery cells of the RESS 16 in response to commands received from the BMS controller and / or the controller 14. In an exemplary embodiment, the RESS 16 provides a DC voltage via a positive and negative output terminal. The positive and negative output terminals are electrically connected to the inverter 20, as discussed in more detail below.

[0034] The traction motor 18 is used to convert electrical energy from the RESS 16 into mechanical energy (i.e., rotational energy) to propel the vehicle 12. In an exemplary embodiment, the traction motor 18 is a three-phase alternating current (AC) induction motor capable of converting AC energy into mechanical energy. In a non-limiting example, the traction motor 18 includes a stator with a plurality of stator windings and a rotor rotatably arranged within the stator with a plurality of rotor windings. The stator windings are excited by three-phase AC supplied by the inverter 20 to generate a rotating stator magnetic field. The rotating stator magnetic field induces currents in the rotor windings, which in turn generates a rotor magnetic field that interacts with the rotating stator magnetic field, causing the rotor to rotate.The amplitude, frequency and / or relative phase shift of the excitation of each of the three phases of the stator windings controls the speed, direction and / or torque of the traction motor 18. The control unit 14 is in electrical communication with the traction motor 18 for monitoring and / or controlling the traction motor 18, for example to measure a temperature, speed and / or the like of the traction motor 18.

[0035] The power inverter 20 is used to convert the direct current (DC) power provided by the RESS 16 into three-phase alternating current (AC) power for use by the traction motor 18. In one exemplary embodiment, the power inverter 20 includes a plurality of power semiconductor devices, such as insulated-gate bipolar transistors (IGBTs), metal-oxide-semiconductor field-effect transistors (MOSFETs), and / or the like, configured to convert DC to three-phase AC. In a non-limiting example, the power inverter 20 operates by switching the plurality of power semiconductor devices in a pattern to produce a sinusoidal AC output for each of the three phases.The pattern can be set to vary the amplitude, frequency, and / or relative phase shift of each of the three phases to control the speed, direction, and / or torque of the traction motor 18 based on signals from the controller 14. The power inverter 20 includes a positive DC terminal 26a and a negative DC terminal 26b, which are electrically connected to the RESS 16. The power inverter 20 also includes a first AC terminal 28a, a second AC terminal 28b, and a third AC terminal 28c, which are electrically connected to the traction motor 18. The power inverter 20 communicates electrically with the controller 14, allowing the controller 14 to activate, deactivate, and otherwise adjust the operation of the power inverter 20.It is understood that various types of inverters, including, for example, multi-stage inverters, are within the scope of this disclosure.

[0036] With reference to Fig. Figure 2 shows a schematic diagram of the power inverter 20. In an exemplary embodiment, the power inverter 20 includes a heat sink 30 and a plurality of power modules 32.

[0037] The heat sink 30 is used to transfer heat away from the plurality of power modules 32 during the operation of the power inverter 20. In an exemplary embodiment, the heat sink 30 includes a cooling plate with one or more internal liquid-tight channels for transferring coolant through the heat sink 30. The heat sink 30 further includes a coolant inlet 34a, where coolant enters the heat sink 30, and a coolant outlet 34b, where coolant exits the heat sink 30. In a non-limiting example, after exiting the heat sink 30 through the coolant outlet 34b, the coolant flows through a radiator to release heat, which is absorbed by the plurality of power modules 32.

[0038] The multiple power modules 32 are self-contained modules for converting DC power to AC power. In a non-restrictive example, which in Fig. As shown in Figure 2, the power inverter 20 comprises a first power module 32a, a second power module 32b, and a third power module 32c. It is understood that the power inverter 20 can comprise any number of power modules without deviating from the scope of this disclosure. In an exemplary embodiment, the plurality of power modules 32 are attached to the heat sink 30 using, for example, a thermal connection, a thermal adhesive, and / or the like.

[0039] With reference to Fig. Figure 3A shows a schematic diagram of the first power module 32a. It is understood that the following disclosure also applies to any number of additional power modules of the power inverter 20, including, for example, the second power module 32b and the third power module 32c. In an exemplary embodiment, the first power module 32a comprises a positive DC busbar 36a, a negative DC busbar 36b, an AC busbar 38 attached to a dielectric substrate 40 (e.g., a directly bonded copper substrate), and a plurality of power switch chips 42.

[0040] The positive DC busbar 36a includes a positive terminal 44a and a positive chip mounting area 46a. The positive terminal 44a is electrically connected to the positive DC terminal 26a. The positive chip mounting area 46a is used to electrically connect a plurality of high-side power-switch chips (discussed below) at a plurality of high-side chip locations 48a via a current-carrying terminal (e.g., a drain or source terminal) of each of the plurality of high-side power-switch chips.

[0041] The negative DC busbar 36b includes a negative terminal 44b and a negative chip mounting area 46b. The negative terminal 44b is electrically connected to the negative DC terminal 26b. The negative chip mounting area 46b is used to electrically connect a plurality of low-side circuit breaker chips (discussed below) at a plurality of low-side chip locations 48b via a current-carrying terminal (e.g., a drain or source terminal) of each of the plurality of low-side circuit breaker chips.

[0042] The positive terminal end 44a and the negative terminal end 44b are collectively referred to herein as terminal ends. The positive chip mounting area 46a and the negative chip mounting area 46b are collectively referred to herein as chip mounting areas. The plurality of high-side chip locations 48a and the plurality of low-side chip locations 48b are collectively referred to herein as a plurality of chip locations. The positive DC bus 36a and the negative DC bus 36b are collectively referred to herein as a plurality of DC bus bars.

[0043] The AC busbar 38 electrically connects a live terminal (e.g., a drain or source terminal) of each of the plurality of circuit breaker chips 42 to the first AC terminal 28a. The plurality of circuit breaker chips 42 includes a first circuit breaker chip 42a, a second circuit breaker chip 42b, a third circuit breaker chip 42c, and a fourth circuit breaker chip 42d. It is understood that each of the plurality of power modules 32 can contain any number of circuit breaker chips.

[0044] Each of the multiple power switch chips 42 incorporates one or more semiconductor devices, such as transistors, thyristors, triacs, GTOs (gate-switching thyristors), IGBTs (insulated-gate bipolar transistors), MOSFETs (metal-oxide-semiconductor field-effect transistors), SCRs (silicon-controlled rectifiers), and / or the like. The first power switch chip 42a is connected to the negative DC terminal 26b at a first chip location 50a in the negative chip mounting area 46b. The second power switch chip 42b is connected to the positive DC terminal 26a at a second chip location 50b in the positive chip mounting area 46a.

[0045] The third power switch chip 42c is connected to the negative DC terminal 26b at a third chip position 50c in the negative chip mounting area 46b. The fourth power switch chip 42d is connected to the positive DC terminal 26a at a fourth chip position 50d in the positive chip mounting area 46a. The second power switch chip 42b and the fourth power switch chip 42d are connected to the positive DC terminal 26a and are thus referred to as the array of high-side power switch chips. The first power switch chip 42a and the third power switch chip 42c are connected to the negative DC terminal 26b and are thus referred to as the array of low-side power switch chips.

[0046] In an exemplary embodiment, each of the plurality of power switch chips 42 is characterized by a plurality of electrical properties. In a non-limiting example, the plurality of electrical properties includes at least: a threshold voltage and a material type. The threshold voltage is a minimum gate-source voltage required to create a conductive channel between the source and drain terminals. The material type is the semiconductor material used to fabricate the power switch chip, such as silicon (Si), gallium arsenide (GaAs), silicon carbide (SiC), gallium nitride (GaN), and / or the like.

[0047] Within the scope of this disclosure, drain-source voltage overshoot is defined as a transient spike in voltage between the drain and source terminals that exceeds the rated operating voltage of the power switch chip. Drain-source voltage overshoot can lead to deterioration or failure of the device over time.

[0048] Both the threshold voltage and the material type influence drain-source voltage overshoot of the power switch chip. In a non-restrictive example, a lower threshold voltage allows the power switch chip to turn on with less gate driver voltage, resulting in faster switching times. Furthermore, wide-bandgap materials such as silicon carbide (SiC) and gallium nitride (GaN) can handle higher voltages and faster switching speeds compared to silicon (Si). However, faster switching can increase the likelihood of overshoot due to higher rates of change of voltage and current, which can induce voltage spikes in inductive elements or parasitic inductances.

[0049] Furthermore, the electrical design and topology of the multitude of power modules 32, including the arrangement of the multitude of power switch chips 42, also influence the drain-source voltage overshoot of the multitude of power switch chips 42. In a non-restrictive example, the parasitic inductance between each of the multitude of chip locations and the terminal end of one of the multitude of DC busbars influences the drain-source voltage overshoot of the multitude of power switch chips 42. Larger parasitic inductances tend to increase the probability and severity of the drain-source voltage overshoot.

[0050] In a non-restrictive example, the multitude of power switch chips 42 is largely provided for the manufacturing process of the multitude of power modules 32. Therefore, the electrical properties of the multitude of power switch chips 42 can vary.

[0051] To ensure the proper operation of the plurality of power modules 32 of the power inverter 20, predetermined threshold values ​​are defined. In an exemplary embodiment, a predetermined voltage overshoot threshold is defined as a maximum permissible drain-source voltage overshoot for each individual power switch chip. The present disclosure provides a new and improved method for manufacturing the plurality of power modules 32 to minimize the drain-source voltage overshoot of each of the plurality of power switch chips 42 during switching.

[0052] With reference to Fig. Figure 3B shows a schematic diagram of the second power module 32b. It is understood that the following disclosure also applies to any number of additional power modules of the power inverter 20, including, for example, the first power module 32a and the third power module 32c. The foregoing with reference to the first power module 32a and Fig. The disclosure provided in 3A also applies to the second performance module 32b and Fig. 3B. In the exemplary embodiment of Fig. 3B refers to the multitude of DC busbars, the AC busbar 38, and the multitude of circuit breaker chips 42, arranged horizontally instead of vertically as in Fig. 3A arranged. It is understood that the arrangements of the multitude of DC busbars, the AC busbar 38 and the multitude of circuit breaker chips 42, which are in Fig. 3A and Fig. The figures shown in Figure 3B are merely exemplary and any arrangement or orientation of the plurality of DC busbars, the AC busbar 38 and the plurality of circuit breaker chips 42 is within the scope of this disclosure.

[0053] Furthermore, the exemplary embodiment of Fig. 3B includes a fifth power switch chip 42e and a sixth power switch chip 42f. The fifth power switch chip 42e is connected to the negative DC terminal 26b at a fifth chip position 50e in the negative chip mounting area 46b. The sixth power switch chip 42f is connected to the positive DC terminal 26a at a sixth chip position 50f in the positive chip mounting area 46a. The second power switch chip 42b, the fourth power switch chip 42d, and the sixth power switch chip 42f are connected to the positive DC terminal 26a and are thus referred to as the plurality of high-side power switch chips. The first power switch chip 42a, the third power switch chip 42c and the fifth power switch chip 42e are connected to the negative DC terminal 26b and are thus referred to as the multitude of low-side power switch chips.It is understood that any arrangement, orientation and quantity of the plurality of DC busbars, the AC busbar 38 and the plurality of circuit breaker chips 42 is within the scope of this disclosure.

[0054] With reference to Fig. Figure 4 shows a flowchart of a process 100 for manufacturing a power inverter. The process 100 starts at block 102 and proceeds to block 104. At block 104, the plurality of DC busbars (i.e., the positive DC busbar 36a and the negative DC busbar 36b) and the AC busbar 38 are attached to the dielectric substrate 40. After block 104, the process 100 proceeds to block 106.

[0055] In Block 106, a parasitic inductance of each of the plurality of chip locations (i.e., the plurality of high-side chip locations 48a and the plurality of low-side chip locations 48b) is determined. In another exemplary embodiment, an intrinsic parasitic inductance of each of the plurality of power-switch chips 42 is determined. Within the scope of the present disclosure, the parasitic inductance of each of the plurality of chip locations is a parasitic inductance between each of the plurality of chip locations and the terminal end of one of the plurality of DC busbars.

[0056] For example, the parasitic inductance of one of the plurality of high-side chip junctions 48a is measured between that one of the plurality of high-side chip junctions 48a and the positive terminal 44a. The parasitic inductance of one of the plurality of low-side chip junctions 48b is measured between that one of the plurality of low-side chip junctions 48b and the negative terminal 44b. Within the scope of this disclosure, the intrinsic parasitic inductance of each of the plurality of power-switch chips 42 is influenced by the material properties and the manufacturing process of each of the plurality of power-switch chips 42.

[0057] In a non-restrictive example, the parasitic inductance of each of the plurality of chip digits varies directly with the busbar length between each of the plurality of chip digits and the terminal end. Therefore, a longer busbar length results in a greater parasitic inductance. In an exemplary embodiment, the parasitic inductance of each of the plurality of chip digits is determined at least partially based on the busbar length. In a non-restrictive example, the parasitic inductance of the first chip digit 50a is determined at least partially based on a first busbar length between the first chip digit 50a and the negative terminal end 44b. The parasitic inductance of the second chip digit 50b is determined at least partially based on a second busbar length between the second chip digit 50b and the positive terminal end 44a.

[0058] In the Fig. In the example shown in Figure 3A, the parasitic inductance of the second chip junction 50b is greater than the parasitic inductance of the first chip junction 50a, because the first busbar length between the first chip junction 50a and the negative terminal 44b is shorter than the second busbar length between the second chip junction 50b and the positive terminal 44a. In the example shown in Figure 3A, the parasitic inductance of the second chip junction 50b is greater than the parasitic inductance of the first chip junction 50a, because the first busbar length between the first chip junction 50a and the negative terminal 44b is shorter than the second busbar length between the second chip junction 50b and the positive terminal 44a. Fig. In the example shown in Figure 3B, the parasitic inductance of the fifth chip digit 50e is smaller than both the parasitic inductance of the first chip digit 50a and the third chip digit 50c, since a fifth busbar length between the fifth chip digit 50e and the negative terminal 44b is smaller than both the first busbar length and a third busbar length between the third chip digit 50c and the negative terminal 44b. Furthermore, the parasitic inductance of the sixth chip digit 50f is smaller than both the parasitic inductance of the second chip digit 50b and the fourth chip digit 50d, since a sixth busbar length between the sixth chip digit 50f and the positive terminal 44a is smaller than both the second busbar length and a fourth busbar length between the fourth chip digit 50d and the positive terminal 44a. After block 106, procedure 100 continues to block 108.

[0059] In Block 108, the plurality of electrical properties of each of the plurality of circuit breaker chips 42 is determined. In one exemplary embodiment, the plurality of electrical properties includes at least one of: the threshold voltage and the material type. In a non-limiting example, the plurality of electrical properties is determined by electrically testing each of the plurality of circuit breaker chips 42 (e.g., measuring voltage and current during switching and current flow in the on-state). In another non-limiting example, the plurality of electrical properties of each of the plurality of circuit breaker chips 42 is provided by the manufacturer of each of the plurality of circuit breaker chips 42. Following Block 108, Method 100 proceeds to Block 110.

[0060] At block 110, the plurality of power switch chips 42 are attached to the plurality of DC busbars at least partially based on the parasitic inductance of each of the plurality of chip locations in order to minimize the drain-source voltage overshoot of each of the plurality of power switch chips 42 during switching. In an exemplary embodiment, one of the plurality of chip locations for each of the plurality of power switch chips 42 is selected at least partially based on the parasitic inductance of each of the plurality of chip locations determined at block 106 and the threshold voltage of each of the plurality of power switch chips 42 determined at block 108.Chips with a relatively higher threshold voltage are placed at chip locations with a relatively higher parasitic inductance to compensate for the effects of switching speed and inductance on voltage overshoot, so that the drain-source voltage overshoot of each of the plurality of power switch chips 42 is less than or equal to the predetermined voltage overshoot threshold. In another exemplary embodiment, chips with similar threshold voltages (i.e., within a predetermined range of each other, for example, ±5%) are grouped together to be adjacent to each other and / or attached to the same power module to minimize voltage overshoot and / or current-division mismatch due to switching mismatches.Furthermore, chips with similar on-resistance are grouped together to be placed adjacent to each other and / or attached to the same power module in order to minimize load current mismatch.

[0061] In a non-restrictive example, for the in Fig. In the embodiment shown in Figure 3A, the first power switch chip 42a is attached to the first chip location 50a. The first power switch chip 42a has a first threshold voltage, and the first chip location 50a has a first parasitic inductance. The third power switch chip 42c is attached to the third chip location 50c. The third power switch chip 42c has a third threshold voltage, and the third chip location 50c has a third parasitic inductance. The third threshold voltage (i.e., the threshold voltage of the third power switch chip 42c) is greater than the first threshold voltage (i.e., the threshold voltage of the first power switch chip 42a), and the third parasitic inductance (i.e., the parasitic inductance of the third chip location 50c) is greater than the first parasitic inductance (i.e., the parasitic inductance of the third chip location 50c).the parasitic inductance of the first chip position 50a), as evidenced by the longer busbar length for the third chip position 50c compared to the first chip position 50a.

[0062] In a non-restrictive example, for the in Fig. In the embodiment shown in Figure 3B, the fifth power switch chip 42e is attached to the fifth chip position 50e. The fifth power switch chip 42e has a fifth threshold voltage, and the fifth chip position 50e has a fifth parasitic inductance. The first power switch chip 42a is attached to the first chip position 50a, and the third power switch chip 42c is attached to the third chip position 50c. The first power switch chip 42a has a first threshold voltage, and the first chip position 50a has a first parasitic inductance. The third power switch chip 42c has a third threshold voltage, and the third chip position 50c has a third parasitic inductance. The first and third threshold voltages are greater than the fifth threshold voltage.The first parasitic inductance and the third parasitic inductance are larger than the fifth parasitic inductance, as evidenced by the longer busbar length for the first chip digit 50a and the third chip digit 50c compared to the fifth chip digit 50e.

[0063] In another non-restrictive example, for the in Fig. In the embodiment shown in Figure 3A, the first power switch chip 42a is attached to the first chip location 50a. The first power switch chip 42a has a first threshold voltage, and the first chip location 50a has a first parasitic inductance. The second power switch chip 42b is attached to the second chip location 50b (i.e., the second power switch chip 42b is attached to one of the plurality of high-side chip locations 48a). The second power switch chip 42b has a second threshold voltage, and the second chip location 50b has a second parasitic inductance. The second threshold voltage (i.e., the threshold voltage of the second power switch chip 42b) is greater than the first threshold voltage (i.e., the threshold voltage of the first power switch chip 42a) and the second parasitic inductance (i.e., the parasitic inductance of the second chip location 50b) is greater than the first parasitic inductance (i.e.,the parasitic inductance of the first chip position 50a), as evidenced by the longer busbar length for the second chip position 50b compared to the first chip position 50a.

[0064] In another exemplary embodiment, one of the plurality of chip locations for each of the plurality of power switch chips 42 is selected at least partially based on the parasitic inductance of each of the plurality of chip locations, determined at block 106, and the material type of each of the plurality of power switch chips 42, determined at block 108. In a non-restrictive example, chips with a faster switching material type are placed at chip locations with a relatively lower parasitic inductance to compensate for the effects of switching speed, reverse recovery, and inductance on voltage overshoot, such that the drain-source voltage overshoot of each of the plurality of power switch chips 42 is less than or equal to the predetermined voltage overshoot threshold.

[0065] In a non-restrictive example, for the in Fig. In the embodiment shown in Figure 3A, the third power switch chip 42c is attached to the third chip location 50c. The third power switch chip 42c has a first material type, and the third chip location 50c has a third parasitic inductance. The fourth power switch chip 42d is attached to the fourth chip location 50d. The fourth power switch chip 42d has a second material type, and the fourth chip location 50d has a fourth parasitic inductance. The second material type (i.e., the material of the fourth power switch chip 42d) is silicon (Si). The first material type (i.e., the material type of the third power switch chip 42c) is silicon carbide (SiC). The fourth parasitic inductance (i.e., the parasitic inductance of the fourth chip location 50d) is larger than the third parasitic inductance (i.e., the parasitic inductance of the fourth chip location 50d).the parasitic inductance of the third chip position 50c), as evidenced by the longer busbar length for the fourth chip position 50d compared to the third chip position 50c.

[0066] In a non-restrictive example, for the in Fig.In the embodiment shown in Figure 3B, the fifth power switch chip 42e is attached to the fifth chip location 50e. The fifth power switch chip 42e has a fifth material type, and the fifth chip location 50e has a fifth parasitic inductance. The first power switch chip 42a is attached to the first chip location 50a, and the third power switch chip 42c is attached to the third chip location 50c. The first power switch chip 42a has a first material type, and the first chip location 50a has a first parasitic inductance. The third power switch chip 42c has a third material type, and the third chip location 50c has a third parasitic inductance. The first and third material types are both silicon (Si). The fifth material type is silicon carbide (SiC).The first parasitic inductance and the third parasitic inductance are larger than the fifth parasitic inductance, as evidenced by the longer busbar length for the first chip digit 50a and the third chip digit 50c compared to the fifth chip digit 50e.

[0067] After selecting one of the plurality of chip locations for each of the plurality of power switch chips 42, the plurality of power switch chips 42 is attached to the dielectric substrate 40. Electrical connections between the components are made using a plurality of conductors (e.g., busbars, bond wires, bond clips, bond tapes, and / or the like). Control connections for connecting gate terminals (not shown) of each of the plurality of power switch chips 42 to gate drivers (not shown) and / or to the inverter control (not shown) and / or to the control 14 are implemented as pins extending orthogonally from the dielectric substrate 40 and electrically connected to the gate terminals using bond wires. After block 110, the procedure 100 proceeds to block 112.

[0068] In block 112, the first power module 32a is attached to the heat sink 30. It is understood that the process 100 may also include additional steps, such as electrical connection of components, component testing, housing, encapsulation or conformal coating of components, quality assurance, and / or the like. After block 112, the process 100 enters a standby state at block 114.

[0069] In an exemplary embodiment, the method 100 is repeatedly restarted at block 102 to generate the plurality of power modules 32 (e.g. the second power module 32b and the third power module 32c) and to attach each of the plurality of power modules 32 to the heat sink 30 to complete the assembly of the power inverter 20.

[0070] Method 100 of the present disclosure offers several advantages. Manufacturing the power inverter 20 according to method 100 reduces voltage overshoot, thereby increasing the performance, durability, and reliability of the power inverter 20. The description in the present disclosure is merely exemplary, and variations that do not deviate from the core of the present disclosure are considered to be within the scope of the present disclosure. Such variations are not to be regarded as a departure from the spirit and scope of the present disclosure.

Claims

[1] Power inverters, including: a plurality of direct current (DC) busbars, each of the plurality of DC busbars having a terminal end and a chip mounting area; and a plurality of power switch chips, wherein each of the plurality of power switch chips is attached to the chip mounting area at one of a plurality of chip locations, wherein the one of the plurality of chip locations for each of the plurality of power switch chips is selected to minimize drain-source voltage overshoot of each of the plurality of power switch chips during switching. [2] Power inverter according to claim 1, wherein one of the plurality of chip locations for each of the plurality of power switch chips is selected at least partially based on a parasitic inductance of each of the plurality of chip locations, and wherein the parasitic inductance of each of the plurality of chip locations is a parasitic inductance between each of the plurality of chip locations and the terminal end of one of the plurality of DC busbars. [3] Power inverter according to claim 2, wherein the parasitic inductance of each of the plurality of chip locations varies directly with a busbar length between each of the plurality of chip locations and the terminal end. [4] Power inverter according to claim 2, wherein one of the plurality of chip locations for each of the plurality of power switch chips is selected at least partially based on a threshold voltage of each of the plurality of power switch chips. [5] Power inverter according to claim 4, wherein: a first power switch chip of the plurality of power switch chips is attached to a first chip location of the plurality of chip locations, wherein the first power switch chip has a first threshold voltage and the first chip location has a first parasitic inductance; and a second power switch chip of the plurality of power switch chips is attached to a second chip location of the plurality of chip locations, wherein the second power switch chip has a second threshold voltage and the second chip location has a second parasitic inductance, and wherein the second threshold voltage is greater than the first threshold voltage and the second parasitic inductance is greater than the first parasitic inductance. [6] Power inverter according to claim 5, wherein: The multitude of DC busbars includes the following: a positive DC busbar, wherein the positive DC busbar has a positive terminal end and a positive chip mounting area; and a negative DC busbar, wherein the negative DC busbar has a negative terminal end and a negative chip mounting area; and The multitude of power switch chips includes the following: a plurality of high-side power switch chips, each of the plurality of high-side power switch chips being attached to the positive chip mounting area of ​​the positive DC busbar at one of a plurality of high-side chip locations; and a multitude of low-side power switch chips, each of the multitude of low-side power switch chips being attached to the negative chip mounting area of ​​the negative DC busbar at one of a multitude of low-side chip locations. [7] Power inverter according to claim 6, wherein the second chip location is one of the plurality of high-side chip locations. [8] Power inverter according to claim 2, wherein one of the plurality of chip locations for each of the plurality of power switch chips is selected at least partially based on a material type of each of the plurality of power switch chips. [9] Power inverter according to claim 8, wherein: a third power switch chip of the plurality of power switch chips is attached to a first chip location of the plurality of chip locations, wherein the third power switch chip has a first material type and the first chip location has a first parasitic inductance; and a fourth power switch chip of the plurality of power switch chips is attached to a second chip location of the plurality of chip locations, wherein the fourth power switch chip has a second material type and the second chip location has a second parasitic inductance, and wherein the second parasitic inductance is greater than the first parasitic inductance. [10] Power inverter according to claim 9, wherein the first material type is silicon carbide and the second material type is silicon.

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