Memory initialization method, computer device, storage medium, and program product
By initializing a memory module using the first CPU core in the server and triggering the remaining CPU cores to execute memory training code in parallel, the problem of long memory initialization time in the prior art is solved, and fast memory initialization is achieved.
Patent Information
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- INSPUR SUZHOU INTELLIGENT TECH CO LTD
- Filing Date
- 2025-09-22
- Publication Date
- 2026-06-04
AI Technical Summary
In the existing technology, during the memory initialization process, the memory initialization code is run in flash memory to perform serial initialization of multiple memory modules, which results in a long initialization time and slow speed.
A memory module is initialized by the first CPU core, and the memory training code is copied to the module. This triggers the other CPU cores to execute the memory training code in parallel, thus completing the initialization of all memory modules.
It reduces memory initialization time, improves memory initialization speed, and achieves fast initialization.
Smart Images
Figure CN2025123011_04062026_PF_FP_ABST
Abstract
Description
Memory initialization methods, computer equipment, storage media and program products
[0001] Cross-references to related applications
[0002] This application claims priority to Chinese Patent Application No. 202411733329.9, filed on November 29, 2024, entitled "Memory Initialization Method, Computer Device, Storage Medium and Program Product", the entire contents of which are incorporated herein by reference. Technical Field
[0003] This application relates to the field of server technology, specifically to memory initialization methods, computer equipment, storage media, and program products. Background Technology
[0004] Memory is a crucial component of a computer system, responsible for temporarily storing data processed by the Central Processing Unit (CPU) and exchanged with external storage. The operating system and running program instructions rely on memory for rapid data access. Meanwhile, the Basic Input Output System (BIOS) is responsible for initializing the hardware and loading the operating system into memory, thereby booting the entire system. The coordinated operation between memory and BIOS is essential for the stable operation of server systems.
[0005] In the boot process of Unified Extensible Firmware Interface (UEFI) BIOS, memory initialization is an important part of the Pre-EFI Initialization (PEI) stage.
[0006] In related technologies, during memory initialization in the PEI stage, memory initialization code is obtained, and the memory initialization code is run on the flash memory to initialize multiple memory modules serially, thereby completing the memory initialization.
[0007] However, this method of running memory initialization code on flash memory and serially initializing multiple memory modules to complete memory initialization results in a long memory initialization time and a slow initialization speed. Summary of the Invention
[0008] In a first aspect, this application provides a memory initialization method applied to a first central processing unit core, comprising:
[0009] During the memory initialization phase, memory initialization code is executed to determine the current startup mode;
[0010] In response to the current startup mode being the first mode, obtain the memory parameter information of the memory module;
[0011] Based on memory parameter information, the first memory module is trained to obtain the first training value;
[0012] Based on the first training values, complete the initialization of the first memory module;
[0013] Copy the memory training code from the memory initialization code to the first memory module;
[0014] The remaining CPU cores are sent notification messages in parallel to the other CPU cores so that the other CPU cores respond to the notification messages, train the remaining memory modules based on memory parameter information and memory training code, and obtain the remaining training values.
[0015] Save the first training value and the remaining training values to the target storage area, and restart the server;
[0016] In response to the current startup mode being the second mode, the first training value and the remaining training values are retrieved from the target storage area; and
[0017] Based on the first training value and the remaining training values, the memory module is initialized.
[0018] In one alternative implementation, runtime memory initialization code is used to determine the current boot mode, including:
[0019] Run the memory initialization code to determine whether the target storage area includes the first training value and the remaining training values;
[0020] In response to the target storage area not containing the first training value and the remaining training values, the current startup mode is determined to be the first mode; and
[0021] In response to the target storage area including the first training value and the remaining training value, the current startup mode is determined to be the second mode.
[0022] In one optional implementation, obtaining the memory parameter information of the memory module includes:
[0023] Based on the address information of the memory module, obtain the memory parameter information of the memory module.
[0024] In one optional implementation, the initialization of the first memory module is completed based on the first training values, including:
[0025] Write the first training value into the register of the first memory controller corresponding to the first memory module so that the first memory module is in working state;
[0026] Based on memory parameter information, determine the decoding address of the first memory module; and
[0027] Based on the decoded address of the first memory module, the first memory module is mapped to the memory address space of the central processing unit, and the memory address space of the central processing unit is set to be valid to complete the initialization of the first memory module.
[0028] In one alternative implementation, copying the memory training code from the memory initialization code to the first memory module includes:
[0029] The amount of memory training code to be copied is determined based on the number of memory modules.
[0030] Based on the number of training codes to be copied, the first storage region of the first memory module is divided into multiple first storage sub-regions; and
[0031] The in-memory training code is copied to multiple first storage sub-regions.
[0032] In one optional implementation, notification information is sent in parallel to the remaining CPU cores, causing the remaining CPU cores to respond to the notification information and train the remaining memory modules based on memory parameter information and memory training code to obtain remaining training values, including:
[0033] Based on the number of memory modules, the target CPU core is selected from the remaining CPU cores; and
[0034] Notification information is sent to the target CPU core in parallel so that the target CPU core responds to the notification information, trains the remaining memory modules based on memory parameter information and the memory training code in the corresponding first storage sub-region, and obtains the remaining training values.
[0035] In this context, one target central processing unit core corresponds to one memory training code in a first storage sub-region, and one memory training code in a first storage sub-region corresponds to one remaining memory module.
[0036] In an optional implementation, the memory initialization method further includes:
[0037] Based on the number of memory modules, the second storage area of the first memory module is divided into multiple second storage sub-areas;
[0038] Store the first training values into the corresponding second storage sub-region; and
[0039] The target CPU core is sent a notification message in parallel to the target CPU core so that the target CPU core stores the remaining training values obtained into the corresponding second storage sub-region.
[0040] Among them, the remaining training values corresponding to a remaining memory module correspond to a second storage sub-region.
[0041] In one optional implementation, saving the first training values and the remaining training values to the target storage area includes:
[0042] Iteratively check whether the corresponding training values are stored in multiple second storage sub-regions;
[0043] In response to the detection that multiple second storage sub-regions store corresponding training values, the first training value and the remaining training value are read from the multiple second storage sub-regions, and the first training value and the remaining training value are saved to the transfer buffer; and
[0044] During the driver execution environment phase, the first training value and the remaining training value are read from the transfer buffer and saved to the target storage area.
[0045] In one optional implementation, the memory module is initialized based on the first training value and the remaining training values, including:
[0046] Write the first training value into the register of the first memory controller corresponding to the first memory module so that the first memory module is in working state;
[0047] Write the remaining training values into the register of the target memory controller of the corresponding remaining memory module to make the remaining memory module active.
[0048] Based on memory parameter information, determine the decoding address of the first memory module and the decoding addresses of the remaining memory modules; and
[0049] Based on the decoded address of the first memory module and the decoded address of the remaining memory module, the first memory module and the remaining memory module are mapped to the memory address space of the central processing unit, and the memory address space of the central processing unit is set to be valid to complete the initialization of the memory modules.
[0050] In an optional implementation, after the memory address space of the central processing unit is made valid, the memory initialization method further includes:
[0051] Perform read / write tests on the memory modules, which include the first memory module and the remaining memory modules;
[0052] Since the read and write tests of the memory module both passed, the initialization of the memory module was confirmed to have been successfully completed; and
[0053] If at least one memory module fails the read / write test, it is determined that the memory module initialization failed.
[0054] In an optional implementation, the memory initialization method further includes:
[0055] In response to a memory module initialization failure, the execution of subsequent stages after the memory initialization stage is stopped, and an error log is recorded so that the user can locate the cause of the memory module initialization failure based on the error log.
[0056] In an optional implementation, the memory initialization method further includes:
[0057] The code in the BIOS security phase is executed, and then the code before the memory initialization code in the pre-initialization phase is run, thus entering the memory initialization phase.
[0058] In one alternative implementation, the first mode is the BIOS's minimum memory boot-fastest mode; and / or, the second mode is the BIOS's boot-fastest mode where all memory is recognized.
[0059] In one alternative implementation, the first training value is the optimal memory configuration parameter for the first memory module.
[0060] In one alternative implementation, the notification information is inter-processor interrupt information.
[0061] In one alternative implementation, mapping the first memory module to the memory address space of the central processing unit includes:
[0062] The first memory module is mapped to the central processing unit's memory address space based on its memory capacity, start address, and end address.
[0063] Secondly, this application provides a server, including: a first central processing unit core, the first central processing unit core being used to execute the memory initialization method of the first aspect or any corresponding embodiment described above.
[0064] Thirdly, this application provides a computer device, including: a memory and a processor, which are communicatively connected to each other. The memory stores computer instructions, and the processor executes the computer instructions to perform the memory initialization method of the first aspect or any corresponding embodiment described above.
[0065] Fourthly, this application provides a computer-readable storage medium storing computer instructions that cause a computer to execute the memory initialization method described in the first aspect or any of its corresponding embodiments.
[0066] Fifthly, this application provides a computer program product, including computer instructions for causing a computer to execute the memory initialization method described in the first aspect or any corresponding embodiment thereof. Attached Figure Description
[0067] To more clearly illustrate the technical solutions in the specific embodiments or related technologies of this application, the drawings used in the description of the specific embodiments or related technologies will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.
[0068] Figure 1 is a schematic diagram of the structure of a multi-way server system in related technologies;
[0069] Figure 2 is a flowchart of the UEFI BIOS boot process in related technologies;
[0070] Figure 3 is a schematic diagram of the structure of UEFI BIOS in related technologies;
[0071] Figure 4 is a schematic diagram of the process of executing MRC code and completing memory initialization in related technologies;
[0072] Figure 5 is a flowchart illustrating a memory initialization method according to one or more embodiments of this application;
[0073] Figure 6 is a flowchart illustrating another memory initialization method according to one or more embodiments of this application;
[0074] Figure 7 is a flowchart illustrating another memory initialization method according to one or more embodiments of this application;
[0075] Figure 8 is a schematic diagram of copying the memory training code to the first memory module and saving the training values to the first memory module according to one or more embodiments of this application;
[0076] Figure 9 is a schematic diagram of the hardware structure of a computer device according to one or more embodiments of this application. Detailed Implementation
[0077] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0078] Memory is a crucial component of a computer system. Also known as internal memory or main memory, it is responsible for temporarily storing CPU processing data and data exchanged with external storage devices such as hard drives. It is also used to store instructions, data, variables, function call parameters, and return values of running programs.
[0079] Memory provides space for temporary data storage, enabling computer systems to quickly read and write data during execution, thus improving system response speed.
[0080] The BIOS (Basic Input / Output System) is a piece of software code embedded in the computer's motherboard. During computer startup, the BIOS is responsible for initializing hardware devices and loading the operating system into memory. Specifically, the BIOS loads the operating system and other necessary software from secondary storage into main memory. Main memory stores the operating system and, during program execution, continuously stores the data and instructions needed by the program. After initialization, the BIOS finally transfers control to the operating system, thus starting the entire system.
[0081] In terms of memory management, the BIOS is responsible for managing the allocation and release of system memory. It detects and identifies installed memory modules and records their information in the system configuration table. The BIOS also provides some basic memory management functions, such as switching to protected mode and setting memory mapping tables.
[0082] It is evident that the collaboration between memory and BIOS is crucial for the stable operation of server systems.
[0083] Figure 1 is a schematic diagram of a multi-processor server system in the related technology. As shown in Figure 1, the multi-processor server system includes two CPUs, namely CPU0 and CPU1, and a BIOS chip, which is a UEFI BIOS.
[0084] CPU0 and CPU1 are connected via UltraPath Interconnect (UPI), and CPU0 is connected to the BIOS chip via Serial Peripheral Interface (SPI).
[0085] The multi-processor server system also includes 32 memory modules, which are connected to the system via Dual Inline Memory Module (DIMM) slots. Essentially, one memory module is connected to the server through one DIMM slot. Each DIMM slot is connected to the CPU, meaning each memory module is connected to the CPU. These memory modules can be Double Data Rate (DDR) memory.
[0086] It is understood that Figure 1 is merely a structural example of a multi-processor server system. The multi-processor server system used in this application embodiment is not limited to this, and may also include more or fewer CPUs, more or fewer memory modules, etc., without specific limitations.
[0087] Figure 2 is a flowchart of the UEFI BIOS boot process in related technologies. As shown in Figure 2, when booting the multi-processor server system shown in Figure 1, the UEFI BIOS boot process generally includes the following stages, that is, the UEFI BIOS initialization process for the multi-processor server system generally includes the following stages:
[0088] 1. Security Phase (SEC): This is the first phase executed after power-on, marking the beginning of the entire system. The computer system enters this phase immediately after power-on. This phase primarily handles system startup, restart, and error signals. At this time, only the CPU and its internal resources are initialized; external devices and memory are not.
[0089] 2. Pre-EFI Initialization (PEI): Most of the code in this stage runs on the flash memory and mainly initializes the CPU and related hardware. The Memory Reference Code (MRC) in the BIOS runs in this stage, which means that memory initialization is performed in this stage.
[0090] The process involves running MRC code to initialize memory, copying other modules from the PEI stage into memory, and then running these modules to initialize the CPU and related hardware.
[0091] 3. Driver Execution Environment Stage (Dynamic Executable, abbreviated as DXE): This stage mainly involves a large amount of driver loading and initialization work. Related modules and code are copied into memory and run in memory.
[0092] 4. Boot Device Selection (BDS) phase: This phase involves other initialization actions.
[0093] The UEFI BIOS is stored in flash memory. Figure 3 is a schematic diagram of the structure of the UEFI BIOS in related technologies. As shown in Figure 3, the UEFI BIOS includes the SEC stage module, PEI stage module, BDS stage module, DXE stage module, and non-volatile random access memory (NVRAM) area.
[0094] The SEC phase module executes the code for the SEC phase, the PEI phase module executes the code for the PEI phase, the BDS phase module executes the code for the BDS phase, and the DXE phase module executes the code for the DXE phase. The NVRAM area is used to store information. The code running in the DXE and BDS phases can call the SetVariable service to save information to this area, ensuring that information is retained and not lost when the server system is powered off or restarted.
[0095] The PEI stage module comprises multiple PEI stage sub-modules and an MRC module. The multiple PEI stage sub-modules include PEI stage sub-module 1, PEI stage sub-module 2, PEI stage sub-module N, PEI stage sub-module N+1, etc., as shown in Figure 3. These PEI stage sub-modules are used for CPU and related hardware initialization. The MRC module is used to run MRC code and perform memory initialization.
[0096] During the UEFI BIOS boot process, different boot modes can be set in the PEI stage. The current boot mode can be retrieved and updated using the `GetBootMode()` and `SetBootMode()` functions. Modules in the PEI, DXE, and BDS stages can call `GetBootMode()` to determine whether certain modules run based on the set current boot mode.
[0097] It's important to note that memory, as a storage device, requires initialization after a multi-processor server system powers on so that the CPU can read and write data through designated interfaces. Because each machine has different motherboards and the same materials used, each machine needs to perform specific memory initialization upon startup. The MRC code, or memory initialization code, is typically provided by the CPU or BIOS manufacturer. When executing the MRC code, the CPU first reads the memory parameter information from the Serial Presence Detect (SPD) chip on the memory module via the internal integrated circuit (I2C) bus. Then, the MRC code, according to the program code set by the CPU manufacturer, performs specific initialization actions on the memory based on the memory parameter information read from the SPD.
[0098] Figure 4 is a schematic diagram of the process of executing MRC code to complete memory initialization in related technologies. As shown in Figure 4, taking the execution of MRC code on the multi-way server system shown in Figure 1 as an example, the process of executing MRC code to complete memory initialization is described, which includes the following steps:
[0099] The first step is to start executing the MRC code and read the SPD information of the memory modules in DIMM slots 0 to DIMM slot 31 in sequence.
[0100] Each DIMM slot is defined with a unique I2C address. The SPD (Special Device Display) is located on the memory module. When a memory module is connected to its corresponding DIMM slot, the SPD is connected to the CPU via the I2C bus. The SPD information of the memory modules in DIMM slots 0-31 is read sequentially according to their unique I2C addresses via the I2C bus. The SPD information contains the memory parameter information.
[0101] The second step is to initialize the memory modules in DIMM slots 0 through DIMM slot 31 in sequence.
[0102] Specifically, after obtaining the SPD information of the memory modules in DIMM slots 0 to DIMM slot 31, the memory modules in DIMM slots 0 to DIMM slot 31 are initialized sequentially according to the SPD information of the memory modules in DIMM slots 0 to DIMM slot 31.
[0103] The third step is to obtain the parameter values of the memory modules after training for DIMM slots 0 to DIMM slot 31.
[0104] The fourth step is to write the trained parameter values of the memory modules in DIMM slots 0 to DIMM slots 31 into the corresponding memory controller registers.
[0105] The fifth step is to map the decoded addresses of the memory modules in DIMM slots 0 to DIMM slots 31 to the CPU memory address space.
[0106] Step 6: Enable the CPU memory address space.
[0107] The seventh step is to perform read and write tests on the CPU's memory address space.
[0108] Step 8: The PEI service is invoked to report the current CPU memory address space to the PEI scheduler, and the MRC code execution ends.
[0109] Understandably, once the CPU memory address space read / write test passes and it is confirmed that the initialization of all memory modules has been successfully completed, the PEI service is called to report the current CPU memory address space to the PEI scheduler so that the PEI scheduler can continue to execute the subsequent PEI phase process.
[0110] The MRC code runs on flash memory and is executed sequentially when initializing the memory modules in each DIMM slot.
[0111] Flash memory typically uses a serial interface, resulting in slower read and write speeds, supporting read speeds of around 10MB-100MB / s. However, no special software initialization is required; the CPU can access its contents upon power-up. DDR memory, on the other hand, uses a parallel interface, offering faster read and write speeds, supporting read speeds of 2400MB-6400MB / s. However, it requires extensive initialization steps before the CPU can use it as storage space and read / write its contents.
[0112] It is evident that the read and write speed of flash memory is far lower than that of DDR memory. The MRC code runs more slowly on flash memory, resulting in longer memory initialization time and slower initialization speed.
[0113] Furthermore, the sequential initialization of memory modules in each DIMM slot results in low code execution efficiency. In multi-way server systems with a large amount of memory, the memory initialization process using related technologies is time-consuming and slow.
[0114] This application provides a memory initialization method. A first central processing unit (CPU) core initializes a memory module, copies memory training code to the memory module, and triggers the other CPU cores to execute the memory training code in the memory module in parallel, thereby completing the initialization of all memory modules. This reduces memory initialization time, increases memory initialization speed, and achieves the effect of fast memory initialization.
[0115] According to an embodiment of this application, a memory initialization method embodiment is provided. It should be noted that the steps shown in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions. Furthermore, although a logical order is shown in the flowchart, in some cases, the steps shown or described may be executed in a different order than that shown here.
[0116] This embodiment provides a memory initialization method that can be used in a first central processing unit (CPU) core in a server. The server may include multiple CPUs, and each CPU may include multiple CPU cores. The first CPU core can be any CPU core in the server. Figure 5 is a flowchart of the memory initialization method according to an embodiment of this application. As shown in Figure 5, the process includes the following steps:
[0117] Step S501: During the memory initialization phase, the memory initialization code is run to determine the current startup mode.
[0118] The process involves the server starting up and running the BIOS for hardware initialization. Specifically, the first CPU core in the server executes the SEC stage code in the BIOS, then runs the code before the MRC code in the PEI stage, and finally reaches the memory initialization stage in the PEI stage to run the memory initialization code, i.e., the MRC code.
[0119] The current boot mode of the BIOS is determined by running memory initialization code.
[0120] Step S502: If the current startup mode is the first mode, then obtain the memory parameter information of the memory module.
[0121] In this embodiment, two new BIOS boot modes are defined: DimmMiniFast (Minimum Memory Boot Fastest Mode) and DimmFullFast (All Memory Memory Recognized, Fastest Boot Mode). The first mode is DimmMiniFast mode, in which only one memory module is initialized and made available, the other memory modules are unavailable, and the BIOS can still boot.
[0122] With the current startup mode set to Mode 1, the first memory module needs to be initialized. This first memory module can be any memory module within the server. To initialize the first memory module, its memory parameter information is first obtained. This memory parameter information includes the memory parameter information for all memory modules.
[0123] Step S503: Based on the memory parameter information, train the first memory module to obtain the first training value.
[0124] Specifically, after obtaining the memory parameter information of the memory module, the first memory module is trained based on the memory parameter information of the first memory module to obtain the first training value.
[0125] It should be noted that memory training is a key step in memory initialization, used to ensure that the various parameters of the memory module (such as timing, voltage, frequency, etc.) are configured correctly so that it can work correctly under predetermined conditions.
[0126] By training the memory modules, the optimal memory configuration parameters can be found, thereby optimizing memory read / write speed and stability.
[0127] Memory training can also detect potential faults in memory modules and attempt to fix or bypass these problems, ensuring system reliability.
[0128] Understandably, the first training value can be the optimal memory configuration parameter for the first memory module.
[0129] Step S504: Based on the first training value, complete the initialization of the first memory module.
[0130] After obtaining the first training value, the first memory module is initialized based on the first training value.
[0131] Step S505: Copy the memory training code from the memory initialization code to the first memory module.
[0132] After the initialization of the first memory module is completed, the first central processing unit core reads the memory initialization code from the BIOS read-only memory (ROM) and copies the memory training code from the memory initialization code to the first memory module.
[0133] Step S506: Send notification information to the remaining CPU cores in parallel so that the remaining CPU cores respond to the notification information, train the remaining memory modules based on memory parameter information and memory training code, and obtain the remaining training values.
[0134] In this process, the first CPU core sends notification information in parallel to the other CPU cores. This notification information is an Inter-Processor Interrupt (IPI) message. This IPI message represents the communication method between different CPU cores in a multi-core CPU.
[0135] The remaining central processing unit cores receive the notification information and, in response to the notification information, train the remaining memory modules in parallel based on the memory parameter information and the memory training code in the first memory module, to obtain the remaining training values corresponding to the remaining memory modules.
[0136] Step S507: Save the first training value and the remaining training values to the target storage area and restart the server.
[0137] After obtaining the remaining training values, the first training value and the remaining training values are saved to the target storage area. This target storage area is the NVRAM area of the BIOS.
[0138] After saving the first training value and the remaining training values to the target storage area, the system restart service (resetsystem service) is called to restart the server, rerun the BIOS, and return to the execution step S501 and subsequent steps.
[0139] Step S508: If the current startup mode is the second mode, then obtain the first training value and the remaining training value from the target storage area.
[0140] The second mode is DimmFullFast. In this mode, all memory modules need to be initialized, all memory modules are available, and the BIOS can boot up.
[0141] If the current startup mode is the second mode, retrieve the first training value and the remaining training values from the target storage area.
[0142] Step S509: Based on the first training value and the remaining training values, complete the initialization of the memory module.
[0143] Specifically, after obtaining the first training value and the remaining training value from the target storage area, the memory module is initialized based on the first training value and the remaining training value.
[0144] The memory initialization method provided in this embodiment, during the memory initialization phase, runs memory initialization code to determine the current startup mode. If the current startup mode is the first mode, it first trains the first memory module based on its memory parameter information to obtain first training values. Based on these first training values, it completes the initialization of the first memory module. The memory training code is copied to the first memory module, and the remaining CPU cores, based on the memory parameter information and the memory training code, train the remaining memory modules in parallel to obtain remaining training values. The first and remaining training values are then saved to the target storage area, and the server is restarted. If the current startup mode is the second mode, the initialization of the memory modules is completed based on the first and remaining training values. This method, which uses the first CPU core to initialize one memory module, copies the memory training code to that memory module, triggers the remaining CPU cores to execute the memory training code in that memory module in parallel, and thus completes the initialization of all memory modules, reduces memory initialization time and improves memory initialization speed by executing the memory training code of multiple memory modules in parallel from the memory modules themselves. This achieves rapid memory initialization.
[0145] This embodiment provides a memory initialization method that can be used in the first central processing unit core of a server. Figure 6 is a flowchart of the memory initialization method according to an embodiment of this application. As shown in Figure 6, the process includes the following steps:
[0146] Step S601: During the memory initialization phase, the memory initialization code is run to determine the current startup mode.
[0147] Specifically, step S601 includes:
[0148] Step S6011: Run the memory initialization code to determine whether the target storage area includes the first training value and the remaining training values.
[0149] During the memory initialization phase, the first central processing unit core runs memory initialization code to determine whether the target memory includes the first training value and the remaining training values.
[0150] Step S6012: If the target storage area does not include the first training value and the remaining training value, determine the current startup mode as the first mode.
[0151] The target storage area does not include the first training value and the remaining training values, indicating that all memory modules have not been initialized, thus determining the current startup mode as the first mode.
[0152] It should be noted that if the target storage area does not include the first training value and the remaining training values, the SetBootMode() parameter is called to set the current boot mode to the first mode.
[0153] Step S6013: If the target storage area includes the first training value and the remaining training value, determine the current startup mode as the second mode.
[0154] The target storage area includes the first training value and the remaining training value, indicating that all modules can be initialized based on the first training value and the remaining training value, and the current startup mode is determined to be the second mode.
[0155] It should be noted that if the target storage area includes the first training value and the remaining training values, the SetBootMode() parameter is called to set the current boot mode to the second mode.
[0156] Step S602: If the current startup mode is the first mode, then obtain the memory parameter information of the memory module.
[0157] Specifically, step S602 includes:
[0158] Step S6021: Obtain memory parameter information of the memory module based on the address information of the memory module.
[0159] Each memory slot is defined with a unique I2C address. The SPD is located on the memory module. When the memory is connected to the memory slot, the SPD on the memory module is connected to the CPU via the I2C bus. The MRC code reads the SPD information of the memory module corresponding to the DIMM slot sequentially according to the unique I2C address via the I2C bus.
[0160] Step S603: Based on the memory parameter information, train the first memory module to obtain the first training value. For details, please refer to step S503 of the embodiment shown in Figure 5, which will not be repeated here.
[0161] Step S604: Based on the first training value, complete the initialization of the first memory module.
[0162] Specifically, step S604 includes:
[0163] Step S6041: Write the first training value into the register of the first memory controller corresponding to the first memory module so that the first memory module is in working state.
[0164] After obtaining the first training value, the first training value is written into the register of the first memory controller corresponding to the first memory module so that the first memory module is in working state.
[0165] Step S6042: Determine the decoding address of the first memory module based on the memory parameter information.
[0166] Specifically, the decoding address of the first memory module is determined based on the memory parameter information of the first memory module. This decoding address includes the start address and end address of the first memory module.
[0167] Step S6043: Based on the decoded address of the first memory module, map the first memory module to the memory address space of the central processing unit, and set the memory address space of the central processing unit to be valid, so as to complete the initialization of the first memory module.
[0168] Specifically, after obtaining the decoded address of the first memory module, the first memory module is mapped to the memory address space of the central processing unit according to the decoded address of the first memory module. That is, the first memory module is mapped to the memory address space of the central processing unit according to the memory capacity, start address and end address of the first memory module.
[0169] The CPU's memory address space is set to be valid, which means the memory address space of the first memory module is set to be valid. At this time, the range of the memory address space that the CPU can read and write is from 0 to the memory capacity of the first memory module.
[0170] Step S605: Copy the memory training code from the memory initialization code to the first memory module. For details, please refer to step S505 of the embodiment shown in Figure 5, which will not be repeated here.
[0171] Step S606: Notification information is sent in parallel to the remaining CPU cores, causing them to respond to the notification information and train the remaining memory modules based on memory parameter information and memory training code to obtain the remaining training values. For details, please refer to step S506 of the embodiment shown in Figure 5, which will not be repeated here.
[0172] Step S607: Save the first training value and the remaining training values to the target storage area and restart the server. For details, please refer to step S507 of the embodiment shown in Figure 5, which will not be repeated here.
[0173] Step S608: If the current startup mode is the second mode, then obtain the first training value and the remaining training values from the target storage area. For details, please refer to step S508 of the embodiment shown in Figure 5, which will not be repeated here.
[0174] Step S609: Based on the first training value and the remaining training values, the memory module is initialized. For details, please refer to step S509 of the embodiment shown in Figure 5, which will not be repeated here.
[0175] The memory initialization method provided in this embodiment accurately determines the current startup mode by judging whether the target storage area includes the first training value and the remaining training value, avoiding unnecessary initialization steps and speeding up the system startup.
[0176] By obtaining the memory module's memory parameter information based on its address information, the memory parameter information can be obtained quickly and accurately.
[0177] By writing the first training value into the register of the first memory controller corresponding to the first memory module, the first memory module is put into a working state. Based on the memory parameter information, the decoding address of the first memory module is determined. Based on the decoding address of the first memory module, the first memory module is mapped to the memory address space of the central processing unit, and the memory address space of the central processing unit is set to be valid. The initialization of the first memory module can be accurately completed, which improves the overall performance and reliability of the system.
[0178] In some optional implementations, step S605 above includes:
[0179] Step a1: Determine the number of memory training codes to be copied based on the number of memory modules.
[0180] Specifically, the number of memory training code modules to be copied is determined based on the number of memory modules currently in the server. The number of memory training code modules to be copied is the same as the number of memory modules.
[0181] Step a2: Based on the number of memory training codes to be copied, the first storage area of the first memory module is divided into multiple first storage sub-areas.
[0182] Specifically, the first memory module is divided into a first storage region, and the first storage region is further divided into a corresponding number of first storage sub-regions according to the number of memory training codes to be copied.
[0183] Step a3: Copy the memory training code to multiple first storage sub-regions.
[0184] Understandably, the memory training code corresponding to each memory module is copied to the corresponding first storage sub-region in the order of the memory modules. Each first storage sub-region contains one copy of the memory training code.
[0185] The memory initialization method provided in this embodiment can execute the initialization process of multiple memory modules in parallel by copying the memory training code to multiple first storage sub-regions of the first memory module, which significantly reduces the memory initialization time and improves the system startup speed.
[0186] In some optional implementations, step S606 includes:
[0187] Step b1: Based on the number of memory modules, select the target CPU core from the remaining CPU cores.
[0188] In this embodiment, the number of central processing unit (CPU) cores in the server is greater than the number of memory modules. The target CPU cores, which are the same number as the number of memory modules, are selected from the CPU cores other than the first CPU core.
[0189] It should be noted that a corresponding number of target CPU cores can be randomly selected from the remaining CPU cores.
[0190] Based on the number of memory modules, target CPU cores are selected from the remaining CPU cores, including:
[0191] Based on the order of the CPU cores in the server, target CPU cores that are the same number as the memory modules are selected from the remaining CPU cores.
[0192] Alternatively, performance monitoring tools can be used to obtain the performance data of each CPU core in the remaining CPU cores. Based on the performance data, the remaining CPU cores can be sorted from high to low performance, and the target CPU cores with the same number of memory modules at the top of the sorted results can be selected.
[0193] Alternatively, system monitoring tools can be used to obtain the load data of each CPU core in the remaining CPU cores. Based on the load data, the information of the remaining CPU cores can be sorted, with the higher the load, the lower the sorting. The target CPU cores with the same number of memory modules as the top sorted results can be selected.
[0194] Selecting target CPU cores based on their order within the server requires no additional monitoring tools or complex algorithms, making it easy to implement and maintain. Using performance data to select target CPU cores allows for better utilization of system resources, improves overall system performance, and accelerates memory initialization. Using load data to select target CPU cores improves system stability and responsiveness, and speeds up memory initialization.
[0195] In practical applications, one of the above methods can be used to filter target central processing unit cores, depending on the actual situation.
[0196] Step b2: Send notification information to the target CPU core in parallel, so that the target CPU core responds to the notification information and trains the remaining memory modules based on the memory parameter information and the memory training code in the corresponding first storage sub-region to obtain the remaining training values.
[0197] In this context, one target central processing unit core corresponds to one memory training code in a first storage sub-region, and one memory training code in a first storage sub-region corresponds to one remaining memory module.
[0198] It is understandable that, for any target CPU core, after receiving the notification information, in response to the notification information, the target CPU core trains the remaining memory module corresponding to the target CPU core based on the memory parameter information of the remaining memory module corresponding to the target CPU core and the memory training code in the first storage sub-region corresponding to the target CPU core, and obtains the remaining training value of the remaining memory module.
[0199] The memory initialization method provided in this embodiment reduces the time required for memory initialization and improves the system startup speed by sending notification information to the target CPU core in parallel.
[0200] In some optional implementations, the memory initialization method further includes:
[0201] Step c1: Based on the number of memory modules, divide the second storage area of the first memory module into multiple second storage sub-areas.
[0202] Specifically, the first memory module is divided into a second storage area, and the second storage area is further divided into a corresponding number of second storage sub-areas based on the number of memory modules in the server.
[0203] Step c2: Store the first training value into the corresponding second storage sub-region.
[0204] It is understandable that the first training value is stored in the corresponding second storage sub-region according to the order of the first memory module in all memory modules.
[0205] Step c3: Send notification information to the target CPU core in parallel so that the target CPU core stores the remaining training values obtained into the corresponding second storage sub-region.
[0206] Among them, the remaining training values corresponding to a remaining memory module correspond to a second storage sub-region.
[0207] The memory initialization method provided in this embodiment divides the second storage area of the first memory module into multiple second storage sub-areas. The remaining training values of each remaining memory module can be stored in one of the second storage sub-areas, avoiding interference and conflict between data. This achieves efficient and orderly storage of the training values of each memory module, significantly improving the performance and reliability of the system.
[0208] In some optional implementations, step S607 above includes:
[0209] Step d1 involves iteratively checking whether the corresponding training values are stored in multiple second storage sub-regions.
[0210] Specifically, after the first central processing unit core sends notification information to the target central processing unit core in parallel, it cyclically checks whether the corresponding training values are stored in multiple second storage sub-regions. The training values include the first training value and the remaining training values.
[0211] Step d2: If multiple second storage sub-regions are found to store corresponding training values, then read the first training value and the remaining training value from the multiple second storage sub-regions and save the first training value and the remaining training value to the transfer buffer.
[0212] If multiple second storage sub-regions are found to contain corresponding training values, it indicates that the training of all memory modules has been completed. The first training value and the remaining training value are read from multiple second storage sub-regions, and an overlay data block (HOB, or transfer buffer) is created. The first training value and the remaining training value are then saved to the transfer buffer.
[0213] It should be noted that HOB is an important data structure used to pass information between different startup phases.
[0214] Step d3: In the driver execution environment stage, read the first training value and the remaining training value from the transfer buffer, and save the first training value and the remaining training value to the target storage area.
[0215] It should be noted that in the first mode, the first CPU core skips other modules in the PEI stage. When it reaches the driver execution environment stage, the first CPU core reads the first training value and the remaining training value from the transfer buffer and calls the Setvariable service to save the first training value and the remaining training value to the NVRAM area.
[0216] The memory initialization method provided in this embodiment ensures that all necessary training values have been correctly stored by cyclically checking whether the corresponding training values are stored in multiple second storage sub-regions. This avoids initialization failure or system abnormalities caused by missing training values, ensures the integrity and consistency of training values in the memory module, and improves the performance and reliability of the system.
[0217] In some optional implementations, step S609 above includes:
[0218] Step e1: Write the first training value into the register of the first memory controller corresponding to the first memory module so that the first memory module is in working state.
[0219] In the second mode, after obtaining the first training value and the remaining training value, the first training value is written into the register of the first memory controller corresponding to the first memory module so that the first memory module is in working state.
[0220] Step e2: Write the remaining training values into the register of the target memory controller of the corresponding remaining memory module so that the remaining memory module is in working state.
[0221] In the second mode, the remaining training values are written to the register of the target memory controller of the corresponding remaining memory module to make the remaining memory module active.
[0222] Step e3: Based on the memory parameter information, determine the decoding address of the first memory module and the decoding address of the remaining memory modules.
[0223] Understandably, in the second mode, it is also necessary to obtain the memory parameter information of the memory modules, and determine the decoding address of the first memory module and the decoding address of the remaining memory modules based on the memory parameter information.
[0224] Step e4: Based on the decoding address of the first memory module and the decoding address of the remaining memory module, map the first memory module and the remaining memory module to the memory address space of the central processing unit, and set the memory address space of the central processing unit to be valid to complete the initialization of the memory modules.
[0225] After obtaining the decoding addresses of the first memory module and the remaining memory modules, the first memory module and the remaining memory modules are mapped to the memory address space of the central processing unit based on the decoding addresses of the first memory module and the remaining memory modules, and the memory address space of the central processing unit is set to be valid, that is, the memory address spaces of the first memory module and the remaining memory modules are set to be valid, thus completing the initialization of all memory modules.
[0226] The memory initialization method provided in this embodiment ensures that each memory module can start up correctly and enter the working state by writing the first training value into the register of the first memory controller corresponding to the first memory module and writing the remaining training value into the register of the target memory controller of the corresponding remaining memory module. This avoids the risk of memory modules failing to work properly due to configuration errors and improves the performance and stability of the system.
[0227] In some alternative implementations, after the memory address space of the central processing unit is made valid, the memory initialization method further includes:
[0228] Step f1 involves performing read / write tests on the memory modules, which include the first memory module and the remaining memory modules.
[0229] After the memory module is initialized, a read / write test is required, which involves reading and writing the memory address space of the memory module to determine whether the memory module has been successfully initialized.
[0230] Step f2: If the read and write tests of the memory module pass, the initialization of the memory module is confirmed to be successful.
[0231] It should be noted that, after the memory module read and write tests pass, the PEI service is called to report the current CPU memory address space to the PEI scheduler so that the PEI scheduler can continue to execute the subsequent PEI phase process.
[0232] Step f3: If at least one memory module fails the read / write test, the memory module initialization is determined to have failed.
[0233] The memory initialization method provided in this embodiment can verify whether each memory module can correctly read and write data through read and write tests, ensuring that the memory modules can work normally after initialization, avoiding system instability or data loss caused by memory failure, and improving system reliability.
[0234] In some optional implementations, the memory initialization method further includes:
[0235] Step g1: If the memory module initialization fails, stop executing the stages after the memory initialization stage and record an error log so that the user can locate the cause of the memory module initialization failure based on the error log.
[0236] The memory initialization method provided in this embodiment prevents the system from continuing to run in an erroneous state by stopping the execution of subsequent stages after the memory initialization stage in the event of a memory module initialization failure. This avoids further failures or data corruption and improves the reliability and maintainability of the system.
[0237] To make the memory initialization method of this application clearer, the memory initialization method of this application embodiment is described in conjunction with a specific embodiment. In this specific embodiment, the server includes two CPUs and 32 memory modules (DIMM0-DIMM31), and each CPU includes 16 CPU cores. Figure 7 is a flowchart of the memory initialization method according to an embodiment of this application. As shown in Figure 7, the memory initialization method includes the following steps:
[0238] The first step involves powering on the server, running the BIOS, and starting the SEC phase code on CPU0 core0. It should be noted that this embodiment describes the memory initialization method executed by CPU0 core0 as an example.
[0239] The second step is for CPU0 core0 to run the code before the PEI stage MRC code, that is, to run the module before the PEI stage MRC.
[0240] The third step involves executing the MRC section, which checks whether all memory modules DIMM0-DIMM31 have not been initialized. This is achieved by reading the MRC-PARM-HOB-NV variable in the BIOS NVRAM area to determine if the MRC-PARM-HOB-NV content exists.
[0241] If it does not exist, call SetBootMode() to set the current boot mode to DimmMiniFast mode.
[0242] If it exists, call SetBootMode() to set the current boot mode to DimmFullFast mode.
[0243] If the current startup mode is DimmMiniFast, proceed with steps four through nineteen.
[0244] If the current startup mode is DimmFullFast, proceed to steps 20 through 27.
[0245] The fourth step is to read the SPD information of DIMM0 to obtain the memory capacity of DIMM0, which is called DIMM0SIZE.
[0246] The fifth step is to initialize the training DIMM0 and obtain the parameter values of DIMM0 after training, which is also the first training value, called PARAM0.
[0247] Step 6: Write PARAM0 to the PARAM0-TRQSD0 register of the memory controller (CPU0-UMC0-DIMM0) corresponding to DIMM0.
[0248] Step 7: Map the decoded address of DIMM0, DIMM0-SIZE, to the CPU's memory address space.
[0249] Step 8: Make DIMM0's memory address space valid. At this point, the readable and writable memory address space (DIMM0SPACE) range for CPU0 and CPU1 is 0-DIMM0SIZE. The current CPU memory address space is reported to the PEI scheduler by calling the PEI service InstallEfiMemory to determine the currently readable and writable memory address space.
[0250] Step 9: CPU0 core0 reads the contents of the MRC module in the BIOS ROM and copies 32 copies of the memory training code (excluding other parts) to DIMM0SPACE. Figure 8 is a schematic diagram of copying the memory training code to the first memory module and saving the training values to the first memory module according to an embodiment of this application. As shown in Figure 8, the first memory module is DIMM0, and the memory training code is MRC-CODE0 to MRC-CODE31.
[0251] Step 10: Divide the memory address space of DIMM0 into 32 parts to store the parameter structure after training of the corresponding DIMM, that is, the training values of the memory module, as shown in MRC-PARM0 to MRC-PARM31 in Figure 8.
[0252] Step 11: DIMM0 has been trained. Copy PARAM0 to the MRC-PARM0 region.
[0253] The twelfth step is to send IPI information to the remaining CPU cores in parallel. Specifically, CPU0 CORE0 sends IPI information to CPU CORE1, CPU CORE2, and so on, up to CPU CORE31, and executes MRC-CODE1 to MRC-CODE31 in sequence.
[0254] For example:
[0255] CPU0 CORE0 sends IPI information to CPU0 CORE1, notifying it to execute MRC-CODE1. After MRC-CODE1 is executed, the memory training information, i.e. the training values, of DIMM1 is stored in the MRC-PARM1 area.
[0256] CPU0 CORE0 sends IPI information to CPU0 CORE2, notifying it to execute MRC-CODE2. After MRC-CODE2 is executed, the memory training information of DIMM2 is stored in the MRC-PARM2 area.
[0257] CPU0 CORE0 sends IPI information to CPU1 CORE0, notifying it to execute MRC-CODE16. After MRC-CODE16 is executed, the memory training information of DIMM16 is stored in the MRC-PARM16 area.
[0258] CPU0 CORE0 sends IPI information to CPU1 CORE15, notifying it to execute MRC-CODE31. After MRC-CODE31 is executed, the memory training information of DIMM31 is stored in the MRC-PARM31 area.
[0259] The process of training memory modules by other central processing unit cores is similar to the example above, and will not be repeated here.
[0260] Step 13: CPU0 CORE0 loops through memory module regions MRC-PARAM0 to MRC-PARAM31 until all memory modules have been trained.
[0261] Step 14: CPU0 CORE0 reads the contents of MRC-PARAM0, MRC-PARAM1...MRC-PARAM31, creates a HOB, and defines it as MRC-PARAM-HOB.
[0262] Step 15: CPU0 and CORE0 complete the first MRC execution.
[0263] Step 16: In DimmMiniFast mode, CPU0 CORE0 executes MRC to complete the initialization of DIMM0 memory, skips the execution of other modules in the PEI stage, only copies the necessary modules of the PEI stage into memory, and runs the necessary modules of the PEI stage.
[0264] Step 17: CPU0 CORE runs to the DXE stage.
[0265] Step 18: In DimmMiniFast mode, the necessary modules of the DXE stage run, read the MRC-PARM-HOB content, and call the Setvariable service to save the MRC-PARM-HOB content into NVRAM, which is called MRC-PARM-HOB-NV.
[0266] Step nineteen: Call the resetsystem service to restart the system. Understandably, after restarting the system, steps one and subsequent steps will be executed again.
[0267] Step 20: Read the contents of MRC-PARM-HOB-NV to obtain MRC-PARAM0, MRC-PARAM1...MRC-PARAM31.
[0268] Step 21: Write the read content into the registers of the corresponding memory controller for each DIMM in sequence.
[0269] Step 22: Map the decoded addresses of DIMM0-DIMM31, DIMM0-SIZE-DIMM31-SIZE, to the CPU's memory address space.
[0270] Step 23: Make the memory address space of DIMM0-DIMM31 valid.
[0271] Step 24: Perform read and write tests on the memory address space of DIMM0-DIMM31.
[0272] Step 25: Call the PEI service InstallEfiMemory to report the current CPU memory address space to the PEI scheduler.
[0273] Step 26: CPU0 CORE0 executes MRC code to complete the memory initialization of DIMM0-DIMM31.
[0274] Step 27: Continue executing other modules. In DimmFullFast mode, this includes executing all remaining modules from the PEI stage, all remaining modules from the DXE stage, and the BDS stage to boot into the operating system (OS).
[0275] The memory initialization method provided in this embodiment utilizes a first central processing unit core to initialize a memory module, copies the memory training code to the memory module, triggers the other central processing unit cores to execute the memory training code in the memory module in parallel, and thus completes the initialization of all memory modules. This reduces the memory initialization time, improves the memory initialization speed, and achieves fast memory initialization.
[0276] This embodiment also provides a server, which includes a first central processing unit core for executing the memory initialization method shown in the above embodiment.
[0277] This application also provides a computer device. Referring to Figure 9, which is a schematic diagram of the structure of a computer device according to an optional embodiment of this application, the computer device includes one or more processors 901, a memory 902, and interfaces for connecting the various components, including high-speed interfaces and low-speed interfaces. The various components communicate with each other using different buses and can be installed on a common motherboard or otherwise as needed. The processor can process instructions executed within the computer device, including instructions stored in or on memory to display graphical information of a GUI on an external input / output device (such as a display device coupled to the interface). In some optional embodiments, multiple processors and / or multiple buses can be used with multiple memories and multiple memory modules, if desired. Similarly, multiple computer devices can be connected, each providing some of the necessary operations (e.g., as a server array, a group of blade servers, or a multiprocessor system). Figure 9 shows an example of a single processor 901.
[0278] Processor 901 may be a central processing unit, a network processor, or a combination thereof. Processor 901 may further include a hardware chip. The hardware chip may be an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or a combination thereof. The programmable logic device may be a complex programmable logic device (CAMP), a field-programmable gate array (FPGA), a general-purpose array logic (GDA), or any combination thereof.
[0279] The memory 902 stores instructions executable by at least one processor 901 to cause at least one processor 901 to perform the method shown in the above embodiments.
[0280] The memory 902 may include a program storage area and a data storage area. The program storage area may store the operating system and applications required for at least one function; the data storage area may store data created based on the use of the computer device. Furthermore, the memory 902 may include high-speed random access memory and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some alternative embodiments, the memory 902 may optionally include memory remotely located relative to the processor 901, and these remote memories can be connected to the computer device via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.
[0281] The memory 902 may include volatile memory, such as random access memory; the memory may also include non-volatile memory, such as flash memory, hard disk or solid-state drive; the memory 902 may also include a combination of the above types of memory.
[0282] The computer device also includes a communication interface 903 for communicating with other devices or communication networks.
[0283] This application also provides a computer-readable storage medium. The methods described in this application can be implemented in hardware or firmware, or implemented as recordable on a storage medium, or implemented as computer code downloaded over a network and originally stored on a remote storage medium or a non-transitory machine-readable storage medium and subsequently stored on a local storage medium. Thus, the methods described herein can be processed by software stored on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. The storage medium can be a magnetic disk, optical disk, read-only memory, random access memory, flash memory, hard disk, or solid-state drive, etc.; further, the storage medium can also include combinations of the above types of memory. It is understood that computers, processors, microprocessor controllers, or programmable hardware include storage components capable of storing or receiving software or computer code. When the software or computer code is accessed and executed by the computer, processor, or hardware, the methods shown in the above embodiments are implemented.
[0284] A portion of this application can be applied as a computer program product, such as computer program instructions, which, when executed by a computer, can invoke or provide the methods and / or technical solutions according to this application through the operation of the computer. Those skilled in the art will understand that the forms in which computer program instructions exist in a computer-readable medium include, but are not limited to, source files, executable files, installation package files, etc. Correspondingly, the ways in which computer program instructions are executed by a computer include, but are not limited to: the computer directly executing the instructions, or the computer compiling the instructions and then executing the corresponding compiled program, or the computer reading and executing the instructions, or the computer reading and installing the instructions and then executing the corresponding installed program. Here, the computer-readable medium can be any available computer-readable storage medium or communication medium accessible to a computer.
[0285] Although embodiments of this application have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of this application, and all such modifications and variations fall within the scope defined by the appended claims.
Claims
1. A memory initialization method, characterized in that, Applied to a first central processing unit core, the method includes: During the memory initialization phase, memory initialization code is executed to determine the current startup mode; In response to the current startup mode being the first mode, obtain the memory parameter information of the memory module; Based on the memory parameter information, the first memory module is trained to obtain the first training value; Based on the first training value, the initialization of the first memory module is completed; Copy the memory training code from the memory initialization code to the first memory module; The remaining CPU cores are sent notification information in parallel to the other CPU cores so that the other CPU cores respond to the notification information and train the remaining memory modules based on the memory parameter information and the memory training code to obtain the remaining training values. Save the first training value and the remaining training values to the target storage area, and restart the server; In response to the current startup mode being the second mode, the first training value and the remaining training values are retrieved from the target storage area; and Based on the first training value and the remaining training value, the memory module is initialized.
2. The method according to claim 1, characterized in that, The runtime memory initialization code determines the current startup mode, including: Run memory initialization code to determine whether the target storage area includes the first training value and the remaining training value; In response to the fact that the target storage area does not include the first training value and the remaining training value, the current startup mode is determined to be the first mode; and In response to the target storage area including the first training value and the remaining training value, the current startup mode is determined to be the second mode.
3. The method according to claim 1, characterized in that, The acquisition of memory parameter information of the memory module includes: Based on the address information of the memory module, obtain the memory parameter information of the memory module.
4. The method according to claim 1, characterized in that, The initialization of the first memory module based on the first training value includes: The first training value is written into the register of the first memory controller corresponding to the first memory module, so that the first memory module is in a working state. Based on the memory parameter information, the decoding address of the first memory module is determined; and Based on the decoded address of the first memory module, the first memory module is mapped to the memory address space of the central processing unit, and the memory address space of the central processing unit is set to be valid, so as to complete the initialization of the first memory module.
5. The method according to claim 1, characterized in that, The step of copying the memory training code from the memory initialization code to the first memory module includes: Based on the number of memory modules, determine the number of memory training codes to be copied; Based on the number of memory training codes to be copied, the first storage area of the first memory module is divided into multiple first storage sub-regions; and The memory training code is copied to multiple first storage sub-regions.
6. The method according to claim 5, characterized in that, The step of sending notification information to the remaining CPU cores in parallel, so that the remaining CPU cores respond to the notification information, and training the remaining memory modules based on the memory parameter information and the memory training code to obtain the remaining training values, includes: Based on the number of memory modules, a target CPU core is selected from the remaining CPU cores; and The target CPU core is sent a notification message in parallel to the target CPU core so that the target CPU core responds to the notification message and trains the remaining memory modules based on the memory parameter information and the memory training code in the corresponding first storage sub-region to obtain the remaining training values. In this context, one target central processing unit core corresponds to one memory training code in a first storage sub-region, and one memory training code in a first storage sub-region corresponds to one remaining memory module.
7. The method according to claim 6, characterized in that, The method further includes: Based on the number of memory modules, the second storage area of the first memory module is divided into multiple second storage sub-areas; Store the first training value into the corresponding second storage sub-region; and The target CPU core is sent a notification message in parallel to the target CPU core so that the target CPU core stores the remaining training values obtained into the corresponding second storage sub-region. Among them, the remaining training values corresponding to a remaining memory module correspond to a second storage sub-region.
8. The method according to claim 7, characterized in that, Saving the first training value and the remaining training values to the target storage area includes: Iteratively check whether the corresponding training values are stored in multiple second storage sub-regions; In response to the detection that corresponding training values are stored in multiple second storage sub-regions, the first training value and the remaining training value are read from the multiple second storage sub-regions, and the first training value and the remaining training value are saved to the transfer buffer; and During the driver execution environment phase, the first training value and the remaining training value are read from the transmission buffer and saved to the target storage area.
9. The method according to claim 1, characterized in that, The initialization of the memory module based on the first training value and the remaining training values includes: The first training value is written into the register of the first memory controller corresponding to the first memory module, so that the first memory module is in a working state. The remaining training values are written into the register of the target memory controller of the corresponding remaining memory module so that the remaining memory module is in a working state; Based on the memory parameter information, the decoding address of the first memory module and the decoding address of the remaining memory modules are determined; and Based on the decoding address of the first memory module and the decoding address of the remaining memory module, the first memory module and the remaining memory module are mapped to the memory address space of the central processing unit, and the memory address space of the central processing unit is set to be valid to complete the initialization of the memory modules.
10. The method according to claim 9, characterized in that, After setting the memory address space of the central processing unit to be valid, the method further includes: The memory module, which includes a first memory module and a remaining memory module, is subjected to read / write tests. Since the read and write tests of the memory module all passed, it is determined that the initialization of the memory module was successfully completed; and If at least one memory module fails the read / write test, it is determined that the memory module initialization failed.
11. The method according to claim 1, characterized in that, The method further includes: In response to the memory module initialization failure, the execution of subsequent stages after the memory initialization stage is stopped, and an error log is recorded so that the user can locate the cause of the memory module initialization failure based on the error log.
12. The method according to claim 1, characterized in that, The method further includes: The code in the security phase of the BIOS is executed, and then the code before the memory initialization code in the pre-initialization phase is run, thus entering the memory initialization phase.
13. The method according to claim 1, characterized in that, The first mode is the BIOS's minimum memory startup speed mode; and / or, the second mode is the BIOS's fastest startup mode that recognizes all memory.
14. The method according to claim 1, characterized in that, The first training value is the optimal memory configuration parameter for the first memory module.
15. The method according to claim 1, characterized in that, The notification information is an inter-processor interrupt information.
16. The method according to claim 4, characterized in that, The step of mapping the first memory module to the memory address space of the central processing unit includes: The first memory module is mapped to the memory address space of the central processing unit based on its memory capacity, start address, and end address.
17. A server, characterized in that, include: A first central processing unit core, the first central processing unit core being configured to execute the memory initialization method according to any one of claims 1 to 16.
18. A computer device, characterized in that, include: A memory and a processor are communicatively connected, the memory stores computer instructions, and the processor executes the computer instructions to perform the memory initialization method according to any one of claims 1 to 16.
19. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions for causing a computer to perform the memory initialization method according to any one of claims 1 to 16.
20. A computer program product, characterized in that, Includes computer instructions for causing a computer to perform the memory initialization method according to any one of claims 1 to 16.