Display panel and manufacturing method therefor, and display apparatus
By using a pixel definition layer as a mask to etch the first electrode layer during the OLED display manufacturing process and setting a support layer between adjacent electrodes, the problem of residual ITO overlapping sub-pixels is solved, improving product quality and yield.
Patent Information
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- BOE TECHNOLOGY GROUP CO LTD
- Filing Date
- 2025-10-14
- Publication Date
- 2026-06-04
AI Technical Summary
During the anodic etching process, residual ITO in OLED displays can easily adhere to the sub-pixels, leading to display abnormalities.
A pixel definition layer is used as a mask to etch the first electrode layer, ensuring that all remaining parts of the first electrode layer are protected by the pixel definition layer, thus preventing ITO from falling off due to lack of Ag layer support. The sides of adjacent electrodes are covered by a support layer and a support portion is provided to prevent ITO drift.
It completely improves the display abnormality problem caused by ITO residue, and significantly improves product quality and yield.
Smart Images
Figure CN2025127461_04062026_PF_FP_ABST
Abstract
Description
Display panel and its manufacturing method, display device Cross-references to related applications
[0001] This disclosure claims priority to Chinese patent application No. 2024117085496, filed on November 26, 2024, the entire contents of which are incorporated herein by reference. Technical Field
[0002] This disclosure relates to the field of display technology, and in particular to a display panel, a method for manufacturing the same, and a display device. Background Technology
[0003] Indium tin oxide (ITO) has gained popularity in recent years due to its high conductivity, high visible light transmittance, high mechanical hardness, and good chemical stability. It is now widely used in transparent electrodes of electronic devices such as LCD (Liquid Crystal Display), OLED (Organic Light-Emitting Diode) displays, touchscreens, solar cells, and electronic instruments. However, in OLED displays, residual ITO from the anodic etching process can easily aggregate between sub-pixels, leading to display abnormalities. Summary of the Invention
[0004] This disclosure provides a display panel and its manufacturing method, as well as a display device, which aims to at least partially solve the problem of residual ITO in OLED displays during the anodic etching process.
[0005] In a first aspect of this disclosure, a display panel is provided, the display panel including: a substrate; a first electrode layer located on the substrate; the first electrode layer including a plurality of mutually spaced first electrodes; and a pixel definition layer located on the side of the first electrode layer away from the substrate; the pixel definition layer including a pixel definition portion corresponding to each of the first electrodes, the pixel definition portion having a pixel opening communicating with the corresponding first electrode; the outer edge of the orthographic projection of the pixel definition portion on the substrate coincides with the edge of the orthographic projection of the corresponding first electrode on the substrate.
[0006] In some embodiments, the display panel may further include a support layer located at least between two adjacent first electrodes and covering the sides of adjacent first electrodes.
[0007] In some embodiments, the support layer may be continuously disposed on the substrate, and the support layer has a first opening corresponding to each of the first electrodes, with the first electrodes located within the corresponding first openings.
[0008] In some embodiments, the support layer may have a plurality of spaced grooves on the side near the substrate, and the pixel definition layer may further include a support portion corresponding to each groove, the support portion being located within the corresponding groove.
[0009] In some embodiments, the first electrode layer may further include residual portions corresponding to each of the support portions, the residual portions and the corresponding support portions being located in the same groove; the edge of the orthographic projection of the residual portion on the substrate coincides with the edge of the orthographic projection of the corresponding support portion on the substrate.
[0010] In some embodiments, the residue may be located between two adjacent first electrodes and spaced apart from the adjacent first electrodes; the support layer is located between the residue and the adjacent first electrodes.
[0011] In some embodiments, the first electrodes may be arranged in multiple columns, with the residue located between two first electrodes in the same column.
[0012] In some embodiments, the display panel may further include: a light-emitting layer, including light-emitting portions corresponding to each of the pixel definition portions; the light-emitting portions are at least located within the corresponding pixel openings and connected to the corresponding first electrode; and a second electrode layer, located on the side of the light-emitting layer away from the substrate and connected to each of the light-emitting portions.
[0013] In some embodiments, the display panel may further include: a driving circuit layer located between the first electrode layer and the substrate; the driving circuit layer including thin-film transistors corresponding to each of the first electrodes; and a planarization layer located between the driving circuit layer and the first electrode layer; the planarization layer having first vias corresponding to each of the first electrodes, the first electrodes being connected to the corresponding thin-film transistors through the corresponding first vias.
[0014] In some embodiments, the first electrode layer may include a first transparent electrode sublayer, a reflective electrode sublayer, and a second transparent electrode sublayer stacked sequentially along a direction away from the substrate, wherein the etching rates of the first transparent electrode sublayer and the second transparent electrode sublayer are both less than the etching rate of the reflective electrode sublayer.
[0015] In a second aspect of this disclosure, a display device is provided, which may include a display panel as provided in the first aspect.
[0016] In a third aspect of this disclosure, a method for manufacturing a display panel is provided. The method may include: providing a substrate; depositing an electrode material on the substrate to form a first electrode layer; forming a pixel definition layer on the first electrode layer and performing a first etching, wherein the pixel definition layer after the first etching includes a plurality of mutually spaced pixel definition portions; etching the first electrode layer exposed between the pixel definition portions, wherein the etched first electrode layer includes a first electrode corresponding to each pixel definition portion, wherein the orthographic projection edge of the first electrode on the substrate coincides with the orthographic projection edge of the corresponding pixel definition portion on the substrate; and performing a second etching on the pixel definition layer, wherein the pixel definition portion after the second etching has a pixel opening communicating with the corresponding first electrode.
[0017] In some embodiments, after the pixel definition layer is etched a second time, the manufacturing method may further include: forming a support layer on each of the first electrodes, the pixel definition layer and the substrate and etching it, wherein the etched support layer has a first opening corresponding to each of the first electrodes, exposing the corresponding first electrode and the pixel definition portion.
[0018] In some embodiments, the pixel definition layer after the first etching may further include multiple support portions, and the first electrode layer after etching may further include residual portions corresponding to each of the support portions. The edge of the orthographic projection of the residual portion on the substrate coincides with the edge of the orthographic projection of the corresponding support portion on the substrate. The support layer covers each of the support portions and the corresponding residual portions.
[0019] In some embodiments, after the pixel definition layer is etched a second time, the manufacturing method may further include: forming a corresponding light-emitting portion in at least each of the pixel openings, the light-emitting portion being connected to the corresponding first electrode, and each of the light-emitting portions forming a light-emitting layer; and forming a second electrode layer on the light-emitting layer, the electrode layer being connected to each of the light-emitting portions.
[0020] In some embodiments, before depositing electrode material on the substrate, the manufacturing method may further include: forming a driving circuit layer on the substrate, the driving circuit layer including thin-film transistors corresponding to each of the first electrodes; and forming a planarization layer on the driving circuit layer and etching it, the etched driving circuit layer having first vias corresponding to each of the first electrodes, the first electrodes being connected to the corresponding thin-film transistors through the corresponding first vias.
[0021] According to one or more embodiments of the present disclosure, a display panel and its manufacturing method and display device are provided. A first electrode layer on a substrate includes a plurality of mutually spaced first electrodes. A pixel definition layer is located on the side of the first electrode layer away from the substrate. The pixel definition layer includes a pixel definition portion corresponding to each first electrode. The pixel definition portion has a pixel opening communicating with the corresponding first electrode. The outer edge of the orthographic projection of the pixel definition portion on the substrate coincides with the edge of the orthographic projection of the corresponding first electrode on the substrate. In this way, each first electrode can be etched by using each pixel definition portion in the pixel definition layer as a mask. Since the pattern of the first electrode layer is formed by using the pixel definition layer as a mask, when the first electrode layer is etched, all the remaining surfaces of the first electrode layer are protected by the pixel definition layer. The residual ITO in the first electrode layer is supported by the pixel definition layer, and there is no situation where it falls off and drifts without support to connect two first electrodes. This completely improves the situation where residual ITO overlaps between sub-pixels, causing display abnormalities, and greatly improves product quality and product yield. Attached Figure Description
[0022] To more clearly illustrate the technical solutions in the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0023] Figure 1 shows a schematic diagram of the structure of the display panel in the manufacturing process of the related technology.
[0024] Figure 2 shows a schematic diagram of the anode structure in Figure 1.
[0025] Figure 3 shows a schematic diagram of the structure of the ITO sublayer remaining in the display panel as shown in Figure 2.
[0026] Figure 4 shows a schematic diagram of the structure of a display panel according to some embodiments of the present disclosure.
[0027] Figure 5 shows a top view of the first electrode layer in Figure 4.
[0028] Figure 6 shows a top view of the pixel definition layer in Figure 4.
[0029] Figure 7 shows a schematic diagram of the structure of the first electrode layer in Figure 4.
[0030] Figure 8 shows a schematic diagram of the structure of a display panel in one embodiment of the present disclosure.
[0031] Figure 9 shows a top view of the display panel in Figure 8.
[0032] Figure 10 shows a schematic diagram of the structure of a display panel according to some embodiments of the present disclosure.
[0033] Figure 11 shows a top view of the first electrode layer in Figure 10.
[0034] Figure 12 shows a top view of the pixel definition layer in Figure 10.
[0035] Figure 13 shows a schematic diagram of the structure of a display panel according to some embodiments of the present disclosure.
[0036] Figure 14 shows a flowchart of a method for manufacturing a display panel according to some embodiments of the present disclosure.
[0037] Figure 15 shows a schematic diagram of the structure of the display panel formed by the manufacturing method in Figure 14.
[0038] Figure 16 shows a flowchart of a method for manufacturing a display panel according to some embodiments of the present disclosure.
[0039] Figure 17 shows a schematic diagram of the structure of a display panel formed according to a manufacturing method of some embodiments of the present disclosure.
[0040] Figure 18 shows a schematic diagram of the structure of a display panel formed according to a manufacturing method of some embodiments of the present disclosure.
[0041] Figure 19 shows a flowchart of a method for manufacturing a display panel according to some embodiments of the present disclosure.
[0042] Explanation of reference numerals in the attached figures:
[0043] 10': Substrate; 21': Channel; 22': Gate insulating layer; 23': Gate; 24': Interlayer insulating layer; 25': Source / drain; 26': Planarization layer; 31': Anode; 311': First ITO sublayer; 312': Ag sublayer; 313': Second ITO sublayer; 314': Residual ITO; 32': Pixel definition layer; 33': Support pillar;
[0044] 10: Substrate; 20: First electrode layer; 21: First electrode; 22: Residual portion; 23: First transparent electrode sublayer; 24: Reflective electrode sublayer; 25: Second transparent electrode sublayer; 30: Pixel definition layer; 31: Pixel definition portion; 310: Pixel opening; 32: Support portion; 40: Support layer; 41: First opening; 42: Groove; 50: Light-emitting layer; 51: Light-emitting portion; 60: Second electrode layer; 70: Driving circuit layer; 71: Channel; 72: Gate; 73: Source; 74: Drain; 75: Gate insulating layer; 76: Interlayer insulating layer; 77: Second via; 80: Planarization layer; 81: First via. Detailed Implementation
[0045] To enable those skilled in the art to more clearly understand this disclosure, the technical solutions in the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. Based on the embodiments of this disclosure, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this disclosure.
[0046] Figure 1 is a schematic diagram of the structure of a display panel in the manufacturing process of related technologies. Referring to Figure 1, before the anode 31' of the display panel is formed, multiple thin-film transistor channels 21', gate insulating layer 22', gate 23', interlayer insulating layer 24', source drain 25', and planarization layer 26' are sequentially formed on the substrate 10'. The planarization layer 26' has an opening communicating with the source drain 25'. During the formation of the anode 31', anode material is first deposited on the planarization layer 26' and within the opening of the planarization layer 26', and then the anode material is patterned to obtain the anode 31' of multiple light-emitting units. After the anode 31' is formed, a pixel definition layer 32' is formed on the anode 31' of each light-emitting unit and the planarization layer 26'. The pixel definition layer 32' has an opening communicating with the anode 31'. Then, a support pillar 33' is formed on the pixel definition layer 32', and the support pillar 33' is located between two adjacent light-emitting units.
[0047] Figure 2 is a schematic diagram of the anode structure in Figure 1. Referring to Figure 2, the anode 31' is generally a sandwich structure consisting of a first ITO sublayer 311', an Ag sublayer 312', and a second ITO sublayer 313' stacked sequentially. The second ITO sublayer 313' serves as a hole injection layer and is located on the side of the anode 31' away from the substrate 10'. Ag has higher reactivity than ITO. When etching the anode material, the etching rate of Ag is 15 to 20 times that of ITO. This results in the etching amount of the Ag sublayer 312' being greater than that of the first ITO sublayer 311' and the second ITO sublayer 313'. The remaining amount of the Ag sublayer 312' is less than that of the first ITO sublayer 311' and the second ITO sublayer 313'. The edge of the second ITO sublayer 313' located on the side of the anode 31' away from the substrate 10' will lack the support of the Ag sublayer 312' and fall off, as shown by the arrow in Figure 2.
[0048] The detached ITO sublayers drift randomly and have a high probability of remaining inside the display panel. Figure 3 is a schematic diagram of the structure of the ITO sublayer remaining inside the display panel as shown in Figure 2. Referring to Figure 3, if the line length of the remaining ITO 314' is greater than the spacing between the subpixels, the remaining ITO 314' can easily overlap between two adjacent subpixels, causing a short circuit between the two adjacent subpixels. At this time, if one subpixel receives a driving signal and is lit, the other subpixel will also receive the same driving signal and be lit synchronously, causing macroscopic dot-like defects on the display panel, resulting in the display not lighting up.
[0049] The Ag sublayer 312' in the middle is thicker, while the first ITO sublayer 311' and the second ITO sublayer 313' on both sides are thinner, only 50 to 100 angstroms.
[0050] Figure 4 is a schematic diagram of the structure of a display panel according to one or more embodiments of the present disclosure. Referring to Figure 4, a first aspect embodiment of the present disclosure provides a display panel, which may include a substrate 10, a first electrode layer 20, and a pixel definition layer 30. The first electrode layer 20 is located on the substrate 10. The first electrode layer 20 includes a plurality of mutually spaced first electrodes 21. The pixel definition layer 30 is located on the side of the first electrode layer 20 away from the substrate 10. The pixel definition layer 30 includes a pixel definition portion 31 corresponding to each first electrode 21, and the pixel definition portion 31 has a pixel opening 310 communicating with the corresponding first electrode 21. The outer edge of the orthographic projection of the pixel definition portion 31 on the substrate 10 coincides with the edge of the orthographic projection of the corresponding first electrode 21 on the substrate 10.
[0051] The aforementioned display panel includes a substrate 10, a first electrode layer 20, and a pixel definition layer 30. The first electrode layer 20 is located on the substrate 10 and includes a plurality of mutually spaced first electrodes 21. The pixel definition layer 30 is located on the side of the first electrode layer 20 away from the substrate 10 and includes a pixel definition portion 31 corresponding to each first electrode 21. The pixel definition portion 31 has a pixel opening 310 communicating with the corresponding first electrode 21. The outer edge of the orthographic projection of the pixel definition portion 31 on the substrate 10 coincides with the edge of the orthographic projection of the corresponding first electrode 21 on the substrate 10. In this way, each first electrode 21 can be etched by using each pixel definition portion 31 in the pixel definition layer 30 as a mask to etch the first electrode layer 20. Since the pattern of the first electrode layer 20 is formed using the pixel definition layer 30 as a mask, when the first electrode layer 20 is etched, all the remaining surfaces of the first electrode layer 20 are protected by the pixel definition layer 30. Even if there is ITO in the first electrode layer 20 that lacks the support of the Ag layer, it is still supported by the pixel definition layer 30 and will not fall off, drift randomly, or eventually overlap between two sub-pixels. This completely improves the situation where residual ITO causes short circuits between two adjacent first electrodes 21, resulting in macroscopic dot defects on the display panel and ultimately abnormal display, thus greatly improving product quality and yield.
[0052] Figure 5 is a top view of the first electrode layer in Figure 4. Referring to Figure 5, by way of example, the first electrodes 21 can be arranged in multiple columns. The size and / or shape of the orthographic projection of the first electrodes 21 in the same column on the substrate 10 can be the same, while the size and / or shape of the orthographic projection of the first electrodes 21 in different columns on the substrate 10 can be different. For example, in two adjacent columns of first electrodes 21, the orthographic projection of one column of first electrodes 21 on the substrate 10 is rectangular, and the orthographic projection of the other column on the substrate 10 is square.
[0053] The distance between two adjacent first electrodes 21 in the same column can be the same, while the distance between two adjacent first electrodes 21 in different columns can be different. The distance between two adjacent first electrodes 21 in each column can be positively correlated with the area of the orthographic projection of the first electrodes 21 in each column onto the substrate 10.
[0054] Figure 6 is a top view of the pixel definition layer in Figure 4. Referring to Figure 6, the pixel definition parts 31 can also be arranged in multiple columns. The size and / or shape of the orthographic projection of the pixel definition parts 31 in the same column on the substrate 10 can be the same, while the size and / or shape of the orthographic projection of the pixel definition parts 31 in different columns on the substrate 10 can be different.
[0055] For example, referring to FIG6, the edge of the orthographic projection of the pixel opening 310 on the substrate 10 can be a similar pattern to the outer edge of the orthographic projection of the pixel defining portion 31 on the substrate 10. The distance between the edge of each pixel opening 310 (i.e., the inner edge of the corresponding pixel defining portion 31) and the outer edge of the corresponding pixel defining portion 31 can be the same, that is, the orthographic projection of the pixel defining portion 31 on the substrate 10 can be annular.
[0056] The size and / or shape of the orthographic projection of the pixel openings 310 of the pixel definition sections 31 in the same column onto the substrate 10 can be the same, while the size and / or shape of the orthographic projection of the pixel openings 310 of the pixel definition sections 31 in different columns onto the substrate 10 can be different. For example, in two adjacent columns of pixel definition sections 31, the orthographic projection of one column of pixel openings 310 onto the substrate 10 is rectangular, while the orthographic projection of the other column of pixel openings 310 onto the substrate 10 is square.
[0057] Figure 7 is a schematic diagram of the structure of the first electrode layer in Figure 4. Referring to Figure 7, in some embodiments, the first electrode layer 20 may include a first transparent electrode sublayer 23, a reflective electrode sublayer 24 and a second transparent electrode sublayer 25 stacked sequentially along a direction away from the substrate 10. The etching rate of the first transparent electrode sublayer 23 and the etching rate of the second transparent electrode sublayer 25 are both less than the etching rate of the reflective electrode sublayer 24.
[0058] For example, the first transparent electrode sublayer 23 and the second transparent electrode sublayer 25 can both be ITO layers, and the reflective electrode sublayer 24 can be an Ag layer. The etching rate of the Ag layer can be 15 to 20 times that of the ITO layer.
[0059] For example, the thickness of the first transparent electrode sublayer 23 and the thickness of the second transparent electrode sublayer 25 can both be less than the thickness of the reflective electrode sublayer 24. The thickness of the ITO layer can be 50 angstroms to 100 angstroms.
[0060] Figure 8 is a schematic diagram of the structure of a display panel in one embodiment of this disclosure. Referring to Figure 8, in some embodiments, the display panel may further include a support layer 40. The support layer 40 is located at least between two adjacent first electrodes 21 and covers the sides of the adjacent first electrodes 21. By providing a support layer 40 between at least two adjacent first electrodes 21 and covering the sides of the first electrodes 21, the support layer 40 can isolate the first electrodes 21 from external influences.
[0061] Figure 9 is a top view of the display panel of Figure 8. Referring to Figure 9, by way of example, the support layer 40 can be continuously disposed on the substrate 10. The support layer 40 has a first opening 41 corresponding to each first electrode 21. The first electrode 21 and the corresponding pixel definition part 22 are located in the corresponding first opening 41.
[0062] Figure 10 is a schematic diagram of the display panel structure in another embodiment of this disclosure. Referring to Figure 10, in some embodiments, the support layer 40 has a plurality of mutually spaced grooves 42 on the side near the substrate 10. The pixel definition layer 30 also includes a support portion 32 corresponding to each groove 42, and the support portion 32 is located in the corresponding groove 42. By providing the support portion 32 in the area of the support layer 40 that needs to provide support, and the support portion 32 being located below the support layer 40, the support layer 40 can be supported, preventing the support layer 40 from collapsing and failing to provide support.
[0063] For example, referring to FIG10, the first electrode layer 20 may further include residual portions 22 corresponding to each support portion 32, and the residual portions 22 and the corresponding support portions 32 are located in the same groove 42. The edge of the orthographic projection of the residual portion 22 on the substrate 10 coincides with the edge of the orthographic projection of the corresponding support portion 32 on the substrate 10.
[0064] Figure 11 is a top view of the first electrode layer of Figure 10. Referring to Figure 11, in some embodiments, the residual portion 22 may be located between two adjacent first electrodes 21 and spaced apart from the adjacent first electrodes 21. The support layer 40 is located between the residual portion 22 and the adjacent first electrodes 21.
[0065] Figure 12 is a top view of the pixel definition layer of Figure 10. Referring to Figure 12, the support portion 32 can also be located between two adjacent pixel definition portions 31 and spaced apart from each other. The support layer 40 is located between the support portion 32 and the adjacent pixel definition portions 31.
[0066] For example, referring to Figure 11, the residue 22 may be located between two first electrodes 21 in the same column.
[0067] Accordingly, referring to Figure 12, the support portion 32 may also be located between two pixel definition portions 31 in the same column.
[0068] For example, referring to Figures 11 and 12, in a direction parallel to the substrate 10 and perpendicular to the column direction, the lengths of the residual portion 22 and the support portion 32 can both be the same as the length of the pixel definition portion 31 in the same column. In a direction parallel to the column direction, the lengths of the residual portions 22 in each column can be the same, and the lengths of the support portions 32 in each column can be the same.
[0069] Figure 13 is a schematic diagram of the display panel structure in another embodiment of this disclosure. Referring to Figure 13, in some embodiments, the display panel may further include a light-emitting layer 50 and a second electrode layer 60. The light-emitting layer 50 includes light-emitting portions 51 corresponding to each pixel definition portion 31. The light-emitting portions 51 are located at least within the corresponding pixel opening 310 and are connected to the corresponding first electrode 21. The second electrode layer 60 is located on the side of the light-emitting layer 50 away from the substrate 10 and is connected to each light-emitting portion 51.
[0070] In some embodiments, referring to Figures 4, 8, 10, and 13, the display panel may further include a driving circuit layer 70 and a planarization layer 80. The driving circuit layer 70 is located between the first electrode layer 20 and the substrate 10. The driving circuit layer 70 includes thin-film transistors corresponding to each first electrode 21. The planarization layer 80 is located between the driving circuit layer 70 and the first electrode layer 20. The planarization layer 80 has first vias 81 corresponding to each first electrode 21, and the first electrode 21 is connected to the corresponding thin-film transistor through the corresponding first via 81.
[0071] For example, referring to Figures 8 and 10, when the display panel also includes a support layer 40, the support layer 40 is located on the side of the planarization layer 80 away from the substrate 10.
[0072] For example, referring to Figures 4, 8, 10 and 13, the driving circuit layer 70 may include a channel 71, a gate 72, a source 73 and a drain 74 of a plurality of thin film transistors, as well as a gate insulating layer 75 and an interlayer insulating layer 76.
[0073] Multiple thin-film transistors have channels 71 spaced apart on a substrate 10. A gate insulating layer 75 covers the channels 71 of the multiple thin-film transistors and the substrate 10.
[0074] The gates 72 of a plurality of thin-film transistors are spaced apart on the side of the gate insulating layer 75 away from the substrate 10 and are disposed opposite to the channels 71 of the same thin-film transistor. That is, the orthographic projection of the gate 72 of each thin-film transistor onto the substrate 10 at least partially overlaps with the orthographic projection of the channel 71 of the same thin-film transistor onto the substrate 10, and a gate insulating layer 75 is provided between the gate 72 of each thin-film transistor and the channel 71 of the same thin-film transistor. An interlayer insulating layer 76 covers the gates 72 of the plurality of thin-film transistors and the gate insulating layer 75.
[0075] The interlayer insulating layer 76 and the gate insulating layer 75 have multiple interconnected second vias 77. The source 73 and drain 74 of the same thin-film transistor are respectively disposed in different second vias 77 and on the side of the interlayer insulating layer 76 away from the substrate 10, so as to be connected to the channel 71 of the same thin-film transistor through the second vias 77. The orthographic projection of the gate 72 of each thin-film transistor on the substrate 10 is located between the orthographic projections of the source 73 and drain 74 of the same thin-film transistor on the substrate 10.
[0076] A planarization layer 80 covers the source 73 and drain 74 of each thin-film transistor and the interlayer insulating layer 76. Each first through hole 81 of the planarization layer 80 is connected to the source 73 of the corresponding thin-film transistor, and the first electrode 21 is connected to the source 73 of the corresponding thin-film transistor through the corresponding first through hole 81.
[0077] A second aspect of this disclosure provides a display device, which may include the display panel provided in any of the above embodiments.
[0078] Figure 14 is a flowchart of a method for manufacturing a display panel in one or more embodiments of the present disclosure, and Figure 15 is a schematic diagram of the structure of the display panel formed by the manufacturing method of Figure 14. Please refer to Figures 14 and 15. According to a third aspect embodiment of the present disclosure, a method for manufacturing a display panel is provided, which may include the following steps S101 to S105.
[0079] Step S101: Provide a substrate.
[0080] Step S102: Electrode material is deposited on the substrate to form a first electrode layer.
[0081] Please refer to Figure 15. The first electrode layer 20 is deposited on the substrate 10.
[0082] For example, step S102 may include: first depositing a layer of ITO on the substrate, then depositing a layer of Ag on the ITO layer, and finally depositing a layer of ITO on the Ag layer.
[0083] Step S103: A pixel definition layer is formed on the first electrode layer and a first etching is performed. The pixel definition layer after the first etching includes a plurality of mutually spaced pixel definition parts.
[0084] For example, referring to FIG15, step S103 may include: firstly depositing a pixel definition layer 30 on the first electrode layer 20, and then etching the pixel definition layer 30 to form a plurality of mutually spaced pixel definition portions 31.
[0085] Step S104: Etch the first electrode layer exposed between the pixel definition parts. The etched first electrode layer includes the first electrode corresponding to each pixel definition part. The orthogonal projection edge of the first electrode on the substrate coincides with the orthogonal projection edge of the corresponding pixel definition part on the substrate.
[0086] Please refer to Figure 15. The first electrode layer 20 is etched to form the first electrode 21 corresponding to each pixel definition part 31. The orthogonal projection edge of the first electrode 21 on the substrate 10 coincides with the orthogonal projection edge of the corresponding pixel definition part 31 on the substrate 10.
[0087] Step S105: Perform a second etching on the pixel definition layer. The pixel definition part after the second etching has a pixel opening that is connected to the corresponding first electrode.
[0088] Please refer to Figure 15. The pixel definition layer 30 is etched twice to form the pixel openings 310 corresponding to each first electrode 21.
[0089] Figure 16 is a flowchart of a method for manufacturing a display panel in one embodiment of the present disclosure. Referring to Figure 16, in some embodiments, after step S105, the manufacturing method may further include the following steps S201 to S202.
[0090] Step S201: At least one corresponding light-emitting part is formed in each pixel opening, the light-emitting part is connected to the corresponding first electrode, and the light-emitting parts form a light-emitting layer.
[0091] In step S202, a second electrode layer is formed on the light-emitting layer, and the electrode layer is connected to each light-emitting part.
[0092] In some embodiments, after step S105, the manufacturing method may further include the following steps: forming a support layer on each first electrode, pixel definition layer and substrate and etching it, wherein the etched support layer has a first opening corresponding to each first electrode, exposing the corresponding first electrode and pixel definition portion.
[0093] Figure 17 is a schematic diagram of the structure of a display panel formed by a manufacturing method in another embodiment of the present disclosure. Referring to Figure 17, the support layer 40 fills the area not covered by the pixel definition layer 30 and the first electrode layer 20. The support layer 40 has a first opening 41 corresponding to each pixel definition part 31. The pixel definition part 31 and the corresponding first electrode 21 are located in the corresponding first opening 41.
[0094] For example, forming and etching a support layer on each first electrode, pixel definition layer and substrate may include: first laying a support layer on each first electrode, pixel definition layer and substrate, then etching the support layer to remove the support layer on each first electrode and the corresponding pixel definition portion, thereby forming each first opening.
[0095] Figure 18 is a schematic diagram of the structure of a display panel formed by a manufacturing method in another embodiment of this disclosure. Referring to Figure 18, exemplarily, the etched pixel definition layer 30 may further include a plurality of support portions 32, and the etched first electrode layer 20 may further include residual portions 22 corresponding to each support portion 32. The edge of the orthographic projection of the residual portion 22 on the substrate 10 coincides with the edge of the orthographic projection of the corresponding support portion 32 on the substrate 10. The support layer 40 covers each support portion 32 and the corresponding residual portion 22.
[0096] Figure 19 is a flowchart of a method for manufacturing a display panel in another embodiment of the present disclosure. Referring to Figure 19, in some embodiments, before step S102, the manufacturing method may further include the following steps S301 to S302.
[0097] Step S301: A driving circuit layer is formed on the substrate, the driving circuit layer including thin film transistors corresponding to each first electrode.
[0098] For example, step S301 may include the following steps: forming a plurality of thin-film transistor channels on a substrate, the channels of the plurality of thin-film transistors being spaced apart from each other; depositing a gate insulating layer on the channels of the plurality of thin-film transistors and on the substrate; forming gates of the plurality of thin-film transistors on the gate insulating layer, the gates of each thin-film transistor being disposed opposite to the channel of the same thin-film transistor; depositing an interlayer insulating layer on the gates of the plurality of thin-film transistors and on the gate insulating layer; forming a plurality of interconnected second vias in the interlayer insulating layer and the gate insulating layer; forming the source and drain of the plurality of thin-film transistors in the plurality of second vias and on the interlayer insulating layer.
[0099] Step S302: A planarization layer is formed on the driving circuit layer and etched. The etched driving circuit layer has a first via corresponding to each first electrode. The first electrode is connected to the corresponding thin film transistor through the corresponding first via.
[0100] For example, step S302 may include the following steps: depositing a planarization layer on the source and drain of a plurality of thin-film transistors and on the substrate; and forming a first connecting hole corresponding to each first electrode in the planarization layer.
[0101] Accordingly, step S102 may include laying electrode material in the plurality of first connecting holes and on the planarization layer.
[0102] According to one or more embodiments of the present disclosure, a display panel and its manufacturing method and display device are provided. A first electrode layer on a substrate includes a plurality of mutually spaced first electrodes. A pixel definition layer is located on the side of the first electrode layer away from the substrate. The pixel definition layer includes a pixel definition portion corresponding to each first electrode. The pixel definition portion has a pixel opening communicating with the corresponding first electrode. The outer edge of the orthographic projection of the pixel definition portion on the substrate coincides with the edge of the orthographic projection of the corresponding first electrode on the substrate. In this way, each first electrode can be etched by using each pixel definition portion in the pixel definition layer as a mask. Since the pattern of the first electrode layer is formed by using the pixel definition layer as a mask, when the first electrode layer is etched, all the remaining surfaces of the first electrode layer are protected by the pixel definition layer. The residual ITO in the first electrode layer is supported by the pixel definition layer, and there is no situation where it falls off and drifts without support to connect two first electrodes. This completely improves the situation where residual ITO overlaps between sub-pixels, causing display abnormalities, and greatly improves product quality and product yield.
[0103] In this disclosure, unless otherwise expressly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.
[0104] In the description of this disclosure, it should be understood that the terms “center,” “longitudinal,” “lateral,” “length,” “width,” “thickness,” “upper,” “lower,” “front,” “rear,” “left,” “right,” “vertical,” “horizontal,” “top,” “bottom,” “inner,” “outer,” “clockwise,” and “counterclockwise” indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this disclosure and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this disclosure.
[0105] In this disclosure, unless otherwise expressly specified and limited, the terms "connection," "fixed," etc., should be interpreted broadly. For example, "fixed" can mean a fixed connection, a detachable connection, or an integral part; it can mean a mechanical connection or an electrical connection; it can mean a direct connection or an indirect connection through an intermediate medium; it can mean the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this disclosure according to the specific circumstances.
[0106] Furthermore, the use of terms such as "first" and "second" in this disclosure is for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, features defined with "first" or "second" may explicitly or implicitly include one or more features. In the description of this disclosure, "multiple" means two or more, unless otherwise explicitly specified.
[0107] Although embodiments of the present disclosure have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the present disclosure, the scope of which is defined by the claims and their equivalents.
Claims
1. A display panel, comprising: Substrate (10); A first electrode layer (20) is located on the substrate (10); the first electrode layer (20) includes a plurality of mutually spaced first electrodes (21); and A pixel definition layer (30) is located on the side of the first electrode layer (20) away from the substrate (10). The pixel definition layer (30) includes a pixel definition portion (31) corresponding to each of the first electrodes (21). The pixel definition portion (31) has a pixel opening (310) communicating with the corresponding first electrode (21). The outer edge of the orthographic projection of the pixel definition portion (31) on the substrate (10) coincides with the edge of the orthographic projection of the corresponding first electrode (21) on the substrate (10).
2. The display panel according to claim 1, further comprising: A support layer (40) is located at least between two adjacent first electrodes (21) and covers the sides of adjacent first electrodes (21).
3. The display panel according to claim 2, wherein, The support layer (40) is continuously disposed on the substrate (10), and the support layer (40) has a first opening (41) corresponding to each of the first electrodes (21), and the first electrode (21) is located in the corresponding first opening (41).
4. The display panel according to claim 2, wherein, The support layer (40) has a plurality of mutually spaced grooves (42) on the side near the substrate (10), and the pixel definition layer (30) also includes a support portion (32) corresponding to each groove (42), and the support portion (32) is located in the corresponding groove (42).
5. The display panel according to claim 4, wherein, The first electrode layer (20) also includes a residual portion (22) corresponding to each of the support portions (32), the residual portion (22) and the corresponding support portion (32) are located in the same groove (42); the edge of the orthographic projection of the residual portion (22) on the substrate (10) coincides with the edge of the orthographic projection of the corresponding support portion (32) on the substrate (10).
6. The display panel according to claim 5, wherein, The residual portion (22) is located between two adjacent first electrodes (21) and spaced apart from each other; the support layer (40) is located between the residual portion (22) and the adjacent first electrodes (21).
7. The display panel according to claim 6, wherein, The first electrodes (21) are arranged in multiple columns, and the residual portion (22) is located between two first electrodes (21) in the same column.
8. The display panel according to any one of claims 1-7, further comprising: The light-emitting layer (50) includes the light-emitting part (51) corresponding to each of the pixel definition parts (31); The light-emitting part (51) is located at least within the corresponding pixel opening (310) and is connected to the corresponding first electrode (21); as well as The second electrode layer (60) is located on the side of the light-emitting layer (50) away from the substrate (10) and is connected to each of the light-emitting parts (51).
9. The display panel according to any one of claims 1-7, further comprising: A driving circuit layer (70) is located between the first electrode layer (20) and the substrate (10); the driving circuit layer (70) includes thin-film transistors corresponding to each of the first electrodes (21); and A planarization layer (80) is located between the driving circuit layer (70) and the first electrode layer (20); the planarization layer (80) has a first through hole (81) corresponding to each of the first electrodes (21), and the first electrode (21) is connected to the corresponding thin film transistor through the corresponding first through hole (81).
10. The display panel according to any one of claims 1-7, wherein, The first electrode layer (20) includes a first transparent electrode sublayer (23), a reflective electrode sublayer (24), and a second transparent electrode sublayer (25) stacked sequentially along a direction away from the substrate (10). The etching rate of the first transparent electrode sublayer (23) and the etching rate of the second transparent electrode sublayer (25) are both less than the etching rate of the reflective electrode sublayer (24).
11. A display device comprising the display panel as described in claims 1-10.
12. A method for manufacturing a display panel, comprising: Provide substrates; Electrode material is deposited on the substrate to form a first electrode layer; A pixel definition layer is formed on the first electrode layer and a first etching is performed. The pixel definition layer after the first etching includes a plurality of mutually spaced pixel definition parts. The first electrode layer exposed between the pixel definition portions is etched, and the etched first electrode layer includes a first electrode corresponding to each pixel definition portion. The orthogonal projection edge of the first electrode on the substrate coincides with the orthogonal projection edge of the corresponding pixel definition portion on the substrate. as well as The pixel definition layer is etched a second time, and the pixel definition portion after the second etching has a pixel opening that communicates with the corresponding first electrode.
13. The manufacturing method according to claim 12, wherein, After the second etching of the pixel definition layer, the process also includes: A support layer is formed and etched on each of the first electrodes, the pixel definition layer and the substrate. The etched support layer has a first opening corresponding to each of the first electrodes, exposing the corresponding first electrode and the pixel definition portion.
14. The manufacturing method according to claim 13, wherein, The pixel definition layer after the first etching also includes multiple support portions, and the first electrode layer after etching also includes residual portions corresponding to each of the support portions. The edge of the orthographic projection of the residual portion on the substrate coincides with the edge of the orthographic projection of the corresponding support portion on the substrate. The support layer covers each of the support portions and the corresponding residual portions.
15. The manufacturing method according to claim 12, wherein, After the second etching of the pixel definition layer, the process also includes: At least one light-emitting portion is formed within each of the pixel openings, the light-emitting portion being connected to the corresponding first electrode, and the light-emitting portions forming a light-emitting layer; and A second electrode layer is formed on the light-emitting layer, and the electrode layer is connected to each of the light-emitting parts.
16. The manufacturing method according to claim 11, wherein, Before depositing the electrode material on the substrate, the method further includes: A driving circuit layer is formed on the substrate, the driving circuit layer including thin-film transistors corresponding to each of the first electrodes; and A planarization layer is formed on the driving circuit layer and etched. The etched driving circuit layer has a first via corresponding to each of the first electrodes. The first electrodes are connected to the corresponding thin film transistors through the corresponding first vias.