Driver circuit and control method therefor, and display panel, controller and display apparatus

Abstract

A driver circuit (100) and a control method therefor, and a display panel, a controller and a display apparatus, which relate to the technical field of display driving. The driver circuit (100) comprises: a first sub-circuit (110), which is used for outputting a group control signal (EN_GRP) under the action of a first driving signal (FRD_IN) and a first clock signal (FRD_CKV), wherein the group control signal (EN_GRP) is used for controlling whether two adjacent rows of pixel circuits (200) are driven simultaneously; and a second sub-circuit (120), wherein one end of the second sub-circuit (120) is electrically connected to the first sub-circuit (110), the other end of the second sub-circuit (120) is used for electrically connecting to one pixel circuit (200), and the second sub-circuit (120) is used for outputting a row scan signal (Qi) under the action of the group control signal (EN_GRP). A hardware circuit is used to generate a rendering signal under the action of a first driving signal (FRD_IN), so as to drive pixel circuits (200) to implement corresponding display, without it being necessary to wait for a display driver integrate circuit to generate all the rendering signals, thereby greatly improving the rendering efficiency and effectively reducing the power consumption of the circuit.

Description

Drive circuit and its control method, display panel, controller and display device Cross-reference to related applications

[0001] This disclosure claims priority to Chinese patent application No. 202411745384.X, filed on November 29, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure relates to the field of driving display technology, and more specifically, to a driving circuit, a display panel, a control method for the driving circuit, a controller, and a display device. Background Technology

[0003] Focal rendering is a device performance optimization technique that concentrates resources on rendering the display area that the human eye is focused on. It can render the area the eye is focused on at high resolution and the surrounding areas at low resolution. This reduces the resources used to render the scene while ensuring no loss of the focused area, thus not affecting the user's visual experience. Current technology typically uses a Display Driver Integrated Circuit (DDIC) to generate all the rendering signals corresponding to the aforementioned zonal rendering based on eye movement signals. These rendering signals are then sent to the driver circuit to drive the pixel circuits to complete the corresponding display. This reduces the efficiency of focal rendering to some extent, impacting the user experience. Furthermore, for different DDICs, if the existing driver circuit cannot drive the pixel circuits under the rendering signals, additional matching driver circuits are required, significantly increasing power consumption and wasting resources.

[0004] Therefore, a new technical solution is urgently needed to solve the above-mentioned technical problems. Summary of the Invention

[0005] The summary section introduces a series of simplified concepts, which will be further explained in detail in the detailed description section. This summary section is not intended to limit the key features and essential technical features of the claimed technical solutions, nor is it intended to determine the scope of protection of the claimed technical solutions.

[0006] A first aspect of this disclosure provides a driving circuit, comprising:

[0007] The first sub-circuit is used to output a group control signal under the action of the first driving signal and the first clock signal. The group control signal is used to control whether two adjacent rows of pixel circuits are driven at the same time. The period of the first clock signal is 1 / x of the refresh time of a row of pixel circuits, where x is a natural number greater than 1.

[0008] The second sub-circuit has one end electrically connected to the first sub-circuit and the other end electrically connected to the pixel circuit. The second sub-circuit is used to output a line scanning signal under the action of the group control signal.

[0009] In some implementations, the first sub-circuit includes: a first flip-flop and a second flip-flop that are electrically connected;

[0010] The first flip-flop is used to output a first control signal under the action of the first clock signal and the first trigger signal;

[0011] The second trigger is used to output a group control signal under the action of the first control signal and the first drive signal.

[0012] In some implementations, the first control signal is the clock trigger signal of the second flip-flop, and the first control signal is a single pulse signal.

[0013] In some implementations, the driving circuit includes N stages. The nth stage driving circuit includes an nth stage first sub-circuit and an nth stage second sub-circuit. The nth stage second sub-circuit includes an nth stage first branch and an nth stage second branch. The nth stage first branch is used to output the row scan signal of the nth row pixel circuit under the action of the group control signal provided by the nth stage first sub-circuit. The nth stage second branch is used to output the row scan signal of the (n+1)th row pixel circuit under the action of the group control signal provided by the nth stage first sub-circuit. The nth stage second branch is also used to output the row scan signal of the (n+1)th row pixel circuit under the action of the group control signal provided by the (n+1)th stage first sub-circuit.

[0014] In some implementations, the first flip-flop of the first sub-circuit of the nth stage is electrically connected to the first flip-flop of the first sub-circuit of the (n+1)th stage. The first flip-flop of the first sub-circuit of the nth stage is used to transmit a first control signal to the first flip-flop of the first sub-circuit of the (n+1)th stage. The first control signal is the first trigger signal of the first flip-flop of the first sub-circuit of the (n+1)th stage. Here, N and n are both natural numbers greater than 0, and n+1≤N.

[0015] In some implementations, the first flip-flop and the second flip-flop are used to reset under the action of a reset signal, the effective level end of the reset signal being before the effective level start of the first trigger signal, the first control signal, and the first drive signal.

[0016] In some implementations, the first sub-circuit of the first stage includes a first transmission gate, which is used to transmit a frame start signal to a first trigger. The frame start signal is a first trigger signal received by the first trigger of the first stage. The first transmission gate is used to be turned on or off under the action of the rendering start signal.

[0017] In some implementations, the effective level start point of the rendering start signal is after the effective level end point of the reset signal, and the effective level end point of the rendering start signal is before the effective level start point of the first drive signal.

[0018] In some implementations, the second sub-circuit includes a second transmission gate, a third transmission gate, a fourth transmission gate, a third flip-flop, and a fourth flip-flop;

[0019] The second transmission gate is electrically connected to the third transmission gate and the third flip-flop respectively, and is used to output the second trigger signal to the third transmission gate and the third flip-flop when it is turned on;

[0020] The third transmission gate is electrically connected to the third and fourth flip-flops respectively, the fourth transmission gate is electrically connected to the third and fourth flip-flops respectively, and the third and fourth transmission gates are electrically connected. Both the third and fourth transmission gates are used to turn on or off under the action of the group control signal.

[0021] When the third transmission gate is turned on and the fourth transmission gate is turned off, the third transmission gate outputs a second trigger signal to the fourth trigger.

[0022] When the fourth transmission gate is turned on and the third transmission gate is turned off, the fourth transmission gate outputs a second control signal to the fourth flip-flop. The second control signal is output by the third flip-flop under the triggering of the second trigger signal and the second clock signal.

[0023] In some implementations, the second sub-circuit further includes a fifth transmission gate electrically connected between the fourth flip-flop and the third transmission gate. The fifth transmission gate is used to turn on or off under the action of the second driving signal, and the second transmission gate is used to turn on or off under the action of the second driving signal.

[0024] A second aspect of this disclosure also provides a display panel, comprising:

[0025] The drive circuit described above;

[0026] Pixel circuit, the number of rows in the pixel circuit is greater than the number of stages in the driving circuit.

[0027] A third aspect of this disclosure also provides a control method for a driving circuit, applied to the driving circuit described above, the control method comprising:

[0028] The first sub-circuit controls the output of a group control signal under the action of the first driving signal and the first clock signal. The group control signal is used to control whether two adjacent rows of pixels are driven at the same time. The period of the first clock signal is 1 / x of the refresh time of a row of pixel circuits, where x is a natural number greater than 1.

[0029] The second sub-circuit controls the output of a line scanning signal to the pixel circuit under the action of the group control signal.

[0030] In some embodiments, before the first sub-circuit outputs a grouping control signal under the action of the first drive signal and the first clock signal, the method further includes:

[0031] The first and second flip-flops are reset under the action of the reset signal. The effective level of the reset signal ends before the effective level start of the first trigger signal, the first control signal, and the first drive signal.

[0032] In some implementations, the method further includes:

[0033] When the first transmission gate is turned on by the rendering start signal, the first transmission gate is controlled to transmit the frame start signal to the first trigger. The frame start signal is the first trigger signal received by the first trigger of the first stage.

[0034] In some implementations, the effective level start point of the rendering start signal is after the effective level end point of the reset signal, and the effective level end point of the rendering start signal is before the effective level start point of the first drive signal.

[0035] In some implementations, the method further includes:

[0036] The second and fifth transmission gates are turned on or off under the action of the second driving signal.

[0037] A fourth aspect of this disclosure also provides a controller, comprising:

[0038] Memory, which stores computer programs;

[0039] A processor is configured to invoke the computer program in the memory, the computer program being configured to execute the control method as described above.

[0040] A fifth aspect of the present disclosure also provides a display device including a display panel as described above and / or a controller as described above.

[0041] In some embodiments, the display device further includes:

[0042] The driver chip is electrically connected to the driver circuit of the display panel.

[0043] The control motherboard is electrically connected to the driver chip.

[0044] According to the above technical solution, the driver circuit with the aforementioned hardware circuit structure rapidly groups the pixel circuits under the action of the first driving signal and the first clock signal. This ensures that more grouping control signals are prepared before display to control whether adjacent rows of pixel circuits in the grouped pixel circuits are driven simultaneously, and then different line scanning signals are output. Combining the line scanning signal and the data signal allows the same group of pixel circuits to display the same content at the same time. For non-focused areas, i.e., when multiple rows of pixel circuits are grouped together, since multiple rows of pixel circuits display the same content, the effect of low-resolution rendering is achieved in non-focused areas. For focused areas, i.e., when one row of pixel circuits is grouped together, since only one row of pixel circuits is used to display the corresponding content, a high-resolution display effect is achieved. In the process of foveated rendering using DDIC, all rendering signals are first generated based on eye movement signals, and then the rendering signals are given to the driver circuit so that the driver circuit drives the pixel circuits to complete the corresponding display. In the embodiments described above, the eye-tracking signal is first converted into a first driving signal using a DDIC. Then, a rendering signal is generated by a hardware circuit under the action of the first driving signal to drive the pixel circuit to complete the corresponding display. This eliminates the need to wait for the DDIC to generate all the rendering signals, greatly improving rendering efficiency. Furthermore, directly generating the rendering signal using the driving circuit eliminates the need for an additional driving circuit that matches the DDIC to receive the rendering signal, effectively reducing circuit power consumption.

[0045] The driving circuit of this disclosure, other advantages, objectives and features of this disclosure will be apparent in part from the description which follows, and in part will be understood by those skilled in the art through study and practice of this disclosure. Attached Figure Description

[0046] The above and various other advantages and benefits of this disclosure will become clear to those skilled in the art upon reading the following detailed description of preferred embodiments.

[0047] Figure 1 is a schematic structural block diagram of a driving circuit provided in an embodiment of this disclosure;

[0048] Figure 2 is a schematic circuit structure diagram of a first sub-circuit provided in an embodiment of this disclosure;

[0049] Figure 3 is a schematic structural block diagram of another driving circuit provided in an embodiment of this disclosure;

[0050] Figure 4 is a schematic circuit structure diagram of another first sub-circuit provided in an embodiment of this disclosure;

[0051] Figure 5 is a schematic circuit structure diagram of a second sub-circuit provided in an embodiment of this disclosure;

[0052] Figure 6 is a schematic diagram of the driving timing of a driving circuit provided in an embodiment of this disclosure;

[0053] Figure 7 is a schematic structural block diagram of a display panel provided in an embodiment of this disclosure;

[0054] Figure 8 is a schematic flowchart of a control method for a drive circuit provided in an embodiment of this disclosure;

[0055] Figure 9 is a schematic structural block diagram of a display device provided in an embodiment of this disclosure. Detailed Implementation

[0056] The present disclosure will now be further described with reference to the accompanying drawings and specific embodiments. The following description is merely illustrative of the basic principles of the present disclosure and is not intended to limit it.

[0057] The terms "first," "second," "third," "fourth," etc. (if present) in this disclosure, claims, and accompanying drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments described herein can be implemented in a sequence other than that illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus. The technical solutions of the embodiments of this disclosure will now be clearly and completely described in conjunction with the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them.

[0058] Numerous specific details are set forth in the following description in order to provide a full understanding of this disclosure, but this disclosure may also be implemented in other ways different from those described herein; obviously, the embodiments in the specification are only some, and not all, of the embodiments of this disclosure.

[0059] Typically, the DDIC generates all the rendering signals corresponding to the foveated rendering based on eye-tracking signals. These signals are then sent to the driver circuitry to drive the pixel circuitry for the corresponding display. For different DDICs, if the existing driver circuitry cannot drive the pixel circuitry under the influence of the rendering signals, an additional matching driver circuitry must be added, significantly increasing power consumption and wasting resources. Furthermore, the DDIC and driver circuitry operate completely independently in a time-sharing manner. That is, the DDIC must first complete the generation of all rendering signals before transmitting them to the driver circuitry. Only after receiving the rendering signals can the driver circuitry drive the pixel circuitry for the corresponding display. During the DDIC's signal generation, the driver circuitry waits for a signal response. The duration of this waiting period is affected by the DDIC's performance, severely impacting the efficiency of the entire foveated rendering display, leading to display delays and affecting the user experience.

[0060] To address the aforementioned technical problems, a driving circuit is proposed according to a first aspect of this disclosure. Figure 1 is a schematic structural block diagram of a driving circuit provided in an embodiment of this disclosure. Referring to Figure 1, the driving circuit 100 may include a first sub-circuit 110 and a second sub-circuit 120. The first sub-circuit 110 is used to output a group control signal under the action of a first driving signal and a first clock signal, wherein the group control signal is used to control whether adjacent rows of pixel circuits are driven simultaneously.

[0061] It should be noted that in foveated rendering technology, as the human eye moves, the display area can be divided into a foveated area and a non-foveated area. The foveated area can be rendered at high resolution, while the non-foveated area can be rendered at low resolution. For example, any existing or future technology can be used to track the user's eye movements, thereby obtaining eye-tracking signals using devices such as display driver integrated circuits. Signal processing and other operations can be performed on the eye-tracking signals to obtain and send a first driving signal to a first sub-circuit. For example, the first driving signal can be obtained through the eye-tracking signal as described above, or it can be obtained in response to a user's input command. In some embodiments, the user can input an area division command through an input device such as a touchscreen. Based on this area division command, the area selected by the user can be determined as the foveated area, and other unselected areas can be determined as non-foveated areas, thereby obtaining the first driving signal. The first driving signal can be understood as an input signal used to represent the division of the display area into foveated and non-foveated areas, and it can be obtained in various forms. The above embodiments are merely exemplary and do not imply a limitation on the first driving signal. For example, referring to Figure 1, a first driving signal FRD_IN and a first clock signal FRD_CKV can be transmitted to the first sub-circuit 110. Under the action of the first driving signal FRD_IN and the first clock signal FRD_CKV, the first sub-circuit 110 can divide the row pixels of the pixel circuit 200, for example, into gaze region row pixels and non-gaze region row pixels, thereby outputting a corresponding grouping control signal EN_GRP. For example, the period of the first clock signal is equal to the refresh time of one row of pixel circuits. x is a natural number greater than 1. The refresh time of a row of pixel circuits is the row period H, and the period of the first clock signal can be... x can be a natural number greater than 1, such as 2, 3, or 4. Taking x = 3 as an example, the period of the first clock signal is... Therefore, the first drive signal can be read three times within one row cycle, and the corresponding group control signal can be generated. In some implementations, this group control signal can be used to simultaneously drive 3+1=4 rows of pixel circuits.

[0062] Therefore, within one row cycle, compared to a normal clock signal with a period equal to the row cycle, using a first clock signal with a faster period as the clock trigger signal for the first sub-circuit ensures that more group control signals are generated within one row cycle. This ensures that more group control signals are prepared before display, enabling simultaneous driving of multiple row pixel circuits.

[0063] The value of the group control signal EN_GRP determines the synchronization of the output signal, that is, whether adjacent rows of pixel circuits are driven simultaneously. When the group control signal EN_GRP = 0, adjacent rows of pixel circuits are not driven simultaneously; when the group control signal EN_GRP = 1, adjacent rows of pixel circuits are driven simultaneously.

[0064] For example, a row of pixels in the gaze area may include a row of pixel circuits, where each row of pixel circuits is driven as a separate group of pixel circuits. In this case, the adjacent pixel circuits of this row belong to different groups of pixel circuits. Therefore, a grouping control signal with a value of 0 can be generated. When the grouping control signal has a value of 0, time-division driving can be controlled between the row of pixel circuits and the pixel circuits adjacent to it.

[0065] For example, for non-focused region rows of pixels, this could include multiple rows of pixel circuits. That is, multiple rows of pixel circuits work together as a group of pixel circuits for display, and these multiple rows of pixel circuits can display the same content. In this case, a group control signal with a value of 1 can be generated. When the group control signal is 1, it can control the simultaneous driving of adjacent rows of pixel circuits within this group. Adjacent rows of pixel circuits within different groups are not driven simultaneously; that is, pixel circuits between different groups are not driven simultaneously, while pixel circuits within the same group are driven simultaneously.

[0066] It should be noted that when two adjacent rows of pixel circuits are driven simultaneously, it means that the gates of the driving transistors in the two adjacent rows of pixel circuits are simultaneously turned on or off. That is, the conduction and cutoff states of the two adjacent rows of pixel circuits are synchronized. Therefore, when the two adjacent rows of pixel circuits are on, they can read the same display data and output the corresponding display results, achieving the effect of foveated rendering. When two adjacent rows of pixel circuits are not driven simultaneously, it means that the on or off states of the gates of the driving transistors in the two adjacent rows of pixel circuits are reversed. In adjacent rows of pixel circuits, if the previous row of pixel circuits is on, the next row of pixel circuits is off.

[0067] For example, referring to Figure 1, one end of the second sub-circuit 120 is electrically connected to the first sub-circuit 110 and is used to receive the group control signal EN_GRP. The other end of the second sub-circuit 120 is used to be electrically connected to the pixel circuit 200, and the second sub-circuit 120 is used to output a line scan signal Qi under the action of the group control signal EN_GRP. Here, i can represent the row number of the pixel circuit.

[0068] For example, the value of the group control signal EN_GRP controls whether two adjacent pixel circuits in each row are driven simultaneously. Therefore, the number of group control signals is less than the number of rows of pixel circuits. In some implementations, the number of group control signals equals the number of rows of pixel circuits minus 1. For example, for the first and second row pixel circuits, when the group control signal EN_GRP = 0, the second sub-circuit can output two row scan signals Q1 and Q2 sequentially under the action of the group control signal. Therefore, the first and second row pixel circuits cannot display content simultaneously. When the group control signal EN_GRP = 1, the second sub-circuit can output two row scan signals Q1 and Q2 simultaneously under the action of the group control signal. Therefore, the first and second row pixel circuits can display the corresponding content simultaneously when data signals are written.

[0069] According to the above technical solution, the driver circuit with the aforementioned hardware circuit structure rapidly groups the pixel circuits under the action of the first driving signal and the first clock signal. This ensures that more grouping control signals are prepared before display to control whether adjacent rows of pixel circuits in the grouped pixel circuits are driven simultaneously, and then different line scanning signals are output. Combining the line scanning signal and the data signal allows the same group of pixel circuits to display the same content at the same time. For non-focused areas, i.e., when multiple rows of pixel circuits are grouped together, since multiple rows of pixel circuits display the same content, the effect of low-resolution rendering is achieved in non-focused areas. For focused areas, i.e., when one row of pixel circuits is grouped together, since only one row of pixel circuits is used to display the corresponding content, a high-resolution display effect is achieved. In the process of foveated rendering using DDIC, all rendering signals are first generated based on eye movement signals, and then the rendering signals are given to the driver circuit so that the driver circuit drives the pixel circuits to complete the corresponding display. In the embodiments described above, the eye-tracking signal is first converted into a first driving signal using a DDIC. Then, a rendering signal is generated by a hardware circuit under the action of the first driving signal to drive the pixel circuit to complete the corresponding display. This eliminates the need to wait for the DDIC to generate all the rendering signals, greatly improving rendering efficiency. Furthermore, directly generating the rendering signal using the driving circuit eliminates the need for an additional driving circuit that matches the DDIC to receive the rendering signal, effectively reducing circuit power consumption.

[0070] Figure 2 is a schematic circuit structure diagram of a first sub-circuit provided in an embodiment of this disclosure. Referring to Figure 2, the first sub-circuit 110 may include a first flip-flop 111 and a second flip-flop 112 electrically connected. The first flip-flop 111 and the second flip-flop 112 may be D flip-flops. The triggering methods of D flip-flops include level triggering and edge triggering. Level triggering means that it can be triggered when the clock pulse = 1, while edge triggering mostly occurs at the leading edge of the clock pulse, i.e., during a positive transition from 0 to 1. The next state of the D flip-flop depends on the state of the D terminal before triggering, i.e., the next state = D. The D flip-flop has two stable states, 0 and 1, and can flip from one stable state to another under the influence of certain external signals. Therefore, the D flip-flop has both reset and reset functions. Referring to Figure 2, the clock terminal CK of the first flip-flop 111 is used to receive the first clock signal FRD_CKV, and the D terminal of the first flip-flop 111 is used to receive the first trigger signal IN. The first flip-flop 111 can be triggered by the first clock signal FRD_CKV, by writing the first trigger signal IN at the D terminal, and then the first flip-flop 111 can output the first control signal C1 from the output terminal OUT. Referring to the foregoing, for example, the period of the first clock signal FRD_CKV can be... In this case, the first trigger signal IN can be shifted three rows backward within one row cycle. Referring to Figure 2, the clock terminal CK of the second flip-flop 112 is used to receive the first control signal C1. The D terminal of the second flip-flop 112 can read the first drive signal FRD_IN three times within one row cycle. Triggered by the first control signal C1, the second flip-flop 112 can write the first drive signal FRD_IN to its D terminal. Afterward, the second flip-flop 112 can output the group control signal EN_GRP from the first output terminal OUT1 and the NOT signal EN_GRP' from the second output terminal OUT2. Based on the above embodiment, the output group control signal EN_GRP can achieve simultaneous driving of four rows of pixel circuits.

[0071] Therefore, the stability characteristics of the trigger can be utilized to output more accurate group control signals, providing a reliable guarantee for subsequent group-driven display.

[0072] In some implementations, the first flip-flop and the second flip-flop are used to reset under the action of a reset signal, the effective level end of the reset signal being before the effective level start of the first trigger signal, the first control signal, and the first drive signal.

[0073] For example, referring to Figure 2, both the first flip-flop 111 and the second flip-flop 112 are provided with a reset port Rn. The reset port Rn is used to receive the reset signal FRD_RN. Under the action of the reset signal FRD_RN, the first flip-flop 111 and the second flip-flop 112 can perform a reset operation. It should be noted that, for the flip-flop, the reset operation can bring it into a definite state that can operate stably. This definite state can be the initial running state or the normal state relative to the error state. This ensures that the flip-flop is in a known and definite stable state before each trigger, thereby ensuring the stability and reliability of subsequent signal transmission. For example, the effective level endpoint of the reset signal is before the effective level start point of the first trigger signal, the first control signal, and the first drive signal. Among them, the effective levels of the reset signal, the first trigger signal, the first control signal, and the first drive signal can all be high. In this case, the effective level endpoint can be the moment when the signal changes from high to low, and the effective level start point can be the moment when the signal changes from low to high. To further improve the stability and reliability of subsequent signal transmission and avoid trigger state errors, the effective level endpoint of the reset signal is set before the effective level start points of the first trigger signal, first control signal, and first drive signal. That is, the falling edge of the effective level of the reset signal precedes the rising edge of the effective levels of the first trigger signal, first control signal, and first drive signal.

[0074] For example, referring to Figure 2, in some embodiments, the first control signal C1 is the clock trigger signal of the second flip-flop 112, that is, the first control signal C1 is the clock terminal CK of the second flip-flop 112 at its input terminal. Furthermore, this first control signal C1 is a single-pulse signal, meaning that there is only one pulse of the first control signal in one frame. According to the working principle of the flip-flop, during the period when the clock pulse = 1, the circuit has a blocking function, and even if the data state at terminal D changes, it will not affect the output state of the flip-flop. Therefore, when the clock trigger signal is a single-pulse signal, it can be guaranteed that the group control signal output by the second flip-flop is stable and unchanged in one frame. The nth-level second sub-circuit includes an nth-level first branch and an nth-level second branch. The nth-level first branch is used to output the row scan signal of the nth row pixel circuit under the action of the group control signal provided by the nth-level first sub-circuit. The nth-level second branch is used to output the row scan signal of the (n+1)th row pixel circuit under the action of the group control signal provided by the nth-level first sub-circuit. The nth-level second branch is also used to output the row scan signal of the (n+1)th row pixel circuit under the action of the group control signal provided by the (n+1)th-level first sub-circuit.

[0075] Figure 3 is a schematic block diagram of another driving circuit provided in an embodiment of this disclosure. Exemplarily, referring to Figure 3, the driving circuit 100 may include N stages, and each stage includes a first sub-circuit 110 and a second sub-circuit 120. Each second sub-circuit 120 may include a first branch 130 and a second branch 140. Referring to Figure 3, in the first stage driving circuit, the first sub-circuit 110 can provide a group control signal EN_GRP1 to the first branch 130 and the second branch 140 of the first stage, respectively. The first branch 130 of the first stage can output a row scan signal Q1 for the first row pixel circuit under the action of the group control signal EN_GRP1. The row scan signal Q1 can be used to drive the first row pixel circuit. The second branch 140 of the first stage can output a row scan signal Q2 for the second row pixel circuit under the action of the group control signal EN_GRP1. The row scan signal Q2 can be used to drive the second row pixel circuit. In the second-stage driving circuit, the first sub-circuit 110 can provide the group control signal EN_GRP2 to the second-stage first branch 130 and the second-stage second branch 140, respectively. The second-stage first branch 130 can output the row scan signal Q2 of the second row pixel circuit under the action of the group control signal EN_GRP2. The second-stage second branch 140 can output the row scan signal Q3 of the third row pixel circuit under the action of the group control signal EN_GRP2. The second-stage first branch can be the same circuit as the first-stage second branch. That is, shared circuitry can exist between the first-stage second sub-circuit and the second-stage second sub-circuit. This shared circuitry, when used to receive the group control signal of the previous-stage first sub-circuit, such as the nth-stage first sub-circuit, can be considered as the second branch of the nth-stage second sub-circuit. When used to receive the group control signal of the next-stage first sub-circuit, the (n+1)th-stage first sub-circuit, it can be considered as the first branch of the (n+1)th-stage second sub-circuit. Similarly, the n-level second sub-circuit can output a line scan signal Qn to the corresponding n-row pixel circuit under the action of n-1 group control signals. That is, the number of stages of the driving circuit is less than the number of rows of the pixel circuit. With a stable and unchanging group control signal obtained according to the above technical solution, it is possible to accurately determine whether each pair of adjacent pixel circuits is controlled simultaneously, thereby ensuring the stability of the line scan signal output by the second sub-circuit and guaranteeing the rendering and display effect.

[0076] In some implementations, the driving circuit includes N stages, and the nth stage driving circuit may include a first sub-circuit of the nth stage and a second sub-circuit of the nth stage. The first flip-flop of the first sub-circuit of the nth stage is electrically connected to the first flip-flop of the first sub-circuit of the (n+1)th stage. The first flip-flop of the first sub-circuit of the nth stage is used to transmit a first control signal to the first flip-flop of the first sub-circuit of the (n+1)th stage. The first control signal is the first trigger signal of the first flip-flop of the first sub-circuit of the (n+1)th stage. Here, N and n are both natural numbers greater than 0, and n+1≤N.

[0077] Figure 4 is a schematic circuit structure diagram of another first sub-circuit provided in an embodiment of this disclosure. In the embodiment shown in Figure 4, n=1, that is, Figure 4 shows the connection relationship between the first-stage first sub-circuit and the second-stage first sub-circuit. For example, referring to Figure 4, both the first flip-flop 111 and the second flip-flop 112 are provided with a reset port Rn. The reset port Rn is used to receive the reset signal FRD_RN. Under the action of the reset signal FRD_RN, the first flip-flop 111 and the second flip-flop 112 can perform a reset operation. The D terminal of the first flip-flop 111 of the first-stage first sub-circuit 110 is used to receive the first trigger signal IN, and the clock terminal CK of the first flip-flop 111 of the first-stage first sub-circuit 110 is used to receive the first clock signal FRD_CKV. Under the trigger of the first clock signal FRD_CKV, the first flip-flop 111 of the first-stage first sub-circuit 110 can write the first trigger signal IN to the D terminal, and then output the first control signal C1 from the output terminal OUT. The output terminal OUT of the first flip-flop 111 of the first sub-circuit 110 of the first stage is electrically connected to the clock terminal of the second flip-flop 112 of the first sub-circuit 110 of the first stage and the D terminal of the first flip-flop 111 of the first sub-circuit 110 of the second stage. Referring to Figure 4, the first control signal C1 serves not only as the clock trigger signal for the second flip-flop 112 of the first sub-circuit 110 of the first stage, but also as the input signal to the D terminal of the first flip-flop 111 of the first sub-circuit 110 of the second stage, i.e., the first trigger signal. Under the combined action of the first clock signal FRD_CKV and the first control signal C1, the first flip-flop 111 of the second sub-circuit 110 can output a new first control signal C1 from its output terminal OUT. Similar to the first control signal C1 output by the first flip-flop of the first sub-circuit of the first stage, the new first control signal output by the first flip-flop of the second sub-circuit of the second stage also serves as the clock trigger signal for the second flip-flop of the second stage, and the first trigger signal for the first flip-flop of the third sub-circuit. Similarly, the first control signal output by the first flip-flop of the nth-stage first sub-circuit also serves as the clock trigger signal for the second flip-flop of the nth-stage first sub-circuit, and the first trigger signal for the first flip-flop of the (n+1)th-stage first sub-circuit. For example, the first control signal C1 serves as the clock trigger signal for the second flip-flop 112 of the first-stage first sub-circuit 110. The first drive signal FRD_IN serves as the D trigger signal for the second flip-flop 112 of the first-stage first sub-circuit 110. Under the action of the first control signal C1 and the first drive signal FRD_IN, the second flip-flop 112 of the first-stage first sub-circuit 110 outputs the group control signal EN_GRP from the output terminal OUT1. <1> Output the group control signal EN_GRP from the output terminal OUT2. <1> Similarly, the second flip-flop 112 of the first sub-circuit 110 of the nth stage can output the group control signal EN_GRP from the output terminal OUT1. <n>Output the group control signal EN_GRP from the output terminal OUT2. <n>.

[0078] Therefore, with the circuit structure having the above-mentioned connection relationship, signal transmission can be achieved by inputting the first trigger signal to the D terminal of the first flip-flop of the first sub-circuit of the first stage, without needing to input a trigger signal separately to the first flip-flop of each first sub-circuit, thus reducing signal input. From a hardware perspective, the circuit connection relationship is simplified, eliminating the need to set a signal input terminal with an electrical connection to the D terminal of the first flip-flop of each first sub-circuit, thereby reducing external signal interference.

[0079] In some embodiments, exemplarily referring to FIG4, the first-stage first sub-circuit 110 may include a first transmission gate 113. The input terminal 1 of the first transmission gate 113 is used to receive a frame start signal FRD_STV. When the first transmission gate 113 is turned on, the frame start signal FRD_STV can be transmitted via the output terminal 2 to the first flip-flop 111 of the first-stage first sub-circuit 110. The frame start signal FRD_STV is the first trigger signal IN received by the first-stage first flip-flop 111. Referring to FIG4, the first transmission gate 113 also includes a control terminal 3, which is used to receive a rendering start signal READY_IN. Exemplarily, when the rendering start signal READY_IN = 1, the first transmission gate 113 can be turned on. When the rendering start signal READY_IN = 0, the first transmission gate 113 is in a turned-off state. The frame start signal serves as the start signal of a frame image. According to the above technical solution, when the first transmission gate is turned on, the frame start signal can be input to the first-stage first flip-flop as the D trigger signal of the flip-flop. In the entire driving circuit, the first transmission gate can be set only before the first flip-flop of the first stage, and the rendering start signal can be written as the frame start signal as a condition for the first flip-flop of the first stage, thus realizing a fast response for rendering and display.

[0080] In some implementations, the effective level start point of the rendering start signal is after the effective level end point of the reset signal, and the effective level end point of the rendering start signal is before the effective level start point of the first drive signal. For example, the effective level of the rendering start signal can be a high level, with its effective level start point being the moment of transition from low to high and its effective level end point being the moment of transition from high to low. Setting the effective level end point of the reset signal before the effective level start point of the rendering start signal allows the reset signal to complete the reset operation on the first stage first flip-flop before the rendering start signal acts on the first transmission gate. As mentioned earlier, the reset signal can ensure that the flip-flop is in a known and determined stable state before each trigger, thus controlling the flip-flop to be in a stable state before the first stage first flip-flop receives the first trigger signal. The effective level end point of the rendering start signal can be set before the effective level start point of the first drive signal. For example, the rendering start signal can be regarded as a start signal for the driving circuit to perform rendering work, and the first drive signal can be regarded as a demand signal or desired signal for specific rendering. Setting the effective level end point of the rendering start signal before the effective level start point of the first drive signal ensures timely response of the first drive signal to the drive circuit, avoids deviations in rendering results due to the loss of the first drive signal, and guarantees the rendering display effect.

[0081] Figure 5 is a schematic circuit structure diagram of a second sub-circuit provided in an embodiment of this disclosure. Exemplarily, the embodiment shown in Figure 5 includes a first-level second sub-circuit and a second-level second sub-circuit. Each level of the second sub-circuit 120 may include a second transmission gate 121, a third transmission gate 122, a fourth transmission gate 123, a third flip-flop 124, and a fourth flip-flop 125. For the first-level second sub-circuit, the first branch may include the third transmission gate 122 and the third flip-flop 124, and the second branch may include the third transmission gate 122, the fourth transmission gate 123, and the fourth flip-flop 125. For the second-level second sub-circuit, the first branch may include the third transmission gate 122 and the fourth flip-flop 125 in the first-level second sub-circuit. The second branch may include the third transmission gate 122, the fourth transmission gate 123, and the fourth flip-flop 125 in the second-level second sub-circuit. Referring to Figure 5, the fourth flip-flop 125 in the first-level second sub-circuit also serves as the third flip-flop 124 in the second-level second sub-circuit. Taking the second sub-circuit of the first stage as an example, the following detailed description is provided (refer to Figure 5). The second transmission gate 121 is electrically connected to the third transmission gate 122 and the third flip-flop 124. The input terminal IN of the second transmission gate 121 is used to receive the frame start signal STV. When the second transmission gate 121 is in the on state, the second trigger signal C2 can be transmitted to the third transmission gate 122 and the third flip-flop 124, which are electrically connected to it, via the output terminal OUT. The third transmission gate 122 is electrically connected to the third flip-flop 124 and the fourth flip-flop 125. The fourth transmission gate 123 is electrically connected to the third flip-flop 124 and the fourth flip-flop 125. The third transmission gate 122 and the fourth transmission gate 123 are electrically connected. The input terminal IN of the third transmission gate 122 is used to receive the second trigger signal C2 transmitted by the second transmission gate 121. The control terminal 1 of the third transmission gate 122 is used to receive the packet control signal EN_GRP output from the second flip-flop in the first sub-circuit. When the packet control signal EN_GRP = 1, the third transmission gate 122 can be turned on. Referring to Figure 5, the control terminal 1 of the fourth transmission gate 123 is also used to receive the packet control signal EN_GRP output from the second flip-flop in the first sub-circuit. Unlike the third transmission gate 122, an NOT gate is added to the control terminal 1 of the fourth transmission gate 123. Therefore, when the packet control signal EN_GRP = 1, the third transmission gate 122 can be turned on, while the fourth transmission gate 123 is in the opposite off state. Conversely, when the packet control signal EN_GRP = 0, the third transmission gate 122 is off, while the fourth transmission gate 123 is in the opposite on state. For example, referring to Figure 5, when the third transmission gate 122 is on and the fourth transmission gate 123 is off, the third transmission gate 122 can output the second trigger signal C2 to the fourth flip-flop 125.At this time, both the third flip-flop 124 and the fourth flip-flop 125 can output the line scan signal via the output terminal OUT under the action of the clock trigger signal CK and the second trigger signal C2. Specifically, the third flip-flop 124 can output the line scan signal Q1, and the fourth flip-flop 125 can output the line scan signal Q2. Referring to Figure 5, in this embodiment, since there is no delay caused by other components, and when the group control signal EN_GRP = 1, because the fourth transmission gate 123 is in the off state, the second trigger signal C2 transmitted from the third transmission gate 122 to the fourth flip-flop 125 has no shunting loss. Therefore, the line scan signal Q1 and the line scan signal Q2 can be output at the same time. Combined with the above description, when the group control signal EN_GRP = 1, the first branch of the first-stage second sub-circuit can output the line scan signal Q1, and at the same time, the second branch of the first-stage second sub-circuit can output the line scan signal Q2, realizing the simultaneous driving of adjacent two row pixel circuits.

[0082] For example, referring to Figure 5, when the fourth transmission gate 123 is on and the third transmission gate 122 is off, the third flip-flop 124 can output a second control signal through its output terminal OUT under the action of the clock trigger signal and the second trigger signal C2. As shown in Figure 5, this second control signal serves as both the line scan signal Q1 and the input signal of the fourth transmission gate 123. When the packet control signal EN_GRP = 0, the fourth transmission gate 123 is on and can output the second control signal to the D terminal of the fourth flip-flop 125. The fourth flip-flop 125 can output the line scan signal Q2 through its output terminal under the action of the second control signal and the clock trigger signal. After the line scan signal Q1 is output, the second control signal is transmitted via the fourth transmission gate 123 to trigger the fourth flip-flop to output the line scan signal Q2. Therefore, in this embodiment, the line scan signal Q1 and the line scan signal Q2 are not output at the same time; the line scan signal Q2 is delayed after the line scan signal Q1 is output. As mentioned above, when the group control signal EN_GRP = 0, the first branch of the first-level second sub-circuit can output the line scan signal Q1, and then the second branch of the first-level second sub-circuit can output the line scan signal Q2, thus realizing that the adjacent two rows of pixel circuits are not driven at the same time.

[0083] In some embodiments, exemplarily referring to FIG. 5, the second sub-circuit 120 may further include a fifth transmission gate 126. The fifth transmission gate 126 is electrically connected between the fourth flip-flop 125 and the third transmission gate 122. Referring to FIG. 5, the second transmission gate 121 may be respectively located at the position corresponding to the start row pixel circuit and the position corresponding to the end row pixel circuit. In the embodiment shown in FIG. 5, the control terminal 1 of the second transmission gate 121 is used to receive the second driving signal GSD_FW, and the control terminal 2 is used to receive the second driving signal GSD_BW. Compared with the second transmission gate 121 located at the position corresponding to the start row pixel circuit, the second transmission gate 121 located at the position corresponding to the end row pixel circuit has an inverted gate at the control terminal 1. Compared with the second transmission gate 121 located at the position corresponding to the end row pixel circuit, the second transmission gate 121 located at the position corresponding to the start row pixel circuit has an inverted gate at the control terminal 2. The control terminals 1 of the fifth transmission gates 126-1 and 126-2 are used to receive the second driving signal GSD_FW, and the control terminals 2 of the fifth transmission gates 126-1 and 126-2 are used to receive the second driving signal GSD_BW. Unlike the fifth transmission gate 126-1, the fifth transmission gate 126-2 has a NOT gate at its control terminal 2. Conversely, unlike the fifth transmission gate 126-1, the fifth transmission gate 126-1 has a NOT gate at its control terminal 1. For example, when the second driving signal GSD_FW = 1 and the second driving signal GSD_BW = 0, the control signals received by the control terminals 1 and 2 of the second transmission gates 121 and 126-2 located at the corresponding positions of the starting row pixel circuits are both high-level, while the control signals received by the control terminals 1 and 2 of the second transmission gates 121 and 126-1 located at the corresponding positions of the ending row pixel circuits are both low-level. Therefore, when the second driving signal GSD_FW = 1 and the second driving signal GSD_BW = 0, the second transmission gate 121 and the fifth transmission gate 126-2 located at the corresponding positions of the starting row pixel circuit are turned on, while the second transmission gate 121 and the fifth transmission gate 126-1 located at the corresponding positions of the ending row pixel circuit are turned off. In this case, the forward scan function can be realized, that is, for the row pixel circuit, the row scan is performed from top to bottom. Conversely, when the second driving signal GSD_FW = 0 and the second driving signal GSD_BW = 1, the control signals received by the control terminals 1 and 2 of the second transmission gate 121 and the fifth transmission gate 126-1 located at the corresponding positions of the ending row pixel circuit are both high level, while the control signals received by the control terminals 1 and 2 of the second transmission gate 121 and the fifth transmission gate 126-2 located at the corresponding positions of the starting row pixel circuit are both low level.Therefore, when the second driving signal GSD_FW = 1 and the second driving signal GSD_BW = 0, the second transmission gate 121 and the fifth transmission gate 126-1 located at the corresponding positions of the termination row pixel circuit are turned on, while the second transmission gate 121 and the fifth transmission gate 126-2 located at the corresponding positions of the start row pixel circuit are turned off. In this case, the reverse scan function can be implemented, that is, for the row pixel circuit, row scanning is performed from bottom to top.

[0084] Therefore, a fifth transmission gate can be added to the second sub-circuit to achieve forward and reverse scanning functions through the above technical solution, thus meeting various needs.

[0085] Figure 6 is a driving timing diagram of a driving circuit provided in an embodiment of this disclosure. For example, referring to Figure 6, taking the driving of a 4-row pixel circuit as an example, as described above, the corresponding driving circuit has 3 stages, including V1, V2, and V3. Referring to the timing diagram corresponding to V1 in Figure 6, FRD_STV is the D trigger signal of the first flip-flop of the first stage. When it is high, the corresponding clock trigger signal FRD_CKV is also high. At this time, the first flip-flop of the first stage outputs a high-level signal DFF_Q1. DFF_Q1 serves as the clock trigger signal of the second flip-flop of the first stage, and the first driving signal FRD_IN serves as the D trigger signal of the second flip-flop of the first stage. When both DFF_Q1 and FRD_IN are high, the second flip-flop of the first stage outputs a high-level group control signal EN_GRP1. That is, EN_GRP1 = 1, at which time the first row pixel circuit and the second row pixel circuit are driven simultaneously. Referring to the timing diagram corresponding to V2 in Figure 6, DFF_Q1 also serves as the D trigger signal for the first flip-flop of the second stage. When DFF_Q1 is high and the clock trigger signal FRD_CKV is also high, the first flip-flop of the second stage can output a high-level signal DFF_Q2. DFF_Q2 serves as the clock trigger signal for the second flip-flop of the second stage, and the first drive signal FRD_IN serves as the D trigger signal for the second flip-flop of the second stage. When both DFF_Q2 and FRD_IN are high, the second flip-flop of the second stage outputs a high-level group control signal EN_GRP2. That is, EN_GRP2 = 2, at which point the second row pixel circuit and the third row pixel circuit are driven simultaneously. Referring to the timing diagram corresponding to V3 in Figure 6, DFF_Q2 also serves as the D trigger signal for the first flip-flop of the third stage. When DFF_Q1 is high and the clock trigger signal FRD_CKV is also high, the first flip-flop of the third stage can output a high-level signal DFF_Q3. DFF_Q3 serves as the clock trigger signal for the third-stage second flip-flop, and the first drive signal FRD_IN serves as the D trigger signal for the third-stage second flip-flop. When DFF_Q3 is high but the first drive signal FRD_IN is low, the third-stage second flip-flop outputs a low-level group control signal EN_GRP3. That is, EN_GRP3 = 0, and the third row pixel circuit and the fourth row pixel circuit are not driven simultaneously. In conjunction with the preceding text, the first row pixel circuit, the second row pixel circuit, and the third row pixel circuit are driven simultaneously as the first group of pixel circuits. The fourth row pixel circuit is driven separately as the second group of pixel circuits and is not driven simultaneously with the first group of pixel circuits. Furthermore, in the embodiment shown in Figure 6, since DFF_Q1, DFF_Q2, and DFF_Q3 are all single-pulse signals within one row cycle, according to the working principle of the D flip-flop, the group control signals output by each stage of the second flip-flop remain stable.

[0086] A second aspect of this disclosure also provides a display panel. FIG7 is a schematic structural block diagram of a display panel provided in an embodiment of this disclosure. Referring to FIG7, the display panel 700 may include: a driving circuit 100 and a pixel circuit 200 as described above. The driving circuit 100 may include N-level first sub-circuits 110 and N-level second sub-circuits 120. The number of rows in the pixel circuit 200 is greater than the number of levels in the driving circuit 100.

[0087] A third aspect of this disclosure also provides a control method for a drive circuit, applied to the drive circuit described above. Figure 8 is a schematic flowchart of a control method for a drive circuit provided by an embodiment of this disclosure. Referring to Figure 8, the control method may include the following steps.

[0088] Step S810: The first sub-circuit is controlled to output a group control signal under the action of the first driving signal and the first clock signal. The group control signal is used to control whether adjacent rows of pixels are driven at the same time.

[0089] Step S820: Control the second sub-circuit to output a line scanning signal to the pixel circuit under the action of the group control signal.

[0090] For example, eye-tracking signals can be processed to obtain and send a first driving signal to the first sub-circuit. The first sub-circuit can divide the row pixels of the pixel circuit under the action of the first driving signal and the first clock signal, thereby outputting more group control signals before display. The value of the group control signal determines the synchronization of the output signals, i.e., whether adjacent rows of pixel circuits are driven simultaneously. For example, for the first and second row pixel circuits, when the group control signal is equal to 0, the second sub-circuit can output two row scan signals sequentially under the action of the group control signal. Therefore, the first and second row pixel circuits cannot display content simultaneously. When the group control signal is equal to 1, the second sub-circuit can output two row scan signals simultaneously under the action of the group control signal.

[0091] In some embodiments, before the first sub-circuit outputs a group control signal under the action of the first driving signal, the method may further include: controlling the first flip-flop and the second flip-flop to reset under the action of a reset signal, wherein the effective level end of the reset signal is before the effective level start of the first trigger signal, the first control signal and the first driving signal.

[0092] For example, under the action of the reset signal, the first and second flip-flops can be reset. For the flip-flops, the reset operation allows them to enter a defined state capable of stable operation. The effective voltage levels of the reset signal, the first trigger signal, the first control signal, and the first drive signal can all be high. In this case, the effective voltage level endpoint can be the moment when the signal transitions from high to low, and the effective voltage level start point can be the moment when the signal transitions from low to high. To further improve the stability and reliability of subsequent signal transmission and avoid flip-flop state errors, the effective voltage level endpoint of the reset signal is set before the effective voltage level start point of the first trigger signal, the first control signal, and the first drive signal.

[0093] In some implementations, the method may further include: when the first transmission gate is turned on under the action of the rendering start signal, controlling the first transmission gate to transmit the frame start signal to the first trigger, wherein the frame start signal is the first trigger signal received by the first trigger of the first stage.

[0094] For example, the input of the first transmission gate is used to receive a frame start signal, and the control terminal of the first transmission gate is used to receive a rendering start signal. When the rendering start signal is equal to 1, the first transmission gate is turned on. When the rendering start signal is equal to 0, the first transmission gate is in the off state. When the first transmission gate is on, the frame start signal can be transmitted via the output terminal to the first flip-flop of the first sub-circuit of the first stage.

[0095] In some implementations, the effective level start point of the rendering start signal is after the effective level end point of the reset signal, and the effective level end point of the rendering start signal is before the effective level start point of the first drive signal.

[0096] For example, the effective level of the rendering start signal can be high, with its effective level starting at the moment of transition from low to high and ending at the moment of transition from high to low. Setting the effective level ending of the reset signal before the effective level starting of the rendering start signal ensures that the reset signal completes the reset operation on the first flip-flop of the first stage before the rendering start signal acts on the first transmission gate. For example, the rendering start signal can be considered as the start signal for the driving circuit to perform rendering work, and the first driving signal can be considered as the demand signal or expected signal for specific rendering. Setting the effective level ending of the rendering start signal before the effective level starting of the first driving signal ensures timely response of the first driving signal written to the driving circuit, avoiding situations where the first driving signal is lost and the rendering result deviates, thus guaranteeing the rendering display effect.

[0097] In some implementations, the method may further include: controlling the second transmission gate and the fifth transmission gate to be turned on or off under the action of the second driving signal.

[0098] For example, referring to Figure 5, when the second driving signal GSD_FW = 1 and the second driving signal GSD_BW = 0, the control signals received by control terminals 1 and 2 of the second transmission gate 121 and the fifth transmission gate 126-2 located at the corresponding positions of the starting row pixel circuit are both high-level, while the control signals received by control terminals 1 and 2 of the second transmission gate 121 and the fifth transmission gate 126-1 located at the corresponding positions of the ending row pixel circuit are both low-level. Therefore, the second transmission gate 121 and the fifth transmission gate 126-2 located at the corresponding positions of the starting row pixel circuit are turned on, and the second transmission gate 121 and the fifth transmission gate 126-1 located at the corresponding positions of the ending row pixel circuit are turned off. In this case, the forward scan function can be realized. Conversely, when the second driving signal GSD_FW = 0 and the second driving signal GSD_BW = 1, the control signals received by control terminals 1 and 2 of the second transmission gate 121 and the fifth transmission gate 126-1 located at the corresponding positions of the termination row pixel circuit are both high-level, while the control signals received by control terminals 1 and 2 of the second transmission gate 121 and the fifth transmission gate 126-2 located at the corresponding positions of the start row pixel circuit are both low-level. Therefore, the second transmission gate 121 and the fifth transmission gate 126-1 located at the corresponding positions of the termination row pixel circuit are turned on, and the second transmission gate 121 and the fifth transmission gate 126-2 located at the corresponding positions of the start row pixel circuit are turned off. Under these conditions, the reverse scan function can be implemented.

[0099] A fourth aspect of this disclosure also provides a controller, comprising: a memory storing a computer program; and a processor for calling the computer program in the memory, the computer program being used to execute the control method described above.

[0100] For example, the controller can be integrated into the driver circuit. In some embodiments, the controller can also be integrated into the driver chip.

[0101] A fifth aspect of this disclosure also provides a display device including a display panel as described above and / or a controller as described above. FIG9 is a schematic structural block diagram of a display device provided in an embodiment of this disclosure. In the embodiment shown in FIG9, the display device 900 may simultaneously include the display panel 700 as described above and the controller 910 as described above. In some embodiments, the display device 900 may further include either the display panel 700 or the controller 910.

[0102] In some embodiments, the display device may further include: a driver chip electrically connected to the driving circuit of the display panel; and a control motherboard electrically connected to the driver chip. For example, the control motherboard may be a device such as a DDIC used to acquire and process eye-tracking signals and generate a first driving signal. The control motherboard can send the first driving signal to the driver chip, enabling the driving circuit to perform the aforementioned driving function under the drive of the driver chip. The driver chip may be attached to a non-display area of ​​the display panel.

[0103] For example, the display device of this disclosure can be applied to scenarios such as in-vehicle displays, smartphones, computers, medical displays, televisions, and smart wearable displays. Smart wearable devices may include smartwatches, AR (augmented reality) devices, and VR (virtual reality) devices, etc. This disclosure does not impose specific limitations.

[0104] Those skilled in the art can understand the specific details and beneficial effects of the display panel, controller, and display device by reading the above description of the driving circuit and its control method; for the sake of brevity, these details will not be repeated here.

[0105] In the several embodiments provided in this disclosure, it should be understood that the disclosed apparatus and / or device can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0106] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0107] Furthermore, the functional units in the various embodiments of this disclosure can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0108] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this disclosure, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this disclosure. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0109] The foregoing description has described specific embodiments, which, along with other embodiments, are covered within the scope of the appended claims. In some cases, the actions or steps recited in the claims may be performed in a different order than those shown in the embodiments and may still achieve the desired results. Furthermore, the processes depicted in the drawings do not necessarily follow the specific or sequential order shown to achieve the desired results. In some embodiments, multitasking and parallel processing are also feasible or advantageous.

[0110] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0111] It should be understood that the above-described embodiments are merely illustrative of the purpose of this disclosure and are not intended to limit the scope of this disclosure. Those skilled in the art can implement this disclosure in other ways without departing from its basic spirit and characteristics. The scope of this disclosure is determined by the appended claims, and any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of one or more embodiments of this specification should be covered herein.< / n> < / n>

Claims

1. A driving circuit, comprising: The first sub-circuit is used to output a group control signal under the action of a first driving signal and a first clock signal. The group control signal is used to control whether two adjacent rows of pixel circuits are driven simultaneously. The period of the first clock signal is the refresh time of one row of pixel circuits. x is a natural number greater than 1; The second sub-circuit has one end electrically connected to the first sub-circuit and the other end electrically connected to the pixel circuit. The second sub-circuit is used to output a line scanning signal under the action of the group control signal.

2. The driving circuit according to claim 1, wherein, The first sub-circuit includes: a first flip-flop and a second flip-flop that are electrically connected; The first trigger is used to output a first control signal under the action of the first clock signal and the first trigger signal; The second trigger is used to output the group control signal under the action of the first control signal and the first drive signal.

3. The driving circuit according to claim 2, wherein, The first control signal is the clock trigger signal of the second flip-flop, and the first control signal is a single pulse signal.

4. The driving circuit according to claim 2, wherein, The driving circuit includes N stages. The nth stage driving circuit includes an nth stage first sub-circuit and an nth stage second sub-circuit. The nth stage second sub-circuit includes an nth stage first branch and an nth stage second branch. The nth stage first branch is used to output the row scan signal of the nth row pixel circuit under the action of the group control signal provided by the nth stage first sub-circuit. The nth stage second branch is used to output the row scan signal of the (n+1)th row pixel circuit under the action of the group control signal provided by the nth stage first sub-circuit. The nth stage second branch is also used to output the row scan signal of the (n+1)th row pixel circuit under the action of the group control signal provided by the (n+1)th stage first sub-circuit.

5. The driving circuit according to claim 4, wherein, The first flip-flop of the first sub-circuit of the nth stage is electrically connected to the first flip-flop of the (n+1)th stage first sub-circuit. The first flip-flop of the first sub-circuit of the nth stage is used to transmit the first control signal to the first flip-flop of the (n+1)th stage first sub-circuit. The first control signal is the first trigger signal of the first flip-flop of the (n+1)th stage first sub-circuit. Here, N and n are both natural numbers greater than 0, and n+1≤N.

6. The driving circuit according to claim 5, wherein, The first and second flip-flops are used to reset under the action of a reset signal, wherein the effective level end of the reset signal is before the effective level start of the first trigger signal, the first control signal, and the first drive signal.

7. The driving circuit according to claim 6, wherein, The first sub-circuit of the first stage includes a first transmission gate, which is used to transmit a frame start signal to the first trigger. The frame start signal is the first trigger signal received by the first trigger of the first stage. The first transmission gate is used to be turned on or off under the action of the rendering start signal.

8. The driving circuit according to claim 7, wherein, The effective level start point of the rendering start signal is after the effective level end point of the reset signal, and the effective level end point of the rendering start signal is before the effective level start point of the first drive signal.

9. The driving circuit according to any one of claims 2 to 8, wherein, The second sub-circuit includes a second transmission gate, a third transmission gate, a fourth transmission gate, a third flip-flop, and a fourth flip-flop; The second transmission gate is electrically connected to the third transmission gate and the third flip-flop, respectively, and is used to output a second trigger signal to the third transmission gate and the third flip-flop when the gate is turned on. The third transmission gate is electrically connected to the third flip-flop and the fourth flip-flop respectively. The fourth transmission gate is electrically connected to the third flip-flop and the fourth flip-flop respectively. The third transmission gate and the fourth transmission gate are electrically connected. Both the third transmission gate and the fourth transmission gate are used to turn on or off under the action of the group control signal. When the third transmission gate is turned on and the fourth transmission gate is turned off, the third transmission gate outputs the second trigger signal to the fourth trigger. When the fourth transmission gate is turned on and the third transmission gate is turned off, the fourth transmission gate outputs a second control signal to the fourth flip-flop, wherein the second control signal is output by the third flip-flop under the triggering of the second trigger signal and the second clock signal.

10. The driving circuit according to claim 9, wherein, The second sub-circuit also includes a fifth transmission gate, electrically connected between the fourth flip-flop and the third transmission gate. The fifth transmission gate is used to turn on or off under the action of the second driving signal, and the second transmission gate is used to turn on or off under the action of the second driving signal.

11. A display panel, comprising: The driving circuit as described in any one of claims 1 to 10; A pixel circuit, wherein the number of rows in the pixel circuit is greater than the number of stages in the driving circuit.

12. A control method for a drive circuit, applied to the drive circuit as described in any one of claims 1 to 10, the control method comprising: The first sub-circuit is controlled to output the group control signal under the action of the first driving signal and the first clock signal. The group control signal is used to control whether adjacent rows of pixels are driven simultaneously. The period of the first clock signal is the refresh time of one row of the pixel circuit. x is a natural number greater than 1; The second sub-circuit is controlled to output a line scan signal to the pixel circuit under the action of the group control signal.

13. The control method according to claim 12, wherein, Before controlling the first sub-circuit to output the group control signal under the action of the first drive signal and the first clock signal, the method further includes: The first and second flip-flops are controlled to reset under the action of a reset signal, wherein the effective level end of the reset signal is before the effective level start of the first trigger signal, the first control signal, and the first drive signal.

14. The control method according to claim 13, further comprising: When the first transmission gate is turned on under the action of the rendering start signal, the first transmission gate is controlled to transmit the frame start signal to the first trigger. The frame start signal is the first trigger signal received by the first trigger of the first stage.

15. The control method according to claim 14, wherein, The effective level start point of the rendering start signal is after the effective level end point of the reset signal, and the effective level end point of the rendering start signal is before the effective level start point of the first drive signal.

16. The control method according to claim 12, further comprising: The second transmission gate and the fifth transmission gate are controlled to be turned on or off under the action of the second driving signal.

17. A controller, comprising: Memory, which stores computer programs; A processor for invoking the computer program in the memory, the computer program being used to execute the control method as described in any one of claims 12 to 16.

18. A display device, comprising: The display panel as claimed in claim 11 and / or the controller as claimed in claim 17.

19. The display device according to claim 18, further comprising: A driver chip, which is electrically connected to the driver circuit of the display panel; The control motherboard is electrically connected to the driver chip.

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