Memory

Abstract

Embodiments of the present application relate to the field of memories. Provided is a memory, comprising a first chip and a second chip which are stacked in a first direction, wherein a plurality of memory cells are formed on the first chip, the memory cells being driven by corresponding sub-word lines; a peripheral circuit is formed on the second chip; and a plurality of sub-word line gating circuits are further formed on the first chip, each of the sub-word line gating circuits being used for gating a corresponding sub-word line.

Description

memory

[0001] This application claims priority to Chinese Patent Application No. 202411734754.X, filed on November 28, 2024, entitled “Memory”, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of memory, and more particularly to a semiconductor memory. Background Technology

[0003] Traditional memory chips are fabricated based on two-dimensional planes, with memory cells arranged on a single plane. However, with the increasing demand for higher capacity and smaller size memory, traditional two-dimensional planar memory technology faces physical and performance limitations.

[0004] To address these issues, 3D memory technology emerged. It achieves higher storage density by stacking multiple layers of memory cells vertically. This stacking structure can significantly increase the storage capacity of memory chips while maintaining a relatively small chip size. Furthermore, 3D memory employs advanced manufacturing processes and materials to improve data transfer speeds and energy efficiency.

[0005] Existing 3D memory places all storage cells on one chip and all circuitry on another. However, this design wastes area due to the driving capabilities required by the storage cells. Summary of the Invention

[0006] This application provides a memory that can fully utilize the area of ​​each chip in a three-dimensional memory and improve integration.

[0007] According to some embodiments of this application, one aspect of this application provides a memory, characterized in that it includes a first chip and a second chip stacked along a first direction; wherein, a plurality of memory cells are formed on the first chip, and the memory cells are driven by corresponding sub-word lines; peripheral circuits are formed on the second chip; and a plurality of sub-word line selection circuits are also formed on the first chip, each of the sub-word line selection circuits being used to select the corresponding sub-word line.

[0008] In some embodiments, the memory cell includes a gate transistor, so a portion of the subword line serves as the gate of the gate transistor.

[0009] In some embodiments, the first chip is provided with multiple storage layers stacked along a first direction, each storage layer is provided with a plurality of storage pads, the plurality of storage pads include a first storage pad and a second storage pad adjacent to each other along a second direction, and a plurality of sub-word line gating circuits are disposed between the first storage pad and the second storage pad; wherein, the second direction is perpendicular to the first direction.

[0010] In some embodiments, the sub-word line gating circuit includes a first transistor and a second transistor; the gates of the first transistor and the second transistor are electrically connected, the drains of the first transistor and the second transistor are electrically connected to the sub-word line, the source of the first transistor is configured to receive a first selection signal, and the source of the second transistor is configured to receive a first power supply signal.

[0011] In some embodiments, each of the memory pads includes a plurality of memory cells arrayed along a second direction and a third direction, and the gates of a column of memory cells arranged along the second direction share a sub-word line; the sources of the first transistors of the plurality of sub-word line gating circuits between the first memory pad and the second memory pad are electrically connected; wherein the third direction is perpendicular to the first direction and perpendicular to the second direction.

[0012] In some embodiments, the sources of the first transistors of the plurality of sub-word line gating circuits between the first storage pad and the second storage pad are connected through a first winding structure; a plurality of steps are also formed between the first storage pad and the second storage pad, and the first winding structure of each storage layer is electrically connected to a step; the first winding structures of different storage layers are electrically connected to different steps.

[0013] In some embodiments, each of the storage pads includes a plurality of storage cells arrayed along a second direction and a third direction, wherein the gates of a column of storage cells arranged along the second direction share a sub-word line; the gates of the first transistors of a plurality of sub-word line gating circuits between the first storage pad and the second storage pad are electrically connected and configured to receive a second selection signal; wherein the third direction is perpendicular to the first direction and perpendicular to the second direction.

[0014] In some embodiments, the gates of the first transistors of the plurality of sub-word line gating circuits between the first storage pad and the second storage pad are connected by a second winding structure; a plurality of steps are also formed between the first storage pad and the second storage pad, and the second winding structure of each storage layer is electrically connected to a step; the second winding structures of different storage layers are electrically connected to different steps.

[0015] In some embodiments, the plurality of storage pads further include a third storage pad and a fourth storage pad, wherein the first storage pad, the plurality of sub-word line gating circuits, the second storage pad, the third storage pad, the plurality of sub-word line gating circuits, and the fourth storage pad are arranged sequentially along a second direction.

[0016] In some embodiments, each storage pad includes a plurality of storage cells arrayed along a second direction and a third direction, wherein the gates of a column of storage cells arranged along the second direction share a sub-word line; each row of storage cells in two adjacent columns of storage cells along the third direction shares a sub-bit line; and multiple sub-bit lines of a row of storage cells arranged along the third direction are connected to the same common bit line; wherein the third direction is perpendicular to the first direction and perpendicular to the second direction.

[0017] The memory provided in this application has at least the following advantages:

[0018] The memory includes a stacked first chip and a second chip. The first chip has multiple memory cells formed on it, and the second chip has peripheral circuitry. The first chip also has multiple sub-word line selection circuits, each of which selects a corresponding sub-word line. By placing the sub-word line selection circuits on the memory cell chip, the driving of the memory cell word lines is achieved on the memory cell chip, thereby reducing the area of ​​the peripheral circuitry chip. This allows for a more rational arrangement of the circuit structure on the peripheral circuitry chip, improving integration density. Furthermore, due to the specific circuit design, location, and connection design of the sub-word line selection circuits, and based on the correct selection of sub-word lines, the number of steps and transistors in the sub-word line selection circuits is reduced, improving the area utilization rate of the memory cell chip. Attached Figure Description

[0019] One or more embodiments are illustrated by way of example with reference to the accompanying drawings. These illustrations do not constitute a limitation on the embodiments, and unless otherwise stated, the figures in the drawings are not to be limited by scale.

[0020] Figure 1 provides a schematic diagram of the structural arrangement of two chips in a three-dimensional memory.

[0021] Figure 2 is a schematic diagram of the structure of a memory provided in an embodiment of this disclosure;

[0022] Figure 3 is a schematic diagram of the layout of a partial structure of a first chip provided in an embodiment of this disclosure;

[0023] Figure 4 is a magnified view of the details of a single sub-word line gating circuit in Figure 3;

[0024] Figure 5 is a three-dimensional view of the sub-word line gating circuit in Figure 3;

[0025] Figure 6 is a schematic diagram of the layout of a partial structure of another first chip provided in an embodiment of this disclosure;

[0026] Figure 7 is a magnified view of the details of a single sub-word line gating circuit in Figure 6;

[0027] Figure 8 is a three-dimensional view of the sub-word line gating circuit in Figure 6;

[0028] Figure 9 is a schematic diagram of the structural arrangement of two chips in a three-dimensional memory provided in an embodiment of this disclosure. Detailed Implementation

[0029] Hereinafter, exemplary embodiments of the invention will be described in detail with reference to the accompanying drawings, enabling those skilled in the art to readily practice the invention. As will be appreciated by those skilled in the art, the described embodiments can be modified in various ways without departing from the spirit or scope of the invention. For example, the exemplary embodiments provided herein are thought to be implementable by combining them, in whole or in part. Specifically, an element described in a particular exemplary embodiment, even if not described in another exemplary embodiment, can be understood as a description relating to another exemplary embodiment, unless a contrary or contradictory description is provided therein.

[0030] Figure 1 provides a schematic diagram of the structural arrangement of two chips in a three-dimensional memory. As shown in the background art, in the three-dimensional memory, the memory cell is located on one chip (shown as an array wafer in Figure 1), and the peripheral circuit is located on another chip (shown as a circuit wafer in Figure 1). Since the memory cell requires a sub-word line driver (SWD), and the data read from the memory cell needs to be amplified by a sense amplifier (SA) before output, the sense amplifier and sub-word line driver need to be placed directly above the memory pad (shown as MAT in Figure 1) and the staircase (shown as a staircase in Figure 1). Then, the bit lines and word lines are electrically led out through hybrid bonding of bit lines (shown as BL HB in Figure 1) and word lines (shown as WL HB in Figure 1). This structure results in a wasted area in the peripheral circuit chip (the blank area between SA and SA in Figure 1), and the utilization rate of the peripheral circuit chip is not high. Furthermore, the sub-word line driver uses a traditional three-transistor structure to drive the sub-word line, which occupies a relatively large chip area.

[0031] This application provides a memory comprising a stacked first chip and a second chip. The first chip has multiple memory cells formed on it; the second chip has peripheral circuitry formed on it; and the first chip also has multiple sub-word line selection circuits, each of which selects a corresponding sub-word line. By placing the sub-word line selection circuits on the memory cell chip, the driving of the memory cell word lines is achieved on the memory cell chip, thereby reducing the area of ​​the peripheral circuitry chip and allowing for a more rational arrangement of the circuit structure on the peripheral circuitry chip, thus improving integration density. Furthermore, due to the specific circuit design, location, and connection design of the sub-word line selection circuits, the number of steps and transistors in the sub-word line selection circuits is reduced based on the correct selection of sub-word lines, improving the area utilization rate of the memory cell chip.

[0032] The embodiments of this application will be described in more detail below with reference to the accompanying drawings.

[0033] Figure 2 is a schematic diagram of a memory structure provided in an embodiment of this disclosure. Referring to Figure 2, a memory 1 includes a first chip 10 and a second chip 20 stacked along a first direction Z; wherein,

[0034] A plurality of memory cells are formed on the first chip 10, and the memory cells are driven by corresponding sub-word lines;

[0035] The second chip 20 has peripheral circuitry formed on it;

[0036] The first chip 10 also has a plurality of sub-word line selection circuits 100, each of which is used to select the corresponding sub-word line.

[0037] Multiple memory cells on the first chip 10 can be arranged in an array. Each memory cell in the array is connected to a word line and a bit line, and is driven by the corresponding word line and the corresponding bit line. In the field of three-dimensional memory, word lines can be divided into common word lines (CWL) and local word lines (LWL). A common word line is connected to multiple local word lines through multiple local word line select transistors. Bit lines can be divided into common bit lines (CBL) and local bit lines (LBL). A common bit line is connected to multiple local bit lines through multiple local bit line select transistors. In this technology, each memory cell is connected to a local word line and a local bit line, and is driven by the corresponding local word line and the local bit line, thereby opening the memory cell.

[0038] Peripheral circuits are formed on the second chip 20, thereby forming a memory array on the first chip and a CMOS circuit on the second chip. The peripheral circuits include CMOS logic circuits such as row decoders, column decoders, sense amplifiers, data input / output circuits, clock generation circuits, and delay-locked loops.

[0039] The first chip 10 also has a plurality of sub-word line selection circuits 100, each sub-word line selection circuit 100 being used to select the corresponding sub-word line, thereby driving the corresponding sub-word line and enabling the memory unit on the corresponding sub-word line.

[0040] In some embodiments, a sub-word line gating circuit 100 is used to drive one sub-word line connected thereto. In other embodiments, a sub-word line gating circuit 100 may also connect two or four sub-word lines, thereby driving two or four sub-word lines, thus realizing the multiplexing of the sub-word line gating circuit and reducing the area of ​​the sub-word line gating circuit. In other embodiments, the sub-word line gating circuit may also drive other numbers of sub-word lines, which is not limited in this application.

[0041] In some embodiments, in response to the sub-word line gating circuit 100 being formed on the first chip, the line decoder may also be partially formed on the first chip 10 to reduce the path of the input signal of the sub-word line gating circuit and improve the driving capability of the sub-word line gating circuit.

[0042] Therefore, by placing the sub-word line selection circuit on the first chip containing the memory cell array, the sub-word line selection circuit is placed closer to the memory cell it drives, thereby improving its driving capability. Furthermore, since the sub-word line selection circuit is located on the first chip, the corresponding space on the second chip is freed up. This freed-up space can be used to house other peripheral circuits, thus reducing chip area and increasing integration density.

[0043] In some embodiments, the memory can be dynamic random access memory (DRAM), and correspondingly, the memory cell can include a gating transistor and a capacitor. In other embodiments, the memory cell of the DRAM memory can also be a 2T0C structure (i.e., dual-transistor zero-capacitor DRAM) or a 1T0C (i.e., single-transistor zero-capacitor DRAM). The following example uses the conventional 1T1C structure, that is, the DRAM memory cell includes a transistor and a capacitor.

[0044] A memory cell may include a gate transistor, and a portion of the sub-word line may serve as the gate of the gate transistor. For example, in a DRAM memory with a 1T1C memory cell, the gate transistor is 1T in 1T1C, where 1T can be a MOS transistor, and its gate is driven by the sub-word line. During fabrication, multiple memory cells can be mounted on a single word line; that is, a single sub-word line serves as the gate of multiple memory cells, or a portion of a sub-word line serves as the gate of a gate transistor.

[0045] Therefore, the corresponding sub-word line can be selected by the sub-word line driving circuit, thereby selecting the corresponding memory cell for data reading and writing.

[0046] In some embodiments, the first chip 10 may be provided with multiple layers of memory stacked along the first direction Z. Each memory layer is provided with multiple memory array tiles (MATs). The multiple memory array tiles are arranged along the second direction Y. The multiple memory array tiles include a first memory array tile MAT1 and a second memory array tile MAT2 that are adjacent along the second direction Y. Multiple sub-word line gating circuits 100 are disposed between the first memory array tile MAT1 and the second memory array tile MAT2. The second direction Y is perpendicular to the first direction Z.

[0047] By placing the sub-word line gating circuit between the first and second storage pads, the sub-word line gating circuit is closer to the sub-word lines, the path is shorter, the driving capability loss on the path is lower, and the first and second storage pads can share the sub-word line gating circuit, saving circuit area.

[0048] Furthermore, since the sub-word line driver SWD is driven by the sub-word line selection circuit, it drives only one corresponding sub-word line LWL in sequence. Compared with the structure of the prior art, the load of resistors and capacitors is reduced. Therefore, more memory cells can be connected on a single sub-word line LWL.

[0049] Figure 3 is a schematic diagram of the layout of a partial structure of a first chip provided in an embodiment of this disclosure. Figure 3 illustrates the layout and specific structure of the first storage pad MAT1, multiple sub-word line gating circuits 100, and the second storage pad MAT2. Figure 3 is a top view. Figure 4 is a detailed enlarged view of a single sub-word line gating circuit in Figure 3.

[0050] Referring to Figure 4, the sub-word line selection circuit 100 includes a first transistor (illustrated as PMOS) and a second transistor (illustrated as NMOS). The gates of the first transistor and the second transistor are electrically connected and receive a second selection signal Sel2. Since there are multiple sub-word lines and sub-word line selection circuits on the first chip, correspondingly, multiple second selection signals are also provided. For one sub-word line selection circuit and its received second selection signal, Sel2... <n>Example. The drains of the first and second transistors are electrically connected to the sub-word line LWL, as shown in Figure 4. The drain regions of the first and second transistors can be directly connected to the corresponding sub-word lines. The source of the first transistor (PMOS) receives the first selection signal Sel1. Since there are multiple sub-word lines and sub-word line selection circuits on the first chip, there are also multiple first selection signals. For one sub-word line selection circuit and its received first selection signal, Sel1... <m>Example. Where m and n are positive integers. The source of the second transistor (NMOS) receives the first power supply signal Vss. For NMOS, the first power supply signal is a low-level signal, for example, it can be ground; the first power supply signal can also be a negative voltage, for example, -0.2V. For different process nodes and products, the negative voltage can be other values. In Figure 4, the gates of the NMOS transistor and the PMOS transistor are electrically connected, receiving the second selection signal Sel2. <n>The active region is located below the gate.

[0051] The first and second selection signals can be generated by the row decoder decoding the address. The row decoder obtains the first and second selection signals by decoding the address, and uses these signals to determine the address of one sub-word line (as mentioned earlier, in other embodiments, it could also be two or four sub-word lines), thereby activating the corresponding sub-word line in the memory array. The first selection signal can be a phase selector, and the second selection signal can be a group selector. The sub-word line driver selects the corresponding sub-word line by receiving the first and second selection signals obtained from the row decoder.

[0052] Because the sub-word line gating circuit is located on the first chip, its path to the memory cell is shorter, resulting in lower drive capability loss along the path. Therefore, the sub-word line gating circuit can use only two transistors. Compared to the existing structure with three or 2.5 transistors, this saves more area.

[0053] In some embodiments, each of the memory pads includes a plurality of memory cells arranged in a second direction Y and a third direction X array, and the gates of a column of memory cells arranged in the second direction Y share a sub-word line;

[0054] The source of the first transistor PMOS of the multiple sub-word line gating circuits between the first storage pad MAT1 and the second storage pad MAT2 is electrically connected.

[0055] Wherein, the third direction X is perpendicular to the first direction Z and perpendicular to the second direction Y.

[0056] Referring again to Figure 3, taking the first memory pad MAT1 as an example, MAT1 includes multiple memory cells arranged in an array along the second direction Y and the third direction X. Each memory cell includes a capacitor Cap and a gate transistor (not shown in Figure 3). One end of the gate transistor is connected to the sub-bit line LBL, and the other end is connected to the capacitor Cap. The control terminal of the gate transistor is connected to the sub-word line LWL. The gates of a column of memory cells arranged along the second direction Y share a sub-word line. That is, a sub-word line LWL extends along the second direction Y as the gate of the gate transistor of the multiple memory cells.

[0057] The sources of the first transistors (PMOS) of the multiple sub-word line gating circuits between the first storage pad MAT1 and the second storage pad MAT2 are electrically connected and receive the same first selection signal Sel1. <m>In the example of Figure 3, the sources of the first transistor PMOS in all sub-word line gating circuits between the first storage pad MAT1 and the second storage pad MAT2 are electrically connected and connected through the first winding structure R1. That is, for two adjacent storage pads MAT1 and MAT2 in a storage layer, they receive the same first selection signal Sel1. <m>Through a first selection signal Sel1 <m>You can select two adjacent MATs in a storage layer.

[0058] Referring again to Figure 3, adjacent sub-word lines LWL in the same storage pad MAT1 are connected to different sub-word line gating circuits; and for different sub-word line gating circuits, the second selection signal Sel2 they receive... <n>Different. For example, in Figure 3, along the third direction X, for different sub-word line gating circuits, the received second selection signal Sel2 is different. <n>Sel2 <0> Sel2 <1> Sel2 <2> Sel2 <3> ...Sel2 <n-4>、Sel2 <n-3>、Sel2 <n-2>、Sel2 <n-1>.

[0059] Therefore, within the same memory layer, adjacent first and second memory pads can share the same first selection signal through a first winding structure, allowing all sub-word line gating circuits to share the same first selection signal. Furthermore, the second selection signal of each sub-word line gating circuit differs, enabling the opening and closing of the sub-word line LWL. Specifically, the second selection signal controls the switching of the first and second transistors, determining which group of sub-word lines LWL is connected to the corresponding first selection signal. Then, by selecting which layer's first selection signal to enable, the sub-word line LWL of that layer is turned on, while other layers' sub-word line LWLs remain off. Sub-word line LWLs whose second selection signal is not enabled are connected to a low-level voltage Vss, thus remaining off. At this time, sub-bit lines LBL on different sub-word lines LWLs can be connected to the same common bit line CBL through bit line gating transistors, sharing a single sensing amplifier on the second chip.

[0060] Therefore, the switching function of the sub-word line LWL is realized by using two transistors (the first transistor PMOS and the second transistor NMOS) and two selection signals (the first selection signal and the second selection signal).

[0061] Furthermore, for adjacent first storage pads MAT1 and second storage pads MAT2, the second selection signals at corresponding positions are the same. Thus, a sub-word line address can simultaneously enable one sub-word line LWL in the first storage pad MAT1 and one sub-word line LWL in the second storage pad MAT2. With the same number of addresses, the storage capacity and the amount of data read and written at one time can be increased.

[0062] Referring again to Figure 3, multiple staircases are formed between the first storage pad MAT1 and the second storage pad MAT2. The first winding structure R1 of each storage layer is electrically connected to a staircase to lead out the first winding structure R1 of each layer for electrical connection; the first winding structure R1 of different storage layers is electrically connected to different staircases.

[0063] Specifically, steps are set inside the first winding structure R1, and each step is connected to the corresponding first winding structure R1 of each memory layer. In the embodiment of Figure 3, there are 80 memory layers, and correspondingly, 80 steps are set (not fully shown in Figure 3). Multiple sub-word line selection circuits of each memory layer are connected to the corresponding first selection signal Sel1<79:0> through the first winding structure R1. The memory layer is led out through the corresponding step, and then each memory layer is led out through the upper metal trace structure on the top of the first chip, and electrically connected to the second chip through hybrid bonding.

[0064] Therefore, by using the steps, the first selection signal of different layers can be controlled to determine which layer's sub-word line LWL is open, while the sub-word lines LWL of other layers are closed.

[0065] Figure 3 is a top view, thus showing multiple steps. For a single storage layer, it is electrically connected to only one step.

[0066] Figure 5 is a three-dimensional perspective view of the sub-word line gating circuit corresponding to Figures 3 and 4. Referring to Figure 5, the sub-word line gating circuit is located in different memory layers. For example, for the m-th layer, the source of the first transistor in the sub-word line gating circuit is connected to the first winding structure, and the first winding structure receives the corresponding first selection signal Sel1. <m>The corresponding first selection signal Sel1 <m>Gating. Multiple memory layers can be connected to a common conductor structure so that the source of the second transistor (NMOS) receives the first power supply voltage signal Vss. Corresponding sub-word line gating circuits in different layers can be connected to the same conductor structure so that the gates of the first transistor (PMOS) and the second transistor (NMOS) can receive the same second selection signal Sel2. <n>In Figure 5, the conductor structure for applying the gate voltage to the active region is located on both sides of the active region along the second direction Y.

[0067] Figures 6-8 illustrate another embodiment of the sub-word line gating circuit of this disclosure. The similarities to those in Figures 3-5 will not be repeated. Figure 6 is a schematic layout diagram of a partial structure of a first chip provided in an embodiment of this disclosure. Figure 6 illustrates the layout and specific structure of the first storage pad MAT1, multiple sub-word line gating circuits 100, and the second storage pad MAT2, as well as their connection relationships. Figure 6 is a top view. Figure 7 is a detailed enlarged view of a single sub-word line gating circuit in Figure 6. Figure 8 is a three-dimensional schematic diagram of the lead-out relationship of the sub-word line gating circuits in a multi-layer memory layer.

[0068] Referring to Figures 6-7, each storage pad includes multiple storage cells arranged in a second direction Y and a third direction X. The gates of a column of storage cells arranged in the second direction Y share a sub-word line LWL. The gates of the first transistors PMOS of the multiple sub-word line gating circuits of the first storage pad MAT1 and the second storage pad MAT2 are electrically connected and configured to receive a second selection signal Sel. <n>Wherein, the third direction X is perpendicular to the first direction Z and perpendicular to the second direction Y. The gates of the first transistors of the multiple sub-word line gating circuits between the first storage pad MAT1 and the second storage pad MAT2 are connected through the second winding structure R2; multiple steps are also formed between the first storage pad MAT1 and the second storage pad MAT2, and the second winding structure of each storage layer is electrically connected to one step; the second winding structures of different storage layers are electrically connected to different steps.

[0069] Specifically, referring to Figure 7, unlike Figure 4, the gates of the two interconnected transistors in the sub-word gating circuit are led out and connected to the step. For a more detailed structure, refer to Figure 6.

[0070] The gates of the first PMOS and second NMOS transistors in the multiple sub-word line gating circuits between the first storage pad MAT1 and the second storage pad MAT2 are electrically connected together and receive the same second selection signal Sel2. <n>In the example of Figure 6, the gates of the first transistor PMOS in all sub-word line gating circuits between the first storage pad MAT1 and the second storage pad MAT2 are electrically connected and connected via the second winding structure R2. That is, for two adjacent storage pads MAT1 and MAT2 in one storage layer, they receive the same second selection signal Sel2. <n>Through a second selection signal Sel2 <n>You can select two adjacent MATs in a storage layer.

[0071] Referring again to Figure 6, adjacent sub-word lines LWL in the same storage pad MAT1 are connected to different sub-word line gating circuits; and for different sub-word line gating circuits, the first selection signal Sel1 they receive is... <m>Different. For example, in Figure 6, along the third direction X, for different sub-word line gating circuits, the first selection signal Sel1 received is different. <m>Sel1 <0> Sel1 <1> Sel1 <2> Sel1 <3> ...Sel1 <n-4>、Sel1 <n-3>、Sel1 <n-2>、Sel1 <n-1>.

[0072] Therefore, within the same memory layer, adjacent first and second memory pads can share the same second selection signal through the second winding structure R2, and the opening and closing functions of the sub-word line LWL are achieved by using different first selection signals for each sub-word line selection circuit. Specifically, the second selection signal controls the switching of the first and second transistors to determine which layer's sub-word line LWL is connected to the corresponding first selection signal. Then, the vertically controlled first selection signal determines which group of sub-word line LWLs is turned on, while other groups are turned off. Sub-word line LWLs that are not turned on by the first selection signal are connected to a low-level voltage Vss, thus being in a closed state. At this time, the sub-bit lines LBL on different sub-word lines LWLs can be connected to the same common bit line CBL through bit line selection transistors, sharing a sense amplifier on the second chip.

[0073] Therefore, the switching function of the sub-word line LWL is realized by using two transistors (the first transistor PMOS and the second transistor NMOS) and two selection signals (the first selection signal and the second selection signal).

[0074] Furthermore, for adjacent first storage pads MAT1 and second storage pads MAT2, the first selection signal at the corresponding position is the same. Thus, a sub-word line address can simultaneously enable one sub-word line LWL in the first storage pad MAT1 and one sub-word line LWL in the second storage pad MAT2. With the same number of addresses, the storage capacity and the amount of data read and written at one time can be increased.

[0075] Referring again to Figure 6, steps are set inside the second winding structure R2, and each step is connected to the corresponding second winding structure R2 of each memory layer. In the embodiment of Figure 6, there are 80 memory layers, and correspondingly, 80 steps are set (not fully shown in Figure 6). Multiple sub-word line selection circuits of each memory layer are connected to the corresponding second selection signal Sel2<79:0> through the second winding structure R2. The memory layer is led out through a corresponding step, and then each memory layer is led out through the upper metal trace structure on the top of the first chip, and electrically connected to the second chip through hybrid bonding.

[0076] Therefore, by using the steps, the second selection signal of different layers can be controlled to determine which layer's sub-word line LWL is open, while the sub-word lines LWL of other layers are closed.

[0077] Figure 6 is a top view, thus showing multiple steps. For a single storage layer, it is electrically connected to only one step.

[0078] Figure 8 is a three-dimensional perspective view of the sub-word line gating circuit corresponding to Figures 6 and 7. Referring to Figure 8, the sub-word line gating circuit is located in different memory layers. For example, for the nth layer, the gate of the first transistor (PMOS) of the sub-word line gating circuit is connected to the second winding structure, and the second winding structure receives the corresponding second selection signal Sel2. <n>The corresponding second selection signal Sel2 <n>Gating. Multiple memory layers can be connected to a common conductor structure so that the source of the second transistor (NMOS) receives the first power supply voltage signal Vss. Corresponding sub-word line gating circuits in different layers can be connected to the same conductor structure so that the source of the first transistor (PMOS) can receive the same first selection signal Sel1. <m>In Figure 8, the conductor structure for applying the gate voltage to the active region is located on both sides of the active region along the first direction Z.

[0079] Figure 9 shows a schematic diagram of the structural arrangement of two chips in a three-dimensional memory according to an embodiment of this disclosure. The embodiments in Figures 3 and 6 are enlarged views of the first storage pad MAT1, the second storage pad MAT2, and the staircase between them in Figure 9. As shown in Figure 9, the three-dimensional memory includes a first chip 10 on which a storage cell array and a staircase are formed; and a second chip 20 on which a sense amplifier SA and peripheral circuits, such as row decoders, column decoders, input / output circuits, etc., are formed. Multiple storage layers are formed on the first chip, and multiple storage pads are formed in each storage layer. The multiple storage pads include a first storage pad MAT1, a second storage pad MAT2, a third storage pad MAT3, and a fourth storage pad MAT4. The first storage pad, multiple sub-word line gating circuits, the second storage pad, the third storage pad, the multiple sub-word line gating circuits, and the fourth storage pad are arranged sequentially along a second direction.

[0080] By adopting the aforementioned sub-word line gating circuit structure and the winding, step, and other structures and layouts, adjacent memory pads can share a single set of sub-word line gating circuits. That is, two memory pads can use only one set of sub-word line gating circuits and steps (as shown in Figure 9, no sub-word line gating circuits or steps are needed between the second and third memory pads), greatly saving the area occupied by the sub-word line gating circuits and steps. Furthermore, since adjacent memory pads share the intermediate step, there is no need to specifically set steps for memory pads located at the edge of the memory layer, thus solving the problem of edge memory pads. Also, as shown in Figure 9, since the space on the second chip where the sub-word line driver (SWD) circuit was originally placed is now freed up, it can be used to place other peripheral circuits.

[0081] This invention is not limited to this; more than four memory pads can be formed on each memory layer. This embodiment only uses four memory pads as an example. When there are more than four memory pads, every two adjacent memory pads can share a sub-word line gating circuit, and only half the number of sub-word line gating circuits are needed to drive all memory pads.

[0082] Referring again to Figure 9, the bit lines on the first chip 10 can be led out via hybrid bonding BL HB after the metal layer is traced, thereby connecting to the sense amplifier SA on the second chip 20. The word lines on the first chip 10 can be led out to the top of the first chip 10 via step electrical leads, and then connected to the peripheral circuitry (such as a line decoder) on the second chip via hybrid bonding WL Ctrl HB at the top of the first chip 10, thereby driving the signal.

[0083] Referring again to Figures 3 and 6, each storage pad includes multiple storage cells arranged in an array along the second direction Y and the third direction X. The gates of a column of storage cells arranged along the second direction Y share a sub-word line LWL. Each row of storage cells in two adjacent columns along the third direction X shares a sub-bit line LBL (shown as a ring in Figures 3 and 6). Multiple sub-bit lines LBL of a row of storage cells arranged along the third direction X are connected to the same common bit line CBL (shown as a line segment in Figures 3 and 6). The third direction X is perpendicular to the first direction Z and perpendicular to the second direction Y.

[0084] Therefore, the use of sub-word line LWL, sub-bit line LBL, common bit line CBL, and common word line CWL can make the opening of bit lines and word lines more flexible and reduce the resistance-capacitance load (RC loading).

[0085] Those skilled in the art will understand that the above-described embodiments are specific examples of implementing this application, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of this application. Any person skilled in the art can make their own modifications and alterations without departing from the spirit and scope of this application; therefore, the scope of protection of this application should be determined by the scope defined in the claims.< / m> < / n> < / n> < / m> < / m> < / n> < / n> < / n> < / n> < / n> < / m> < / m> < / n> < / n> < / m> < / m> < / m> < / n> < / m> < / n>

Claims

1. A memory, characterized in that, Includes a first chip and a second chip stacked along a first direction; wherein, Multiple memory cells are formed on the first chip, and each memory cell is driven by a corresponding sub-word line; The second chip has peripheral circuitry formed on it; The first chip also has multiple sub-word line selection circuits, each of which is used to select the corresponding sub-word line.

2. The memory according to claim 1, characterized in that, The memory cell includes a gate transistor, so a portion of the subword line serves as the gate of the gate transistor.

3. The memory according to claim 1, characterized in that, The first chip has multiple memory layers stacked along a first direction. Each memory layer has multiple memory pads. The multiple memory pads include a first memory pad and a second memory pad that are adjacent along a second direction. Multiple sub-word line selection circuits are disposed between the first memory pad and the second memory pad. The second direction is perpendicular to the first direction.

4. The memory according to claim 3, characterized in that, The sub-word line gating circuit includes a first transistor and a second transistor; The gates of the first transistor and the second transistor are electrically connected, the drains of the first transistor and the second transistor are electrically connected to the sub-word line, the source of the first transistor is configured to receive a first selection signal, and the source of the second transistor is configured to receive a first power supply signal.

5. The memory according to claim 4, characterized in that, Each of the aforementioned storage pads includes a plurality of storage cells arranged in an array along a second direction and a third direction, wherein the gates of a column of storage cells arranged along the second direction share a common subword line; The source of the first transistor of the plurality of sub-word line gating circuits between the first storage pad and the second storage pad is electrically connected; Wherein, the third direction is perpendicular to the first direction and perpendicular to the second direction.

6. The memory according to claim 5, characterized in that, The sources of the first transistors in the multiple sub-word line gating circuits between the first storage pad and the second storage pad are connected through a first winding structure; Multiple steps are formed between the first storage pad and the second storage pad, and the first winding structure of each storage layer is electrically connected to one step; the first winding structures of different storage layers are electrically connected to different steps.

7. The memory according to claim 4, characterized in that, Each of the aforementioned storage pads includes a plurality of storage cells arranged in an array along a second direction and a third direction, wherein the gates of a column of storage cells arranged along the second direction share a common subword line; The gates of the first transistors in the plurality of sub-word line gating circuits between the first storage pad and the second storage pad are electrically connected and configured to receive a second selection signal; Wherein, the third direction is perpendicular to the first direction and perpendicular to the second direction.

8. The memory according to claim 7, characterized in that, The gates of the first transistors in the plurality of sub-word line gating circuits between the first storage pad and the second storage pad are connected through a second winding structure; Multiple steps are formed between the first storage pad and the second storage pad, and the second winding structure of each storage layer is electrically connected to one step; the second winding structures of different storage layers are electrically connected to different steps.

9. The memory according to claim 3, characterized in that, The plurality of storage pads also include a third storage pad and a fourth storage pad, wherein the first storage pad, the plurality of sub-word line gating circuits, the second storage pad, the third storage pad, the plurality of sub-word line gating circuits, and the fourth storage pad are arranged sequentially along the second direction.

10. The memory according to claim 3, characterized in that, Each storage pad includes multiple storage cells arranged in an array along the second direction and the third direction, and the gates of a column of storage cells arranged along the second direction share a sub-word line; Each row of storage cells in two adjacent columns along the third direction shares a sub-bit line; Multiple sub-bit lines of a row of memory cells arranged along a third direction are connected to the same common bit line; Wherein, the third direction is perpendicular to the first direction and perpendicular to the second direction.

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