Display panel

Abstract

A display panel. The display panel comprises a first active area (AA1), a second active area (AA2), and a first non-active area (NAA1), wherein in a first direction (X), the first non-active area (NAA1) is located on at least one side of the first active area (AA1), and the first active area (AA1) and the second active area (AA2) are arranged in a second direction (Y), the first direction (X) intersecting the second direction (Y). The display panel comprises: at least one first signal line (S1) and at least one row of first pixels (P1), which first signal line (S1) and first pixels (P1) are located in the first active area (AA1), wherein the first signal line (S1) extends along the first direction (X), and the first signal line (S1) is connected to one row of first pixels (P1); at least one second signal line (S2) and at least one row of second pixels (P2), which second signal line (S2) and second pixels (P2) are located in the second active area (AA2), wherein the second signal line (S2) extends along the first direction (X), and the second signal line (S2) is connected to one row of second pixels (P2), the number of first pixels (P1) arranged in the first direction (X) being less than the number of second pixels (P2) arranged in the first direction (X); and at least one compensation capacitor (C1), which is located in the first non-active area (NAA1), wherein the compensation capacitor (C1) is connected to the first signal line (S1).

Description

Display panel

[0001] This application claims priority to Chinese Patent Application No. 202411718428.X, filed with the Chinese Patent Office on November 27, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of display technology, such as a display panel. Background Technology

[0003] When the display panel is irregularly shaped, the signal lines connected to different pixels are of different lengths, resulting in different load values ​​for different signal lines. This leads to brightness differences among different pixels and reduces the display effect of the display panel. Summary of the Invention

[0004] This application provides a display panel to improve the brightness difference of the display panel and enhance the display effect of the display panel.

[0005] In a first aspect, embodiments of this application provide a display panel, including a first display area, a second display area, and a first non-display area; along a first direction, the first non-display area is located on at least one side of the first display area, and the first display area and the second display area are arranged along a second direction, the first direction intersecting the second direction; the display panel includes:

[0006] The first signal line is located in the first display area and the first pixel is located in the first row; the first signal line extends along the first direction and is connected to the first pixel in the row.

[0007] The second display area has at least one second signal line and at least one row of second pixels; the second signal line extends along the first direction and is connected to a row of second pixels; the number of first pixels arranged along the first direction is less than the number of second pixels arranged along the first direction.

[0008] At least one compensation capacitor is located in the first non-display area, and the compensation capacitor is connected to the first signal line.

[0009] Secondly, embodiments of this application also provide a display panel, including a first display area, a second display area, and a first non-display area; along a first direction, the first non-display area is located on at least one side of the first display area, the first display area and the second display area are arranged along a second direction, and the first direction intersects the second direction; the display panel includes:

[0010] The first signal line is located in the first display area and the first pixel is located in the first row; the first signal line extends along the first direction and is connected to the first pixel in the row.

[0011] The second display area has at least one second signal line and at least one row of second pixels; the second signal line extends along the first direction and is connected to a row of second pixels; the number of first pixels arranged along the first direction is less than the number of second pixels arranged along the first direction.

[0012] Multiple cascaded gate driving circuits are provided; the gate driving circuits are disposed in the first non-display area; the gate driving circuits include a first capacitor; the first capacitor is connected to the first signal line or the second signal line; the capacitance value of the first capacitor connected to the first signal line is greater than the capacitance value of the first capacitor connected to the second signal line. Attached Figure Description

[0013] Figure 1 is a schematic diagram of the structure of a display panel provided in an embodiment of this application;

[0014] Figure 2 is a partial structural diagram of a display panel in the first non-display area according to an embodiment of this application;

[0015] Figure 3 is a partial structural diagram of a display panel in the first non-display area according to an embodiment of this application;

[0016] Figure 4 is a partial cross-sectional view of another display panel provided in the first non-display area according to an embodiment of this application;

[0017] Figure 5 is a partial cross-sectional view of another display panel provided in the first non-display area according to an embodiment of this application;

[0018] Figure 6 is a partial cross-sectional view of another display panel provided in the first non-display area according to an embodiment of this application;

[0019] Figure 7 is a schematic diagram of another display panel provided in an embodiment of this application;

[0020] Figure 8 is a schematic diagram of another display panel provided in an embodiment of this application;

[0021] Figure 9 is a schematic diagram of a gate driving circuit provided in an embodiment of this application;

[0022] Figure 10 is a partial structural schematic diagram of a first gate driving circuit provided in an embodiment of this application;

[0023] Figure 11 is a partial structural schematic diagram of a second gate driving circuit provided in an embodiment of this application;

[0024] Figure 12 is a schematic diagram of another first gate driving circuit provided in an embodiment of this application;

[0025] Figure 13 is a partial structural schematic diagram of another first gate driving circuit provided in an embodiment of this application;

[0026] Figure 14 is a schematic diagram of the cross-sectional structure of a first capacitor obtained by cutting along AA' according to an embodiment of this application;

[0027] Figure 15 is a schematic diagram of another display panel provided in an embodiment of this application;

[0028] Figure 16 is a schematic diagram of the structure of a display device provided in an embodiment of this application. Detailed Implementation

[0029] The present application will now be described in detail with reference to the accompanying drawings and embodiments. The specific embodiments described herein are merely illustrative of the present application. For ease of description, only the parts relevant to the present application are shown in the drawings, not the entire structure.

[0030] The display panel comprises multiple pixels, each pixel including a display element and pixel circuitry. The pixel circuitry is connected to the display element and drives it to display content. Scan signal lines are provided on the display panel to provide scan signals to a row of pixels. When the display panel has an irregular display area, at least two rows may have different numbers of pixels, and / or at least two scan signal lines may have different lengths, resulting in different load values ​​for the different scan signal lines. When the scan signal lines provide scan signals to the pixels, the scan signals received by pixels in different rows differ, leading to brightness differences between pixels in different rows and reducing the display panel's display quality.

[0031] To address the aforementioned technical problems, this application provides a display panel. Figure 1 is a schematic diagram of the structure of a display panel provided in this application embodiment. As shown in Figure 1, the display panel includes a first display area AA1, a second display area AA2, and a first non-display area NAA1; along the first direction X, the first non-display area NAA1 is located on one side of the first display area AA1, and the first display area AA1 and the second display area AA2 are arranged along the second direction Y; the first direction X intersects the second direction Y; the display panel includes:

[0032] At least one first signal line S1 and at least one row of first pixels P1 are located in the first display area AA1; the first signal line S1 extends along the first direction X and is connected to the row of first pixels P1.

[0033] The second display area AA2 has at least one second signal line S2 and at least one row of second pixels P2; the second signal line S2 extends along the first direction X and is connected to the row of second pixels P2; the number of first pixels P1 arranged along the first direction X is less than the number of second pixels P2 arranged along the first direction X.

[0034] At least one compensation capacitor C1 is located in the first non-display area NAA1, and the compensation capacitor C1 is connected to the first signal line S1.

[0035] In some embodiments, when the display panel has an irregular display area, the number of pixels in at least two rows is different. For example, Figure 1 illustrates a display panel with a notch, such that a first display area AA1 is divided into a first sub-area AA11 and a second sub-area AA12 arranged along a first direction X. A first pixel P1 can be distributed within the first sub-area AA11 and the second sub-area AA12. In this case, the number of pixels in a row in the first display area AA1 is the sum of the number of first pixels P1 in a row in the first sub-area AA11 and the number of first pixels P1 in a row in the second sub-area AA12. A first signal line S1 can be connected to both a row of first pixels P1 in the first sub-area AA11 and a row of first pixels P1 in the second sub-area AA12, providing a scan signal for a row of first pixels P1 in the first display area AA1. A second signal line S2 can be connected to a row of second pixels P2, providing a scan signal for a row of second pixels P2 in the second display area AA2. The second display area AA2 is arranged along a second direction Y with the first display area AA1. When a gap is provided between the first sub-region AA11 and the second sub-region AA12, the length of the first display area AA1 that can be used to arrange the first pixel P1 along the first direction X is less than the length of the second display area AA2 that can be used to arrange the second pixel P2 along the first direction X. This results in the number of first pixels P1 arranged being less than the number of second pixels P2 arranged, and the load corresponding to the first signal line S1 being less than the load of the second signal line S2. In other embodiments, the display panel may also provide a hole area in the first display area AA1. Similarly, along the first direction X, the number of first pixels P1 arranged is less than the number of second pixels P2 arranged, resulting in the load corresponding to the first signal line S1 being less than the load of the second signal line S2.

[0036] The display panel may include two first non-display areas NAA1, respectively located on the side of the first sub-area AA11 away from the second sub-area AA12 and on the side of the second sub-area AA12 away from the first sub-area AA11. By setting a compensation capacitor C1 in the first non-display area NAA1, the area requirement of the non-display area between the first sub-area AA11 and the second sub-area AA12 can be avoided. This helps to reduce the wiring space in the non-display area between the first sub-area AA11 and the second sub-area AA12, thus achieving a narrow bezel in irregular display areas.

[0037] Furthermore, the first non-display area NAA1 is located on the side of the first display area AA1 along the first direction X. When the non-display area of ​​the display panel includes a curved edge, the first non-display area NAA1 includes a curved non-display area. By setting a compensation capacitor C1 in the first non-display area NAA1, the bezel area of ​​the display panel can be fully utilized. When the compensation capacitor C1 is connected to the first signal line S1, the compensation capacitor C1 can act as a load for the first signal line S1. That is, by increasing the load of the first signal line S1 through the compensation capacitor C1, the load difference between the first signal line S1 and the second signal line S2 can be reduced. This reduces the brightness difference between the first display area AA1 and the second display area AA2 caused by the load difference between the first signal line S1 and the second signal line S2, improves the brightness consistency between the first display area AA1 and the second display area AA2, and thus improves the display effect of the display panel. For example, the first signal line S1 can extend from the first non-display area NAA1 to the first display area AA1. In the first non-display area NAA1, the compensation capacitor C1 is directly connected to the first signal line S1 as the load of the first signal line S1, which can simplify the wiring of the display panel.

[0038] When the first display area AA1 includes multiple rows of first pixels P1, the display panel includes multiple first signal lines S1. Each first signal line S1 can be connected to a row of first pixels P1 to provide a scanning signal for that row of first pixels P1. At this time, the first non-display area NAA1 is provided with multiple compensation capacitors C1. Each compensation capacitor C1 is connected to one of the first signal lines S1 to increase the load of each first signal line S1, reduce the load difference between the first signal line S1 and the second signal line S2, and improve the display effect of the display panel.

[0039] In this embodiment, by setting a compensation capacitor in the first non-display area, the bezel area of ​​the display panel can be fully utilized. At the same time, the compensation capacitor can increase the load of the first signal line, thereby reducing the load difference between the first signal line and the second signal line, thus reducing the brightness difference between the first display area and the second display area, improving the brightness consistency between the first display area and the second display area, and thus improving the display effect of the display panel.

[0040] Figure 2 is a partial structural diagram of a display panel in the first non-display area NAA1 according to an embodiment of this application. As shown in Figure 2, the display panel also includes a gate driving circuit GIP; the gate driving circuit GIP is disposed in the first non-display area NAA1, and the compensation capacitor C1 is disposed on the side of the gate driving circuit GIP near the first display area AA1; the gate driving circuit GIP is connected to the first signal line S1 and is used to provide a scanning signal for the first signal line S1.

[0041] In some embodiments, the gate drive circuit GIP may include a scan drive circuit disposed in the first non-display area NAA1 and connected to the first signal line S1. The scan drive circuit can be connected to the pixel circuit through the first signal line S1 to provide a scan signal to the pixel circuit. When the compensation capacitor C1 is disposed on the side of the gate drive circuit GIP close to the first display area AA1, it can be disposed on the path connecting the first signal line S1 and the gate drive circuit GIP, thereby simplifying the connection between the compensation capacitor C1 and the first signal line S1 and simplifying the wiring design of the first non-display area NAA1.

[0042] In some embodiments, the display panel further includes a substrate and a driving circuit layer, the driving circuit layer being disposed on the substrate, and the pixel circuit in the first pixel being located in the driving circuit layer; the driving circuit layer includes at least two conductive layers, and the compensation capacitor includes at least two plates, with the at least two plates of the compensation capacitor located in different conductive layers respectively.

[0043] In some embodiments, the driving circuit layer includes at least two conductive layers for forming a pixel circuit. Exemplarily, the pixel circuit includes transistors and storage capacitors. When the transistor is a top-gate transistor, the conductive layers included in the driving circuit layer can be at least two of a semiconductor layer, a first metal layer, a second metal layer, and a third metal layer sequentially stacked on the substrate. The semiconductor layer can form the active region and channel region of the transistor, the first metal layer can form the gate of the transistor, the second metal layer can form the electrode of the storage capacitor, and the third metal layer can form the source and drain of the transistor. The compensation capacitor includes overlapping first and second electrodes, which can be disposed in the same layer as different conductive layers, and the vertical projections of the first and second electrodes on the substrate overlap. An insulating layer between the conductive layers serves as the dielectric layer for forming the compensation capacitor. This avoids the need for additional film layers when forming the compensation capacitor, simplifying the manufacturing process of the display panel. Exemplarily, the materials of the two electrodes of the compensation capacitor can be the same as the materials of the conductive layers disposed in the same layer. When manufacturing a display panel, compensation capacitors can be formed simultaneously with the pixel circuits in the patterned conductive layer, avoiding additional manufacturing processes. For example, when the first electrode of the compensation capacitor is disposed on the same layer as the first metal layer, it can be formed simultaneously with the gate of the transistor in the patterned first metal layer. When the second electrode of the compensation capacitor is disposed on the same layer as the third metal layer, it can be formed simultaneously with the source and drain of the transistor in the patterned third metal layer.

[0044] Figure 3 is a partial cross-sectional view of a display panel in the first non-display area according to an embodiment of this application. As shown in Figure 3, the driving circuit layer includes a first conductive layer M1 and a second conductive layer M2 stacked together. The first conductive layer M1 is disposed on the side of the second conductive layer M2 close to the substrate. The compensation capacitor C1 includes a first electrode C11 and a second electrode C12. The first electrode C11 of the compensation capacitor C1 is located on the first conductive layer M1, and the second electrode C12 of the compensation capacitor C1 is located on the second conductive layer M2. The orthographic projections of the first electrode C11 and the second electrode C12 of the compensation capacitor C1 on the substrate at least partially overlap. The first signal line S1 is connected to the first electrode C11 of the compensation capacitor C1.

[0045] For example, the first conductive layer M1 can be a first metal layer of the driving circuit layer, used to form the gate of the transistor. The second conductive layer M2 can be a second metal layer of the driving circuit layer, used to form the electrode of the storage capacitor. By setting the first electrode C11 of the compensation capacitor C1 to be located in the first conductive layer M1, the space of the first conductive layer M1 can be fully utilized, which is conducive to arranging a large area of ​​the first electrode C11, thereby increasing the capacitance value of the compensation capacitor C1, improving the compensation effect of the compensation capacitor, and thus improving the brightness consistency between the first display area and the second display area.

[0046] In some embodiments, the second plate of the compensation capacitor is configured to be connected to a signal with a constant potential, which can prevent the potential of the second plate of the compensation capacitor from changing, thereby preventing the coupling effect of the compensation capacitor from affecting the scanning signal on the first signal line S1.

[0047] In some embodiments, the second plate of the compensation capacitor is configured to receive a power supply signal or an initialization signal.

[0048] For example, the power signal may include a first power signal and a second power signal. The first power signal transmits a positive power signal, such as +7V, to the pixel circuit. The second power signal is input to the cathode of the display element, such as -7V. The initialization signal is also a fixed potential, used to initialize the gate of the driving transistor in the pixel and the anode of the display element; for example, the initialization signal is 1-3V. By connecting the power signal or the initialization signal to the second plate of the compensation capacitor, the influence of the compensation capacitor on the scanning signal can be avoided, and additional signal transmission lines can be avoided, which simplifies the wiring design of the display panel and the manufacturing process of the display panel. In addition, the power signal has good potential stability. When the power signal is connected to the second plate of the compensation capacitor, the potential stability of the second plate of the compensation capacitor can be improved, thereby reducing the influence of other signals on the scanning signal.

[0049] In addition, when the initialization signal is connected to the second plate of the compensation capacitor, the compensation capacitor can serve as a load for the initialization signal, thereby increasing the voltage stabilizing capacitor of the initialization signal, improving the stability of the initialization signal, and thus improving the display effect of the display panel.

[0050] In some embodiments, referring further to Figures 2 and 3, the second plates C12 of the plurality of compensation capacitors C1 are connected as one unit.

[0051] For example, different first signal lines S1 are connected to the first plates C11 of different compensation capacitors C1 to avoid display panel malfunctions caused by short circuits of different first signal lines S1. At the same time, the second plates C12 of multiple compensation capacitors C1 are connected as one unit. This not only makes full use of the space in the first non-display area NAA1 to arrange the second plates C12 and maximizes the capacitance value of the compensation capacitors C1, but also simplifies the manufacturing process of the second plates C12 of multiple compensation capacitors C1.

[0052] In some embodiments, the second electrode C12 of different compensation capacitors C1 can also be independent electrodes set in the same layer. In this case, different second electrode C12 can be dispersed according to the pattern of the film layer where the second electrode C12 is located, so as to avoid the compensation capacitor C1 occupying a large amount of extra space and improve the space utilization of the first non-display area NAA1.

[0053] Referring again to Figures 2 and 3, the first signal line S1 is located in the first conductive layer M1, extends to the first non-display area NAA1, and includes an overlap portion S11 that at least partially overlaps with the second electrode C12 of the compensation capacitor C1. The overlap portion S11 of the first signal line S1 is multiplexed as the first electrode C11 of the compensation capacitor C1.

[0054] For example, when the first signal line S1 is located in the first conductive layer M1, the overlapping portion S11 of the first signal line S1 can be reused as the first electrode C11 of the compensation capacitor C1. This not only avoids the need to set the first electrode C11 of the compensation capacitor C1 separately, but also avoids the connection between the first electrode C11 and the first signal line S1, simplifying the manufacturing process of the display panel. Moreover, it can make full use of the space of the first conductive layer M1 in the first non-display area NAA1, which is beneficial to increase the capacitance value of the compensation capacitor C1.

[0055] Referring again to Figures 2 and 3, the width of the overlapping portion S11 of the first signal line S1 is greater than the width of the first signal line S1 in the first display area AA1.

[0056] For example, when the overlapping portion S11 of the first signal line S1 is multiplexed as the first plate C11 of the compensation capacitor C1, the width of the overlapping portion S11 can be increased, thereby increasing the area of ​​the first plate C11 of the compensation capacitor C1. This is beneficial to increasing the capacitance value of the compensation capacitor C1, thereby better compensating for the brightness abnormalities of the first display area AA1 and the second display area AA2, and improving the brightness consistency of the display panel.

[0057] Figure 4 is a partial cross-sectional view of another display panel provided in the first non-display area according to an embodiment of this application. As shown in Figure 4, the driving circuit layer further includes a third conductive layer M3, which is disposed on the side of the second conductive layer M2 away from the first conductive layer M1; the compensation capacitor C1 further includes a third electrode C13, which is located on the third conductive layer M3. The third electrode C13 of the compensation capacitor C1 is connected to the first electrode C11 of the compensation capacitor C1. The first signal line S1 extends to the first non-display area NAA1, and the first signal line S1 includes an overlap portion S11 that overlaps at least partially with the second electrode C12 of the compensation capacitor C1. The overlap portion S11 of the first signal line S1 is multiplexed as the third electrode C13 of the compensation capacitor C1.

[0058] For example, the third conductive layer M3 can be the third metal layer of the driving circuit layer, used to form the source and drain of the transistor in the pixel. The first signal line S1 can be disposed on the third conductive layer M3. In this case, the first signal line S1 can be connected to the first electrode C11 of the first conductive layer M1 through a via, so that the compensation capacitor C1 can be used as the load of the first signal line S1, thereby increasing the load of the first signal line S1, reducing the load difference between the first signal line S1 and the second signal line S2, and thus reducing the brightness difference between the first display area AA1 and the second display area AA2. When the overlapping portion S11 of the first signal line S1 is reused as the third electrode C13 of the compensation capacitor C1, the third electrode C13 of the compensation capacitor C1 and the second electrode C12 of the compensation capacitor C1 can form a capacitor, and at the same time, the second electrode C12 of the compensation capacitor C1 and the first electrode C11 of the compensation capacitor C1 can form a capacitor, thereby increasing the capacitance value of the compensation capacitor C1, better compensating for the brightness abnormality of the first display area AA1 and the second display area AA2, and improving the brightness consistency of the display panel.

[0059] Referring again to Figure 4, the display panel also includes a light emission control signal line EM, which is located in the third conductive layer M3.

[0060] For example, the light emission control signal line EM is connected to the light emission control signal input terminal of the pixel circuit to provide a light emission control signal to the pixel circuit. The light emission control signal line EM is located on the third conductive layer M3, which helps to simplify the wiring design of the display panel and avoids short circuits between different signal lines.

[0061] In some embodiments, the display panel may further include a power signal line VDD and an initialization signal line VREF. The power signal line VDD is used to provide a power signal to the pixels, and the initialization signal line VREF is used to provide an initialization signal to the pixels. Figure 4 exemplarily shows the second plate C12 of the compensation capacitor C1 connected to the power signal. In this case, the initialization signal line VREF may be located in the third conductive layer M3. In some embodiments, Figure 5 is a partial cross-sectional view of another display panel provided in the first non-display area according to an embodiment of this application. As shown in Figure 5, the second plate C12 of the compensation capacitor C1 may also be connected to the initialization signal, that is, the second plate C12 of the compensation capacitor C1 is connected to the initialization signal line VREF, thereby increasing the transmission capacitance on the initialization signal line VREF, which can make the potential of the initialization signal on the initialization signal line VREF more stable, thereby improving the effect of pixel circuit initialization and improving display performance. The second plate C12 of the compensation capacitor C1 has a fixed potential, so the second plate C12 of the compensation capacitor C1 can also be reused as a shielding structure to avoid crosstalk problems between signal lines.

[0062] Figure 6 is a partial cross-sectional view of another display panel provided in the first non-display area according to an embodiment of this application. As shown in Figure 6, the driving circuit layer includes a first conductive layer, a second conductive layer M2, a third conductive layer M3, and a fourth conductive layer M4 stacked sequentially. The compensation capacitor C1 includes a first electrode C11 and a second electrode C12. The first electrode C11 of the compensation capacitor C1 is located on the second conductive layer M2, and the second electrode C12 of the compensation capacitor C1 is located on the third conductive layer M3. The orthographic projections of the first electrode C11 and the second electrode C12 of the compensation capacitor C1 on the substrate at least partially overlap. The compensation capacitor C1 also includes a third electrode C13, which is located on the fourth conductive layer M4 and is connected to the first electrode C11 of the compensation capacitor C1. The first signal line S1 extends to the first non-display area NAA1, and the first signal line S1 includes an overlap portion S11 that at least partially overlaps with the second electrode C12 of the compensation capacitor C1. The overlap portion S11 of the first signal line S1 is multiplexed as the third electrode C13 of the compensation capacitor C1.

[0063] Figure 6 illustrates an exemplary film layer configuration for another electrode plate of the compensation capacitor C1. As shown in Figure 6, the first signal line S1 is located on the fourth conductive layer M4, and the first electrode plate C11 of the compensation capacitor C1 is located on the second conductive layer M2 and connected to the first signal line S1 through a via, thus enabling the compensation capacitor C1 to act as a load on the first signal line S1. The orthogonal projections of the first electrode plate C11 and the second electrode plate C12 of the compensation capacitor C1 on the substrate at least partially overlap, allowing the first electrode plate C11 and the second electrode plate C12 of the compensation capacitor C1 to form a capacitor. Simultaneously, the overlapping portion S11 of the first signal line S1 is reused as the third electrode plate C13 of the compensation capacitor C1, allowing the second electrode plate C12 and the third electrode plate C13 of the compensation capacitor C1 to form a capacitor. This increases the capacitance value of the compensation capacitor C1, better compensating for brightness anomalies in the first display area AA1 and the second display area AA2, and improving the brightness consistency of the display panel.

[0064] In some embodiments, the width of the overlapping portion S11 of the first signal line S1 is greater than the width of the first signal line S1 in the first display area AA1.

[0065] For example, when the overlapping portion S11 of the first signal line S1 is reused as the third plate C13 of the compensation capacitor C1, the width of the overlapping portion S11 can be increased, thereby increasing the area of ​​the third plate C13 of the compensation capacitor C1. This is beneficial to increase the capacitance value of the compensation capacitor C1, thereby better compensating for the brightness abnormalities of the first display area AA1 and the second display area AA2, and improving the brightness consistency of the display panel.

[0066] In some embodiments, the second plate of the compensation capacitor is used to connect to a signal with a constant potential, which can prevent the potential of the second plate of the compensation capacitor from changing, thereby preventing the coupling effect of the compensation capacitor from affecting the scanning signal on the first signal line S1.

[0067] In some embodiments, the second plate of the compensation capacitor is used to connect to a power signal or an initialization signal. This not only avoids the influence of the compensation capacitor on the scanning signal, but also avoids the need for additional signal transmission lines, which helps to simplify the wiring design of the display panel and the manufacturing process of the display panel.

[0068] In some embodiments, the display panel further includes a light emission control signal line located in a fourth conductive layer.

[0069] Referring again to Figure 6, the compensation capacitor C1 also includes a fourth plate C14. The fourth plate C14 of the compensation capacitor C1 is connected to the second plate C12 of the compensation capacitor C1. The vertical projection of the fourth plate C14 of the compensation capacitor C1 on the substrate at least partially overlaps with the vertical projection of the first plate C11 on the substrate.

[0070] For example, the vertical projection of the fourth plate C14 of the compensation capacitor C1 onto the substrate at least partially overlaps with the vertical projection of the first plate C11 onto the substrate, forming a capacitor between the fourth plate C14 and the first plate C11 of the compensation capacitor C1. Simultaneously, the first plate C11 of the compensation capacitor C1 is connected to the first signal line S1, so that the capacitor formed by the fourth plate C14 and the first plate C11 is connected to the first signal line S1, thus serving as a load for the first signal line S1 to reduce the load difference between the first signal line S1 and the second signal line S2. In this case, the capacitance between the fourth plate C14 and the first plate C11 of the compensation capacitor C1 increases the capacitance value of the compensation capacitor C1, thereby minimizing the load difference between the first signal line S1 and the second signal line S2. Furthermore, the fourth plate C14 of compensation capacitor C1 is connected to the second plate C12 of compensation capacitor C1. When a constant potential signal is applied to the second plate C12 of compensation capacitor C1, a constant potential signal is also applied to the fourth plate C14 of compensation capacitor C1, making the capacitance between the fourth plate C14 and the first plate C11 of compensation capacitor C1 one of the parallel sub-capacitors of compensation capacitor C1. At the same time, the fourth plate C14 can also be reused as a shielding structure to prevent other signals from affecting the scanning signal provided by the first signal line S1, thereby improving the reliability of the display panel.

[0071] Referring again to Figure 6, the driving circuit layer also includes a semiconductor layer M0, which is disposed on the side of the first conductive layer near the substrate. The fourth electrode C14 is located in the first conductive layer or the semiconductor layer M0.

[0072] For example, the semiconductor layer M0 can be used to form the active region of a transistor in a pixel, where the active region overlaps with the first conductive layer to form the transistor. Figure 6 illustrates an example of a fourth electrode C14 located in the semiconductor layer M0. The semiconductor layer M0 can then be heavily doped to form the fourth electrode C14 of the compensation capacitor C1, which at least partially overlaps with the vertical projection of the first electrode C11 onto the substrate, thereby increasing the capacitance value of the compensation capacitor C1.

[0073] In some embodiments, the fourth electrode C14 may be located on the first conductive layer, while the first electrode C11 is located on the second conductive layer M2, such that the vertical distance between the fourth electrode C14 and the first electrode C11 is equal to the thickness of the insulating layer between the first conductive layer and the second conductive layer M2. That is, the vertical distance between the fourth electrode C14 and the first electrode C11 is relatively small, which can increase the capacitance value of the capacitor formed by the fourth electrode C14 and the first electrode C11, and further increase the capacitance value of the compensation capacitor C1, which is beneficial to reducing the load difference between the first signal line S1 and the second signal line S2.

[0074] Figure 7 is a schematic diagram of another display panel provided in an embodiment of this application. As shown in Figure 7, the display panel further includes a second non-display area NAA2 and a third non-display area NAA3; along the first direction X, the second non-display area NAA2 is disposed on at least one side of the second display area AA2; along the second direction Y, the third non-display area NAA3 is disposed on the side of the first display area AA1 away from the second display area AA2; when the display panel includes a plurality of compensation capacitors C1, at least one compensation capacitor C1 is disposed in the second non-display area NAA2 and / or the third non-display area NAA3.

[0075] For example, as shown in Figure 7, the second non-display area NAA2 can be the non-display areas on the left and right sides of the second display area AA2. The second non-display area NAA2 can form the non-display areas on the left and right sides of the display area together with the first non-display area NAA1. The third non-display area NAA3 can include the non-display areas on the top and bottom sides of the display area. When the first display area AA1 includes multiple rows of first pixels, corresponding to multiple first signal lines S1, the display panel needs to be equipped with multiple compensation capacitors C1. At this time, at least one compensation capacitor C1 can be set to extend from the first non-display area NAA1 to at least one of the non-display areas on both sides, which is beneficial to increase the space for arranging the compensation capacitor C1, thereby increasing the capacitance value of the compensation capacitor C1 and further reducing the load difference between the first signal line S1 and the second signal line S2. For example, as shown in Figure 7, when the first display area AA1 is set on the top edge of the display area of ​​the display panel, the compensation capacitor C1 can extend to the third non-display area NAA3, that is, the top edge of the display panel, to increase the arrangement space of the compensation capacitor C1.

[0076] In some embodiments, FIG8 is a schematic diagram of another display panel structure provided by an embodiment of the present application, and FIG9 is a schematic diagram of a gate driving circuit provided by an embodiment of the present application. As shown in FIG8 and FIG9, the display panel further includes a second non-display area NAA2 and a plurality of cascaded gate driving circuits GIP; along the first direction X, the second non-display area NAA2 is disposed on at least one side of the second display area AA2; the gate driving circuit GIP is disposed in the first non-display area NAA1 and the second non-display area NAA2; the gate driving circuit GIP includes a first capacitor Cs1 and a first transistor T1; the first terminal of the first transistor T1 is used to receive the clock signal provided by the clock signal input terminal CLK2, the second terminal of the first transistor T1 is connected to the first plate of the first capacitor Cs1, and the second terminal of the first transistor T1 is connected to the first signal line S1 or the second signal line S2, and the gate of the first transistor T1 is connected to the second plate of the first capacitor Cs1; the capacitance value of the first capacitor Cs1 connected to the first signal line S1 is greater than the capacitance value of the first capacitor Cs1 connected to the second signal line S2.

[0077] For example, the output terminal GOUT of each gate driving circuit GIP in the cascaded gate driving circuit GIP can be connected to a first signal line S1 or a second signal line S2 to provide a scan signal for the first signal line S1 or the second signal line S2. The gate driving circuit GIP includes a first transistor T1. When the first transistor T1 is turned on, it can output a clock signal provided by the clock signal input terminal CLK2 to the output terminal GOUT of the gate driving circuit GIP as a scan signal. The first plate of the first capacitor Cs1 is connected to the output terminal GOUT of the gate driving circuit GIP to maintain the scan signal output by the gate driving circuit GIP. At this time, the first plate of the first capacitor Cs1 is connected to the first signal line S1 or the second signal line S2, making the first capacitor Cs1 act as a load for the first signal line S1 or the second signal line S2. Along the first direction X, when the number of first pixels P1 is less than the number of second pixels P2, the load of the first signal line S1 in the first display area AA1 is less than the load of the second signal line S2 in the second display area AA2. At this time, setting the capacitance value of the first capacitor Cs1 connected to the first signal line S1 to be greater than the capacitance value of the first capacitor Cs1 connected to the second signal line S2 can make the load of the first signal line S1 in the first non-display area NAA1 greater than the load of the second signal line S2 in the second non-display area NAA2. This can reduce the load difference between the first signal line S1 and the second signal line S2 in the display area, thereby reducing the brightness difference between the first display area AA1 and the second display area AA2 caused by the load difference between the first signal line S1 and the second signal line S2, improving the brightness consistency between the first display area AA1 and the second display area AA2, and thus improving the display effect of the display panel.

[0078] Referring again to Figure 9, the gate drive circuit GIP also includes a second transistor T2 and a potential sustaining capacitor Cs3. The first terminal of the second transistor T2 and the first plate of the potential sustaining capacitor Cs3 are connected to the high voltage signal input terminal VGH. The gate of the second transistor T2 and the second plate of the potential sustaining capacitor Cs3 are connected to the first node N1. When the potential of the first node N1 is low, the second transistor T2 transmits the high voltage signal provided by the high voltage signal input terminal VGH to the output terminal GOUT. The gate drive circuit also includes a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and an eighth transistor T8. The gates of the third transistor T3 and the fifth transistor T5 are connected to the inverting clock signal input terminal CLK1. The first terminal of the third transistor T3 serves as the input terminal SIN of the gate drive circuit GIP. The first terminal of the fifth transistor T5 and the gate of the eighth transistor T8 are connected to the low voltage signal input terminal VGL. The second terminal of the third transistor T3 is connected to the gate of the fourth transistor T4, the second terminal of the sixth transistor T6, and the first terminal of the eighth transistor T8. The first terminal of the fourth transistor T4 and the gate of the sixth transistor T6 are connected to the clock signal input terminal CLK2. The second terminal of the fourth transistor T4 is connected to the second terminal of the fifth transistor T5, the gate of the seventh transistor T7, and the first node N1. The first terminal of the seventh transistor T7 is connected to the high voltage signal input terminal VGH. The second terminal of the seventh transistor T7 is connected to the first terminal of the sixth transistor T6. The second terminal of the eighth transistor T8 is connected to the gate of the first transistor T1. The inverted clock signal input terminal CLK1 provides an inverted clock signal with the opposite potential to the clock signal. The states of different transistors are controlled by the inverted clock signal, the clock signal, the high-voltage signal, the low-voltage signal, and the start signal input to the gate drive circuit GIP (GIP), respectively. This allows for the shifting output of the start signal input to the gate drive circuit GIP (GIP). When different gate drive circuits (GIP) are cascaded, they can provide shifted scan signals for the first signal line S1 and the second signal line S2, thereby enabling progressive pixel driving within the first display area AA1 and the second display area AA2.

[0079] In some embodiments, the compensation capacitor C1 includes a first capacitor Cs1, thereby directly compensating for the load difference between the first signal line S1 and the second signal line S2 by adjusting the capacitance value of the first capacitor Cs1 in different gate drive circuits GIP, avoiding the need to set an additional compensation capacitor C1, and simplifying the manufacturing process of the display panel.

[0080] Figure 10 is a partial structural schematic diagram of a first gate driving circuit provided in an embodiment of this application, and Figure 11 is a partial structural schematic diagram of a second gate driving circuit provided in an embodiment of this application. As shown in Figures 8 to 11, the gate driving circuit GIP connected to the first signal line S1 is the first gate driving circuit GIP1, and the gate driving circuit GIP connected to the second signal line S2 is the second gate driving circuit GIP2; along the first direction X, the width d1 of the first plate of the first capacitor Cs1 in the first gate driving circuit GIP1 is greater than the width d2 of the first plate of the first capacitor Cs1 in the second gate driving circuit GIP2; the width d3 of the second plate of the first capacitor Cs1 in the first gate driving circuit GIP1 is greater than the width d4 of the second plate of the first capacitor Cs1 in the second gate driving circuit GIP2.

[0081] For example, as shown in Figures 10 and 11, along the first direction X, the width d1 of the first plate of the first capacitor Cs1 in the first gate drive circuit GIP1 is greater than the width d2 of the first plate of the first capacitor Cs1 in the second gate drive circuit GIP2. At the same time, the width d3 of the second plate of the first capacitor Cs1 in the first gate drive circuit GIP1 is greater than the width d4 of the second plate of the first capacitor Cs1 in the second gate drive circuit GIP2. This makes the overlapping area of ​​the two plates of the first capacitor Cs1 in the first gate drive circuit GIP1 greater than the overlapping area of ​​the two plates of the first capacitor Cs1 in the second gate drive circuit GIP2. As a result, the capacitance value of the first capacitor Cs1 in the first gate drive circuit GIP1 is greater than the capacitance value of the first capacitor Cs1 in the second gate drive circuit GIP2, which is used to compensate for the load difference between the first signal line S1 and the second signal line S2.

[0082] In some embodiments, the display panel further includes a substrate and a first conductive layer and a second conductive layer stacked on the substrate, wherein the first conductive layer is disposed on the side of the second conductive layer close to the substrate; the first electrode of the first capacitor Cs1 is located on the second conductive layer, and the second electrode of the first capacitor Cs1 is located on the first conductive layer.

[0083] For example, the first conductive layer can form the gate of the first transistor T1 and the second plate of the first capacitor Cs1, and the second conductive layer can form the first plate of the first capacitor Cs1 and be connected to the second plate of the first transistor T1 through a via.

[0084] Referring again to Figures 10 and 11, along the second direction Y, the length l1 of the first plate of the first capacitor Cs1 in the first gate drive circuit GIP1 is greater than the length l2 of the first plate of the first capacitor Cs1 in the second gate drive circuit GIP2, and the length l3 of the second plate of the first capacitor Cs1 in the first gate drive circuit GIP1 is greater than the length l4 of the second plate of the first capacitor Cs1 in the second gate drive circuit GIP2.

[0085] For example, along the second direction Y, the length l1 of the first plate of the first capacitor Cs1 in the first gate drive circuit GIP1 is greater than the length l2 of the first plate of the first capacitor Cs1 in the second gate drive circuit GIP2, and the length l3 of the second plate of the first capacitor Cs1 in the first gate drive circuit GIP1 is greater than the length l4 of the second plate of the first capacitor Cs1 in the second gate drive circuit GIP2. Similarly, the overlapping area of ​​the two plates of the first capacitor Cs1 in the first gate drive circuit GIP1 can be greater than the overlapping area of ​​the two plates of the first capacitor Cs1 in the second gate drive circuit GIP2, thereby making the capacitance value of the first capacitor Cs1 in the first gate drive circuit GIP1 greater than the capacitance value of the first capacitor Cs1 in the second gate drive circuit GIP2, to compensate for the load difference between the first signal line S1 and the second signal line S2.

[0086] Referring again to Figure 10, at least a portion of the plates of the first capacitor Cs1 in the first gate drive circuit GIP1 extend between adjacent first gate drive circuits GIP1, or extend between the first gate drive circuit GIP1 and the second gate drive circuit GIP2.

[0087] For example, there is space between adjacent gate driving circuits GIP. Along the second direction Y, when the next stage gate driving circuit GIP of the first gate driving circuit GIP1 is the first gate driving circuit GIP1, the two plates of the first capacitor Cs1 in the first gate driving circuit GIP1 can be extended from one side of the first transistor T1 along the first direction X to the space between two adjacent first gate driving circuits GIP1, so that the two plates of the first capacitor Cs1 in the first gate driving circuit GIP1 can utilize the space between adjacent first gate driving circuits GIP1, further increasing the capacitance value of the first capacitor Cs1 in the first gate driving circuit GIP1, compensating for the load difference between the first signal line S1 and the second signal line S2, and improving the space utilization of the first non-display area NAA1. Similarly, along the second direction Y, when the next stage gate drive circuit GIP of the last first gate drive circuit GIP1 is the second gate drive circuit GIP2, the two plates of the first capacitor Cs1 in the last first gate drive circuit GIP1 can be extended from one side of the first transistor T1 along the first direction X to between the last first gate drive circuit GIP1 and the first second gate drive circuit GIP2, which can also increase the capacitance value of the first capacitor Cs1 in the first gate drive circuit GIP1.

[0088] In some embodiments, continuing to refer to Figures 10 and 11, along the second direction Y, the distance d5 between adjacent first gate drive circuits GIP1 is greater than the distance d6 between adjacent second gate drive circuits GIP2. Exemplarily, the boundary of the semiconductor layer pattern in the gate drive circuit can be the boundary of the corresponding gate drive circuit.

[0089] For example, when the plate of the first capacitor Cs1 in the first gate drive circuit GIP1 extends between adjacent first gate drive circuits GIP1, or extends between the first gate drive circuit GIP1 and the second gate drive circuit GIP2, the distance d5 between adjacent first gate drive circuits GIP1 can be set to be greater than the distance d6 between adjacent second gate drive circuits GIP2, so that there is a larger space between adjacent first gate drive circuits GIP1 for setting the two plates of the first capacitor Cs1, thereby increasing the capacitance value of the first capacitor Cs1 and further compensating for the load difference between the first signal line S1 and the second signal line S2.

[0090] Figure 12 is a schematic diagram of another first gate driving circuit provided in an embodiment of this application. Figure 13 is a partial schematic diagram of another first gate driving circuit provided in an embodiment of this application. Figure 14 is a cross-sectional schematic diagram of a first capacitor obtained by cross-sectioning along AA' provided in an embodiment of this application. As shown in Figures 12 to 14, the display panel further includes a third conductive layer M3, which is disposed on the side of the second conductive layer M2 away from the substrate. The compensation capacitor C1 further includes a second capacitor Cs2. The first electrode of the first capacitor Cs1 is reused as the first electrode of the second capacitor Cs2, and the second electrode of the second capacitor Cs2 is located in the third conductive layer M3. The vertical projection of the second electrode of the second capacitor Cs2 on the substrate overlaps with the vertical projection of the first electrode of the first capacitor Cs1 on the substrate.

[0091] For example, the third conductive layer M3 can be the third metal layer of the driving circuit layer, used to form the source and drain of the transistor in the pixel. The second plate of the second capacitor Cs2 is located on the third conductive layer M3, and the vertical projection of the second plate of the second capacitor Cs2 on the substrate overlaps with the vertical projection of the first plate of the first capacitor Cs1 on the substrate. This allows the first plate of the first capacitor Cs1 and the second plate of the second capacitor Cs2 in the first gate driving circuit GIP1 to form the second capacitor Cs2. At this time, both the first capacitor Cs1 and the second capacitor Cs2 are connected to the output terminal GOUT of the first gate driving circuit GIP1, which can further increase the load of the first signal line S1, better compensate for the load difference between the first signal line S1 and the second signal line S2, and improve the brightness uniformity of the display panel.

[0092] The display panel may also include a fixed-potential signal line for providing a fixed-potential signal. The second plate of the second capacitor Cs2 is connected to the fixed-potential signal line, thus preventing the second capacitor Cs2 from affecting the scan signal. For example, as shown in FIG12, the fixed-potential signal line may include a power signal line VDD, which may be disposed on the third conductive layer M3. In this case, the second plate of the second capacitor Cs2 can be connected to the power signal line VDD, so that the second plate of the second capacitor Cs2 has a fixed potential, thus preventing the second capacitor Cs2 from affecting the scan signal.

[0093] Referring again to Figure 13, a cascaded signal line ST is provided between adjacent gate drive circuits GIP. The cascaded signal line ST is connected to the first plate of the first capacitor Cs1 in the previous stage gate drive circuit GIP, and the cascaded signal line ST is connected to the start signal input terminal SIN of the current stage gate drive circuit GIP. The cascaded signal line ST is located in the third conductive layer M3.

[0094] For example, the cascaded signal line ST is connected between the output terminal GOUT of the previous stage gate drive circuit GIP and the start signal input terminal SIN of the current stage gate drive circuit GIP, so that the scan signal output by the previous stage gate drive circuit GIP serves as the start signal of the current stage gate drive circuit GIP, enabling the shifted output of scan signals corresponding to different rows of pixels. The cascaded signal line ST does not overlap with the second plate of the second capacitor Cs2, avoiding a short circuit between the cascaded signal line ST and the second plate of the second capacitor Cs2.

[0095] In some embodiments, as shown in FIG7, when the first display area AA1 includes multiple first signal lines S1, the capacitance values ​​of the compensation capacitors C1 connected to the first signal lines S1 are equal.

[0096] In some embodiments, when the display panel is provided with multiple compensation capacitors C1, the capacitance value of each compensation capacitor C1 can be equal, making the load corresponding to each first signal line S1 equal, thereby reducing the brightness difference of the first display area AA1. Simultaneously, the load difference between different first signal lines S1 and second signal lines S2 can be reduced synchronously, reducing the brightness difference between the first display area AA1 and the second display area AA2, and improving the display effect of the display panel. For example, the capacitance value of each compensation capacitor C1 can be the capacitance value corresponding to compensating for the load difference between the first signal line S1 and the second signal line S2, so that after the first signal line S1 is connected to the compensation capacitor C1, the load difference between the first signal line S1 and the second signal line S2 tends to 0, reducing the brightness difference between the first display area AA1 and the second display area AA2, and improving the display effect of the display panel.

[0097] In some embodiments, FIG15 is a schematic diagram of another display panel structure provided in an embodiment of this application. As shown in FIG15, it can also be configured such that, in the plurality of first signal lines S1, along the direction Y from the second display area AA2 to the first display area AA1, the capacitance value of the compensation capacitor C1 connected to the first signal line S1 gradually decreases.

[0098] For example, as shown in Figure 15, along the direction Y from the second display area AA2 to the first display area AA1, the area of ​​the compensation capacitor C1 connected to the first signal line S1 gradually decreases, causing the capacitance value of the compensation capacitor C1 connected to the first signal line S1 to gradually decrease. This allows the display brightness of the first display area AA1 to gradually decrease from the edge near the second display area AA2, thereby improving the brightness difference between the first display area AA1 and the second display area AA2 within the visible range of the human eye. Moreover, along the direction from the second display area AA2 to the first display area AA1, the capacitance value of the compensation capacitor C1 connected to the first signal line S1 can gradually decrease, thereby gradually reducing the space required for the compensation capacitor C1, which is beneficial for achieving a narrow bezel on the display panel.

[0099] In some embodiments, along the direction Y from the second display area AA2 to the first display area AA1, the ratio of the sum of the capacitance values ​​of the compensation capacitor C1 and the equivalent capacitance of the first pixel P1 connected to the first first signal line S1 to the sum of the capacitance values ​​of the compensation capacitor C1 and the equivalent capacitance of the first pixel P1 connected to the last first signal line S1 is less than or equal to 100:40.

[0100] For example, the total load of the first signal line S1 includes the sum of the capacitance values ​​of the compensation capacitor C1 and the equivalent capacitance of the first pixel P1. Along the direction Y from the second display area AA2 to the first display area AA1, the ratio of the sum of the capacitance values ​​of the compensation capacitor C1 and the equivalent capacitance of the first pixel P1 connected to the first first signal line S1 to the sum of the capacitance values ​​of the compensation capacitor C1 and the equivalent capacitance of the first pixel P1 connected to the last first signal line S1 is less than or equal to 100:40. This allows the load of the first signal line S1 adjacent to the second signal line S2 to tend to be equal to the load of the second signal line S2. Furthermore, along the direction from the second display area AA2 to the first display area AA1, the load of the first signal line S1 gradually decreases. This allows the brightness of the display panel to gradually decrease from the first pixel P1 in the first row closest to the second display area AA2, improving the brightness difference between the first display area AA1 and the second display area AA2 within the visible range of the human eye.

[0101] In some embodiments, as shown in FIG8, the first display area AA1 includes a first sub-area AA11 and a second sub-area AA12 arranged along the first direction X, and a first non-display area NAA1 is disposed on the side of the first sub-area AA11 away from the second sub-area AA12, and / or the side of the second sub-area AA12 away from the first sub-area AA11.

[0102] For example, when setting a compensation capacitor C1 in the first non-display area NAA1, the compensation capacitor C1 can be set in the conventional non-display area on the left and right sides of the display panel, avoiding the need to set an additional compensation capacitor C1 in the non-display area between the first sub-area AA11 and the second sub-area AA12. This helps to reduce the wiring space in the non-display area between the first sub-area AA11 and the second sub-area AA12, and achieve a narrow bezel of the display panel in irregular display areas. When the non-display area of ​​the display panel includes a curved edge, the first non-display area NAA1 includes a curved non-display area. Setting a compensation capacitor C1 in the first non-display area NAA1 can make full use of the bezel area of ​​the display panel.

[0103] This application embodiment also provides a display panel. As shown in FIG8, the display panel includes a first display area AA1, a second display area AA2, and a first non-display area NAA1; along a first direction X, the first non-display area NAA1 is located on at least one side of the first display area AA1, and the first display area AA1 and the second display area AA2 are arranged along a second direction Y, wherein the first direction X intersects the second direction Y; the display panel further includes:

[0104] At least one first signal line S1 and at least one row of first pixels P1 are located in the first display area AA1; the first signal line S1 extends along the first direction X and is connected to the row of first pixels P1.

[0105] The second display area AA2 has at least one second signal line S2 and at least one row of second pixels P2; the second signal line S2 extends along the first direction X and is connected to the row of second pixels P2; the number of first pixels P1 arranged along the first direction X is less than the number of second pixels P2 arranged along the first direction X.

[0106] Multiple cascaded gate drive circuits (GIPs) are provided in the first non-display area NAA1. Each gate drive circuit (GIP) includes a first capacitor (Cs1). The first capacitor (Cs1) is connected to either a first signal line (S1) or a second signal line (S2). The capacitance value of the first capacitor (Cs1) connected to the first signal line (S1) is greater than the capacitance value of the first capacitor (Cs1) connected to the second signal line (S2).

[0107] For example, when the number of first pixels P1 arranged along the first direction X is less than the number of second pixels P2 arranged along the first direction X, the load of the first signal line S1 in the first display area AA1 is less than the load of the second signal line S2 in the second display area AA2. In this case, setting the capacitance value of the first capacitor Cs1 connected to the first signal line S1 to be greater than the capacitance value of the first capacitor Cs1 connected to the second signal line S2 allows the load of the first signal line S1 in the first non-display area NAA1 to be greater than the load of the second signal line S2 in the second non-display area NAA2. This reduces the load difference between the first signal line S1 and the second signal line S2 in the display area, thereby reducing the brightness difference between the first display area AA1 and the second display area AA2 caused by the load difference between the first signal line S1 and the second signal line S2, improving the brightness consistency between the first display area AA1 and the second display area AA2, and ultimately improving the display effect of the display panel.

[0108] In some embodiments, as shown in FIG9, the gate drive circuit GIP further includes a first transistor T1; the first terminal of the first transistor T1 is used to receive the clock signal CLK2, the second terminal of the first transistor T1 is connected to the first plate of the first capacitor Cs1, and the gate of the first transistor T1 is connected to the second plate of the first capacitor Cs1.

[0109] For example, the second terminal of the first transistor T1 is connected to the first plate of the first capacitor Cs1, and is connected to the first signal line S1 or the second signal line S2 as the output terminal GOUT of the gate drive circuit GIP, so that the first capacitor Cs1 serves as the load of the first signal line S1 or the second signal line S2. Thus, the load of the first signal line S1 or the second signal line S2 can be adjusted by adjusting the capacitance value of the first capacitor Cs1.

[0110] This application also provides a display device. Figure 16 is a schematic diagram of the structure of a display device provided in an embodiment of this application. As shown in Figure 16, the display device 100 includes the display panel 10 provided in any embodiment of this application. Since the display device 100 includes the display panel 10 provided in any embodiment of this application, it has the same beneficial effects as the display panel 10 provided in any embodiment of this application, and will not be described again here. The display device 100 can be, for example, any product or component with display function such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, smart wearable device, or information kiosks in public lobbies.

Claims

1. A display panel, comprising a first display area, a second display area, and a first non-display area; wherein, along a first direction, the first non-display area is located on at least one side of the first display area, and the first display area and the second display area are arranged along a second direction, the first direction intersecting the second direction; the display panel comprising: At least one first signal line and at least one row of first pixels are located in the first display area; The first signal line extends along the first direction and is connected to a row of the first pixel; The second display area has at least one second signal line and at least one row of second pixels; the second signal line extends along the first direction and is connected to a row of second pixels; The number of first pixels arranged along the first direction is less than the number of second pixels arranged along the first direction; At least one compensation capacitor is located in the first non-display area, and the compensation capacitor is connected to the first signal line.

2. The display panel according to claim 1 further includes a gate driving circuit; the gate driving circuit is disposed in the first non-display area, and the compensation capacitor is disposed on the side of the gate driving circuit close to the first display area; the gate driving circuit is connected to the first signal line and is configured to provide a scanning signal for the first signal line.

3. The display panel according to claim 2 further includes a substrate and a driving circuit layer, the driving circuit layer being disposed on the substrate, and the pixel circuit in the first pixel being located in the driving circuit layer; the driving circuit layer includes at least two conductive layers, and the compensation capacitor includes at least two plates, the at least two plates of the compensation capacitor being located in different conductive layers respectively.

4. The display panel of claim 3, wherein, The driving circuit layer includes a first conductive layer and a second conductive layer stacked together. The first conductive layer is disposed on the side of the second conductive layer close to the substrate. The compensation capacitor includes a first electrode and a second electrode. The first electrode of the compensation capacitor is located on the first conductive layer, and the second electrode of the compensation capacitor is located on the second conductive layer. The orthographic projections of the first electrode and the second electrode of the compensation capacitor on the substrate at least partially overlap. The first signal line is connected to the first electrode of the compensation capacitor.

5. The display panel of claim 4, wherein, The second plate of the compensation capacitor is configured to receive a signal with a constant potential; the second plate of the compensation capacitor is configured to receive a power supply signal or an initialization signal. The second plates of the multiple compensation capacitors are connected as one unit.

6. The display panel of claim 4, wherein, The first signal line is located in the first conductive layer, extends to the first non-display area, and includes an overlap portion that at least partially overlaps with the second plate of the compensation capacitor. The overlap portion of the first signal line is multiplexed as the first plate of the compensation capacitor.

7. The display panel of claim 4, wherein, The driving circuit layer further includes a third conductive layer, which is disposed on the side of the second conductive layer away from the first conductive layer. The compensation capacitor further includes a third electrode plate, which is located in the third conductive layer. The third electrode plate of the compensation capacitor is connected to the first electrode plate of the compensation capacitor. The first signal line extends to the first non-display area and includes an overlap portion that at least partially overlaps with the second electrode plate of the compensation capacitor. The overlap portion of the first signal line is multiplexed as the third electrode plate of the compensation capacitor.

8. The display panel of claim 3, wherein, The driving circuit layer includes a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer stacked in sequence. The compensation capacitor includes a first electrode plate and a second electrode plate. The first electrode plate of the compensation capacitor is located on the second conductive layer, and the second electrode plate of the compensation capacitor is located on the third conductive layer. The orthographic projections of the first electrode plate and the second electrode plate of the compensation capacitor on the substrate at least partially overlap. The compensation capacitor also includes a third plate, which is located in the fourth conductive layer and is connected to the first plate of the compensation capacitor. The first signal line extends to the first non-display area, and the first signal line includes an overlap portion that at least partially overlaps with the second plate of the compensation capacitor, the overlap portion of the first signal line being multiplexed as the third plate of the compensation capacitor.

9. The display panel of claim 8, wherein, The compensation capacitor further includes a fourth plate, which is connected to the second plate of the compensation capacitor. The vertical projection of the fourth plate of the compensation capacitor on the substrate at least partially overlaps with the vertical projection of the first plate on the substrate. The driving circuit layer further includes a semiconductor layer, which is disposed on the side of the first conductive layer near the substrate, and the fourth electrode is located in the first conductive layer or the semiconductor layer.

10. The display panel according to any one of claims 2-9, further comprising a second non-display area and a third non-display area; the second non-display area is disposed on at least one side of the second display area along the first direction; the third non-display area is disposed on the side of the first display area away from the second display area along the second direction; the display panel includes a plurality of the compensation capacitors, and at least one of the compensation capacitors is disposed in at least one of the second non-display area and the third non-display area.

11. The display panel according to claim 1, further comprising a second non-display area and a plurality of cascaded gate driving circuits; the second non-display area is disposed on at least one side of the second display area along the first direction; the gate driving circuit is disposed in the first non-display area and the second non-display area; the gate driving circuit includes a first capacitor and a first transistor; the first terminal of the first transistor is configured to receive a clock signal, the second terminal of the first transistor is connected to the first plate of the first capacitor, and the second terminal of the first transistor is connected to the first signal line or the second signal line, the gate of the first transistor is connected to the second plate of the first capacitor; the capacitance value of the first capacitor connected to the first signal line is greater than the capacitance value of the first capacitor connected to the second signal line.

12. The display panel of claim 11, wherein, The gate driving circuit connected to the first signal line is the first gate driving circuit, and the gate driving circuit connected to the second signal line is the second gate driving circuit; along the first direction, the width of the first plate of the first capacitor in the first gate driving circuit is greater than the width of the first plate of the first capacitor in the second gate driving circuit, and the width of the second plate of the first capacitor in the first gate driving circuit is greater than the width of the second plate of the first capacitor in the second gate driving circuit. Along the second direction, the length of the first plate of the first capacitor in the first gate driving circuit is greater than the length of the first plate of the first capacitor in the second gate driving circuit, and the length of the second plate of the first capacitor in the first gate driving circuit is greater than the length of the second plate of the first capacitor in the second gate driving circuit. The compensation capacitor includes the first capacitor.

13. The display panel of claim 11, wherein, The gate driving circuit connected to the first signal line is the first gate driving circuit, and the gate driving circuit connected to the second signal line is the second gate driving circuit; at least a portion of the plates of the first capacitor in the first gate driving circuit extend between adjacent first gate driving circuits, or extend between the first gate driving circuit and the second gate driving circuit.

14. The display panel of claim 13, wherein, Along the second direction, the distance between adjacent first gate driving circuits is greater than the distance between adjacent second gate driving circuits.

15. The display panel according to claim 11, the display panel further comprising a substrate and a first conductive layer and a second conductive layer stacked on the substrate, the first conductive layer being disposed on the side of the second conductive layer close to the substrate; the first electrode of the first capacitor being located on the second conductive layer, and the second electrode of the first capacitor being located on the first conductive layer. The display panel further includes a third conductive layer disposed on the side of the second conductive layer away from the substrate; the compensation capacitor further includes a second capacitor; the first electrode of the first capacitor is reused as the first electrode of the second capacitor, and the second electrode of the second capacitor is located on the third conductive layer; the vertical projection of the second electrode of the second capacitor on the substrate overlaps with the vertical projection of the first electrode of the first capacitor on the substrate.

16. The display panel of claim 1, wherein, The first display area includes multiple first signal lines, and the capacitance values ​​of the compensation capacitors connected to the first signal lines are equal; or, along the direction from the second display area to the first display area, the capacitance values ​​of the compensation capacitors connected to the first signal lines gradually decrease.

17. The display panel of claim 16, wherein, Alternatively, along the direction from the second display area to the first display area, the ratio of the sum of the capacitance values ​​of the compensation capacitor and the equivalent capacitance of the first pixel connected to the first first signal line to the sum of the capacitance values ​​of the compensation capacitor and the equivalent capacitance of the first pixel connected to the last first signal line is less than or equal to 100:

40.

18. The display panel of claim 1, wherein, The first display area includes a first sub-area and a second sub-area arranged along the first direction, and the first non-display area is located on at least one of the following: the side of the first sub-area away from the second sub-area, and the side of the second sub-area away from the first sub-area.

19. A display panel, comprising a first display area, a second display area, and a first non-display area; wherein, along a first direction, the first non-display area is located on at least one side of the first display area, and the first display area and the second display area are arranged along a second direction, the first direction intersecting the second direction; the display panel further comprising: At least one first signal line and at least one row of first pixels are located in the first display area; The first signal line extends along the first direction and is connected to a row of the first pixel; The second display area has at least one second signal line and at least one row of second pixels; the second signal line extends along the first direction and is connected to a row of second pixels; The number of first pixels arranged along the first direction is less than the number of second pixels arranged along the first direction; Multiple cascaded gate driving circuits are provided; the gate driving circuits are disposed in the first non-display area; the gate driving circuits include a first capacitor; the first capacitor is connected to the first signal line or the second signal line; the capacitance value of the first capacitor connected to the first signal line is greater than the capacitance value of the first capacitor connected to the second signal line.

20. The display panel of claim 19, wherein, The gate driving circuit further includes a first transistor; the first terminal of the first transistor is configured to receive a clock signal, the second terminal of the first transistor is connected to the first plate of the first capacitor, and the gate of the first transistor is connected to the second plate of the first capacitor.

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